1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Main component of the bnxt_re driver 37 */ 38 39 #include <linux/module.h> 40 #include <linux/netdevice.h> 41 #include <linux/ethtool.h> 42 #include <linux/mutex.h> 43 #include <linux/list.h> 44 #include <linux/rculist.h> 45 #include <linux/spinlock.h> 46 #include <linux/pci.h> 47 #include <net/dcbnl.h> 48 #include <net/ipv6.h> 49 #include <net/addrconf.h> 50 #include <linux/if_ether.h> 51 #include <linux/auxiliary_bus.h> 52 53 #include <rdma/ib_verbs.h> 54 #include <rdma/ib_user_verbs.h> 55 #include <rdma/ib_umem.h> 56 #include <rdma/ib_addr.h> 57 #include <linux/hashtable.h> 58 59 #include "bnxt_ulp.h" 60 #include "roce_hsi.h" 61 #include "qplib_res.h" 62 #include "qplib_sp.h" 63 #include "qplib_fp.h" 64 #include "qplib_rcfw.h" 65 #include "bnxt_re.h" 66 #include "ib_verbs.h" 67 #include <rdma/bnxt_re-abi.h> 68 #include "bnxt.h" 69 #include "hw_counters.h" 70 71 static char version[] = 72 BNXT_RE_DESC "\n"; 73 74 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>"); 75 MODULE_DESCRIPTION(BNXT_RE_DESC); 76 MODULE_LICENSE("Dual BSD/GPL"); 77 78 /* globals */ 79 static DEFINE_MUTEX(bnxt_re_mutex); 80 81 static void bnxt_re_stop_irq(void *handle); 82 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev); 83 static int bnxt_re_netdev_event(struct notifier_block *notifier, 84 unsigned long event, void *ptr); 85 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev); 86 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type); 87 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev); 88 89 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 90 u32 *offset); 91 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable); 92 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev) 93 { 94 struct bnxt_qplib_chip_ctx *cctx; 95 struct bnxt_en_dev *en_dev; 96 struct bnxt_qplib_res *res; 97 u32 l2db_len = 0; 98 u32 offset = 0; 99 u32 barlen; 100 int rc; 101 102 res = &rdev->qplib_res; 103 en_dev = rdev->en_dev; 104 cctx = rdev->chip_ctx; 105 106 /* Issue qcfg */ 107 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset); 108 if (rc) 109 dev_info(rdev_to_dev(rdev), 110 "Couldn't get DB bar size, Low latency framework is disabled\n"); 111 /* set register offsets for both UC and WC */ 112 if (bnxt_qplib_is_chip_gen_p7(cctx)) { 113 res->dpi_tbl.ucreg.offset = offset; 114 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 115 } else { 116 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET : 117 BNXT_QPLIB_DBR_PF_DB_OFFSET; 118 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset; 119 } 120 121 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size 122 * is equal to the DB-Bar actual size. This indicates that L2 123 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping 124 * in such cases and DB-push will be disabled. 125 */ 126 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION); 127 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) { 128 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 129 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n"); 130 } 131 } 132 133 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev) 134 { 135 struct bnxt_qplib_chip_ctx *cctx; 136 137 cctx = rdev->chip_ctx; 138 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? 139 BNXT_QPLIB_WQE_MODE_VARIABLE : BNXT_QPLIB_WQE_MODE_STATIC; 140 if (bnxt_re_hwrm_qcaps(rdev)) 141 dev_err(rdev_to_dev(rdev), 142 "Failed to query hwrm qcaps\n"); 143 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) { 144 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT; 145 cctx->modes.toggle_bits |= BNXT_QPLIB_SRQ_TOGGLE_BIT; 146 } 147 } 148 149 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev) 150 { 151 struct bnxt_qplib_chip_ctx *chip_ctx; 152 153 if (!rdev->chip_ctx) 154 return; 155 chip_ctx = rdev->chip_ctx; 156 rdev->chip_ctx = NULL; 157 rdev->rcfw.res = NULL; 158 rdev->qplib_res.cctx = NULL; 159 rdev->qplib_res.pdev = NULL; 160 rdev->qplib_res.netdev = NULL; 161 kfree(chip_ctx); 162 } 163 164 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev) 165 { 166 struct bnxt_qplib_chip_ctx *chip_ctx; 167 struct bnxt_en_dev *en_dev; 168 int rc; 169 170 en_dev = rdev->en_dev; 171 172 rdev->qplib_res.pdev = en_dev->pdev; 173 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL); 174 if (!chip_ctx) 175 return -ENOMEM; 176 chip_ctx->chip_num = en_dev->chip_num; 177 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size; 178 179 rdev->chip_ctx = chip_ctx; 180 /* rest members to follow eventually */ 181 182 rdev->qplib_res.cctx = rdev->chip_ctx; 183 rdev->rcfw.res = &rdev->qplib_res; 184 rdev->qplib_res.dattr = &rdev->dev_attr; 185 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev); 186 187 bnxt_re_set_drv_mode(rdev); 188 189 bnxt_re_set_db_offset(rdev); 190 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res); 191 if (rc) { 192 kfree(rdev->chip_ctx); 193 rdev->chip_ctx = NULL; 194 return rc; 195 } 196 197 if (bnxt_qplib_determine_atomics(en_dev->pdev)) 198 ibdev_info(&rdev->ibdev, 199 "platform doesn't support global atomics."); 200 return 0; 201 } 202 203 /* SR-IOV helper functions */ 204 205 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev) 206 { 207 if (BNXT_EN_VF(rdev->en_dev)) 208 rdev->is_virtfn = 1; 209 } 210 211 /* Set the maximum number of each resource that the driver actually wants 212 * to allocate. This may be up to the maximum number the firmware has 213 * reserved for the function. The driver may choose to allocate fewer 214 * resources than the firmware maximum. 215 */ 216 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev) 217 { 218 struct bnxt_qplib_dev_attr *attr; 219 struct bnxt_qplib_ctx *ctx; 220 int i; 221 222 attr = &rdev->dev_attr; 223 ctx = &rdev->qplib_ctx; 224 225 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT, 226 attr->max_qp); 227 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K; 228 /* Use max_mr from fw since max_mrw does not get set */ 229 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr); 230 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT, 231 attr->max_srq); 232 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq); 233 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 234 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++) 235 rdev->qplib_ctx.tqm_ctx.qcount[i] = 236 rdev->dev_attr.tqm_alloc_reqs[i]; 237 } 238 239 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf) 240 { 241 struct bnxt_qplib_vf_res *vf_res; 242 u32 mrws = 0; 243 u32 vf_pct; 244 u32 nvfs; 245 246 vf_res = &qplib_ctx->vf_res; 247 /* 248 * Reserve a set of resources for the PF. Divide the remaining 249 * resources among the VFs 250 */ 251 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF; 252 nvfs = num_vf; 253 num_vf = 100 * num_vf; 254 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf; 255 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf; 256 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf; 257 /* 258 * The driver allows many more MRs than other resources. If the 259 * firmware does also, then reserve a fixed amount for the PF and 260 * divide the rest among VFs. VFs may use many MRs for NFS 261 * mounts, ISER, NVME applications, etc. If the firmware severely 262 * restricts the number of MRs, then let PF have half and divide 263 * the rest among VFs, as for the other resource types. 264 */ 265 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) { 266 mrws = qplib_ctx->mrw_count * vf_pct; 267 nvfs = num_vf; 268 } else { 269 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF; 270 } 271 vf_res->max_mrw_per_vf = (mrws / nvfs); 272 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF; 273 } 274 275 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev) 276 { 277 u32 num_vfs; 278 279 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res)); 280 bnxt_re_limit_pf_res(rdev); 281 282 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 283 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs; 284 if (num_vfs) 285 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs); 286 } 287 288 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev) 289 { 290 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev); 291 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 292 bnxt_re_set_resource_limits(rdev); 293 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw, 294 &rdev->qplib_ctx); 295 } 296 } 297 298 static void bnxt_re_shutdown(struct auxiliary_device *adev) 299 { 300 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 301 struct bnxt_re_dev *rdev; 302 303 rdev = en_info->rdev; 304 ib_unregister_device(&rdev->ibdev); 305 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 306 } 307 308 static void bnxt_re_stop_irq(void *handle) 309 { 310 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle); 311 struct bnxt_qplib_rcfw *rcfw; 312 struct bnxt_re_dev *rdev; 313 struct bnxt_qplib_nq *nq; 314 int indx; 315 316 rdev = en_info->rdev; 317 rcfw = &rdev->rcfw; 318 319 for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) { 320 nq = &rdev->nq[indx - 1]; 321 bnxt_qplib_nq_stop_irq(nq, false); 322 } 323 324 bnxt_qplib_rcfw_stop_irq(rcfw, false); 325 } 326 327 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent) 328 { 329 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle); 330 struct bnxt_msix_entry *msix_ent; 331 struct bnxt_qplib_rcfw *rcfw; 332 struct bnxt_re_dev *rdev; 333 struct bnxt_qplib_nq *nq; 334 int indx, rc; 335 336 rdev = en_info->rdev; 337 msix_ent = rdev->en_dev->msix_entries; 338 rcfw = &rdev->rcfw; 339 if (!ent) { 340 /* Not setting the f/w timeout bit in rcfw. 341 * During the driver unload the first command 342 * to f/w will timeout and that will set the 343 * timeout bit. 344 */ 345 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n"); 346 return; 347 } 348 349 /* Vectors may change after restart, so update with new vectors 350 * in device sctructure. 351 */ 352 for (indx = 0; indx < rdev->num_msix; indx++) 353 rdev->en_dev->msix_entries[indx].vector = ent[indx].vector; 354 355 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector, 356 false); 357 if (rc) { 358 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n"); 359 return; 360 } 361 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) { 362 nq = &rdev->nq[indx - 1]; 363 rc = bnxt_qplib_nq_start_irq(nq, indx - 1, 364 msix_ent[indx].vector, false); 365 if (rc) { 366 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n", 367 indx - 1); 368 return; 369 } 370 } 371 } 372 373 static struct bnxt_ulp_ops bnxt_re_ulp_ops = { 374 .ulp_irq_stop = bnxt_re_stop_irq, 375 .ulp_irq_restart = bnxt_re_start_irq 376 }; 377 378 /* RoCE -> Net driver */ 379 380 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev) 381 { 382 struct bnxt_en_dev *en_dev; 383 384 en_dev = rdev->en_dev; 385 return bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev->adev); 386 } 387 388 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd) 389 { 390 hdr->req_type = cpu_to_le16(opcd); 391 hdr->cmpl_ring = cpu_to_le16(-1); 392 hdr->target_id = cpu_to_le16(-1); 393 } 394 395 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg, 396 int msg_len, void *resp, int resp_max_len, 397 int timeout) 398 { 399 fw_msg->msg = msg; 400 fw_msg->msg_len = msg_len; 401 fw_msg->resp = resp; 402 fw_msg->resp_max_len = resp_max_len; 403 fw_msg->timeout = timeout; 404 } 405 406 /* Query device config using common hwrm */ 407 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 408 u32 *offset) 409 { 410 struct bnxt_en_dev *en_dev = rdev->en_dev; 411 struct hwrm_func_qcfg_output resp = {0}; 412 struct hwrm_func_qcfg_input req = {0}; 413 struct bnxt_fw_msg fw_msg = {}; 414 int rc; 415 416 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG); 417 req.fid = cpu_to_le16(0xffff); 418 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 419 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 420 rc = bnxt_send_msg(en_dev, &fw_msg); 421 if (!rc) { 422 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024); 423 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024); 424 } 425 return rc; 426 } 427 428 /* Query function capabilities using common hwrm */ 429 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev) 430 { 431 struct bnxt_en_dev *en_dev = rdev->en_dev; 432 struct hwrm_func_qcaps_output resp = {}; 433 struct hwrm_func_qcaps_input req = {}; 434 struct bnxt_qplib_chip_ctx *cctx; 435 struct bnxt_fw_msg fw_msg = {}; 436 u32 flags_ext2; 437 int rc; 438 439 cctx = rdev->chip_ctx; 440 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS); 441 req.fid = cpu_to_le16(0xffff); 442 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 443 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 444 445 rc = bnxt_send_msg(en_dev, &fw_msg); 446 if (rc) 447 return rc; 448 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE; 449 450 flags_ext2 = le32_to_cpu(resp.flags_ext2); 451 cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED || 452 flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED; 453 return 0; 454 } 455 456 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev) 457 { 458 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 459 struct hwrm_func_dbr_pacing_qcfg_output resp = {}; 460 struct hwrm_func_dbr_pacing_qcfg_input req = {}; 461 struct bnxt_en_dev *en_dev = rdev->en_dev; 462 struct bnxt_qplib_chip_ctx *cctx; 463 struct bnxt_fw_msg fw_msg = {}; 464 int rc; 465 466 cctx = rdev->chip_ctx; 467 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG); 468 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 469 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 470 rc = bnxt_send_msg(en_dev, &fw_msg); 471 if (rc) 472 return rc; 473 474 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 475 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) == 476 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC) 477 cctx->dbr_stat_db_fifo = 478 le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 479 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK; 480 481 pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth); 482 if (!pacing_data->fifo_max_depth) 483 pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx); 484 pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask); 485 pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift; 486 487 return 0; 488 } 489 490 /* Update the pacing tunable parameters to the default values */ 491 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev) 492 { 493 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 494 495 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing; 496 pacing_data->pacing_th = rdev->pacing.pacing_algo_th; 497 pacing_data->alarm_th = 498 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 499 } 500 501 static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev) 502 { 503 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 504 u32 read_val, fifo_occup; 505 506 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off); 507 fifo_occup = pacing_data->fifo_max_depth - 508 ((read_val & pacing_data->fifo_room_mask) >> 509 pacing_data->fifo_room_shift); 510 return fifo_occup; 511 } 512 513 static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev) 514 { 515 u32 max_occup, fifo_occup; 516 517 fifo_occup = __get_fifo_occupancy(rdev); 518 max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1; 519 if (fifo_occup == max_occup) 520 return true; 521 522 return false; 523 } 524 525 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev) 526 { 527 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 528 u32 retry_fifo_check = 1000; 529 u32 fifo_occup; 530 531 /* loop shouldn't run infintely as the occupancy usually goes 532 * below pacing algo threshold as soon as pacing kicks in. 533 */ 534 while (1) { 535 fifo_occup = __get_fifo_occupancy(rdev); 536 /* Fifo occupancy cannot be greater the MAX FIFO depth */ 537 if (fifo_occup > pacing_data->fifo_max_depth) 538 break; 539 540 if (fifo_occup < pacing_data->pacing_th) 541 break; 542 if (!retry_fifo_check--) { 543 dev_info_once(rdev_to_dev(rdev), 544 "%s: fifo_occup = 0x%xfifo_max_depth = 0x%x pacing_th = 0x%x\n", 545 __func__, fifo_occup, pacing_data->fifo_max_depth, 546 pacing_data->pacing_th); 547 break; 548 } 549 550 } 551 } 552 553 static void bnxt_re_db_fifo_check(struct work_struct *work) 554 { 555 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 556 dbq_fifo_check_work); 557 struct bnxt_qplib_db_pacing_data *pacing_data; 558 u32 pacing_save; 559 560 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 561 return; 562 pacing_data = rdev->qplib_res.pacing_data; 563 pacing_save = rdev->pacing.do_pacing_save; 564 __wait_for_fifo_occupancy_below_th(rdev); 565 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 566 if (pacing_save > rdev->pacing.dbr_def_do_pacing) { 567 /* Double the do_pacing value during the congestion */ 568 pacing_save = pacing_save << 1; 569 } else { 570 /* 571 * when a new congestion is detected increase the do_pacing 572 * by 8 times. And also increase the pacing_th by 4 times. The 573 * reason to increase pacing_th is to give more space for the 574 * queue to oscillate down without getting empty, but also more 575 * room for the queue to increase without causing another alarm. 576 */ 577 pacing_save = pacing_save << 3; 578 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4; 579 } 580 581 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING) 582 pacing_save = BNXT_RE_MAX_DBR_DO_PACING; 583 584 pacing_data->do_pacing = pacing_save; 585 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 586 pacing_data->alarm_th = 587 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 588 schedule_delayed_work(&rdev->dbq_pacing_work, 589 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 590 rdev->stats.pacing.alerts++; 591 mutex_unlock(&rdev->pacing.dbq_lock); 592 } 593 594 static void bnxt_re_pacing_timer_exp(struct work_struct *work) 595 { 596 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 597 dbq_pacing_work.work); 598 struct bnxt_qplib_db_pacing_data *pacing_data; 599 u32 fifo_occup; 600 601 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 602 return; 603 604 pacing_data = rdev->qplib_res.pacing_data; 605 fifo_occup = __get_fifo_occupancy(rdev); 606 607 if (fifo_occup > pacing_data->pacing_th) 608 goto restart_timer; 609 610 /* 611 * Instead of immediately going back to the default do_pacing 612 * reduce it by 1/8 times and restart the timer. 613 */ 614 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3); 615 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing); 616 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) { 617 bnxt_re_set_default_pacing_data(rdev); 618 rdev->stats.pacing.complete++; 619 goto dbq_unlock; 620 } 621 622 restart_timer: 623 schedule_delayed_work(&rdev->dbq_pacing_work, 624 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 625 rdev->stats.pacing.resched++; 626 dbq_unlock: 627 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 628 mutex_unlock(&rdev->pacing.dbq_lock); 629 } 630 631 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev) 632 { 633 struct bnxt_qplib_db_pacing_data *pacing_data; 634 635 if (!rdev->pacing.dbr_pacing) 636 return; 637 mutex_lock(&rdev->pacing.dbq_lock); 638 pacing_data = rdev->qplib_res.pacing_data; 639 640 /* 641 * Increase the alarm_th to max so that other user lib instances do not 642 * keep alerting the driver. 643 */ 644 pacing_data->alarm_th = pacing_data->fifo_max_depth; 645 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING; 646 cancel_work_sync(&rdev->dbq_fifo_check_work); 647 schedule_work(&rdev->dbq_fifo_check_work); 648 mutex_unlock(&rdev->pacing.dbq_lock); 649 } 650 651 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev) 652 { 653 /* Allocate a page for app use */ 654 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL); 655 if (!rdev->pacing.dbr_page) 656 return -ENOMEM; 657 658 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE); 659 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page; 660 661 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) { 662 free_page((u64)rdev->pacing.dbr_page); 663 rdev->pacing.dbr_page = NULL; 664 return -EIO; 665 } 666 667 /* MAP HW window 2 for reading db fifo depth */ 668 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK, 669 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 670 rdev->pacing.dbr_db_fifo_reg_off = 671 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) + 672 BNXT_RE_GRC_FIFO_REG_BASE; 673 rdev->pacing.dbr_bar_addr = 674 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off; 675 676 if (is_dbr_fifo_full(rdev)) { 677 free_page((u64)rdev->pacing.dbr_page); 678 rdev->pacing.dbr_page = NULL; 679 return -EIO; 680 } 681 682 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD; 683 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME; 684 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION; 685 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing; 686 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off; 687 bnxt_re_set_default_pacing_data(rdev); 688 /* Initialize worker for DBR Pacing */ 689 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check); 690 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp); 691 return 0; 692 } 693 694 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev) 695 { 696 cancel_work_sync(&rdev->dbq_fifo_check_work); 697 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 698 if (rdev->pacing.dbr_page) 699 free_page((u64)rdev->pacing.dbr_page); 700 701 rdev->pacing.dbr_page = NULL; 702 rdev->pacing.dbr_pacing = false; 703 } 704 705 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev, 706 u16 fw_ring_id, int type) 707 { 708 struct bnxt_en_dev *en_dev; 709 struct hwrm_ring_free_input req = {}; 710 struct hwrm_ring_free_output resp; 711 struct bnxt_fw_msg fw_msg = {}; 712 int rc = -EINVAL; 713 714 if (!rdev) 715 return rc; 716 717 en_dev = rdev->en_dev; 718 719 if (!en_dev) 720 return rc; 721 722 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 723 return 0; 724 725 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE); 726 req.ring_type = type; 727 req.ring_id = cpu_to_le16(fw_ring_id); 728 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 729 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 730 rc = bnxt_send_msg(en_dev, &fw_msg); 731 if (rc) 732 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x", 733 req.ring_id, rc); 734 return rc; 735 } 736 737 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev, 738 struct bnxt_re_ring_attr *ring_attr, 739 u16 *fw_ring_id) 740 { 741 struct bnxt_en_dev *en_dev = rdev->en_dev; 742 struct hwrm_ring_alloc_input req = {}; 743 struct hwrm_ring_alloc_output resp; 744 struct bnxt_fw_msg fw_msg = {}; 745 int rc = -EINVAL; 746 747 if (!en_dev) 748 return rc; 749 750 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC); 751 req.enables = 0; 752 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]); 753 if (ring_attr->pages > 1) { 754 /* Page size is in log2 units */ 755 req.page_size = BNXT_PAGE_SHIFT; 756 req.page_tbl_depth = 1; 757 } 758 req.fbo = 0; 759 /* Association of ring index with doorbell index and MSIX number */ 760 req.logical_id = cpu_to_le16(ring_attr->lrid); 761 req.length = cpu_to_le32(ring_attr->depth + 1); 762 req.ring_type = ring_attr->type; 763 req.int_mode = ring_attr->mode; 764 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 765 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 766 rc = bnxt_send_msg(en_dev, &fw_msg); 767 if (!rc) 768 *fw_ring_id = le16_to_cpu(resp.ring_id); 769 770 return rc; 771 } 772 773 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev, 774 u32 fw_stats_ctx_id) 775 { 776 struct bnxt_en_dev *en_dev = rdev->en_dev; 777 struct hwrm_stat_ctx_free_input req = {}; 778 struct hwrm_stat_ctx_free_output resp = {}; 779 struct bnxt_fw_msg fw_msg = {}; 780 int rc = -EINVAL; 781 782 if (!en_dev) 783 return rc; 784 785 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 786 return 0; 787 788 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE); 789 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id); 790 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 791 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 792 rc = bnxt_send_msg(en_dev, &fw_msg); 793 if (rc) 794 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x", 795 rc); 796 797 return rc; 798 } 799 800 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev, 801 dma_addr_t dma_map, 802 u32 *fw_stats_ctx_id) 803 { 804 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx; 805 struct hwrm_stat_ctx_alloc_output resp = {}; 806 struct hwrm_stat_ctx_alloc_input req = {}; 807 struct bnxt_en_dev *en_dev = rdev->en_dev; 808 struct bnxt_fw_msg fw_msg = {}; 809 int rc = -EINVAL; 810 811 *fw_stats_ctx_id = INVALID_STATS_CTX_ID; 812 813 if (!en_dev) 814 return rc; 815 816 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC); 817 req.update_period_ms = cpu_to_le32(1000); 818 req.stats_dma_addr = cpu_to_le64(dma_map); 819 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size); 820 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE; 821 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 822 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 823 rc = bnxt_send_msg(en_dev, &fw_msg); 824 if (!rc) 825 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id); 826 827 return rc; 828 } 829 830 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext) 831 { 832 } 833 834 /* Device */ 835 836 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev) 837 { 838 struct ib_device *ibdev = 839 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE); 840 if (!ibdev) 841 return NULL; 842 843 return container_of(ibdev, struct bnxt_re_dev, ibdev); 844 } 845 846 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 847 char *buf) 848 { 849 struct bnxt_re_dev *rdev = 850 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 851 852 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor); 853 } 854 static DEVICE_ATTR_RO(hw_rev); 855 856 static ssize_t hca_type_show(struct device *device, 857 struct device_attribute *attr, char *buf) 858 { 859 struct bnxt_re_dev *rdev = 860 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 861 862 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc); 863 } 864 static DEVICE_ATTR_RO(hca_type); 865 866 static struct attribute *bnxt_re_attributes[] = { 867 &dev_attr_hw_rev.attr, 868 &dev_attr_hca_type.attr, 869 NULL 870 }; 871 872 static const struct attribute_group bnxt_re_dev_attr_group = { 873 .attrs = bnxt_re_attributes, 874 }; 875 876 static const struct ib_device_ops bnxt_re_dev_ops = { 877 .owner = THIS_MODULE, 878 .driver_id = RDMA_DRIVER_BNXT_RE, 879 .uverbs_abi_ver = BNXT_RE_ABI_VERSION, 880 881 .add_gid = bnxt_re_add_gid, 882 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats, 883 .alloc_mr = bnxt_re_alloc_mr, 884 .alloc_pd = bnxt_re_alloc_pd, 885 .alloc_ucontext = bnxt_re_alloc_ucontext, 886 .create_ah = bnxt_re_create_ah, 887 .create_cq = bnxt_re_create_cq, 888 .create_qp = bnxt_re_create_qp, 889 .create_srq = bnxt_re_create_srq, 890 .create_user_ah = bnxt_re_create_ah, 891 .dealloc_pd = bnxt_re_dealloc_pd, 892 .dealloc_ucontext = bnxt_re_dealloc_ucontext, 893 .del_gid = bnxt_re_del_gid, 894 .dereg_mr = bnxt_re_dereg_mr, 895 .destroy_ah = bnxt_re_destroy_ah, 896 .destroy_cq = bnxt_re_destroy_cq, 897 .destroy_qp = bnxt_re_destroy_qp, 898 .destroy_srq = bnxt_re_destroy_srq, 899 .device_group = &bnxt_re_dev_attr_group, 900 .disassociate_ucontext = bnxt_re_disassociate_ucontext, 901 .get_dev_fw_str = bnxt_re_query_fw_str, 902 .get_dma_mr = bnxt_re_get_dma_mr, 903 .get_hw_stats = bnxt_re_ib_get_hw_stats, 904 .get_link_layer = bnxt_re_get_link_layer, 905 .get_port_immutable = bnxt_re_get_port_immutable, 906 .map_mr_sg = bnxt_re_map_mr_sg, 907 .mmap = bnxt_re_mmap, 908 .mmap_free = bnxt_re_mmap_free, 909 .modify_qp = bnxt_re_modify_qp, 910 .modify_srq = bnxt_re_modify_srq, 911 .poll_cq = bnxt_re_poll_cq, 912 .post_recv = bnxt_re_post_recv, 913 .post_send = bnxt_re_post_send, 914 .post_srq_recv = bnxt_re_post_srq_recv, 915 .query_ah = bnxt_re_query_ah, 916 .query_device = bnxt_re_query_device, 917 .query_pkey = bnxt_re_query_pkey, 918 .query_port = bnxt_re_query_port, 919 .query_qp = bnxt_re_query_qp, 920 .query_srq = bnxt_re_query_srq, 921 .reg_user_mr = bnxt_re_reg_user_mr, 922 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf, 923 .req_notify_cq = bnxt_re_req_notify_cq, 924 .resize_cq = bnxt_re_resize_cq, 925 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah), 926 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq), 927 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd), 928 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp), 929 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq), 930 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx), 931 }; 932 933 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev) 934 { 935 struct ib_device *ibdev = &rdev->ibdev; 936 int ret; 937 938 /* ib device init */ 939 ibdev->node_type = RDMA_NODE_IB_CA; 940 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA", 941 strlen(BNXT_RE_DESC) + 5); 942 ibdev->phys_port_cnt = 1; 943 944 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr); 945 946 ibdev->num_comp_vectors = rdev->num_msix - 1; 947 ibdev->dev.parent = &rdev->en_dev->pdev->dev; 948 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY; 949 950 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 951 ibdev->driver_def = bnxt_re_uapi_defs; 952 953 ib_set_device_ops(ibdev, &bnxt_re_dev_ops); 954 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1); 955 if (ret) 956 return ret; 957 958 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX); 959 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ); 960 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev); 961 } 962 963 static struct bnxt_re_dev *bnxt_re_dev_add(struct auxiliary_device *adev, 964 struct bnxt_en_dev *en_dev) 965 { 966 struct bnxt_re_dev *rdev; 967 968 /* Allocate bnxt_re_dev instance here */ 969 rdev = ib_alloc_device(bnxt_re_dev, ibdev); 970 if (!rdev) { 971 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!", 972 ROCE_DRV_MODULE_NAME); 973 return NULL; 974 } 975 /* Default values */ 976 rdev->nb.notifier_call = NULL; 977 rdev->netdev = en_dev->net; 978 rdev->en_dev = en_dev; 979 rdev->adev = adev; 980 rdev->id = rdev->en_dev->pdev->devfn; 981 INIT_LIST_HEAD(&rdev->qp_list); 982 mutex_init(&rdev->qp_lock); 983 mutex_init(&rdev->pacing.dbq_lock); 984 atomic_set(&rdev->stats.res.qp_count, 0); 985 atomic_set(&rdev->stats.res.cq_count, 0); 986 atomic_set(&rdev->stats.res.srq_count, 0); 987 atomic_set(&rdev->stats.res.mr_count, 0); 988 atomic_set(&rdev->stats.res.mw_count, 0); 989 atomic_set(&rdev->stats.res.ah_count, 0); 990 atomic_set(&rdev->stats.res.pd_count, 0); 991 rdev->cosq[0] = 0xFFFF; 992 rdev->cosq[1] = 0xFFFF; 993 994 return rdev; 995 } 996 997 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event 998 *unaffi_async) 999 { 1000 switch (unaffi_async->event) { 1001 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 1002 break; 1003 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 1004 break; 1005 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 1006 break; 1007 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 1008 break; 1009 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 1010 break; 1011 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 1012 break; 1013 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 1014 break; 1015 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 1016 break; 1017 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 1018 break; 1019 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 1020 break; 1021 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 1022 break; 1023 default: 1024 return -EINVAL; 1025 } 1026 return 0; 1027 } 1028 1029 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event, 1030 struct bnxt_re_qp *qp) 1031 { 1032 struct creq_qp_error_notification *err_event; 1033 struct bnxt_re_srq *srq = NULL; 1034 struct ib_event event = {}; 1035 unsigned int flags; 1036 1037 if (qp->qplib_qp.srq) 1038 srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq, 1039 qplib_srq); 1040 1041 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR && 1042 rdma_is_kernel_res(&qp->ib_qp.res)) { 1043 flags = bnxt_re_lock_cqs(qp); 1044 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1045 bnxt_re_unlock_cqs(qp, flags); 1046 } 1047 1048 event.device = &qp->rdev->ibdev; 1049 event.element.qp = &qp->ib_qp; 1050 event.event = IB_EVENT_QP_FATAL; 1051 1052 err_event = (struct creq_qp_error_notification *)qp_event; 1053 1054 switch (err_event->req_err_state_reason) { 1055 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR: 1056 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT: 1057 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT: 1058 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2: 1059 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3: 1060 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP: 1061 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND: 1062 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG: 1063 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE: 1064 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR: 1065 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR: 1066 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR: 1067 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR: 1068 event.event = IB_EVENT_QP_ACCESS_ERR; 1069 break; 1070 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1: 1071 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4: 1072 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH: 1073 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR: 1074 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR: 1075 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR: 1076 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR: 1077 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR: 1078 event.event = IB_EVENT_QP_REQ_ERR; 1079 break; 1080 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR: 1081 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR: 1082 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR: 1083 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR: 1084 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR: 1085 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR: 1086 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR: 1087 event.event = IB_EVENT_QP_FATAL; 1088 break; 1089 1090 default: 1091 break; 1092 } 1093 1094 switch (err_event->res_err_state_reason) { 1095 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX: 1096 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH: 1097 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT: 1098 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY: 1099 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR: 1100 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION: 1101 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR: 1102 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY: 1103 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR: 1104 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION: 1105 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR: 1106 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC: 1107 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND: 1108 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY: 1109 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR: 1110 event.event = IB_EVENT_QP_ACCESS_ERR; 1111 break; 1112 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE: 1113 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR: 1114 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE: 1115 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE: 1116 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR: 1117 event.event = IB_EVENT_QP_REQ_ERR; 1118 break; 1119 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW: 1120 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR: 1121 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR: 1122 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR: 1123 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR: 1124 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR: 1125 event.event = IB_EVENT_QP_FATAL; 1126 break; 1127 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR: 1128 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR: 1129 if (srq) 1130 event.event = IB_EVENT_SRQ_ERR; 1131 break; 1132 default: 1133 break; 1134 } 1135 1136 if (err_event->res_err_state_reason || err_event->req_err_state_reason) { 1137 ibdev_dbg(&qp->rdev->ibdev, 1138 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n", 1139 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user", 1140 qp->qplib_qp.id, 1141 err_event->sq_cons_idx, 1142 err_event->rq_cons_idx, 1143 err_event->req_slow_path_state, 1144 err_event->req_err_state_reason, 1145 err_event->res_slow_path_state, 1146 err_event->res_err_state_reason); 1147 } else { 1148 if (srq) 1149 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 1150 } 1151 1152 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) { 1153 (*srq->ib_srq.event_handler)(&event, 1154 srq->ib_srq.srq_context); 1155 } else if (event.device && qp->ib_qp.event_handler) { 1156 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context); 1157 } 1158 1159 return 0; 1160 } 1161 1162 static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq) 1163 { 1164 struct creq_cq_error_notification *cqerr; 1165 struct ib_event ibevent = {}; 1166 1167 cqerr = event; 1168 switch (cqerr->cq_err_reason) { 1169 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR: 1170 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR: 1171 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR: 1172 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR: 1173 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR: 1174 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR: 1175 ibevent.event = IB_EVENT_CQ_ERR; 1176 break; 1177 default: 1178 break; 1179 } 1180 1181 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) { 1182 ibevent.element.cq = &cq->ib_cq; 1183 ibevent.device = &cq->rdev->ibdev; 1184 1185 ibdev_dbg(&cq->rdev->ibdev, 1186 "%s err reason %d\n", __func__, cqerr->cq_err_reason); 1187 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context); 1188 } 1189 1190 return 0; 1191 } 1192 1193 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async, 1194 void *obj) 1195 { 1196 struct bnxt_qplib_qp *lib_qp; 1197 struct bnxt_qplib_cq *lib_cq; 1198 struct bnxt_re_qp *qp; 1199 struct bnxt_re_cq *cq; 1200 int rc = 0; 1201 u8 event; 1202 1203 if (!obj) 1204 return rc; /* QP was already dead, still return success */ 1205 1206 event = affi_async->event; 1207 switch (event) { 1208 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 1209 lib_qp = obj; 1210 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp); 1211 rc = bnxt_re_handle_qp_async_event(affi_async, qp); 1212 break; 1213 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION: 1214 lib_cq = obj; 1215 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq); 1216 rc = bnxt_re_handle_cq_async_error(affi_async, cq); 1217 break; 1218 default: 1219 rc = -EINVAL; 1220 } 1221 return rc; 1222 } 1223 1224 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw, 1225 void *aeqe, void *obj) 1226 { 1227 struct creq_qp_event *affi_async; 1228 struct creq_func_event *unaffi_async; 1229 u8 type; 1230 int rc; 1231 1232 type = ((struct creq_base *)aeqe)->type; 1233 if (type == CREQ_BASE_TYPE_FUNC_EVENT) { 1234 unaffi_async = aeqe; 1235 rc = bnxt_re_handle_unaffi_async_event(unaffi_async); 1236 } else { 1237 affi_async = aeqe; 1238 rc = bnxt_re_handle_affi_async_event(affi_async, obj); 1239 } 1240 1241 return rc; 1242 } 1243 1244 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq, 1245 struct bnxt_qplib_srq *handle, u8 event) 1246 { 1247 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq, 1248 qplib_srq); 1249 struct ib_event ib_event; 1250 1251 ib_event.device = &srq->rdev->ibdev; 1252 ib_event.element.srq = &srq->ib_srq; 1253 1254 if (srq->ib_srq.event_handler) { 1255 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT) 1256 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED; 1257 (*srq->ib_srq.event_handler)(&ib_event, 1258 srq->ib_srq.srq_context); 1259 } 1260 return 0; 1261 } 1262 1263 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq, 1264 struct bnxt_qplib_cq *handle) 1265 { 1266 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq, 1267 qplib_cq); 1268 1269 if (cq->ib_cq.comp_handler) 1270 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context); 1271 1272 return 0; 1273 } 1274 1275 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev) 1276 { 1277 int i; 1278 1279 for (i = 1; i < rdev->num_msix; i++) 1280 bnxt_qplib_disable_nq(&rdev->nq[i - 1]); 1281 1282 if (rdev->qplib_res.rcfw) 1283 bnxt_qplib_cleanup_res(&rdev->qplib_res); 1284 } 1285 1286 static int bnxt_re_init_res(struct bnxt_re_dev *rdev) 1287 { 1288 int num_vec_enabled = 0; 1289 int rc = 0, i; 1290 u32 db_offt; 1291 1292 bnxt_qplib_init_res(&rdev->qplib_res); 1293 1294 for (i = 1; i < rdev->num_msix ; i++) { 1295 db_offt = rdev->en_dev->msix_entries[i].db_offset; 1296 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1], 1297 i - 1, rdev->en_dev->msix_entries[i].vector, 1298 db_offt, &bnxt_re_cqn_handler, 1299 &bnxt_re_srqn_handler); 1300 if (rc) { 1301 ibdev_err(&rdev->ibdev, 1302 "Failed to enable NQ with rc = 0x%x", rc); 1303 goto fail; 1304 } 1305 num_vec_enabled++; 1306 } 1307 return 0; 1308 fail: 1309 for (i = num_vec_enabled; i >= 0; i--) 1310 bnxt_qplib_disable_nq(&rdev->nq[i]); 1311 return rc; 1312 } 1313 1314 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev) 1315 { 1316 u8 type; 1317 int i; 1318 1319 for (i = 0; i < rdev->num_msix - 1; i++) { 1320 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1321 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 1322 bnxt_qplib_free_nq(&rdev->nq[i]); 1323 rdev->nq[i].res = NULL; 1324 } 1325 } 1326 1327 static void bnxt_re_free_res(struct bnxt_re_dev *rdev) 1328 { 1329 bnxt_re_free_nq_res(rdev); 1330 1331 if (rdev->qplib_res.dpi_tbl.max) { 1332 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1333 &rdev->dpi_privileged); 1334 } 1335 if (rdev->qplib_res.rcfw) { 1336 bnxt_qplib_free_res(&rdev->qplib_res); 1337 rdev->qplib_res.rcfw = NULL; 1338 } 1339 } 1340 1341 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev) 1342 { 1343 struct bnxt_re_ring_attr rattr = {}; 1344 int num_vec_created = 0; 1345 int rc, i; 1346 u8 type; 1347 1348 /* Configure and allocate resources for qplib */ 1349 rdev->qplib_res.rcfw = &rdev->rcfw; 1350 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 1351 if (rc) 1352 goto fail; 1353 1354 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev, 1355 rdev->netdev, &rdev->dev_attr); 1356 if (rc) 1357 goto fail; 1358 1359 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res, 1360 &rdev->dpi_privileged, 1361 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL); 1362 if (rc) 1363 goto dealloc_res; 1364 1365 for (i = 0; i < rdev->num_msix - 1; i++) { 1366 struct bnxt_qplib_nq *nq; 1367 1368 nq = &rdev->nq[i]; 1369 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT; 1370 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, &rdev->nq[i]); 1371 if (rc) { 1372 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x", 1373 i, rc); 1374 goto free_nq; 1375 } 1376 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1377 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1378 rattr.pages = nq->hwq.pbl[rdev->nq[i].hwq.level].pg_count; 1379 rattr.type = type; 1380 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1381 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1; 1382 rattr.lrid = rdev->en_dev->msix_entries[i + 1].ring_idx; 1383 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id); 1384 if (rc) { 1385 ibdev_err(&rdev->ibdev, 1386 "Failed to allocate NQ fw id with rc = 0x%x", 1387 rc); 1388 bnxt_qplib_free_nq(&rdev->nq[i]); 1389 goto free_nq; 1390 } 1391 num_vec_created++; 1392 } 1393 return 0; 1394 free_nq: 1395 for (i = num_vec_created - 1; i >= 0; i--) { 1396 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1397 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 1398 bnxt_qplib_free_nq(&rdev->nq[i]); 1399 } 1400 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1401 &rdev->dpi_privileged); 1402 dealloc_res: 1403 bnxt_qplib_free_res(&rdev->qplib_res); 1404 1405 fail: 1406 rdev->qplib_res.rcfw = NULL; 1407 return rc; 1408 } 1409 1410 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp, 1411 u8 port_num, enum ib_event_type event) 1412 { 1413 struct ib_event ib_event; 1414 1415 ib_event.device = ibdev; 1416 if (qp) { 1417 ib_event.element.qp = qp; 1418 ib_event.event = event; 1419 if (qp->event_handler) 1420 qp->event_handler(&ib_event, qp->qp_context); 1421 1422 } else { 1423 ib_event.element.port_num = port_num; 1424 ib_event.event = event; 1425 ib_dispatch_event(&ib_event); 1426 } 1427 } 1428 1429 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev, 1430 struct bnxt_re_qp *qp) 1431 { 1432 return (qp->ib_qp.qp_type == IB_QPT_GSI) || 1433 (qp == rdev->gsi_ctx.gsi_sqp); 1434 } 1435 1436 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev) 1437 { 1438 int mask = IB_QP_STATE; 1439 struct ib_qp_attr qp_attr; 1440 struct bnxt_re_qp *qp; 1441 1442 qp_attr.qp_state = IB_QPS_ERR; 1443 mutex_lock(&rdev->qp_lock); 1444 list_for_each_entry(qp, &rdev->qp_list, list) { 1445 /* Modify the state of all QPs except QP1/Shadow QP */ 1446 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) { 1447 if (qp->qplib_qp.state != 1448 CMDQ_MODIFY_QP_NEW_STATE_RESET && 1449 qp->qplib_qp.state != 1450 CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1451 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp, 1452 1, IB_EVENT_QP_FATAL); 1453 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask, 1454 NULL); 1455 } 1456 } 1457 } 1458 mutex_unlock(&rdev->qp_lock); 1459 } 1460 1461 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev) 1462 { 1463 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 1464 struct bnxt_qplib_gid gid; 1465 u16 gid_idx, index; 1466 int rc = 0; 1467 1468 if (!ib_device_try_get(&rdev->ibdev)) 1469 return 0; 1470 1471 for (index = 0; index < sgid_tbl->active; index++) { 1472 gid_idx = sgid_tbl->hw_id[index]; 1473 1474 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero, 1475 sizeof(bnxt_qplib_gid_zero))) 1476 continue; 1477 /* need to modify the VLAN enable setting of non VLAN GID only 1478 * as setting is done for VLAN GID while adding GID 1479 */ 1480 if (sgid_tbl->vlan[index]) 1481 continue; 1482 1483 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid)); 1484 1485 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx, 1486 rdev->qplib_res.netdev->dev_addr); 1487 } 1488 1489 ib_device_put(&rdev->ibdev); 1490 return rc; 1491 } 1492 1493 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev) 1494 { 1495 u32 prio_map = 0, tmp_map = 0; 1496 struct net_device *netdev; 1497 struct dcb_app app = {}; 1498 1499 netdev = rdev->netdev; 1500 1501 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE; 1502 app.protocol = ETH_P_IBOE; 1503 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1504 prio_map = tmp_map; 1505 1506 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM; 1507 app.protocol = ROCE_V2_UDP_DPORT; 1508 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1509 prio_map |= tmp_map; 1510 1511 return prio_map; 1512 } 1513 1514 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev) 1515 { 1516 u8 prio_map = 0; 1517 1518 /* Get priority for roce */ 1519 prio_map = bnxt_re_get_priority_mask(rdev); 1520 1521 if (prio_map == rdev->cur_prio_map) 1522 return 0; 1523 rdev->cur_prio_map = prio_map; 1524 /* Actual priorities are not programmed as they are already 1525 * done by L2 driver; just enable or disable priority vlan tagging 1526 */ 1527 if ((prio_map == 0 && rdev->qplib_res.prio) || 1528 (prio_map != 0 && !rdev->qplib_res.prio)) { 1529 rdev->qplib_res.prio = prio_map; 1530 bnxt_re_update_gid(rdev); 1531 } 1532 1533 return 0; 1534 } 1535 1536 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev) 1537 { 1538 struct bnxt_en_dev *en_dev = rdev->en_dev; 1539 struct hwrm_ver_get_output resp = {}; 1540 struct hwrm_ver_get_input req = {}; 1541 struct bnxt_qplib_chip_ctx *cctx; 1542 struct bnxt_fw_msg fw_msg = {}; 1543 int rc; 1544 1545 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET); 1546 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 1547 req.hwrm_intf_min = HWRM_VERSION_MINOR; 1548 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 1549 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 1550 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 1551 rc = bnxt_send_msg(en_dev, &fw_msg); 1552 if (rc) { 1553 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x", 1554 rc); 1555 return; 1556 } 1557 1558 cctx = rdev->chip_ctx; 1559 cctx->hwrm_intf_ver = 1560 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 | 1561 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 | 1562 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 | 1563 le16_to_cpu(resp.hwrm_intf_patch); 1564 1565 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout); 1566 1567 if (!cctx->hwrm_cmd_max_timeout) 1568 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT; 1569 } 1570 1571 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev) 1572 { 1573 int rc; 1574 u32 event; 1575 1576 /* Register ib dev */ 1577 rc = bnxt_re_register_ib(rdev); 1578 if (rc) { 1579 pr_err("Failed to register with IB: %#x\n", rc); 1580 return rc; 1581 } 1582 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully"); 1583 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags); 1584 1585 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ? 1586 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 1587 1588 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event); 1589 1590 return rc; 1591 } 1592 1593 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type) 1594 { 1595 u8 type; 1596 int rc; 1597 1598 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags)) 1599 cancel_delayed_work_sync(&rdev->worker); 1600 1601 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, 1602 &rdev->flags)) 1603 bnxt_re_cleanup_res(rdev); 1604 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags)) 1605 bnxt_re_free_res(rdev); 1606 1607 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) { 1608 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw); 1609 if (rc) 1610 ibdev_warn(&rdev->ibdev, 1611 "Failed to deinitialize RCFW: %#x", rc); 1612 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1613 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1614 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1615 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1616 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1617 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1618 } 1619 1620 rdev->num_msix = 0; 1621 1622 if (rdev->pacing.dbr_pacing) 1623 bnxt_re_deinitialize_dbr_pacing(rdev); 1624 1625 bnxt_re_destroy_chip_ctx(rdev); 1626 if (op_type == BNXT_RE_COMPLETE_REMOVE) { 1627 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags)) 1628 bnxt_unregister_dev(rdev->en_dev); 1629 } 1630 } 1631 1632 /* worker thread for polling periodic events. Now used for QoS programming*/ 1633 static void bnxt_re_worker(struct work_struct *work) 1634 { 1635 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 1636 worker.work); 1637 1638 bnxt_re_setup_qos(rdev); 1639 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1640 } 1641 1642 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 op_type) 1643 { 1644 struct bnxt_re_ring_attr rattr = {}; 1645 struct bnxt_qplib_creq_ctx *creq; 1646 u32 db_offt; 1647 int vid; 1648 u8 type; 1649 int rc; 1650 1651 if (op_type == BNXT_RE_COMPLETE_INIT) { 1652 /* Registered a new RoCE device instance to netdev */ 1653 rc = bnxt_re_register_netdev(rdev); 1654 if (rc) { 1655 ibdev_err(&rdev->ibdev, 1656 "Failed to register with netedev: %#x\n", rc); 1657 return -EINVAL; 1658 } 1659 } 1660 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1661 1662 rc = bnxt_re_setup_chip_ctx(rdev); 1663 if (rc) { 1664 bnxt_unregister_dev(rdev->en_dev); 1665 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1666 ibdev_err(&rdev->ibdev, "Failed to get chip context\n"); 1667 return -EINVAL; 1668 } 1669 1670 /* Check whether VF or PF */ 1671 bnxt_re_get_sriov_func_type(rdev); 1672 1673 if (!rdev->en_dev->ulp_tbl->msix_requested) { 1674 ibdev_err(&rdev->ibdev, 1675 "Failed to get MSI-X vectors: %#x\n", rc); 1676 rc = -EINVAL; 1677 goto fail; 1678 } 1679 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n", 1680 rdev->en_dev->ulp_tbl->msix_requested); 1681 rdev->num_msix = rdev->en_dev->ulp_tbl->msix_requested; 1682 1683 bnxt_re_query_hwrm_intf_version(rdev); 1684 1685 /* Establish RCFW Communication Channel to initialize the context 1686 * memory for the function and all child VFs 1687 */ 1688 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw, 1689 &rdev->qplib_ctx, 1690 BNXT_RE_MAX_QPC_COUNT); 1691 if (rc) { 1692 ibdev_err(&rdev->ibdev, 1693 "Failed to allocate RCFW Channel: %#x\n", rc); 1694 goto fail; 1695 } 1696 1697 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1698 creq = &rdev->rcfw.creq; 1699 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1700 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count; 1701 rattr.type = type; 1702 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1703 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1; 1704 rattr.lrid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx; 1705 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id); 1706 if (rc) { 1707 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc); 1708 goto free_rcfw; 1709 } 1710 db_offt = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].db_offset; 1711 vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector; 1712 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw, 1713 vid, db_offt, 1714 &bnxt_re_aeq_handler); 1715 if (rc) { 1716 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n", 1717 rc); 1718 goto free_ring; 1719 } 1720 1721 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) { 1722 rc = bnxt_re_initialize_dbr_pacing(rdev); 1723 if (!rc) { 1724 rdev->pacing.dbr_pacing = true; 1725 } else { 1726 ibdev_err(&rdev->ibdev, 1727 "DBR pacing disabled with error : %d\n", rc); 1728 rdev->pacing.dbr_pacing = false; 1729 } 1730 } 1731 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 1732 if (rc) 1733 goto disable_rcfw; 1734 1735 bnxt_re_set_resource_limits(rdev); 1736 1737 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0, 1738 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)); 1739 if (rc) { 1740 ibdev_err(&rdev->ibdev, 1741 "Failed to allocate QPLIB context: %#x\n", rc); 1742 goto disable_rcfw; 1743 } 1744 rc = bnxt_re_net_stats_ctx_alloc(rdev, 1745 rdev->qplib_ctx.stats.dma_map, 1746 &rdev->qplib_ctx.stats.fw_id); 1747 if (rc) { 1748 ibdev_err(&rdev->ibdev, 1749 "Failed to allocate stats context: %#x\n", rc); 1750 goto free_ctx; 1751 } 1752 1753 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx, 1754 rdev->is_virtfn); 1755 if (rc) { 1756 ibdev_err(&rdev->ibdev, 1757 "Failed to initialize RCFW: %#x\n", rc); 1758 goto free_sctx; 1759 } 1760 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags); 1761 1762 /* Resources based on the 'new' device caps */ 1763 rc = bnxt_re_alloc_res(rdev); 1764 if (rc) { 1765 ibdev_err(&rdev->ibdev, 1766 "Failed to allocate resources: %#x\n", rc); 1767 goto fail; 1768 } 1769 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags); 1770 rc = bnxt_re_init_res(rdev); 1771 if (rc) { 1772 ibdev_err(&rdev->ibdev, 1773 "Failed to initialize resources: %#x\n", rc); 1774 goto fail; 1775 } 1776 1777 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags); 1778 1779 if (!rdev->is_virtfn) { 1780 rc = bnxt_re_setup_qos(rdev); 1781 if (rc) 1782 ibdev_info(&rdev->ibdev, 1783 "RoCE priority not yet configured\n"); 1784 1785 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker); 1786 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags); 1787 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1788 /* 1789 * Use the total VF count since the actual VF count may not be 1790 * available at this point. 1791 */ 1792 bnxt_re_vf_res_config(rdev); 1793 } 1794 hash_init(rdev->cq_hash); 1795 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) 1796 hash_init(rdev->srq_hash); 1797 1798 return 0; 1799 free_sctx: 1800 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1801 free_ctx: 1802 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1803 disable_rcfw: 1804 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1805 free_ring: 1806 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1807 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1808 free_rcfw: 1809 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1810 fail: 1811 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 1812 1813 return rc; 1814 } 1815 1816 static void bnxt_re_update_en_info_rdev(struct bnxt_re_dev *rdev, 1817 struct bnxt_re_en_dev_info *en_info, 1818 struct auxiliary_device *adev) 1819 { 1820 /* Before updating the rdev pointer in bnxt_re_en_dev_info structure, 1821 * take the rtnl lock to avoid accessing invalid rdev pointer from 1822 * L2 ULP callbacks. This is applicable in all the places where rdev 1823 * pointer is updated in bnxt_re_en_dev_info. 1824 */ 1825 rtnl_lock(); 1826 en_info->rdev = rdev; 1827 rtnl_unlock(); 1828 } 1829 1830 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 op_type) 1831 { 1832 struct bnxt_aux_priv *aux_priv = 1833 container_of(adev, struct bnxt_aux_priv, aux_dev); 1834 struct bnxt_re_en_dev_info *en_info; 1835 struct bnxt_en_dev *en_dev; 1836 struct bnxt_re_dev *rdev; 1837 int rc; 1838 1839 en_info = auxiliary_get_drvdata(adev); 1840 en_dev = en_info->en_dev; 1841 1842 1843 rdev = bnxt_re_dev_add(adev, en_dev); 1844 if (!rdev || !rdev_to_dev(rdev)) { 1845 rc = -ENOMEM; 1846 goto exit; 1847 } 1848 1849 bnxt_re_update_en_info_rdev(rdev, en_info, adev); 1850 1851 rc = bnxt_re_dev_init(rdev, op_type); 1852 if (rc) 1853 goto re_dev_dealloc; 1854 1855 rc = bnxt_re_ib_init(rdev); 1856 if (rc) { 1857 pr_err("Failed to register with IB: %s", 1858 aux_priv->aux_dev.name); 1859 goto re_dev_uninit; 1860 } 1861 1862 rdev->nb.notifier_call = bnxt_re_netdev_event; 1863 rc = register_netdevice_notifier(&rdev->nb); 1864 if (rc) { 1865 rdev->nb.notifier_call = NULL; 1866 pr_err("%s: Cannot register to netdevice_notifier", 1867 ROCE_DRV_MODULE_NAME); 1868 goto re_dev_unreg; 1869 } 1870 bnxt_re_setup_cc(rdev, true); 1871 1872 return 0; 1873 1874 re_dev_unreg: 1875 ib_unregister_device(&rdev->ibdev); 1876 re_dev_uninit: 1877 bnxt_re_update_en_info_rdev(NULL, en_info, adev); 1878 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 1879 re_dev_dealloc: 1880 ib_dealloc_device(&rdev->ibdev); 1881 exit: 1882 return rc; 1883 } 1884 1885 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable) 1886 { 1887 struct bnxt_qplib_cc_param cc_param = {}; 1888 1889 /* Do not enable congestion control on VFs */ 1890 if (rdev->is_virtfn) 1891 return; 1892 1893 /* Currently enabling only for GenP5 adapters */ 1894 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 1895 return; 1896 1897 if (enable) { 1898 cc_param.enable = 1; 1899 cc_param.cc_mode = CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE; 1900 } 1901 1902 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE | 1903 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC | 1904 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN); 1905 1906 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param)) 1907 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable); 1908 } 1909 1910 /* 1911 * "Notifier chain callback can be invoked for the same chain from 1912 * different CPUs at the same time". 1913 * 1914 * For cases when the netdev is already present, our call to the 1915 * register_netdevice_notifier() will actually get the rtnl_lock() 1916 * before sending NETDEV_REGISTER and (if up) NETDEV_UP 1917 * events. 1918 * 1919 * But for cases when the netdev is not already present, the notifier 1920 * chain is subjected to be invoked from different CPUs simultaneously. 1921 * 1922 * This is protected by the netdev_mutex. 1923 */ 1924 static int bnxt_re_netdev_event(struct notifier_block *notifier, 1925 unsigned long event, void *ptr) 1926 { 1927 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr); 1928 struct bnxt_re_dev *rdev; 1929 1930 real_dev = rdma_vlan_dev_real_dev(netdev); 1931 if (!real_dev) 1932 real_dev = netdev; 1933 1934 if (real_dev != netdev) 1935 goto exit; 1936 1937 rdev = bnxt_re_from_netdev(real_dev); 1938 if (!rdev) 1939 return NOTIFY_DONE; 1940 1941 1942 switch (event) { 1943 case NETDEV_UP: 1944 case NETDEV_DOWN: 1945 case NETDEV_CHANGE: 1946 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, 1947 netif_carrier_ok(real_dev) ? 1948 IB_EVENT_PORT_ACTIVE : 1949 IB_EVENT_PORT_ERR); 1950 break; 1951 default: 1952 break; 1953 } 1954 ib_device_put(&rdev->ibdev); 1955 exit: 1956 return NOTIFY_DONE; 1957 } 1958 1959 #define BNXT_ADEV_NAME "bnxt_en" 1960 1961 static void bnxt_re_remove_device(struct bnxt_re_dev *rdev, u8 op_type, 1962 struct auxiliary_device *aux_dev) 1963 { 1964 if (rdev->nb.notifier_call) { 1965 unregister_netdevice_notifier(&rdev->nb); 1966 rdev->nb.notifier_call = NULL; 1967 } else { 1968 /* If notifier is null, we should have already done a 1969 * clean up before coming here. 1970 */ 1971 return; 1972 } 1973 bnxt_re_setup_cc(rdev, false); 1974 ib_unregister_device(&rdev->ibdev); 1975 bnxt_re_dev_uninit(rdev, op_type); 1976 ib_dealloc_device(&rdev->ibdev); 1977 } 1978 1979 static void bnxt_re_remove(struct auxiliary_device *adev) 1980 { 1981 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 1982 struct bnxt_re_dev *rdev; 1983 1984 mutex_lock(&bnxt_re_mutex); 1985 rdev = en_info->rdev; 1986 1987 if (rdev) 1988 bnxt_re_remove_device(rdev, BNXT_RE_COMPLETE_REMOVE, adev); 1989 kfree(en_info); 1990 mutex_unlock(&bnxt_re_mutex); 1991 } 1992 1993 static int bnxt_re_probe(struct auxiliary_device *adev, 1994 const struct auxiliary_device_id *id) 1995 { 1996 struct bnxt_aux_priv *aux_priv = 1997 container_of(adev, struct bnxt_aux_priv, aux_dev); 1998 struct bnxt_re_en_dev_info *en_info; 1999 struct bnxt_en_dev *en_dev; 2000 int rc; 2001 2002 en_dev = aux_priv->edev; 2003 2004 mutex_lock(&bnxt_re_mutex); 2005 en_info = kzalloc(sizeof(*en_info), GFP_KERNEL); 2006 if (!en_info) { 2007 mutex_unlock(&bnxt_re_mutex); 2008 return -ENOMEM; 2009 } 2010 en_info->en_dev = en_dev; 2011 2012 auxiliary_set_drvdata(adev, en_info); 2013 2014 rc = bnxt_re_add_device(adev, BNXT_RE_COMPLETE_INIT); 2015 if (rc) 2016 goto err; 2017 mutex_unlock(&bnxt_re_mutex); 2018 return 0; 2019 2020 err: 2021 mutex_unlock(&bnxt_re_mutex); 2022 kfree(en_info); 2023 2024 return rc; 2025 } 2026 2027 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state) 2028 { 2029 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 2030 struct bnxt_en_dev *en_dev; 2031 struct bnxt_re_dev *rdev; 2032 2033 rdev = en_info->rdev; 2034 en_dev = en_info->en_dev; 2035 mutex_lock(&bnxt_re_mutex); 2036 /* L2 driver may invoke this callback during device error/crash or device 2037 * reset. Current RoCE driver doesn't recover the device in case of 2038 * error. Handle the error by dispatching fatal events to all qps 2039 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 2040 * L2 driver want to modify the MSIx table. 2041 */ 2042 2043 ibdev_info(&rdev->ibdev, "Handle device suspend call"); 2044 /* Check the current device state from bnxt_en_dev and move the 2045 * device to detached state if FW_FATAL_COND is set. 2046 * This prevents more commands to HW during clean-up, 2047 * in case the device is already in error. 2048 */ 2049 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) 2050 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 2051 2052 bnxt_re_dev_stop(rdev); 2053 bnxt_re_stop_irq(adev); 2054 /* Move the device states to detached and avoid sending any more 2055 * commands to HW 2056 */ 2057 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags); 2058 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 2059 wake_up_all(&rdev->rcfw.cmdq.waitq); 2060 2061 if (rdev->pacing.dbr_pacing) 2062 bnxt_re_set_pacing_dev_state(rdev); 2063 2064 ibdev_info(&rdev->ibdev, "%s: L2 driver notified to stop en_state 0x%lx", 2065 __func__, en_dev->en_state); 2066 bnxt_re_remove_device(rdev, BNXT_RE_PRE_RECOVERY_REMOVE, adev); 2067 mutex_unlock(&bnxt_re_mutex); 2068 2069 return 0; 2070 } 2071 2072 static int bnxt_re_resume(struct auxiliary_device *adev) 2073 { 2074 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 2075 struct bnxt_re_dev *rdev; 2076 2077 mutex_lock(&bnxt_re_mutex); 2078 /* L2 driver may invoke this callback during device recovery, resume. 2079 * reset. Current RoCE driver doesn't recover the device in case of 2080 * error. Handle the error by dispatching fatal events to all qps 2081 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 2082 * L2 driver want to modify the MSIx table. 2083 */ 2084 2085 bnxt_re_add_device(adev, BNXT_RE_POST_RECOVERY_INIT); 2086 rdev = en_info->rdev; 2087 ibdev_info(&rdev->ibdev, "Device resume completed"); 2088 mutex_unlock(&bnxt_re_mutex); 2089 2090 return 0; 2091 } 2092 2093 static const struct auxiliary_device_id bnxt_re_id_table[] = { 2094 { .name = BNXT_ADEV_NAME ".rdma", }, 2095 {}, 2096 }; 2097 2098 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table); 2099 2100 static struct auxiliary_driver bnxt_re_driver = { 2101 .name = "rdma", 2102 .probe = bnxt_re_probe, 2103 .remove = bnxt_re_remove, 2104 .shutdown = bnxt_re_shutdown, 2105 .suspend = bnxt_re_suspend, 2106 .resume = bnxt_re_resume, 2107 .id_table = bnxt_re_id_table, 2108 }; 2109 2110 static int __init bnxt_re_mod_init(void) 2111 { 2112 int rc; 2113 2114 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version); 2115 rc = auxiliary_driver_register(&bnxt_re_driver); 2116 if (rc) { 2117 pr_err("%s: Failed to register auxiliary driver\n", 2118 ROCE_DRV_MODULE_NAME); 2119 return rc; 2120 } 2121 return 0; 2122 } 2123 2124 static void __exit bnxt_re_mod_exit(void) 2125 { 2126 auxiliary_driver_unregister(&bnxt_re_driver); 2127 } 2128 2129 module_init(bnxt_re_mod_init); 2130 module_exit(bnxt_re_mod_exit); 2131