1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Main component of the bnxt_re driver 37 */ 38 39 #include <linux/module.h> 40 #include <linux/netdevice.h> 41 #include <linux/ethtool.h> 42 #include <linux/mutex.h> 43 #include <linux/list.h> 44 #include <linux/rculist.h> 45 #include <linux/spinlock.h> 46 #include <linux/pci.h> 47 #include <net/dcbnl.h> 48 #include <net/ipv6.h> 49 #include <net/addrconf.h> 50 #include <linux/if_ether.h> 51 #include <linux/auxiliary_bus.h> 52 53 #include <rdma/ib_verbs.h> 54 #include <rdma/ib_user_verbs.h> 55 #include <rdma/ib_umem.h> 56 #include <rdma/ib_addr.h> 57 #include <linux/hashtable.h> 58 59 #include "bnxt_ulp.h" 60 #include "roce_hsi.h" 61 #include "qplib_res.h" 62 #include "qplib_sp.h" 63 #include "qplib_fp.h" 64 #include "qplib_rcfw.h" 65 #include "bnxt_re.h" 66 #include "ib_verbs.h" 67 #include <rdma/bnxt_re-abi.h> 68 #include "bnxt.h" 69 #include "hw_counters.h" 70 71 static char version[] = 72 BNXT_RE_DESC "\n"; 73 74 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>"); 75 MODULE_DESCRIPTION(BNXT_RE_DESC); 76 MODULE_LICENSE("Dual BSD/GPL"); 77 78 /* globals */ 79 static DEFINE_MUTEX(bnxt_re_mutex); 80 81 static void bnxt_re_stop_irq(void *handle); 82 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev); 83 static int bnxt_re_netdev_event(struct notifier_block *notifier, 84 unsigned long event, void *ptr); 85 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev); 86 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type); 87 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev); 88 89 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 90 u32 *offset); 91 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable); 92 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev) 93 { 94 struct bnxt_qplib_chip_ctx *cctx; 95 struct bnxt_en_dev *en_dev; 96 struct bnxt_qplib_res *res; 97 u32 l2db_len = 0; 98 u32 offset = 0; 99 u32 barlen; 100 int rc; 101 102 res = &rdev->qplib_res; 103 en_dev = rdev->en_dev; 104 cctx = rdev->chip_ctx; 105 106 /* Issue qcfg */ 107 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset); 108 if (rc) 109 dev_info(rdev_to_dev(rdev), 110 "Couldn't get DB bar size, Low latency framework is disabled\n"); 111 /* set register offsets for both UC and WC */ 112 if (bnxt_qplib_is_chip_gen_p7(cctx)) { 113 res->dpi_tbl.ucreg.offset = offset; 114 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 115 } else { 116 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET : 117 BNXT_QPLIB_DBR_PF_DB_OFFSET; 118 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset; 119 } 120 121 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size 122 * is equal to the DB-Bar actual size. This indicates that L2 123 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping 124 * in such cases and DB-push will be disabled. 125 */ 126 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION); 127 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) { 128 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 129 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n"); 130 } 131 } 132 133 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev) 134 { 135 struct bnxt_qplib_chip_ctx *cctx; 136 137 cctx = rdev->chip_ctx; 138 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? 139 BNXT_QPLIB_WQE_MODE_VARIABLE : BNXT_QPLIB_WQE_MODE_STATIC; 140 if (bnxt_re_hwrm_qcaps(rdev)) 141 dev_err(rdev_to_dev(rdev), 142 "Failed to query hwrm qcaps\n"); 143 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) { 144 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT; 145 cctx->modes.toggle_bits |= BNXT_QPLIB_SRQ_TOGGLE_BIT; 146 } 147 } 148 149 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev) 150 { 151 struct bnxt_qplib_chip_ctx *chip_ctx; 152 153 if (!rdev->chip_ctx) 154 return; 155 chip_ctx = rdev->chip_ctx; 156 rdev->chip_ctx = NULL; 157 rdev->rcfw.res = NULL; 158 rdev->qplib_res.cctx = NULL; 159 rdev->qplib_res.pdev = NULL; 160 rdev->qplib_res.netdev = NULL; 161 kfree(chip_ctx); 162 } 163 164 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev) 165 { 166 struct bnxt_qplib_chip_ctx *chip_ctx; 167 struct bnxt_en_dev *en_dev; 168 int rc; 169 170 en_dev = rdev->en_dev; 171 172 rdev->qplib_res.pdev = en_dev->pdev; 173 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL); 174 if (!chip_ctx) 175 return -ENOMEM; 176 chip_ctx->chip_num = en_dev->chip_num; 177 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size; 178 179 rdev->chip_ctx = chip_ctx; 180 /* rest members to follow eventually */ 181 182 rdev->qplib_res.cctx = rdev->chip_ctx; 183 rdev->rcfw.res = &rdev->qplib_res; 184 rdev->qplib_res.dattr = &rdev->dev_attr; 185 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev); 186 187 bnxt_re_set_drv_mode(rdev); 188 189 bnxt_re_set_db_offset(rdev); 190 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res); 191 if (rc) 192 return rc; 193 194 if (bnxt_qplib_determine_atomics(en_dev->pdev)) 195 ibdev_info(&rdev->ibdev, 196 "platform doesn't support global atomics."); 197 return 0; 198 } 199 200 /* SR-IOV helper functions */ 201 202 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev) 203 { 204 if (BNXT_EN_VF(rdev->en_dev)) 205 rdev->is_virtfn = 1; 206 } 207 208 /* Set the maximum number of each resource that the driver actually wants 209 * to allocate. This may be up to the maximum number the firmware has 210 * reserved for the function. The driver may choose to allocate fewer 211 * resources than the firmware maximum. 212 */ 213 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev) 214 { 215 struct bnxt_qplib_dev_attr *attr; 216 struct bnxt_qplib_ctx *ctx; 217 int i; 218 219 attr = &rdev->dev_attr; 220 ctx = &rdev->qplib_ctx; 221 222 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT, 223 attr->max_qp); 224 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K; 225 /* Use max_mr from fw since max_mrw does not get set */ 226 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr); 227 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT, 228 attr->max_srq); 229 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq); 230 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 231 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++) 232 rdev->qplib_ctx.tqm_ctx.qcount[i] = 233 rdev->dev_attr.tqm_alloc_reqs[i]; 234 } 235 236 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf) 237 { 238 struct bnxt_qplib_vf_res *vf_res; 239 u32 mrws = 0; 240 u32 vf_pct; 241 u32 nvfs; 242 243 vf_res = &qplib_ctx->vf_res; 244 /* 245 * Reserve a set of resources for the PF. Divide the remaining 246 * resources among the VFs 247 */ 248 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF; 249 nvfs = num_vf; 250 num_vf = 100 * num_vf; 251 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf; 252 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf; 253 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf; 254 /* 255 * The driver allows many more MRs than other resources. If the 256 * firmware does also, then reserve a fixed amount for the PF and 257 * divide the rest among VFs. VFs may use many MRs for NFS 258 * mounts, ISER, NVME applications, etc. If the firmware severely 259 * restricts the number of MRs, then let PF have half and divide 260 * the rest among VFs, as for the other resource types. 261 */ 262 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) { 263 mrws = qplib_ctx->mrw_count * vf_pct; 264 nvfs = num_vf; 265 } else { 266 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF; 267 } 268 vf_res->max_mrw_per_vf = (mrws / nvfs); 269 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF; 270 } 271 272 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev) 273 { 274 u32 num_vfs; 275 276 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res)); 277 bnxt_re_limit_pf_res(rdev); 278 279 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 280 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs; 281 if (num_vfs) 282 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs); 283 } 284 285 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev) 286 { 287 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev); 288 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 289 bnxt_re_set_resource_limits(rdev); 290 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw, 291 &rdev->qplib_ctx); 292 } 293 } 294 295 static void bnxt_re_shutdown(struct auxiliary_device *adev) 296 { 297 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 298 struct bnxt_re_dev *rdev; 299 300 if (!en_info) 301 return; 302 303 rdev = en_info->rdev; 304 ib_unregister_device(&rdev->ibdev); 305 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 306 } 307 308 static void bnxt_re_stop_irq(void *handle) 309 { 310 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle); 311 struct bnxt_qplib_rcfw *rcfw; 312 struct bnxt_re_dev *rdev; 313 struct bnxt_qplib_nq *nq; 314 int indx; 315 316 if (!en_info) 317 return; 318 319 rdev = en_info->rdev; 320 rcfw = &rdev->rcfw; 321 322 for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) { 323 nq = &rdev->nq[indx - 1]; 324 bnxt_qplib_nq_stop_irq(nq, false); 325 } 326 327 bnxt_qplib_rcfw_stop_irq(rcfw, false); 328 } 329 330 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent) 331 { 332 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle); 333 struct bnxt_msix_entry *msix_ent; 334 struct bnxt_qplib_rcfw *rcfw; 335 struct bnxt_re_dev *rdev; 336 struct bnxt_qplib_nq *nq; 337 int indx, rc; 338 339 if (!en_info) 340 return; 341 342 rdev = en_info->rdev; 343 msix_ent = rdev->en_dev->msix_entries; 344 rcfw = &rdev->rcfw; 345 if (!ent) { 346 /* Not setting the f/w timeout bit in rcfw. 347 * During the driver unload the first command 348 * to f/w will timeout and that will set the 349 * timeout bit. 350 */ 351 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n"); 352 return; 353 } 354 355 /* Vectors may change after restart, so update with new vectors 356 * in device sctructure. 357 */ 358 for (indx = 0; indx < rdev->num_msix; indx++) 359 rdev->en_dev->msix_entries[indx].vector = ent[indx].vector; 360 361 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector, 362 false); 363 if (rc) { 364 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n"); 365 return; 366 } 367 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) { 368 nq = &rdev->nq[indx - 1]; 369 rc = bnxt_qplib_nq_start_irq(nq, indx - 1, 370 msix_ent[indx].vector, false); 371 if (rc) { 372 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n", 373 indx - 1); 374 return; 375 } 376 } 377 } 378 379 static struct bnxt_ulp_ops bnxt_re_ulp_ops = { 380 .ulp_irq_stop = bnxt_re_stop_irq, 381 .ulp_irq_restart = bnxt_re_start_irq 382 }; 383 384 /* RoCE -> Net driver */ 385 386 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev) 387 { 388 struct bnxt_en_dev *en_dev; 389 390 en_dev = rdev->en_dev; 391 return bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev->adev); 392 } 393 394 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd) 395 { 396 hdr->req_type = cpu_to_le16(opcd); 397 hdr->cmpl_ring = cpu_to_le16(-1); 398 hdr->target_id = cpu_to_le16(-1); 399 } 400 401 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg, 402 int msg_len, void *resp, int resp_max_len, 403 int timeout) 404 { 405 fw_msg->msg = msg; 406 fw_msg->msg_len = msg_len; 407 fw_msg->resp = resp; 408 fw_msg->resp_max_len = resp_max_len; 409 fw_msg->timeout = timeout; 410 } 411 412 /* Query device config using common hwrm */ 413 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 414 u32 *offset) 415 { 416 struct bnxt_en_dev *en_dev = rdev->en_dev; 417 struct hwrm_func_qcfg_output resp = {0}; 418 struct hwrm_func_qcfg_input req = {0}; 419 struct bnxt_fw_msg fw_msg = {}; 420 int rc; 421 422 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG); 423 req.fid = cpu_to_le16(0xffff); 424 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 425 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 426 rc = bnxt_send_msg(en_dev, &fw_msg); 427 if (!rc) { 428 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024); 429 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024); 430 } 431 return rc; 432 } 433 434 /* Query function capabilities using common hwrm */ 435 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev) 436 { 437 struct bnxt_en_dev *en_dev = rdev->en_dev; 438 struct hwrm_func_qcaps_output resp = {}; 439 struct hwrm_func_qcaps_input req = {}; 440 struct bnxt_qplib_chip_ctx *cctx; 441 struct bnxt_fw_msg fw_msg = {}; 442 u32 flags_ext2; 443 int rc; 444 445 cctx = rdev->chip_ctx; 446 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS); 447 req.fid = cpu_to_le16(0xffff); 448 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 449 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 450 451 rc = bnxt_send_msg(en_dev, &fw_msg); 452 if (rc) 453 return rc; 454 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE; 455 456 flags_ext2 = le32_to_cpu(resp.flags_ext2); 457 cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED || 458 flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED; 459 return 0; 460 } 461 462 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev) 463 { 464 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 465 struct hwrm_func_dbr_pacing_qcfg_output resp = {}; 466 struct hwrm_func_dbr_pacing_qcfg_input req = {}; 467 struct bnxt_en_dev *en_dev = rdev->en_dev; 468 struct bnxt_qplib_chip_ctx *cctx; 469 struct bnxt_fw_msg fw_msg = {}; 470 int rc; 471 472 cctx = rdev->chip_ctx; 473 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG); 474 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 475 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 476 rc = bnxt_send_msg(en_dev, &fw_msg); 477 if (rc) 478 return rc; 479 480 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 481 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) == 482 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC) 483 cctx->dbr_stat_db_fifo = 484 le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 485 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK; 486 487 pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth); 488 if (!pacing_data->fifo_max_depth) 489 pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx); 490 pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask); 491 pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift; 492 493 return 0; 494 } 495 496 /* Update the pacing tunable parameters to the default values */ 497 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev) 498 { 499 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 500 501 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing; 502 pacing_data->pacing_th = rdev->pacing.pacing_algo_th; 503 pacing_data->alarm_th = 504 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 505 } 506 507 static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev) 508 { 509 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 510 u32 read_val, fifo_occup; 511 512 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off); 513 fifo_occup = pacing_data->fifo_max_depth - 514 ((read_val & pacing_data->fifo_room_mask) >> 515 pacing_data->fifo_room_shift); 516 return fifo_occup; 517 } 518 519 static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev) 520 { 521 u32 max_occup, fifo_occup; 522 523 fifo_occup = __get_fifo_occupancy(rdev); 524 max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1; 525 if (fifo_occup == max_occup) 526 return true; 527 528 return false; 529 } 530 531 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev) 532 { 533 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 534 u32 fifo_occup; 535 536 /* loop shouldn't run infintely as the occupancy usually goes 537 * below pacing algo threshold as soon as pacing kicks in. 538 */ 539 while (1) { 540 fifo_occup = __get_fifo_occupancy(rdev); 541 /* Fifo occupancy cannot be greater the MAX FIFO depth */ 542 if (fifo_occup > pacing_data->fifo_max_depth) 543 break; 544 545 if (fifo_occup < pacing_data->pacing_th) 546 break; 547 } 548 } 549 550 static void bnxt_re_db_fifo_check(struct work_struct *work) 551 { 552 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 553 dbq_fifo_check_work); 554 struct bnxt_qplib_db_pacing_data *pacing_data; 555 u32 pacing_save; 556 557 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 558 return; 559 pacing_data = rdev->qplib_res.pacing_data; 560 pacing_save = rdev->pacing.do_pacing_save; 561 __wait_for_fifo_occupancy_below_th(rdev); 562 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 563 if (pacing_save > rdev->pacing.dbr_def_do_pacing) { 564 /* Double the do_pacing value during the congestion */ 565 pacing_save = pacing_save << 1; 566 } else { 567 /* 568 * when a new congestion is detected increase the do_pacing 569 * by 8 times. And also increase the pacing_th by 4 times. The 570 * reason to increase pacing_th is to give more space for the 571 * queue to oscillate down without getting empty, but also more 572 * room for the queue to increase without causing another alarm. 573 */ 574 pacing_save = pacing_save << 3; 575 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4; 576 } 577 578 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING) 579 pacing_save = BNXT_RE_MAX_DBR_DO_PACING; 580 581 pacing_data->do_pacing = pacing_save; 582 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 583 pacing_data->alarm_th = 584 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 585 schedule_delayed_work(&rdev->dbq_pacing_work, 586 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 587 rdev->stats.pacing.alerts++; 588 mutex_unlock(&rdev->pacing.dbq_lock); 589 } 590 591 static void bnxt_re_pacing_timer_exp(struct work_struct *work) 592 { 593 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 594 dbq_pacing_work.work); 595 struct bnxt_qplib_db_pacing_data *pacing_data; 596 u32 fifo_occup; 597 598 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 599 return; 600 601 pacing_data = rdev->qplib_res.pacing_data; 602 fifo_occup = __get_fifo_occupancy(rdev); 603 604 if (fifo_occup > pacing_data->pacing_th) 605 goto restart_timer; 606 607 /* 608 * Instead of immediately going back to the default do_pacing 609 * reduce it by 1/8 times and restart the timer. 610 */ 611 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3); 612 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing); 613 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) { 614 bnxt_re_set_default_pacing_data(rdev); 615 rdev->stats.pacing.complete++; 616 goto dbq_unlock; 617 } 618 619 restart_timer: 620 schedule_delayed_work(&rdev->dbq_pacing_work, 621 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 622 rdev->stats.pacing.resched++; 623 dbq_unlock: 624 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 625 mutex_unlock(&rdev->pacing.dbq_lock); 626 } 627 628 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev) 629 { 630 struct bnxt_qplib_db_pacing_data *pacing_data; 631 632 if (!rdev->pacing.dbr_pacing) 633 return; 634 mutex_lock(&rdev->pacing.dbq_lock); 635 pacing_data = rdev->qplib_res.pacing_data; 636 637 /* 638 * Increase the alarm_th to max so that other user lib instances do not 639 * keep alerting the driver. 640 */ 641 pacing_data->alarm_th = pacing_data->fifo_max_depth; 642 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING; 643 cancel_work_sync(&rdev->dbq_fifo_check_work); 644 schedule_work(&rdev->dbq_fifo_check_work); 645 mutex_unlock(&rdev->pacing.dbq_lock); 646 } 647 648 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev) 649 { 650 /* Allocate a page for app use */ 651 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL); 652 if (!rdev->pacing.dbr_page) 653 return -ENOMEM; 654 655 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE); 656 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page; 657 658 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) { 659 free_page((u64)rdev->pacing.dbr_page); 660 rdev->pacing.dbr_page = NULL; 661 return -EIO; 662 } 663 664 /* MAP HW window 2 for reading db fifo depth */ 665 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK, 666 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 667 rdev->pacing.dbr_db_fifo_reg_off = 668 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) + 669 BNXT_RE_GRC_FIFO_REG_BASE; 670 rdev->pacing.dbr_bar_addr = 671 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off; 672 673 if (is_dbr_fifo_full(rdev)) { 674 free_page((u64)rdev->pacing.dbr_page); 675 rdev->pacing.dbr_page = NULL; 676 return -EIO; 677 } 678 679 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD; 680 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME; 681 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION; 682 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing; 683 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off; 684 bnxt_re_set_default_pacing_data(rdev); 685 /* Initialize worker for DBR Pacing */ 686 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check); 687 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp); 688 return 0; 689 } 690 691 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev) 692 { 693 cancel_work_sync(&rdev->dbq_fifo_check_work); 694 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 695 if (rdev->pacing.dbr_page) 696 free_page((u64)rdev->pacing.dbr_page); 697 698 rdev->pacing.dbr_page = NULL; 699 rdev->pacing.dbr_pacing = false; 700 } 701 702 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev, 703 u16 fw_ring_id, int type) 704 { 705 struct bnxt_en_dev *en_dev; 706 struct hwrm_ring_free_input req = {}; 707 struct hwrm_ring_free_output resp; 708 struct bnxt_fw_msg fw_msg = {}; 709 int rc = -EINVAL; 710 711 if (!rdev) 712 return rc; 713 714 en_dev = rdev->en_dev; 715 716 if (!en_dev) 717 return rc; 718 719 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 720 return 0; 721 722 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE); 723 req.ring_type = type; 724 req.ring_id = cpu_to_le16(fw_ring_id); 725 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 726 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 727 rc = bnxt_send_msg(en_dev, &fw_msg); 728 if (rc) 729 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x", 730 req.ring_id, rc); 731 return rc; 732 } 733 734 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev, 735 struct bnxt_re_ring_attr *ring_attr, 736 u16 *fw_ring_id) 737 { 738 struct bnxt_en_dev *en_dev = rdev->en_dev; 739 struct hwrm_ring_alloc_input req = {}; 740 struct hwrm_ring_alloc_output resp; 741 struct bnxt_fw_msg fw_msg = {}; 742 int rc = -EINVAL; 743 744 if (!en_dev) 745 return rc; 746 747 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC); 748 req.enables = 0; 749 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]); 750 if (ring_attr->pages > 1) { 751 /* Page size is in log2 units */ 752 req.page_size = BNXT_PAGE_SHIFT; 753 req.page_tbl_depth = 1; 754 } 755 req.fbo = 0; 756 /* Association of ring index with doorbell index and MSIX number */ 757 req.logical_id = cpu_to_le16(ring_attr->lrid); 758 req.length = cpu_to_le32(ring_attr->depth + 1); 759 req.ring_type = ring_attr->type; 760 req.int_mode = ring_attr->mode; 761 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 762 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 763 rc = bnxt_send_msg(en_dev, &fw_msg); 764 if (!rc) 765 *fw_ring_id = le16_to_cpu(resp.ring_id); 766 767 return rc; 768 } 769 770 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev, 771 u32 fw_stats_ctx_id) 772 { 773 struct bnxt_en_dev *en_dev = rdev->en_dev; 774 struct hwrm_stat_ctx_free_input req = {}; 775 struct hwrm_stat_ctx_free_output resp = {}; 776 struct bnxt_fw_msg fw_msg = {}; 777 int rc = -EINVAL; 778 779 if (!en_dev) 780 return rc; 781 782 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 783 return 0; 784 785 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE); 786 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id); 787 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 788 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 789 rc = bnxt_send_msg(en_dev, &fw_msg); 790 if (rc) 791 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x", 792 rc); 793 794 return rc; 795 } 796 797 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev, 798 dma_addr_t dma_map, 799 u32 *fw_stats_ctx_id) 800 { 801 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx; 802 struct hwrm_stat_ctx_alloc_output resp = {}; 803 struct hwrm_stat_ctx_alloc_input req = {}; 804 struct bnxt_en_dev *en_dev = rdev->en_dev; 805 struct bnxt_fw_msg fw_msg = {}; 806 int rc = -EINVAL; 807 808 *fw_stats_ctx_id = INVALID_STATS_CTX_ID; 809 810 if (!en_dev) 811 return rc; 812 813 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC); 814 req.update_period_ms = cpu_to_le32(1000); 815 req.stats_dma_addr = cpu_to_le64(dma_map); 816 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size); 817 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE; 818 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 819 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 820 rc = bnxt_send_msg(en_dev, &fw_msg); 821 if (!rc) 822 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id); 823 824 return rc; 825 } 826 827 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext) 828 { 829 } 830 831 /* Device */ 832 833 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev) 834 { 835 struct ib_device *ibdev = 836 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE); 837 if (!ibdev) 838 return NULL; 839 840 return container_of(ibdev, struct bnxt_re_dev, ibdev); 841 } 842 843 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 844 char *buf) 845 { 846 struct bnxt_re_dev *rdev = 847 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 848 849 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor); 850 } 851 static DEVICE_ATTR_RO(hw_rev); 852 853 static ssize_t hca_type_show(struct device *device, 854 struct device_attribute *attr, char *buf) 855 { 856 struct bnxt_re_dev *rdev = 857 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 858 859 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc); 860 } 861 static DEVICE_ATTR_RO(hca_type); 862 863 static struct attribute *bnxt_re_attributes[] = { 864 &dev_attr_hw_rev.attr, 865 &dev_attr_hca_type.attr, 866 NULL 867 }; 868 869 static const struct attribute_group bnxt_re_dev_attr_group = { 870 .attrs = bnxt_re_attributes, 871 }; 872 873 static const struct ib_device_ops bnxt_re_dev_ops = { 874 .owner = THIS_MODULE, 875 .driver_id = RDMA_DRIVER_BNXT_RE, 876 .uverbs_abi_ver = BNXT_RE_ABI_VERSION, 877 878 .add_gid = bnxt_re_add_gid, 879 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats, 880 .alloc_mr = bnxt_re_alloc_mr, 881 .alloc_pd = bnxt_re_alloc_pd, 882 .alloc_ucontext = bnxt_re_alloc_ucontext, 883 .create_ah = bnxt_re_create_ah, 884 .create_cq = bnxt_re_create_cq, 885 .create_qp = bnxt_re_create_qp, 886 .create_srq = bnxt_re_create_srq, 887 .create_user_ah = bnxt_re_create_ah, 888 .dealloc_pd = bnxt_re_dealloc_pd, 889 .dealloc_ucontext = bnxt_re_dealloc_ucontext, 890 .del_gid = bnxt_re_del_gid, 891 .dereg_mr = bnxt_re_dereg_mr, 892 .destroy_ah = bnxt_re_destroy_ah, 893 .destroy_cq = bnxt_re_destroy_cq, 894 .destroy_qp = bnxt_re_destroy_qp, 895 .destroy_srq = bnxt_re_destroy_srq, 896 .device_group = &bnxt_re_dev_attr_group, 897 .disassociate_ucontext = bnxt_re_disassociate_ucontext, 898 .get_dev_fw_str = bnxt_re_query_fw_str, 899 .get_dma_mr = bnxt_re_get_dma_mr, 900 .get_hw_stats = bnxt_re_ib_get_hw_stats, 901 .get_link_layer = bnxt_re_get_link_layer, 902 .get_port_immutable = bnxt_re_get_port_immutable, 903 .map_mr_sg = bnxt_re_map_mr_sg, 904 .mmap = bnxt_re_mmap, 905 .mmap_free = bnxt_re_mmap_free, 906 .modify_qp = bnxt_re_modify_qp, 907 .modify_srq = bnxt_re_modify_srq, 908 .poll_cq = bnxt_re_poll_cq, 909 .post_recv = bnxt_re_post_recv, 910 .post_send = bnxt_re_post_send, 911 .post_srq_recv = bnxt_re_post_srq_recv, 912 .query_ah = bnxt_re_query_ah, 913 .query_device = bnxt_re_query_device, 914 .query_pkey = bnxt_re_query_pkey, 915 .query_port = bnxt_re_query_port, 916 .query_qp = bnxt_re_query_qp, 917 .query_srq = bnxt_re_query_srq, 918 .reg_user_mr = bnxt_re_reg_user_mr, 919 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf, 920 .req_notify_cq = bnxt_re_req_notify_cq, 921 .resize_cq = bnxt_re_resize_cq, 922 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah), 923 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq), 924 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd), 925 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp), 926 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq), 927 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx), 928 }; 929 930 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev) 931 { 932 struct ib_device *ibdev = &rdev->ibdev; 933 int ret; 934 935 /* ib device init */ 936 ibdev->node_type = RDMA_NODE_IB_CA; 937 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA", 938 strlen(BNXT_RE_DESC) + 5); 939 ibdev->phys_port_cnt = 1; 940 941 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr); 942 943 ibdev->num_comp_vectors = rdev->num_msix - 1; 944 ibdev->dev.parent = &rdev->en_dev->pdev->dev; 945 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY; 946 947 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 948 ibdev->driver_def = bnxt_re_uapi_defs; 949 950 ib_set_device_ops(ibdev, &bnxt_re_dev_ops); 951 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1); 952 if (ret) 953 return ret; 954 955 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX); 956 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ); 957 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev); 958 } 959 960 static struct bnxt_re_dev *bnxt_re_dev_add(struct bnxt_aux_priv *aux_priv, 961 struct bnxt_en_dev *en_dev) 962 { 963 struct bnxt_re_dev *rdev; 964 965 /* Allocate bnxt_re_dev instance here */ 966 rdev = ib_alloc_device(bnxt_re_dev, ibdev); 967 if (!rdev) { 968 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!", 969 ROCE_DRV_MODULE_NAME); 970 return NULL; 971 } 972 /* Default values */ 973 rdev->nb.notifier_call = NULL; 974 rdev->netdev = en_dev->net; 975 rdev->en_dev = en_dev; 976 rdev->id = rdev->en_dev->pdev->devfn; 977 INIT_LIST_HEAD(&rdev->qp_list); 978 mutex_init(&rdev->qp_lock); 979 mutex_init(&rdev->pacing.dbq_lock); 980 atomic_set(&rdev->stats.res.qp_count, 0); 981 atomic_set(&rdev->stats.res.cq_count, 0); 982 atomic_set(&rdev->stats.res.srq_count, 0); 983 atomic_set(&rdev->stats.res.mr_count, 0); 984 atomic_set(&rdev->stats.res.mw_count, 0); 985 atomic_set(&rdev->stats.res.ah_count, 0); 986 atomic_set(&rdev->stats.res.pd_count, 0); 987 rdev->cosq[0] = 0xFFFF; 988 rdev->cosq[1] = 0xFFFF; 989 990 return rdev; 991 } 992 993 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event 994 *unaffi_async) 995 { 996 switch (unaffi_async->event) { 997 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 998 break; 999 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 1000 break; 1001 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 1002 break; 1003 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 1004 break; 1005 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 1006 break; 1007 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 1008 break; 1009 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 1010 break; 1011 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 1012 break; 1013 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 1014 break; 1015 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 1016 break; 1017 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 1018 break; 1019 default: 1020 return -EINVAL; 1021 } 1022 return 0; 1023 } 1024 1025 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event, 1026 struct bnxt_re_qp *qp) 1027 { 1028 struct bnxt_re_srq *srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq, 1029 qplib_srq); 1030 struct creq_qp_error_notification *err_event; 1031 struct ib_event event = {}; 1032 unsigned int flags; 1033 1034 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR && 1035 rdma_is_kernel_res(&qp->ib_qp.res)) { 1036 flags = bnxt_re_lock_cqs(qp); 1037 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1038 bnxt_re_unlock_cqs(qp, flags); 1039 } 1040 1041 event.device = &qp->rdev->ibdev; 1042 event.element.qp = &qp->ib_qp; 1043 event.event = IB_EVENT_QP_FATAL; 1044 1045 err_event = (struct creq_qp_error_notification *)qp_event; 1046 1047 switch (err_event->req_err_state_reason) { 1048 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR: 1049 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT: 1050 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT: 1051 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2: 1052 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3: 1053 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP: 1054 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND: 1055 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG: 1056 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE: 1057 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR: 1058 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR: 1059 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR: 1060 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR: 1061 event.event = IB_EVENT_QP_ACCESS_ERR; 1062 break; 1063 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1: 1064 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4: 1065 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH: 1066 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR: 1067 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR: 1068 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR: 1069 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR: 1070 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR: 1071 event.event = IB_EVENT_QP_REQ_ERR; 1072 break; 1073 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR: 1074 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR: 1075 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR: 1076 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR: 1077 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR: 1078 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR: 1079 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR: 1080 event.event = IB_EVENT_QP_FATAL; 1081 break; 1082 1083 default: 1084 break; 1085 } 1086 1087 switch (err_event->res_err_state_reason) { 1088 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX: 1089 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH: 1090 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT: 1091 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY: 1092 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR: 1093 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION: 1094 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR: 1095 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY: 1096 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR: 1097 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION: 1098 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR: 1099 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC: 1100 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND: 1101 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY: 1102 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR: 1103 event.event = IB_EVENT_QP_ACCESS_ERR; 1104 break; 1105 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE: 1106 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR: 1107 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE: 1108 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE: 1109 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR: 1110 event.event = IB_EVENT_QP_REQ_ERR; 1111 break; 1112 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW: 1113 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR: 1114 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR: 1115 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR: 1116 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR: 1117 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR: 1118 event.event = IB_EVENT_QP_FATAL; 1119 break; 1120 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR: 1121 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR: 1122 if (srq) 1123 event.event = IB_EVENT_SRQ_ERR; 1124 break; 1125 default: 1126 break; 1127 } 1128 1129 if (err_event->res_err_state_reason || err_event->req_err_state_reason) { 1130 ibdev_dbg(&qp->rdev->ibdev, 1131 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n", 1132 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user", 1133 qp->qplib_qp.id, 1134 err_event->sq_cons_idx, 1135 err_event->rq_cons_idx, 1136 err_event->req_slow_path_state, 1137 err_event->req_err_state_reason, 1138 err_event->res_slow_path_state, 1139 err_event->res_err_state_reason); 1140 } else { 1141 if (srq) 1142 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 1143 } 1144 1145 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) { 1146 (*srq->ib_srq.event_handler)(&event, 1147 srq->ib_srq.srq_context); 1148 } else if (event.device && qp->ib_qp.event_handler) { 1149 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context); 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq) 1156 { 1157 struct creq_cq_error_notification *cqerr; 1158 struct ib_event ibevent = {}; 1159 1160 cqerr = event; 1161 switch (cqerr->cq_err_reason) { 1162 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR: 1163 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR: 1164 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR: 1165 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR: 1166 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR: 1167 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR: 1168 ibevent.event = IB_EVENT_CQ_ERR; 1169 break; 1170 default: 1171 break; 1172 } 1173 1174 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) { 1175 ibevent.element.cq = &cq->ib_cq; 1176 ibevent.device = &cq->rdev->ibdev; 1177 1178 ibdev_dbg(&cq->rdev->ibdev, 1179 "%s err reason %d\n", __func__, cqerr->cq_err_reason); 1180 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context); 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async, 1187 void *obj) 1188 { 1189 struct bnxt_qplib_qp *lib_qp; 1190 struct bnxt_qplib_cq *lib_cq; 1191 struct bnxt_re_qp *qp; 1192 struct bnxt_re_cq *cq; 1193 int rc = 0; 1194 u8 event; 1195 1196 if (!obj) 1197 return rc; /* QP was already dead, still return success */ 1198 1199 event = affi_async->event; 1200 switch (event) { 1201 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 1202 lib_qp = obj; 1203 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp); 1204 rc = bnxt_re_handle_qp_async_event(affi_async, qp); 1205 break; 1206 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION: 1207 lib_cq = obj; 1208 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq); 1209 rc = bnxt_re_handle_cq_async_error(affi_async, cq); 1210 break; 1211 default: 1212 rc = -EINVAL; 1213 } 1214 return rc; 1215 } 1216 1217 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw, 1218 void *aeqe, void *obj) 1219 { 1220 struct creq_qp_event *affi_async; 1221 struct creq_func_event *unaffi_async; 1222 u8 type; 1223 int rc; 1224 1225 type = ((struct creq_base *)aeqe)->type; 1226 if (type == CREQ_BASE_TYPE_FUNC_EVENT) { 1227 unaffi_async = aeqe; 1228 rc = bnxt_re_handle_unaffi_async_event(unaffi_async); 1229 } else { 1230 affi_async = aeqe; 1231 rc = bnxt_re_handle_affi_async_event(affi_async, obj); 1232 } 1233 1234 return rc; 1235 } 1236 1237 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq, 1238 struct bnxt_qplib_srq *handle, u8 event) 1239 { 1240 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq, 1241 qplib_srq); 1242 struct ib_event ib_event; 1243 1244 ib_event.device = &srq->rdev->ibdev; 1245 ib_event.element.srq = &srq->ib_srq; 1246 1247 if (srq->ib_srq.event_handler) { 1248 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT) 1249 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED; 1250 (*srq->ib_srq.event_handler)(&ib_event, 1251 srq->ib_srq.srq_context); 1252 } 1253 return 0; 1254 } 1255 1256 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq, 1257 struct bnxt_qplib_cq *handle) 1258 { 1259 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq, 1260 qplib_cq); 1261 u32 *cq_ptr; 1262 1263 if (cq->ib_cq.comp_handler) { 1264 if (cq->uctx_cq_page) { 1265 cq_ptr = (u32 *)cq->uctx_cq_page; 1266 *cq_ptr = cq->qplib_cq.toggle; 1267 } 1268 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context); 1269 } 1270 1271 return 0; 1272 } 1273 1274 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev) 1275 { 1276 int i; 1277 1278 for (i = 1; i < rdev->num_msix; i++) 1279 bnxt_qplib_disable_nq(&rdev->nq[i - 1]); 1280 1281 if (rdev->qplib_res.rcfw) 1282 bnxt_qplib_cleanup_res(&rdev->qplib_res); 1283 } 1284 1285 static int bnxt_re_init_res(struct bnxt_re_dev *rdev) 1286 { 1287 int num_vec_enabled = 0; 1288 int rc = 0, i; 1289 u32 db_offt; 1290 1291 bnxt_qplib_init_res(&rdev->qplib_res); 1292 1293 for (i = 1; i < rdev->num_msix ; i++) { 1294 db_offt = rdev->en_dev->msix_entries[i].db_offset; 1295 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1], 1296 i - 1, rdev->en_dev->msix_entries[i].vector, 1297 db_offt, &bnxt_re_cqn_handler, 1298 &bnxt_re_srqn_handler); 1299 if (rc) { 1300 ibdev_err(&rdev->ibdev, 1301 "Failed to enable NQ with rc = 0x%x", rc); 1302 goto fail; 1303 } 1304 num_vec_enabled++; 1305 } 1306 return 0; 1307 fail: 1308 for (i = num_vec_enabled; i >= 0; i--) 1309 bnxt_qplib_disable_nq(&rdev->nq[i]); 1310 return rc; 1311 } 1312 1313 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev) 1314 { 1315 u8 type; 1316 int i; 1317 1318 for (i = 0; i < rdev->num_msix - 1; i++) { 1319 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1320 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 1321 bnxt_qplib_free_nq(&rdev->nq[i]); 1322 rdev->nq[i].res = NULL; 1323 } 1324 } 1325 1326 static void bnxt_re_free_res(struct bnxt_re_dev *rdev) 1327 { 1328 bnxt_re_free_nq_res(rdev); 1329 1330 if (rdev->qplib_res.dpi_tbl.max) { 1331 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1332 &rdev->dpi_privileged); 1333 } 1334 if (rdev->qplib_res.rcfw) { 1335 bnxt_qplib_free_res(&rdev->qplib_res); 1336 rdev->qplib_res.rcfw = NULL; 1337 } 1338 } 1339 1340 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev) 1341 { 1342 struct bnxt_re_ring_attr rattr = {}; 1343 int num_vec_created = 0; 1344 int rc, i; 1345 u8 type; 1346 1347 /* Configure and allocate resources for qplib */ 1348 rdev->qplib_res.rcfw = &rdev->rcfw; 1349 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 1350 if (rc) 1351 goto fail; 1352 1353 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev, 1354 rdev->netdev, &rdev->dev_attr); 1355 if (rc) 1356 goto fail; 1357 1358 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res, 1359 &rdev->dpi_privileged, 1360 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL); 1361 if (rc) 1362 goto dealloc_res; 1363 1364 for (i = 0; i < rdev->num_msix - 1; i++) { 1365 struct bnxt_qplib_nq *nq; 1366 1367 nq = &rdev->nq[i]; 1368 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT; 1369 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, &rdev->nq[i]); 1370 if (rc) { 1371 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x", 1372 i, rc); 1373 goto free_nq; 1374 } 1375 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1376 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1377 rattr.pages = nq->hwq.pbl[rdev->nq[i].hwq.level].pg_count; 1378 rattr.type = type; 1379 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1380 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1; 1381 rattr.lrid = rdev->en_dev->msix_entries[i + 1].ring_idx; 1382 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id); 1383 if (rc) { 1384 ibdev_err(&rdev->ibdev, 1385 "Failed to allocate NQ fw id with rc = 0x%x", 1386 rc); 1387 bnxt_qplib_free_nq(&rdev->nq[i]); 1388 goto free_nq; 1389 } 1390 num_vec_created++; 1391 } 1392 return 0; 1393 free_nq: 1394 for (i = num_vec_created - 1; i >= 0; i--) { 1395 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1396 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 1397 bnxt_qplib_free_nq(&rdev->nq[i]); 1398 } 1399 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1400 &rdev->dpi_privileged); 1401 dealloc_res: 1402 bnxt_qplib_free_res(&rdev->qplib_res); 1403 1404 fail: 1405 rdev->qplib_res.rcfw = NULL; 1406 return rc; 1407 } 1408 1409 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp, 1410 u8 port_num, enum ib_event_type event) 1411 { 1412 struct ib_event ib_event; 1413 1414 ib_event.device = ibdev; 1415 if (qp) { 1416 ib_event.element.qp = qp; 1417 ib_event.event = event; 1418 if (qp->event_handler) 1419 qp->event_handler(&ib_event, qp->qp_context); 1420 1421 } else { 1422 ib_event.element.port_num = port_num; 1423 ib_event.event = event; 1424 ib_dispatch_event(&ib_event); 1425 } 1426 } 1427 1428 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev, 1429 struct bnxt_re_qp *qp) 1430 { 1431 return (qp->ib_qp.qp_type == IB_QPT_GSI) || 1432 (qp == rdev->gsi_ctx.gsi_sqp); 1433 } 1434 1435 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev) 1436 { 1437 int mask = IB_QP_STATE; 1438 struct ib_qp_attr qp_attr; 1439 struct bnxt_re_qp *qp; 1440 1441 qp_attr.qp_state = IB_QPS_ERR; 1442 mutex_lock(&rdev->qp_lock); 1443 list_for_each_entry(qp, &rdev->qp_list, list) { 1444 /* Modify the state of all QPs except QP1/Shadow QP */ 1445 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) { 1446 if (qp->qplib_qp.state != 1447 CMDQ_MODIFY_QP_NEW_STATE_RESET && 1448 qp->qplib_qp.state != 1449 CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1450 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp, 1451 1, IB_EVENT_QP_FATAL); 1452 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask, 1453 NULL); 1454 } 1455 } 1456 } 1457 mutex_unlock(&rdev->qp_lock); 1458 } 1459 1460 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev) 1461 { 1462 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 1463 struct bnxt_qplib_gid gid; 1464 u16 gid_idx, index; 1465 int rc = 0; 1466 1467 if (!ib_device_try_get(&rdev->ibdev)) 1468 return 0; 1469 1470 for (index = 0; index < sgid_tbl->active; index++) { 1471 gid_idx = sgid_tbl->hw_id[index]; 1472 1473 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero, 1474 sizeof(bnxt_qplib_gid_zero))) 1475 continue; 1476 /* need to modify the VLAN enable setting of non VLAN GID only 1477 * as setting is done for VLAN GID while adding GID 1478 */ 1479 if (sgid_tbl->vlan[index]) 1480 continue; 1481 1482 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid)); 1483 1484 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx, 1485 rdev->qplib_res.netdev->dev_addr); 1486 } 1487 1488 ib_device_put(&rdev->ibdev); 1489 return rc; 1490 } 1491 1492 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev) 1493 { 1494 u32 prio_map = 0, tmp_map = 0; 1495 struct net_device *netdev; 1496 struct dcb_app app = {}; 1497 1498 netdev = rdev->netdev; 1499 1500 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE; 1501 app.protocol = ETH_P_IBOE; 1502 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1503 prio_map = tmp_map; 1504 1505 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM; 1506 app.protocol = ROCE_V2_UDP_DPORT; 1507 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1508 prio_map |= tmp_map; 1509 1510 return prio_map; 1511 } 1512 1513 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev) 1514 { 1515 u8 prio_map = 0; 1516 1517 /* Get priority for roce */ 1518 prio_map = bnxt_re_get_priority_mask(rdev); 1519 1520 if (prio_map == rdev->cur_prio_map) 1521 return 0; 1522 rdev->cur_prio_map = prio_map; 1523 /* Actual priorities are not programmed as they are already 1524 * done by L2 driver; just enable or disable priority vlan tagging 1525 */ 1526 if ((prio_map == 0 && rdev->qplib_res.prio) || 1527 (prio_map != 0 && !rdev->qplib_res.prio)) { 1528 rdev->qplib_res.prio = prio_map; 1529 bnxt_re_update_gid(rdev); 1530 } 1531 1532 return 0; 1533 } 1534 1535 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev) 1536 { 1537 struct bnxt_en_dev *en_dev = rdev->en_dev; 1538 struct hwrm_ver_get_output resp = {}; 1539 struct hwrm_ver_get_input req = {}; 1540 struct bnxt_qplib_chip_ctx *cctx; 1541 struct bnxt_fw_msg fw_msg = {}; 1542 int rc; 1543 1544 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET); 1545 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 1546 req.hwrm_intf_min = HWRM_VERSION_MINOR; 1547 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 1548 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 1549 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 1550 rc = bnxt_send_msg(en_dev, &fw_msg); 1551 if (rc) { 1552 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x", 1553 rc); 1554 return; 1555 } 1556 1557 cctx = rdev->chip_ctx; 1558 cctx->hwrm_intf_ver = 1559 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 | 1560 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 | 1561 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 | 1562 le16_to_cpu(resp.hwrm_intf_patch); 1563 1564 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout); 1565 1566 if (!cctx->hwrm_cmd_max_timeout) 1567 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT; 1568 } 1569 1570 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev) 1571 { 1572 int rc; 1573 u32 event; 1574 1575 /* Register ib dev */ 1576 rc = bnxt_re_register_ib(rdev); 1577 if (rc) { 1578 pr_err("Failed to register with IB: %#x\n", rc); 1579 return rc; 1580 } 1581 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully"); 1582 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags); 1583 1584 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ? 1585 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 1586 1587 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event); 1588 1589 return rc; 1590 } 1591 1592 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type) 1593 { 1594 u8 type; 1595 int rc; 1596 1597 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags)) 1598 cancel_delayed_work_sync(&rdev->worker); 1599 1600 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, 1601 &rdev->flags)) 1602 bnxt_re_cleanup_res(rdev); 1603 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags)) 1604 bnxt_re_free_res(rdev); 1605 1606 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) { 1607 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw); 1608 if (rc) 1609 ibdev_warn(&rdev->ibdev, 1610 "Failed to deinitialize RCFW: %#x", rc); 1611 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1612 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1613 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1614 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1615 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1616 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1617 } 1618 1619 rdev->num_msix = 0; 1620 1621 if (rdev->pacing.dbr_pacing) 1622 bnxt_re_deinitialize_dbr_pacing(rdev); 1623 1624 bnxt_re_destroy_chip_ctx(rdev); 1625 if (op_type == BNXT_RE_COMPLETE_REMOVE) { 1626 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags)) 1627 bnxt_unregister_dev(rdev->en_dev); 1628 } 1629 } 1630 1631 /* worker thread for polling periodic events. Now used for QoS programming*/ 1632 static void bnxt_re_worker(struct work_struct *work) 1633 { 1634 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 1635 worker.work); 1636 1637 bnxt_re_setup_qos(rdev); 1638 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1639 } 1640 1641 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 op_type) 1642 { 1643 struct bnxt_re_ring_attr rattr = {}; 1644 struct bnxt_qplib_creq_ctx *creq; 1645 u32 db_offt; 1646 int vid; 1647 u8 type; 1648 int rc; 1649 1650 if (op_type == BNXT_RE_COMPLETE_INIT) { 1651 /* Registered a new RoCE device instance to netdev */ 1652 rc = bnxt_re_register_netdev(rdev); 1653 if (rc) { 1654 ibdev_err(&rdev->ibdev, 1655 "Failed to register with netedev: %#x\n", rc); 1656 return -EINVAL; 1657 } 1658 } 1659 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1660 1661 rc = bnxt_re_setup_chip_ctx(rdev); 1662 if (rc) { 1663 bnxt_unregister_dev(rdev->en_dev); 1664 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1665 ibdev_err(&rdev->ibdev, "Failed to get chip context\n"); 1666 return -EINVAL; 1667 } 1668 1669 /* Check whether VF or PF */ 1670 bnxt_re_get_sriov_func_type(rdev); 1671 1672 if (!rdev->en_dev->ulp_tbl->msix_requested) { 1673 ibdev_err(&rdev->ibdev, 1674 "Failed to get MSI-X vectors: %#x\n", rc); 1675 rc = -EINVAL; 1676 goto fail; 1677 } 1678 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n", 1679 rdev->en_dev->ulp_tbl->msix_requested); 1680 rdev->num_msix = rdev->en_dev->ulp_tbl->msix_requested; 1681 1682 bnxt_re_query_hwrm_intf_version(rdev); 1683 1684 /* Establish RCFW Communication Channel to initialize the context 1685 * memory for the function and all child VFs 1686 */ 1687 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw, 1688 &rdev->qplib_ctx, 1689 BNXT_RE_MAX_QPC_COUNT); 1690 if (rc) { 1691 ibdev_err(&rdev->ibdev, 1692 "Failed to allocate RCFW Channel: %#x\n", rc); 1693 goto fail; 1694 } 1695 1696 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1697 creq = &rdev->rcfw.creq; 1698 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1699 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count; 1700 rattr.type = type; 1701 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1702 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1; 1703 rattr.lrid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx; 1704 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id); 1705 if (rc) { 1706 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc); 1707 goto free_rcfw; 1708 } 1709 db_offt = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].db_offset; 1710 vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector; 1711 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw, 1712 vid, db_offt, 1713 &bnxt_re_aeq_handler); 1714 if (rc) { 1715 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n", 1716 rc); 1717 goto free_ring; 1718 } 1719 1720 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) { 1721 rc = bnxt_re_initialize_dbr_pacing(rdev); 1722 if (!rc) { 1723 rdev->pacing.dbr_pacing = true; 1724 } else { 1725 ibdev_err(&rdev->ibdev, 1726 "DBR pacing disabled with error : %d\n", rc); 1727 rdev->pacing.dbr_pacing = false; 1728 } 1729 } 1730 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 1731 if (rc) 1732 goto disable_rcfw; 1733 1734 bnxt_re_set_resource_limits(rdev); 1735 1736 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0, 1737 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)); 1738 if (rc) { 1739 ibdev_err(&rdev->ibdev, 1740 "Failed to allocate QPLIB context: %#x\n", rc); 1741 goto disable_rcfw; 1742 } 1743 rc = bnxt_re_net_stats_ctx_alloc(rdev, 1744 rdev->qplib_ctx.stats.dma_map, 1745 &rdev->qplib_ctx.stats.fw_id); 1746 if (rc) { 1747 ibdev_err(&rdev->ibdev, 1748 "Failed to allocate stats context: %#x\n", rc); 1749 goto free_ctx; 1750 } 1751 1752 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx, 1753 rdev->is_virtfn); 1754 if (rc) { 1755 ibdev_err(&rdev->ibdev, 1756 "Failed to initialize RCFW: %#x\n", rc); 1757 goto free_sctx; 1758 } 1759 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags); 1760 1761 /* Resources based on the 'new' device caps */ 1762 rc = bnxt_re_alloc_res(rdev); 1763 if (rc) { 1764 ibdev_err(&rdev->ibdev, 1765 "Failed to allocate resources: %#x\n", rc); 1766 goto fail; 1767 } 1768 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags); 1769 rc = bnxt_re_init_res(rdev); 1770 if (rc) { 1771 ibdev_err(&rdev->ibdev, 1772 "Failed to initialize resources: %#x\n", rc); 1773 goto fail; 1774 } 1775 1776 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags); 1777 1778 if (!rdev->is_virtfn) { 1779 rc = bnxt_re_setup_qos(rdev); 1780 if (rc) 1781 ibdev_info(&rdev->ibdev, 1782 "RoCE priority not yet configured\n"); 1783 1784 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker); 1785 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags); 1786 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1787 /* 1788 * Use the total VF count since the actual VF count may not be 1789 * available at this point. 1790 */ 1791 bnxt_re_vf_res_config(rdev); 1792 } 1793 hash_init(rdev->cq_hash); 1794 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) 1795 hash_init(rdev->srq_hash); 1796 1797 return 0; 1798 free_sctx: 1799 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1800 free_ctx: 1801 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1802 disable_rcfw: 1803 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1804 free_ring: 1805 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1806 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1807 free_rcfw: 1808 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1809 fail: 1810 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 1811 1812 return rc; 1813 } 1814 1815 static void bnxt_re_update_en_info_rdev(struct bnxt_re_dev *rdev, 1816 struct bnxt_re_en_dev_info *en_info, 1817 struct auxiliary_device *adev) 1818 { 1819 /* Before updating the rdev pointer in bnxt_re_en_dev_info structure, 1820 * take the rtnl lock to avoid accessing invalid rdev pointer from 1821 * L2 ULP callbacks. This is applicable in all the places where rdev 1822 * pointer is updated in bnxt_re_en_dev_info. 1823 */ 1824 rtnl_lock(); 1825 en_info->rdev = rdev; 1826 rdev->adev = adev; 1827 rtnl_unlock(); 1828 } 1829 1830 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 op_type) 1831 { 1832 struct bnxt_aux_priv *aux_priv = 1833 container_of(adev, struct bnxt_aux_priv, aux_dev); 1834 struct bnxt_re_en_dev_info *en_info; 1835 struct bnxt_en_dev *en_dev; 1836 struct bnxt_re_dev *rdev; 1837 int rc; 1838 1839 en_info = auxiliary_get_drvdata(adev); 1840 en_dev = en_info->en_dev; 1841 1842 1843 rdev = bnxt_re_dev_add(aux_priv, en_dev); 1844 if (!rdev || !rdev_to_dev(rdev)) { 1845 rc = -ENOMEM; 1846 goto exit; 1847 } 1848 1849 bnxt_re_update_en_info_rdev(rdev, en_info, adev); 1850 1851 rc = bnxt_re_dev_init(rdev, op_type); 1852 if (rc) 1853 goto re_dev_dealloc; 1854 1855 rc = bnxt_re_ib_init(rdev); 1856 if (rc) { 1857 pr_err("Failed to register with IB: %s", 1858 aux_priv->aux_dev.name); 1859 goto re_dev_uninit; 1860 } 1861 1862 rdev->nb.notifier_call = bnxt_re_netdev_event; 1863 rc = register_netdevice_notifier(&rdev->nb); 1864 if (rc) { 1865 rdev->nb.notifier_call = NULL; 1866 pr_err("%s: Cannot register to netdevice_notifier", 1867 ROCE_DRV_MODULE_NAME); 1868 return rc; 1869 } 1870 bnxt_re_setup_cc(rdev, true); 1871 1872 return 0; 1873 1874 re_dev_uninit: 1875 bnxt_re_update_en_info_rdev(NULL, en_info, adev); 1876 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 1877 re_dev_dealloc: 1878 ib_dealloc_device(&rdev->ibdev); 1879 exit: 1880 return rc; 1881 } 1882 1883 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable) 1884 { 1885 struct bnxt_qplib_cc_param cc_param = {}; 1886 1887 /* Do not enable congestion control on VFs */ 1888 if (rdev->is_virtfn) 1889 return; 1890 1891 /* Currently enabling only for GenP5 adapters */ 1892 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 1893 return; 1894 1895 if (enable) { 1896 cc_param.enable = 1; 1897 cc_param.cc_mode = CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE; 1898 } 1899 1900 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE | 1901 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC | 1902 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN); 1903 1904 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param)) 1905 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable); 1906 } 1907 1908 /* 1909 * "Notifier chain callback can be invoked for the same chain from 1910 * different CPUs at the same time". 1911 * 1912 * For cases when the netdev is already present, our call to the 1913 * register_netdevice_notifier() will actually get the rtnl_lock() 1914 * before sending NETDEV_REGISTER and (if up) NETDEV_UP 1915 * events. 1916 * 1917 * But for cases when the netdev is not already present, the notifier 1918 * chain is subjected to be invoked from different CPUs simultaneously. 1919 * 1920 * This is protected by the netdev_mutex. 1921 */ 1922 static int bnxt_re_netdev_event(struct notifier_block *notifier, 1923 unsigned long event, void *ptr) 1924 { 1925 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr); 1926 struct bnxt_re_dev *rdev; 1927 1928 real_dev = rdma_vlan_dev_real_dev(netdev); 1929 if (!real_dev) 1930 real_dev = netdev; 1931 1932 if (real_dev != netdev) 1933 goto exit; 1934 1935 rdev = bnxt_re_from_netdev(real_dev); 1936 if (!rdev) 1937 return NOTIFY_DONE; 1938 1939 1940 switch (event) { 1941 case NETDEV_UP: 1942 case NETDEV_DOWN: 1943 case NETDEV_CHANGE: 1944 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, 1945 netif_carrier_ok(real_dev) ? 1946 IB_EVENT_PORT_ACTIVE : 1947 IB_EVENT_PORT_ERR); 1948 break; 1949 default: 1950 break; 1951 } 1952 ib_device_put(&rdev->ibdev); 1953 exit: 1954 return NOTIFY_DONE; 1955 } 1956 1957 #define BNXT_ADEV_NAME "bnxt_en" 1958 1959 static void bnxt_re_remove_device(struct bnxt_re_dev *rdev, u8 op_type, 1960 struct auxiliary_device *aux_dev) 1961 { 1962 if (rdev->nb.notifier_call) { 1963 unregister_netdevice_notifier(&rdev->nb); 1964 rdev->nb.notifier_call = NULL; 1965 } else { 1966 /* If notifier is null, we should have already done a 1967 * clean up before coming here. 1968 */ 1969 return; 1970 } 1971 bnxt_re_setup_cc(rdev, false); 1972 ib_unregister_device(&rdev->ibdev); 1973 bnxt_re_dev_uninit(rdev, op_type); 1974 ib_dealloc_device(&rdev->ibdev); 1975 } 1976 1977 static void bnxt_re_remove(struct auxiliary_device *adev) 1978 { 1979 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 1980 struct bnxt_re_dev *rdev; 1981 1982 mutex_lock(&bnxt_re_mutex); 1983 if (!en_info) { 1984 mutex_unlock(&bnxt_re_mutex); 1985 return; 1986 } 1987 rdev = en_info->rdev; 1988 1989 if (rdev) 1990 bnxt_re_remove_device(rdev, BNXT_RE_COMPLETE_REMOVE, adev); 1991 kfree(en_info); 1992 mutex_unlock(&bnxt_re_mutex); 1993 } 1994 1995 static int bnxt_re_probe(struct auxiliary_device *adev, 1996 const struct auxiliary_device_id *id) 1997 { 1998 struct bnxt_aux_priv *aux_priv = 1999 container_of(adev, struct bnxt_aux_priv, aux_dev); 2000 struct bnxt_re_en_dev_info *en_info; 2001 struct bnxt_en_dev *en_dev; 2002 int rc; 2003 2004 en_dev = aux_priv->edev; 2005 2006 mutex_lock(&bnxt_re_mutex); 2007 en_info = kzalloc(sizeof(*en_info), GFP_KERNEL); 2008 if (!en_info) { 2009 mutex_unlock(&bnxt_re_mutex); 2010 return -ENOMEM; 2011 } 2012 en_info->en_dev = en_dev; 2013 2014 auxiliary_set_drvdata(adev, en_info); 2015 2016 rc = bnxt_re_add_device(adev, BNXT_RE_COMPLETE_INIT); 2017 if (rc) 2018 goto err; 2019 mutex_unlock(&bnxt_re_mutex); 2020 return 0; 2021 2022 err: 2023 mutex_unlock(&bnxt_re_mutex); 2024 bnxt_re_remove(adev); 2025 2026 return rc; 2027 } 2028 2029 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state) 2030 { 2031 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 2032 struct bnxt_en_dev *en_dev; 2033 struct bnxt_re_dev *rdev; 2034 2035 if (!en_info) 2036 return 0; 2037 2038 rdev = en_info->rdev; 2039 en_dev = en_info->en_dev; 2040 mutex_lock(&bnxt_re_mutex); 2041 /* L2 driver may invoke this callback during device error/crash or device 2042 * reset. Current RoCE driver doesn't recover the device in case of 2043 * error. Handle the error by dispatching fatal events to all qps 2044 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 2045 * L2 driver want to modify the MSIx table. 2046 */ 2047 2048 ibdev_info(&rdev->ibdev, "Handle device suspend call"); 2049 /* Check the current device state from bnxt_en_dev and move the 2050 * device to detached state if FW_FATAL_COND is set. 2051 * This prevents more commands to HW during clean-up, 2052 * in case the device is already in error. 2053 */ 2054 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) 2055 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 2056 2057 bnxt_re_dev_stop(rdev); 2058 bnxt_re_stop_irq(adev); 2059 /* Move the device states to detached and avoid sending any more 2060 * commands to HW 2061 */ 2062 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags); 2063 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 2064 wake_up_all(&rdev->rcfw.cmdq.waitq); 2065 2066 if (rdev->pacing.dbr_pacing) 2067 bnxt_re_set_pacing_dev_state(rdev); 2068 2069 ibdev_info(&rdev->ibdev, "%s: L2 driver notified to stop en_state 0x%lx", 2070 __func__, en_dev->en_state); 2071 bnxt_re_remove_device(rdev, BNXT_RE_PRE_RECOVERY_REMOVE, adev); 2072 mutex_unlock(&bnxt_re_mutex); 2073 2074 return 0; 2075 } 2076 2077 static int bnxt_re_resume(struct auxiliary_device *adev) 2078 { 2079 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 2080 struct bnxt_re_dev *rdev; 2081 2082 if (!en_info) 2083 return 0; 2084 2085 mutex_lock(&bnxt_re_mutex); 2086 /* L2 driver may invoke this callback during device recovery, resume. 2087 * reset. Current RoCE driver doesn't recover the device in case of 2088 * error. Handle the error by dispatching fatal events to all qps 2089 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 2090 * L2 driver want to modify the MSIx table. 2091 */ 2092 2093 bnxt_re_add_device(adev, BNXT_RE_POST_RECOVERY_INIT); 2094 rdev = en_info->rdev; 2095 ibdev_info(&rdev->ibdev, "Device resume completed"); 2096 mutex_unlock(&bnxt_re_mutex); 2097 2098 return 0; 2099 } 2100 2101 static const struct auxiliary_device_id bnxt_re_id_table[] = { 2102 { .name = BNXT_ADEV_NAME ".rdma", }, 2103 {}, 2104 }; 2105 2106 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table); 2107 2108 static struct auxiliary_driver bnxt_re_driver = { 2109 .name = "rdma", 2110 .probe = bnxt_re_probe, 2111 .remove = bnxt_re_remove, 2112 .shutdown = bnxt_re_shutdown, 2113 .suspend = bnxt_re_suspend, 2114 .resume = bnxt_re_resume, 2115 .id_table = bnxt_re_id_table, 2116 }; 2117 2118 static int __init bnxt_re_mod_init(void) 2119 { 2120 int rc; 2121 2122 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version); 2123 rc = auxiliary_driver_register(&bnxt_re_driver); 2124 if (rc) { 2125 pr_err("%s: Failed to register auxiliary driver\n", 2126 ROCE_DRV_MODULE_NAME); 2127 return rc; 2128 } 2129 return 0; 2130 } 2131 2132 static void __exit bnxt_re_mod_exit(void) 2133 { 2134 auxiliary_driver_unregister(&bnxt_re_driver); 2135 } 2136 2137 module_init(bnxt_re_mod_init); 2138 module_exit(bnxt_re_mod_exit); 2139