1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 #include <net/addrconf.h> 45 46 #include <rdma/ib_verbs.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_umem.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_mad.h> 51 #include <rdma/ib_cache.h> 52 #include <rdma/ib_pma.h> 53 #include <rdma/uverbs_ioctl.h> 54 #include <linux/hashtable.h> 55 56 #include "roce_hsi.h" 57 #include "qplib_res.h" 58 #include "qplib_sp.h" 59 #include "qplib_fp.h" 60 #include "qplib_rcfw.h" 61 62 #include "bnxt_re.h" 63 #include "ib_verbs.h" 64 #include "debugfs.h" 65 66 #include <rdma/uverbs_types.h> 67 #include <rdma/uverbs_std_types.h> 68 69 #include <rdma/ib_user_ioctl_cmds.h> 70 71 #define UVERBS_MODULE_NAME bnxt_re 72 #include <rdma/uverbs_named_ioctl.h> 73 74 #include <rdma/bnxt_re-abi.h> 75 76 static int __from_ib_access_flags(int iflags) 77 { 78 int qflags = 0; 79 80 if (iflags & IB_ACCESS_LOCAL_WRITE) 81 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 82 if (iflags & IB_ACCESS_REMOTE_READ) 83 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 84 if (iflags & IB_ACCESS_REMOTE_WRITE) 85 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 86 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 87 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 88 if (iflags & IB_ACCESS_MW_BIND) 89 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 90 if (iflags & IB_ZERO_BASED) 91 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 92 if (iflags & IB_ACCESS_ON_DEMAND) 93 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 94 return qflags; 95 }; 96 97 static int __to_ib_access_flags(int qflags) 98 { 99 int iflags = 0; 100 101 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 102 iflags |= IB_ACCESS_LOCAL_WRITE; 103 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 104 iflags |= IB_ACCESS_REMOTE_WRITE; 105 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 106 iflags |= IB_ACCESS_REMOTE_READ; 107 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 108 iflags |= IB_ACCESS_REMOTE_ATOMIC; 109 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 110 iflags |= IB_ACCESS_MW_BIND; 111 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 112 iflags |= IB_ZERO_BASED; 113 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 114 iflags |= IB_ACCESS_ON_DEMAND; 115 return iflags; 116 } 117 118 static u8 __qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx *cctx, int iflags) 119 { 120 u8 qflags = 0; 121 122 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx)) 123 /* For Wh+ */ 124 return (u8)__from_ib_access_flags(iflags); 125 126 /* For P5, P7 and later chips */ 127 if (iflags & IB_ACCESS_LOCAL_WRITE) 128 qflags |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE; 129 if (iflags & IB_ACCESS_REMOTE_WRITE) 130 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 131 if (iflags & IB_ACCESS_REMOTE_READ) 132 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 133 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 134 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC; 135 136 return qflags; 137 } 138 139 static int __qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx *cctx, u8 qflags) 140 { 141 int iflags = 0; 142 143 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx)) 144 /* For Wh+ */ 145 return __to_ib_access_flags(qflags); 146 147 /* For P5, P7 and later chips */ 148 if (qflags & CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE) 149 iflags |= IB_ACCESS_LOCAL_WRITE; 150 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE) 151 iflags |= IB_ACCESS_REMOTE_WRITE; 152 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_READ) 153 iflags |= IB_ACCESS_REMOTE_READ; 154 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC) 155 iflags |= IB_ACCESS_REMOTE_ATOMIC; 156 157 return iflags; 158 } 159 160 static void bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev *rdev, 161 struct bnxt_qplib_mrw *qplib_mr) 162 { 163 if (_is_relaxed_ordering_supported(rdev->dev_attr->dev_cap_flags2) && 164 pcie_relaxed_ordering_enabled(rdev->en_dev->pdev)) 165 qplib_mr->flags |= CMDQ_REGISTER_MR_FLAGS_ENABLE_RO; 166 } 167 168 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 169 struct bnxt_qplib_sge *sg_list, int num) 170 { 171 int i, total = 0; 172 173 for (i = 0; i < num; i++) { 174 sg_list[i].addr = ib_sg_list[i].addr; 175 sg_list[i].lkey = ib_sg_list[i].lkey; 176 sg_list[i].size = ib_sg_list[i].length; 177 total += sg_list[i].size; 178 } 179 return total; 180 } 181 182 /* Device */ 183 int bnxt_re_query_device(struct ib_device *ibdev, 184 struct ib_device_attr *ib_attr, 185 struct ib_udata *udata) 186 { 187 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 188 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 189 190 memset(ib_attr, 0, sizeof(*ib_attr)); 191 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 192 min(sizeof(dev_attr->fw_ver), 193 sizeof(ib_attr->fw_ver))); 194 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid, 195 rdev->netdev->dev_addr); 196 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 197 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED; 198 199 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 200 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 201 ib_attr->hw_ver = rdev->en_dev->pdev->revision; 202 ib_attr->max_qp = dev_attr->max_qp; 203 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 204 ib_attr->device_cap_flags = 205 IB_DEVICE_CURR_QP_STATE_MOD 206 | IB_DEVICE_RC_RNR_NAK_GEN 207 | IB_DEVICE_SHUTDOWN_PORT 208 | IB_DEVICE_SYS_IMAGE_GUID 209 | IB_DEVICE_RESIZE_MAX_WR 210 | IB_DEVICE_PORT_ACTIVE_EVENT 211 | IB_DEVICE_N_NOTIFY_CQ 212 | IB_DEVICE_MEM_WINDOW 213 | IB_DEVICE_MEM_WINDOW_TYPE_2B 214 | IB_DEVICE_MEM_MGT_EXTENSIONS; 215 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY; 216 ib_attr->max_send_sge = dev_attr->max_qp_sges; 217 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 218 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 219 ib_attr->max_cq = dev_attr->max_cq; 220 ib_attr->max_cqe = dev_attr->max_cq_wqes; 221 ib_attr->max_mr = dev_attr->max_mr; 222 ib_attr->max_pd = dev_attr->max_pd; 223 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 224 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 225 ib_attr->atomic_cap = IB_ATOMIC_NONE; 226 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 227 if (dev_attr->is_atomic) { 228 ib_attr->atomic_cap = IB_ATOMIC_GLOB; 229 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; 230 } 231 232 ib_attr->max_ee_rd_atom = 0; 233 ib_attr->max_res_rd_atom = 0; 234 ib_attr->max_ee_init_rd_atom = 0; 235 ib_attr->max_ee = 0; 236 ib_attr->max_rdd = 0; 237 ib_attr->max_mw = dev_attr->max_mw; 238 ib_attr->max_raw_ipv6_qp = 0; 239 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 240 ib_attr->max_mcast_grp = 0; 241 ib_attr->max_mcast_qp_attach = 0; 242 ib_attr->max_total_mcast_qp_attach = 0; 243 ib_attr->max_ah = dev_attr->max_ah; 244 245 ib_attr->max_srq = dev_attr->max_srq; 246 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 247 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 248 249 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 250 251 ib_attr->max_pkeys = 1; 252 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 253 return 0; 254 } 255 256 int bnxt_re_modify_device(struct ib_device *ibdev, 257 int device_modify_mask, 258 struct ib_device_modify *device_modify) 259 { 260 ibdev_dbg(ibdev, "Modify device with mask 0x%x", device_modify_mask); 261 262 if (device_modify_mask & ~IB_DEVICE_MODIFY_NODE_DESC) 263 return -EOPNOTSUPP; 264 265 if (!(device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC)) 266 return 0; 267 268 memcpy(ibdev->node_desc, device_modify->node_desc, IB_DEVICE_NODE_DESC_MAX); 269 return 0; 270 } 271 272 /* Port */ 273 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num, 274 struct ib_port_attr *port_attr) 275 { 276 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 277 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 278 int rc; 279 280 memset(port_attr, 0, sizeof(*port_attr)); 281 282 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 283 port_attr->state = IB_PORT_ACTIVE; 284 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 285 } else { 286 port_attr->state = IB_PORT_DOWN; 287 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 288 } 289 port_attr->max_mtu = IB_MTU_4096; 290 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 291 port_attr->gid_tbl_len = dev_attr->max_sgid; 292 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 293 IB_PORT_DEVICE_MGMT_SUP | 294 IB_PORT_VENDOR_CLASS_SUP; 295 port_attr->ip_gids = true; 296 297 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 298 port_attr->bad_pkey_cntr = 0; 299 port_attr->qkey_viol_cntr = 0; 300 port_attr->pkey_tbl_len = dev_attr->max_pkey; 301 port_attr->lid = 0; 302 port_attr->sm_lid = 0; 303 port_attr->lmc = 0; 304 port_attr->max_vl_num = 4; 305 port_attr->sm_sl = 0; 306 port_attr->subnet_timeout = 0; 307 port_attr->init_type_reply = 0; 308 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed, 309 &port_attr->active_width); 310 311 return rc; 312 } 313 314 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num, 315 struct ib_port_immutable *immutable) 316 { 317 struct ib_port_attr port_attr; 318 319 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 320 return -EINVAL; 321 322 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 323 immutable->gid_tbl_len = port_attr.gid_tbl_len; 324 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 325 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 326 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 327 return 0; 328 } 329 330 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 331 { 332 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 333 334 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 335 rdev->dev_attr->fw_ver[0], rdev->dev_attr->fw_ver[1], 336 rdev->dev_attr->fw_ver[2], rdev->dev_attr->fw_ver[3]); 337 } 338 339 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num, 340 u16 index, u16 *pkey) 341 { 342 if (index > 0) 343 return -EINVAL; 344 345 *pkey = IB_DEFAULT_PKEY_FULL; 346 347 return 0; 348 } 349 350 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num, 351 int index, union ib_gid *gid) 352 { 353 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 354 int rc; 355 356 /* Ignore port_num */ 357 memset(gid, 0, sizeof(*gid)); 358 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 359 &rdev->qplib_res.sgid_tbl, index, 360 (struct bnxt_qplib_gid *)gid); 361 return rc; 362 } 363 364 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 365 { 366 int rc = 0; 367 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 368 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 369 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 370 struct bnxt_qplib_gid *gid_to_del; 371 u16 vlan_id = 0xFFFF; 372 373 /* Delete the entry from the hardware */ 374 ctx = *context; 375 if (!ctx) 376 return -EINVAL; 377 378 if (sgid_tbl && sgid_tbl->active) { 379 if (ctx->idx >= sgid_tbl->max) 380 return -EINVAL; 381 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 382 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 383 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 384 * or via the ib_unregister_device path. In the former case QP1 385 * may not be destroyed yet, in which case just return as FW 386 * needs that entry to be present and will fail it's deletion. 387 * We could get invoked again after QP1 is destroyed OR get an 388 * ADD_GID call with a different GID value for the same index 389 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 390 */ 391 if (ctx->idx == 0 && 392 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 393 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) { 394 ibdev_dbg(&rdev->ibdev, 395 "Trying to delete GID0 while QP1 is alive\n"); 396 return -EFAULT; 397 } 398 ctx->refcnt--; 399 if (!ctx->refcnt) { 400 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 401 vlan_id, true); 402 if (rc) { 403 ibdev_err(&rdev->ibdev, 404 "Failed to remove GID: %#x", rc); 405 } else { 406 ctx_tbl = sgid_tbl->ctx; 407 ctx_tbl[ctx->idx] = NULL; 408 kfree(ctx); 409 } 410 } 411 } else { 412 return -EINVAL; 413 } 414 return rc; 415 } 416 417 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 418 { 419 int rc; 420 u32 tbl_idx = 0; 421 u16 vlan_id = 0xFFFF; 422 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 423 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 424 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 425 426 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 427 if (rc) 428 return rc; 429 430 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 431 rdev->qplib_res.netdev->dev_addr, 432 vlan_id, true, &tbl_idx); 433 if (rc == -EALREADY) { 434 ctx_tbl = sgid_tbl->ctx; 435 ctx_tbl[tbl_idx]->refcnt++; 436 *context = ctx_tbl[tbl_idx]; 437 return 0; 438 } 439 440 if (rc < 0) { 441 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc); 442 return rc; 443 } 444 445 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 446 if (!ctx) 447 return -ENOMEM; 448 ctx_tbl = sgid_tbl->ctx; 449 ctx->idx = tbl_idx; 450 ctx->refcnt = 1; 451 ctx_tbl[tbl_idx] = ctx; 452 *context = ctx; 453 454 return rc; 455 } 456 457 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 458 u32 port_num) 459 { 460 return IB_LINK_LAYER_ETHERNET; 461 } 462 463 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 464 465 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 466 { 467 struct bnxt_re_fence_data *fence = &pd->fence; 468 struct ib_mr *ib_mr = &fence->mr->ib_mr; 469 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 470 struct bnxt_re_dev *rdev = pd->rdev; 471 472 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 473 return; 474 475 memset(wqe, 0, sizeof(*wqe)); 476 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 477 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 478 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 479 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 480 wqe->bind.zero_based = false; 481 wqe->bind.parent_l_key = ib_mr->lkey; 482 wqe->bind.va = (u64)(unsigned long)fence->va; 483 wqe->bind.length = fence->size; 484 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 485 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 486 487 /* Save the initial rkey in fence structure for now; 488 * wqe->bind.r_key will be set at (re)bind time. 489 */ 490 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 491 } 492 493 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 494 { 495 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 496 qplib_qp); 497 struct ib_pd *ib_pd = qp->ib_qp.pd; 498 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 499 struct bnxt_re_fence_data *fence = &pd->fence; 500 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 501 struct bnxt_qplib_swqe wqe; 502 int rc; 503 504 memcpy(&wqe, fence_wqe, sizeof(wqe)); 505 wqe.bind.r_key = fence->bind_rkey; 506 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 507 508 ibdev_dbg(&qp->rdev->ibdev, 509 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 510 wqe.bind.r_key, qp->qplib_qp.id, pd); 511 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 512 if (rc) { 513 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n"); 514 return rc; 515 } 516 bnxt_qplib_post_send_db(&qp->qplib_qp); 517 518 return rc; 519 } 520 521 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 522 { 523 struct bnxt_re_fence_data *fence = &pd->fence; 524 struct bnxt_re_dev *rdev = pd->rdev; 525 struct device *dev = &rdev->en_dev->pdev->dev; 526 struct bnxt_re_mr *mr = fence->mr; 527 528 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 529 return; 530 531 if (fence->mw) { 532 bnxt_re_dealloc_mw(fence->mw); 533 fence->mw = NULL; 534 } 535 if (mr) { 536 if (mr->ib_mr.rkey) 537 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 538 true); 539 if (mr->ib_mr.lkey) 540 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 541 kfree(mr); 542 fence->mr = NULL; 543 } 544 if (fence->dma_addr) { 545 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 546 DMA_BIDIRECTIONAL); 547 fence->dma_addr = 0; 548 } 549 } 550 551 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 552 { 553 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 554 struct bnxt_re_fence_data *fence = &pd->fence; 555 struct bnxt_re_dev *rdev = pd->rdev; 556 struct device *dev = &rdev->en_dev->pdev->dev; 557 struct bnxt_re_mr *mr = NULL; 558 dma_addr_t dma_addr = 0; 559 struct ib_mw *mw; 560 int rc; 561 562 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 563 return 0; 564 565 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 566 DMA_BIDIRECTIONAL); 567 rc = dma_mapping_error(dev, dma_addr); 568 if (rc) { 569 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n"); 570 rc = -EIO; 571 fence->dma_addr = 0; 572 goto fail; 573 } 574 fence->dma_addr = dma_addr; 575 576 /* Allocate a MR */ 577 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 578 if (!mr) { 579 rc = -ENOMEM; 580 goto fail; 581 } 582 fence->mr = mr; 583 mr->rdev = rdev; 584 mr->qplib_mr.pd = &pd->qplib_pd; 585 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 586 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 587 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) { 588 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 589 if (rc) { 590 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); 591 goto fail; 592 } 593 594 /* Register MR */ 595 mr->ib_mr.lkey = mr->qplib_mr.lkey; 596 } else { 597 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR; 598 } 599 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 600 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 601 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 602 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE); 603 if (rc) { 604 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n"); 605 goto fail; 606 } 607 mr->ib_mr.rkey = mr->qplib_mr.rkey; 608 609 /* Create a fence MW only for kernel consumers */ 610 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 611 if (IS_ERR(mw)) { 612 ibdev_err(&rdev->ibdev, 613 "Failed to create fence-MW for PD: %p\n", pd); 614 rc = PTR_ERR(mw); 615 goto fail; 616 } 617 fence->mw = mw; 618 619 bnxt_re_create_fence_wqe(pd); 620 return 0; 621 622 fail: 623 bnxt_re_destroy_fence_mr(pd); 624 return rc; 625 } 626 627 static struct bnxt_re_user_mmap_entry* 628 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset, 629 enum bnxt_re_mmap_flag mmap_flag, u64 *offset) 630 { 631 struct bnxt_re_user_mmap_entry *entry; 632 int ret; 633 634 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 635 if (!entry) 636 return NULL; 637 638 entry->mem_offset = mem_offset; 639 entry->mmap_flag = mmap_flag; 640 entry->uctx = uctx; 641 642 switch (mmap_flag) { 643 case BNXT_RE_MMAP_SH_PAGE: 644 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx, 645 &entry->rdma_entry, PAGE_SIZE, 0); 646 break; 647 case BNXT_RE_MMAP_UC_DB: 648 case BNXT_RE_MMAP_WC_DB: 649 case BNXT_RE_MMAP_DBR_BAR: 650 case BNXT_RE_MMAP_DBR_PAGE: 651 case BNXT_RE_MMAP_TOGGLE_PAGE: 652 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx, 653 &entry->rdma_entry, PAGE_SIZE); 654 break; 655 default: 656 ret = -EINVAL; 657 break; 658 } 659 660 if (ret) { 661 kfree(entry); 662 return NULL; 663 } 664 if (offset) 665 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 666 667 return entry; 668 } 669 670 /* Protection Domains */ 671 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 672 { 673 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 674 struct bnxt_re_dev *rdev = pd->rdev; 675 676 if (udata) { 677 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 678 pd->pd_db_mmap = NULL; 679 } 680 681 bnxt_re_destroy_fence_mr(pd); 682 683 if (pd->qplib_pd.id) { 684 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res, 685 &rdev->qplib_res.pd_tbl, 686 &pd->qplib_pd)) 687 atomic_dec(&rdev->stats.res.pd_count); 688 } 689 return 0; 690 } 691 692 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 693 { 694 struct ib_device *ibdev = ibpd->device; 695 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 696 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 697 udata, struct bnxt_re_ucontext, ib_uctx); 698 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 699 struct bnxt_re_user_mmap_entry *entry = NULL; 700 u32 active_pds; 701 int rc = 0; 702 703 pd->rdev = rdev; 704 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) { 705 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD"); 706 rc = -ENOMEM; 707 goto fail; 708 } 709 710 if (udata) { 711 struct bnxt_re_pd_resp resp = {}; 712 713 if (!ucntx->dpi.dbr) { 714 /* Allocate DPI in alloc_pd to avoid failing of 715 * ibv_devinfo and family of application when DPIs 716 * are depleted. 717 */ 718 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, 719 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) { 720 rc = -ENOMEM; 721 goto dbfail; 722 } 723 } 724 725 resp.pdid = pd->qplib_pd.id; 726 /* Still allow mapping this DBR to the new user PD. */ 727 resp.dpi = ucntx->dpi.dpi; 728 729 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr, 730 BNXT_RE_MMAP_UC_DB, &resp.dbr); 731 732 if (!entry) { 733 rc = -ENOMEM; 734 goto dbfail; 735 } 736 737 pd->pd_db_mmap = &entry->rdma_entry; 738 739 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 740 if (rc) { 741 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 742 rc = -EFAULT; 743 goto dbfail; 744 } 745 } 746 747 if (!udata) 748 if (bnxt_re_create_fence_mr(pd)) 749 ibdev_warn(&rdev->ibdev, 750 "Failed to create Fence-MR\n"); 751 active_pds = atomic_inc_return(&rdev->stats.res.pd_count); 752 if (active_pds > rdev->stats.res.pd_watermark) 753 rdev->stats.res.pd_watermark = active_pds; 754 755 return 0; 756 dbfail: 757 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 758 &pd->qplib_pd); 759 fail: 760 return rc; 761 } 762 763 /* Address Handles */ 764 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 765 { 766 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 767 struct bnxt_re_dev *rdev = ah->rdev; 768 bool block = true; 769 int rc; 770 771 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE); 772 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block); 773 if (BNXT_RE_CHECK_RC(rc)) { 774 if (rc == -ETIMEDOUT) 775 rc = 0; 776 else 777 goto fail; 778 } 779 atomic_dec(&rdev->stats.res.ah_count); 780 fail: 781 return rc; 782 } 783 784 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 785 { 786 u8 nw_type; 787 788 switch (ntype) { 789 case RDMA_NETWORK_IPV4: 790 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 791 break; 792 case RDMA_NETWORK_IPV6: 793 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 794 break; 795 default: 796 nw_type = CMDQ_CREATE_AH_TYPE_V1; 797 break; 798 } 799 return nw_type; 800 } 801 802 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr, 803 struct ib_udata *udata) 804 { 805 struct ib_pd *ib_pd = ib_ah->pd; 806 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 807 struct rdma_ah_attr *ah_attr = init_attr->ah_attr; 808 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 809 struct bnxt_re_dev *rdev = pd->rdev; 810 const struct ib_gid_attr *sgid_attr; 811 struct bnxt_re_gid_ctx *ctx; 812 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 813 u32 active_ahs; 814 u8 nw_type; 815 int rc; 816 817 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 818 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set"); 819 return -EINVAL; 820 } 821 822 ah->rdev = rdev; 823 ah->qplib_ah.pd = &pd->qplib_pd; 824 825 /* Supply the configuration for the HW */ 826 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 827 sizeof(union ib_gid)); 828 sgid_attr = grh->sgid_attr; 829 /* Get the HW context of the GID. The reference 830 * of GID table entry is already taken by the caller. 831 */ 832 ctx = rdma_read_gid_hw_context(sgid_attr); 833 ah->qplib_ah.sgid_index = ctx->idx; 834 ah->qplib_ah.host_sgid_index = grh->sgid_index; 835 ah->qplib_ah.traffic_class = grh->traffic_class; 836 ah->qplib_ah.flow_label = grh->flow_label; 837 ah->qplib_ah.hop_limit = grh->hop_limit; 838 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 839 840 /* Get network header type for this GID */ 841 nw_type = rdma_gid_attr_network_type(sgid_attr); 842 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 843 844 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 845 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 846 !(init_attr->flags & 847 RDMA_CREATE_AH_SLEEPABLE)); 848 if (rc) { 849 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH"); 850 return rc; 851 } 852 853 /* Write AVID to shared page. */ 854 if (udata) { 855 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 856 udata, struct bnxt_re_ucontext, ib_uctx); 857 unsigned long flag; 858 u32 *wrptr; 859 860 spin_lock_irqsave(&uctx->sh_lock, flag); 861 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 862 *wrptr = ah->qplib_ah.id; 863 wmb(); /* make sure cache is updated. */ 864 spin_unlock_irqrestore(&uctx->sh_lock, flag); 865 } 866 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count); 867 if (active_ahs > rdev->stats.res.ah_watermark) 868 rdev->stats.res.ah_watermark = active_ahs; 869 870 return 0; 871 } 872 873 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 874 { 875 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 876 877 ah_attr->type = ib_ah->type; 878 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 879 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 880 rdma_ah_set_grh(ah_attr, NULL, 0, 881 ah->qplib_ah.host_sgid_index, 882 0, ah->qplib_ah.traffic_class); 883 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 884 rdma_ah_set_port_num(ah_attr, 1); 885 rdma_ah_set_static_rate(ah_attr, 0); 886 return 0; 887 } 888 889 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 890 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 891 { 892 unsigned long flags; 893 894 spin_lock_irqsave(&qp->scq->cq_lock, flags); 895 if (qp->rcq != qp->scq) 896 spin_lock(&qp->rcq->cq_lock); 897 else 898 __acquire(&qp->rcq->cq_lock); 899 900 return flags; 901 } 902 903 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 904 unsigned long flags) 905 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 906 { 907 if (qp->rcq != qp->scq) 908 spin_unlock(&qp->rcq->cq_lock); 909 else 910 __release(&qp->rcq->cq_lock); 911 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 912 } 913 914 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp) 915 { 916 struct bnxt_re_qp *gsi_sqp; 917 struct bnxt_re_ah *gsi_sah; 918 struct bnxt_re_dev *rdev; 919 int rc; 920 921 rdev = qp->rdev; 922 gsi_sqp = rdev->gsi_ctx.gsi_sqp; 923 gsi_sah = rdev->gsi_ctx.gsi_sah; 924 925 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n"); 926 bnxt_qplib_destroy_ah(&rdev->qplib_res, 927 &gsi_sah->qplib_ah, 928 true); 929 atomic_dec(&rdev->stats.res.ah_count); 930 bnxt_qplib_clean_qp(&qp->qplib_qp); 931 932 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n"); 933 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp); 934 if (rc) { 935 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed"); 936 goto fail; 937 } 938 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp); 939 940 /* remove from active qp list */ 941 mutex_lock(&rdev->qp_lock); 942 list_del(&gsi_sqp->list); 943 mutex_unlock(&rdev->qp_lock); 944 atomic_dec(&rdev->stats.res.qp_count); 945 946 kfree(rdev->gsi_ctx.sqp_tbl); 947 kfree(gsi_sah); 948 kfree(gsi_sqp); 949 rdev->gsi_ctx.gsi_sqp = NULL; 950 rdev->gsi_ctx.gsi_sah = NULL; 951 rdev->gsi_ctx.sqp_tbl = NULL; 952 953 return 0; 954 fail: 955 return rc; 956 } 957 958 /* Queue Pairs */ 959 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 960 { 961 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 962 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 963 struct bnxt_re_dev *rdev = qp->rdev; 964 struct bnxt_qplib_nq *scq_nq = NULL; 965 struct bnxt_qplib_nq *rcq_nq = NULL; 966 unsigned int flags; 967 int rc; 968 969 bnxt_re_debug_rem_qpinfo(rdev, qp); 970 971 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 972 973 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 974 if (rc) 975 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP"); 976 977 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 978 flags = bnxt_re_lock_cqs(qp); 979 bnxt_qplib_clean_qp(&qp->qplib_qp); 980 bnxt_re_unlock_cqs(qp, flags); 981 } 982 983 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 984 985 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 986 bnxt_re_destroy_gsi_sqp(qp); 987 988 mutex_lock(&rdev->qp_lock); 989 list_del(&qp->list); 990 mutex_unlock(&rdev->qp_lock); 991 atomic_dec(&rdev->stats.res.qp_count); 992 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC) 993 atomic_dec(&rdev->stats.res.rc_qp_count); 994 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD) 995 atomic_dec(&rdev->stats.res.ud_qp_count); 996 997 ib_umem_release(qp->rumem); 998 ib_umem_release(qp->sumem); 999 1000 /* Flush all the entries of notification queue associated with 1001 * given qp. 1002 */ 1003 scq_nq = qplib_qp->scq->nq; 1004 rcq_nq = qplib_qp->rcq->nq; 1005 bnxt_re_synchronize_nq(scq_nq); 1006 if (scq_nq != rcq_nq) 1007 bnxt_re_synchronize_nq(rcq_nq); 1008 1009 return 0; 1010 } 1011 1012 static u8 __from_ib_qp_type(enum ib_qp_type type) 1013 { 1014 switch (type) { 1015 case IB_QPT_GSI: 1016 return CMDQ_CREATE_QP1_TYPE_GSI; 1017 case IB_QPT_RC: 1018 return CMDQ_CREATE_QP_TYPE_RC; 1019 case IB_QPT_UD: 1020 return CMDQ_CREATE_QP_TYPE_UD; 1021 default: 1022 return IB_QPT_MAX; 1023 } 1024 } 1025 1026 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp, 1027 int rsge, int max) 1028 { 1029 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 1030 rsge = max; 1031 return bnxt_re_get_rwqe_size(rsge); 1032 } 1033 1034 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge) 1035 { 1036 u16 wqe_size, calc_ils; 1037 1038 wqe_size = bnxt_re_get_swqe_size(nsge); 1039 if (ilsize) { 1040 calc_ils = sizeof(struct sq_send_hdr) + ilsize; 1041 wqe_size = max_t(u16, calc_ils, wqe_size); 1042 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr)); 1043 } 1044 return wqe_size; 1045 } 1046 1047 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp, 1048 struct ib_qp_init_attr *init_attr) 1049 { 1050 struct bnxt_qplib_dev_attr *dev_attr; 1051 struct bnxt_qplib_qp *qplqp; 1052 struct bnxt_re_dev *rdev; 1053 struct bnxt_qplib_q *sq; 1054 int align, ilsize; 1055 1056 rdev = qp->rdev; 1057 qplqp = &qp->qplib_qp; 1058 sq = &qplqp->sq; 1059 dev_attr = rdev->dev_attr; 1060 1061 align = sizeof(struct sq_send_hdr); 1062 ilsize = ALIGN(init_attr->cap.max_inline_data, align); 1063 1064 /* For gen p4 and gen p5 fixed wqe compatibility mode 1065 * wqe size is fixed to 128 bytes - ie 6 SGEs 1066 */ 1067 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) { 1068 sq->wqe_size = bnxt_re_get_swqe_size(BNXT_STATIC_MAX_SGE); 1069 sq->max_sge = BNXT_STATIC_MAX_SGE; 1070 } else { 1071 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge); 1072 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges)) 1073 return -EINVAL; 1074 } 1075 1076 if (init_attr->cap.max_inline_data) { 1077 qplqp->max_inline_data = sq->wqe_size - 1078 sizeof(struct sq_send_hdr); 1079 init_attr->cap.max_inline_data = qplqp->max_inline_data; 1080 } 1081 1082 return 0; 1083 } 1084 1085 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 1086 struct bnxt_re_qp *qp, struct bnxt_re_ucontext *cntx, 1087 struct bnxt_re_qp_req *ureq) 1088 { 1089 struct bnxt_qplib_qp *qplib_qp; 1090 int bytes = 0, psn_sz; 1091 struct ib_umem *umem; 1092 int psn_nume; 1093 1094 qplib_qp = &qp->qplib_qp; 1095 1096 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size); 1097 /* Consider mapping PSN search memory only for RC QPs. */ 1098 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 1099 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 1100 sizeof(struct sq_psn_search_ext) : 1101 sizeof(struct sq_psn_search); 1102 if (cntx && bnxt_re_is_var_size_supported(rdev, cntx)) { 1103 psn_nume = ureq->sq_slots; 1104 } else { 1105 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 1106 qplib_qp->sq.max_wqe : ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) / 1107 sizeof(struct bnxt_qplib_sge)); 1108 } 1109 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 1110 psn_nume = roundup_pow_of_two(psn_nume); 1111 bytes += (psn_nume * psn_sz); 1112 } 1113 1114 bytes = PAGE_ALIGN(bytes); 1115 umem = ib_umem_get(&rdev->ibdev, ureq->qpsva, bytes, 1116 IB_ACCESS_LOCAL_WRITE); 1117 if (IS_ERR(umem)) 1118 return PTR_ERR(umem); 1119 1120 qp->sumem = umem; 1121 qplib_qp->sq.sg_info.umem = umem; 1122 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE; 1123 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT; 1124 qplib_qp->qp_handle = ureq->qp_handle; 1125 1126 if (!qp->qplib_qp.srq) { 1127 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size); 1128 bytes = PAGE_ALIGN(bytes); 1129 umem = ib_umem_get(&rdev->ibdev, ureq->qprva, bytes, 1130 IB_ACCESS_LOCAL_WRITE); 1131 if (IS_ERR(umem)) 1132 goto rqfail; 1133 qp->rumem = umem; 1134 qplib_qp->rq.sg_info.umem = umem; 1135 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE; 1136 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT; 1137 } 1138 1139 qplib_qp->dpi = &cntx->dpi; 1140 return 0; 1141 rqfail: 1142 ib_umem_release(qp->sumem); 1143 qp->sumem = NULL; 1144 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 1145 1146 return PTR_ERR(umem); 1147 } 1148 1149 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 1150 (struct bnxt_re_pd *pd, 1151 struct bnxt_qplib_res *qp1_res, 1152 struct bnxt_qplib_qp *qp1_qp) 1153 { 1154 struct bnxt_re_dev *rdev = pd->rdev; 1155 struct bnxt_re_ah *ah; 1156 union ib_gid sgid; 1157 int rc; 1158 1159 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 1160 if (!ah) 1161 return NULL; 1162 1163 ah->rdev = rdev; 1164 ah->qplib_ah.pd = &pd->qplib_pd; 1165 1166 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 1167 if (rc) 1168 goto fail; 1169 1170 /* supply the dgid data same as sgid */ 1171 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 1172 sizeof(union ib_gid)); 1173 ah->qplib_ah.sgid_index = 0; 1174 1175 ah->qplib_ah.traffic_class = 0; 1176 ah->qplib_ah.flow_label = 0; 1177 ah->qplib_ah.hop_limit = 1; 1178 ah->qplib_ah.sl = 0; 1179 /* Have DMAC same as SMAC */ 1180 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 1181 1182 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 1183 if (rc) { 1184 ibdev_err(&rdev->ibdev, 1185 "Failed to allocate HW AH for Shadow QP"); 1186 goto fail; 1187 } 1188 atomic_inc(&rdev->stats.res.ah_count); 1189 1190 return ah; 1191 1192 fail: 1193 kfree(ah); 1194 return NULL; 1195 } 1196 1197 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 1198 (struct bnxt_re_pd *pd, 1199 struct bnxt_qplib_res *qp1_res, 1200 struct bnxt_qplib_qp *qp1_qp) 1201 { 1202 struct bnxt_re_dev *rdev = pd->rdev; 1203 struct bnxt_re_qp *qp; 1204 int rc; 1205 1206 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1207 if (!qp) 1208 return NULL; 1209 1210 qp->rdev = rdev; 1211 1212 /* Initialize the shadow QP structure from the QP1 values */ 1213 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1214 1215 qp->qplib_qp.pd = &pd->qplib_pd; 1216 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1217 qp->qplib_qp.type = IB_QPT_UD; 1218 1219 qp->qplib_qp.max_inline_data = 0; 1220 qp->qplib_qp.sig_type = true; 1221 1222 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 1223 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6); 1224 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1225 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe; 1226 qp->qplib_qp.sq.max_sge = 2; 1227 /* Q full delta can be 1 since it is internal QP */ 1228 qp->qplib_qp.sq.q_full_delta = 1; 1229 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE; 1230 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT; 1231 1232 qp->qplib_qp.scq = qp1_qp->scq; 1233 qp->qplib_qp.rcq = qp1_qp->rcq; 1234 1235 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6); 1236 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1237 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe; 1238 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1239 /* Q full delta can be 1 since it is internal QP */ 1240 qp->qplib_qp.rq.q_full_delta = 1; 1241 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE; 1242 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT; 1243 1244 qp->qplib_qp.mtu = qp1_qp->mtu; 1245 1246 qp->qplib_qp.sq_hdr_buf_size = 0; 1247 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1248 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1249 1250 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1251 if (rc) 1252 goto fail; 1253 1254 spin_lock_init(&qp->sq_lock); 1255 INIT_LIST_HEAD(&qp->list); 1256 mutex_lock(&rdev->qp_lock); 1257 list_add_tail(&qp->list, &rdev->qp_list); 1258 atomic_inc(&rdev->stats.res.qp_count); 1259 mutex_unlock(&rdev->qp_lock); 1260 return qp; 1261 fail: 1262 kfree(qp); 1263 return NULL; 1264 } 1265 1266 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 1267 struct ib_qp_init_attr *init_attr, 1268 struct bnxt_re_ucontext *uctx) 1269 { 1270 struct bnxt_qplib_dev_attr *dev_attr; 1271 struct bnxt_qplib_qp *qplqp; 1272 struct bnxt_re_dev *rdev; 1273 struct bnxt_qplib_q *rq; 1274 int entries; 1275 1276 rdev = qp->rdev; 1277 qplqp = &qp->qplib_qp; 1278 rq = &qplqp->rq; 1279 dev_attr = rdev->dev_attr; 1280 1281 if (init_attr->srq) { 1282 struct bnxt_re_srq *srq; 1283 1284 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq); 1285 qplqp->srq = &srq->qplib_srq; 1286 rq->max_wqe = 0; 1287 } else { 1288 rq->max_sge = init_attr->cap.max_recv_sge; 1289 if (rq->max_sge > dev_attr->max_qp_sges) 1290 rq->max_sge = dev_attr->max_qp_sges; 1291 init_attr->cap.max_recv_sge = rq->max_sge; 1292 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge, 1293 dev_attr->max_qp_sges); 1294 /* Allocate 1 more than what's provided so posting max doesn't 1295 * mean empty. 1296 */ 1297 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx); 1298 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1299 rq->max_sw_wqe = rq->max_wqe; 1300 rq->q_full_delta = 0; 1301 rq->sg_info.pgsize = PAGE_SIZE; 1302 rq->sg_info.pgshft = PAGE_SHIFT; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 1309 { 1310 struct bnxt_qplib_dev_attr *dev_attr; 1311 struct bnxt_qplib_qp *qplqp; 1312 struct bnxt_re_dev *rdev; 1313 1314 rdev = qp->rdev; 1315 qplqp = &qp->qplib_qp; 1316 dev_attr = rdev->dev_attr; 1317 1318 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1319 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1320 if (qplqp->rq.max_sge > dev_attr->max_qp_sges) 1321 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1322 qplqp->rq.max_sge = 6; 1323 } 1324 } 1325 1326 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 1327 struct ib_qp_init_attr *init_attr, 1328 struct bnxt_re_ucontext *uctx, 1329 struct bnxt_re_qp_req *ureq) 1330 { 1331 struct bnxt_qplib_dev_attr *dev_attr; 1332 struct bnxt_qplib_qp *qplqp; 1333 struct bnxt_re_dev *rdev; 1334 struct bnxt_qplib_q *sq; 1335 int diff = 0; 1336 int entries; 1337 int rc; 1338 1339 rdev = qp->rdev; 1340 qplqp = &qp->qplib_qp; 1341 sq = &qplqp->sq; 1342 dev_attr = rdev->dev_attr; 1343 1344 sq->max_sge = init_attr->cap.max_send_sge; 1345 entries = init_attr->cap.max_send_wr; 1346 if (uctx && qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) { 1347 sq->max_wqe = ureq->sq_slots; 1348 sq->max_sw_wqe = ureq->sq_slots; 1349 sq->wqe_size = sizeof(struct sq_sge); 1350 } else { 1351 if (sq->max_sge > dev_attr->max_qp_sges) { 1352 sq->max_sge = dev_attr->max_qp_sges; 1353 init_attr->cap.max_send_sge = sq->max_sge; 1354 } 1355 1356 rc = bnxt_re_setup_swqe_size(qp, init_attr); 1357 if (rc) 1358 return rc; 1359 1360 /* Allocate 128 + 1 more than what's provided */ 1361 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ? 1362 0 : BNXT_QPLIB_RESERVED_QP_WRS; 1363 entries = bnxt_re_init_depth(entries + diff + 1, uctx); 1364 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1); 1365 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 1366 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true); 1367 else 1368 sq->max_sw_wqe = sq->max_wqe; 1369 1370 } 1371 sq->q_full_delta = diff + 1; 1372 /* 1373 * Reserving one slot for Phantom WQE. Application can 1374 * post one extra entry in this case. But allowing this to avoid 1375 * unexpected Queue full condition 1376 */ 1377 qplqp->sq.q_full_delta -= 1; 1378 qplqp->sq.sg_info.pgsize = PAGE_SIZE; 1379 qplqp->sq.sg_info.pgshft = PAGE_SHIFT; 1380 1381 return 0; 1382 } 1383 1384 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 1385 struct ib_qp_init_attr *init_attr, 1386 struct bnxt_re_ucontext *uctx) 1387 { 1388 struct bnxt_qplib_dev_attr *dev_attr; 1389 struct bnxt_qplib_qp *qplqp; 1390 struct bnxt_re_dev *rdev; 1391 int entries; 1392 1393 rdev = qp->rdev; 1394 qplqp = &qp->qplib_qp; 1395 dev_attr = rdev->dev_attr; 1396 1397 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1398 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx); 1399 qplqp->sq.max_wqe = min_t(u32, entries, 1400 dev_attr->max_qp_wqes + 1); 1401 qplqp->sq.q_full_delta = qplqp->sq.max_wqe - 1402 init_attr->cap.max_send_wr; 1403 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ 1404 if (qplqp->sq.max_sge > dev_attr->max_qp_sges) 1405 qplqp->sq.max_sge = dev_attr->max_qp_sges; 1406 } 1407 } 1408 1409 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 1410 struct ib_qp_init_attr *init_attr) 1411 { 1412 struct bnxt_qplib_chip_ctx *chip_ctx; 1413 int qptype; 1414 1415 chip_ctx = rdev->chip_ctx; 1416 1417 qptype = __from_ib_qp_type(init_attr->qp_type); 1418 if (qptype == IB_QPT_MAX) { 1419 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype); 1420 qptype = -EOPNOTSUPP; 1421 goto out; 1422 } 1423 1424 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) && 1425 init_attr->qp_type == IB_QPT_GSI) 1426 qptype = CMDQ_CREATE_QP_TYPE_GSI; 1427 out: 1428 return qptype; 1429 } 1430 1431 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1432 struct ib_qp_init_attr *init_attr, 1433 struct bnxt_re_ucontext *uctx, 1434 struct bnxt_re_qp_req *ureq) 1435 { 1436 struct bnxt_qplib_dev_attr *dev_attr; 1437 struct bnxt_qplib_qp *qplqp; 1438 struct bnxt_re_dev *rdev; 1439 struct bnxt_re_cq *cq; 1440 int rc = 0, qptype; 1441 1442 rdev = qp->rdev; 1443 qplqp = &qp->qplib_qp; 1444 dev_attr = rdev->dev_attr; 1445 1446 /* Setup misc params */ 1447 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); 1448 qplqp->pd = &pd->qplib_pd; 1449 qplqp->qp_handle = (u64)qplqp; 1450 qplqp->max_inline_data = init_attr->cap.max_inline_data; 1451 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR; 1452 qptype = bnxt_re_init_qp_type(rdev, init_attr); 1453 if (qptype < 0) { 1454 rc = qptype; 1455 goto out; 1456 } 1457 qplqp->type = (u8)qptype; 1458 qplqp->wqe_mode = bnxt_re_is_var_size_supported(rdev, uctx); 1459 if (init_attr->qp_type == IB_QPT_RC) { 1460 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom; 1461 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1462 } 1463 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1464 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */ 1465 if (init_attr->create_flags) { 1466 ibdev_dbg(&rdev->ibdev, 1467 "QP create flags 0x%x not supported", 1468 init_attr->create_flags); 1469 return -EOPNOTSUPP; 1470 } 1471 1472 /* Setup CQs */ 1473 if (init_attr->send_cq) { 1474 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq); 1475 qplqp->scq = &cq->qplib_cq; 1476 qp->scq = cq; 1477 } 1478 1479 if (init_attr->recv_cq) { 1480 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq); 1481 qplqp->rcq = &cq->qplib_cq; 1482 qp->rcq = cq; 1483 } 1484 1485 /* Setup RQ/SRQ */ 1486 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx); 1487 if (rc) 1488 goto out; 1489 if (init_attr->qp_type == IB_QPT_GSI) 1490 bnxt_re_adjust_gsi_rq_attr(qp); 1491 1492 /* Setup SQ */ 1493 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx, ureq); 1494 if (rc) 1495 goto out; 1496 if (init_attr->qp_type == IB_QPT_GSI) 1497 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx); 1498 1499 if (uctx) /* This will update DPI and qp_handle */ 1500 rc = bnxt_re_init_user_qp(rdev, pd, qp, uctx, ureq); 1501 out: 1502 return rc; 1503 } 1504 1505 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp, 1506 struct bnxt_re_pd *pd) 1507 { 1508 struct bnxt_re_sqp_entries *sqp_tbl; 1509 struct bnxt_re_dev *rdev; 1510 struct bnxt_re_qp *sqp; 1511 struct bnxt_re_ah *sah; 1512 int rc = 0; 1513 1514 rdev = qp->rdev; 1515 /* Create a shadow QP to handle the QP1 traffic */ 1516 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl), 1517 GFP_KERNEL); 1518 if (!sqp_tbl) 1519 return -ENOMEM; 1520 rdev->gsi_ctx.sqp_tbl = sqp_tbl; 1521 1522 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp); 1523 if (!sqp) { 1524 rc = -ENODEV; 1525 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1"); 1526 goto out; 1527 } 1528 rdev->gsi_ctx.gsi_sqp = sqp; 1529 1530 sqp->rcq = qp->rcq; 1531 sqp->scq = qp->scq; 1532 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1533 &qp->qplib_qp); 1534 if (!sah) { 1535 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1536 &sqp->qplib_qp); 1537 rc = -ENODEV; 1538 ibdev_err(&rdev->ibdev, 1539 "Failed to create AH entry for ShadowQP"); 1540 goto out; 1541 } 1542 rdev->gsi_ctx.gsi_sah = sah; 1543 1544 return 0; 1545 out: 1546 kfree(sqp_tbl); 1547 return rc; 1548 } 1549 1550 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1551 struct ib_qp_init_attr *init_attr) 1552 { 1553 struct bnxt_re_dev *rdev; 1554 struct bnxt_qplib_qp *qplqp; 1555 int rc; 1556 1557 rdev = qp->rdev; 1558 qplqp = &qp->qplib_qp; 1559 1560 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1561 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1562 1563 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp); 1564 if (rc) { 1565 ibdev_err(&rdev->ibdev, "create HW QP1 failed!"); 1566 goto out; 1567 } 1568 1569 rc = bnxt_re_create_shadow_gsi(qp, pd); 1570 out: 1571 return rc; 1572 } 1573 1574 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev, 1575 struct ib_qp_init_attr *init_attr, 1576 struct bnxt_qplib_dev_attr *dev_attr) 1577 { 1578 bool rc = true; 1579 1580 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes || 1581 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes || 1582 init_attr->cap.max_send_sge > dev_attr->max_qp_sges || 1583 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges || 1584 init_attr->cap.max_inline_data > dev_attr->max_inline_data) { 1585 ibdev_err(&rdev->ibdev, 1586 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x", 1587 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes, 1588 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes, 1589 init_attr->cap.max_send_sge, dev_attr->max_qp_sges, 1590 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges, 1591 init_attr->cap.max_inline_data, 1592 dev_attr->max_inline_data); 1593 rc = false; 1594 } 1595 return rc; 1596 } 1597 1598 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr, 1599 struct ib_udata *udata) 1600 { 1601 struct bnxt_qplib_dev_attr *dev_attr; 1602 struct bnxt_re_ucontext *uctx; 1603 struct bnxt_re_qp_req ureq; 1604 struct bnxt_re_dev *rdev; 1605 struct bnxt_re_pd *pd; 1606 struct bnxt_re_qp *qp; 1607 struct ib_pd *ib_pd; 1608 u32 active_qps; 1609 int rc; 1610 1611 ib_pd = ib_qp->pd; 1612 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1613 rdev = pd->rdev; 1614 dev_attr = rdev->dev_attr; 1615 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1616 1617 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1618 if (udata) 1619 if (ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)))) 1620 return -EFAULT; 1621 1622 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr); 1623 if (!rc) { 1624 rc = -EINVAL; 1625 goto fail; 1626 } 1627 1628 qp->rdev = rdev; 1629 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, uctx, &ureq); 1630 if (rc) 1631 goto fail; 1632 1633 if (qp_init_attr->qp_type == IB_QPT_GSI && 1634 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) { 1635 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr); 1636 if (rc == -ENODEV) 1637 goto qp_destroy; 1638 if (rc) 1639 goto fail; 1640 } else { 1641 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1642 if (rc) { 1643 ibdev_err(&rdev->ibdev, "Failed to create HW QP"); 1644 goto free_umem; 1645 } 1646 if (udata) { 1647 struct bnxt_re_qp_resp resp; 1648 1649 resp.qpid = qp->qplib_qp.id; 1650 resp.rsvd = 0; 1651 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1652 if (rc) { 1653 ibdev_err(&rdev->ibdev, "Failed to copy QP udata"); 1654 goto qp_destroy; 1655 } 1656 } 1657 } 1658 1659 qp->ib_qp.qp_num = qp->qplib_qp.id; 1660 if (qp_init_attr->qp_type == IB_QPT_GSI) 1661 rdev->gsi_ctx.gsi_qp = qp; 1662 spin_lock_init(&qp->sq_lock); 1663 spin_lock_init(&qp->rq_lock); 1664 INIT_LIST_HEAD(&qp->list); 1665 mutex_lock(&rdev->qp_lock); 1666 list_add_tail(&qp->list, &rdev->qp_list); 1667 mutex_unlock(&rdev->qp_lock); 1668 active_qps = atomic_inc_return(&rdev->stats.res.qp_count); 1669 if (active_qps > rdev->stats.res.qp_watermark) 1670 rdev->stats.res.qp_watermark = active_qps; 1671 if (qp_init_attr->qp_type == IB_QPT_RC) { 1672 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count); 1673 if (active_qps > rdev->stats.res.rc_qp_watermark) 1674 rdev->stats.res.rc_qp_watermark = active_qps; 1675 } else if (qp_init_attr->qp_type == IB_QPT_UD) { 1676 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count); 1677 if (active_qps > rdev->stats.res.ud_qp_watermark) 1678 rdev->stats.res.ud_qp_watermark = active_qps; 1679 } 1680 bnxt_re_debug_add_qpinfo(rdev, qp); 1681 1682 return 0; 1683 qp_destroy: 1684 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1685 free_umem: 1686 ib_umem_release(qp->rumem); 1687 ib_umem_release(qp->sumem); 1688 fail: 1689 return rc; 1690 } 1691 1692 static u8 __from_ib_qp_state(enum ib_qp_state state) 1693 { 1694 switch (state) { 1695 case IB_QPS_RESET: 1696 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1697 case IB_QPS_INIT: 1698 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1699 case IB_QPS_RTR: 1700 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1701 case IB_QPS_RTS: 1702 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1703 case IB_QPS_SQD: 1704 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1705 case IB_QPS_SQE: 1706 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1707 case IB_QPS_ERR: 1708 default: 1709 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1710 } 1711 } 1712 1713 static enum ib_qp_state __to_ib_qp_state(u8 state) 1714 { 1715 switch (state) { 1716 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1717 return IB_QPS_RESET; 1718 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1719 return IB_QPS_INIT; 1720 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1721 return IB_QPS_RTR; 1722 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1723 return IB_QPS_RTS; 1724 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1725 return IB_QPS_SQD; 1726 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1727 return IB_QPS_SQE; 1728 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1729 default: 1730 return IB_QPS_ERR; 1731 } 1732 } 1733 1734 static u32 __from_ib_mtu(enum ib_mtu mtu) 1735 { 1736 switch (mtu) { 1737 case IB_MTU_256: 1738 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1739 case IB_MTU_512: 1740 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1741 case IB_MTU_1024: 1742 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1743 case IB_MTU_2048: 1744 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1745 case IB_MTU_4096: 1746 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1747 default: 1748 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1749 } 1750 } 1751 1752 static enum ib_mtu __to_ib_mtu(u32 mtu) 1753 { 1754 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1755 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1756 return IB_MTU_256; 1757 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1758 return IB_MTU_512; 1759 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1760 return IB_MTU_1024; 1761 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1762 return IB_MTU_2048; 1763 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1764 return IB_MTU_4096; 1765 default: 1766 return IB_MTU_2048; 1767 } 1768 } 1769 1770 /* Shared Receive Queues */ 1771 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1772 { 1773 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1774 ib_srq); 1775 struct bnxt_re_dev *rdev = srq->rdev; 1776 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1777 struct bnxt_qplib_nq *nq = NULL; 1778 1779 if (qplib_srq->cq) 1780 nq = qplib_srq->cq->nq; 1781 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) { 1782 free_page((unsigned long)srq->uctx_srq_page); 1783 hash_del(&srq->hash_entry); 1784 } 1785 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1786 ib_umem_release(srq->umem); 1787 atomic_dec(&rdev->stats.res.srq_count); 1788 if (nq) 1789 nq->budget--; 1790 return 0; 1791 } 1792 1793 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1794 struct bnxt_re_pd *pd, 1795 struct bnxt_re_srq *srq, 1796 struct ib_udata *udata) 1797 { 1798 struct bnxt_re_srq_req ureq; 1799 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1800 struct ib_umem *umem; 1801 int bytes = 0; 1802 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1803 udata, struct bnxt_re_ucontext, ib_uctx); 1804 1805 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1806 return -EFAULT; 1807 1808 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size); 1809 bytes = PAGE_ALIGN(bytes); 1810 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes, 1811 IB_ACCESS_LOCAL_WRITE); 1812 if (IS_ERR(umem)) 1813 return PTR_ERR(umem); 1814 1815 srq->umem = umem; 1816 qplib_srq->sg_info.umem = umem; 1817 qplib_srq->sg_info.pgsize = PAGE_SIZE; 1818 qplib_srq->sg_info.pgshft = PAGE_SHIFT; 1819 qplib_srq->srq_handle = ureq.srq_handle; 1820 qplib_srq->dpi = &cntx->dpi; 1821 1822 return 0; 1823 } 1824 1825 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1826 struct ib_srq_init_attr *srq_init_attr, 1827 struct ib_udata *udata) 1828 { 1829 struct bnxt_qplib_dev_attr *dev_attr; 1830 struct bnxt_qplib_nq *nq = NULL; 1831 struct bnxt_re_ucontext *uctx; 1832 struct bnxt_re_dev *rdev; 1833 struct bnxt_re_srq *srq; 1834 struct bnxt_re_pd *pd; 1835 struct ib_pd *ib_pd; 1836 u32 active_srqs; 1837 int rc, entries; 1838 1839 ib_pd = ib_srq->pd; 1840 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1841 rdev = pd->rdev; 1842 dev_attr = rdev->dev_attr; 1843 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1844 1845 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1846 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded"); 1847 rc = -EINVAL; 1848 goto exit; 1849 } 1850 1851 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1852 rc = -EOPNOTSUPP; 1853 goto exit; 1854 } 1855 1856 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1857 srq->rdev = rdev; 1858 srq->qplib_srq.pd = &pd->qplib_pd; 1859 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1860 /* Allocate 1 more than what's provided so posting max doesn't 1861 * mean empty 1862 */ 1863 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx); 1864 if (entries > dev_attr->max_srq_wqes + 1) 1865 entries = dev_attr->max_srq_wqes + 1; 1866 srq->qplib_srq.max_wqe = entries; 1867 1868 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1869 /* 128 byte wqe size for SRQ . So use max sges */ 1870 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges); 1871 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1872 srq->srq_limit = srq_init_attr->attr.srq_limit; 1873 srq->qplib_srq.eventq_hw_ring_id = rdev->nqr->nq[0].ring_id; 1874 srq->qplib_srq.sg_info.pgsize = PAGE_SIZE; 1875 srq->qplib_srq.sg_info.pgshft = PAGE_SHIFT; 1876 nq = &rdev->nqr->nq[0]; 1877 1878 if (udata) { 1879 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1880 if (rc) 1881 goto fail; 1882 } 1883 1884 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1885 if (rc) { 1886 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!"); 1887 goto fail; 1888 } 1889 1890 if (udata) { 1891 struct bnxt_re_srq_resp resp = {}; 1892 1893 resp.srqid = srq->qplib_srq.id; 1894 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) { 1895 hash_add(rdev->srq_hash, &srq->hash_entry, srq->qplib_srq.id); 1896 srq->uctx_srq_page = (void *)get_zeroed_page(GFP_KERNEL); 1897 if (!srq->uctx_srq_page) { 1898 rc = -ENOMEM; 1899 goto fail; 1900 } 1901 resp.comp_mask |= BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT; 1902 } 1903 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1904 if (rc) { 1905 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!"); 1906 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1907 &srq->qplib_srq); 1908 goto fail; 1909 } 1910 } 1911 if (nq) 1912 nq->budget++; 1913 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count); 1914 if (active_srqs > rdev->stats.res.srq_watermark) 1915 rdev->stats.res.srq_watermark = active_srqs; 1916 spin_lock_init(&srq->lock); 1917 1918 return 0; 1919 1920 fail: 1921 ib_umem_release(srq->umem); 1922 exit: 1923 return rc; 1924 } 1925 1926 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1927 enum ib_srq_attr_mask srq_attr_mask, 1928 struct ib_udata *udata) 1929 { 1930 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1931 ib_srq); 1932 struct bnxt_re_dev *rdev = srq->rdev; 1933 int rc; 1934 1935 switch (srq_attr_mask) { 1936 case IB_SRQ_MAX_WR: 1937 /* SRQ resize is not supported */ 1938 return -EINVAL; 1939 case IB_SRQ_LIMIT: 1940 /* Change the SRQ threshold */ 1941 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1942 return -EINVAL; 1943 1944 srq->qplib_srq.threshold = srq_attr->srq_limit; 1945 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1946 if (rc) { 1947 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!"); 1948 return rc; 1949 } 1950 /* On success, update the shadow */ 1951 srq->srq_limit = srq_attr->srq_limit; 1952 /* No need to Build and send response back to udata */ 1953 return 0; 1954 default: 1955 ibdev_err(&rdev->ibdev, 1956 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1957 return -EINVAL; 1958 } 1959 } 1960 1961 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1962 { 1963 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1964 ib_srq); 1965 struct bnxt_re_srq tsrq; 1966 struct bnxt_re_dev *rdev = srq->rdev; 1967 int rc; 1968 1969 /* Get live SRQ attr */ 1970 tsrq.qplib_srq.id = srq->qplib_srq.id; 1971 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1972 if (rc) { 1973 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!"); 1974 return rc; 1975 } 1976 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1977 srq_attr->max_sge = srq->qplib_srq.max_sge; 1978 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1979 1980 return 0; 1981 } 1982 1983 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1984 const struct ib_recv_wr **bad_wr) 1985 { 1986 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1987 ib_srq); 1988 struct bnxt_qplib_swqe wqe; 1989 unsigned long flags; 1990 int rc = 0; 1991 1992 spin_lock_irqsave(&srq->lock, flags); 1993 while (wr) { 1994 /* Transcribe each ib_recv_wr to qplib_swqe */ 1995 wqe.num_sge = wr->num_sge; 1996 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1997 wqe.wr_id = wr->wr_id; 1998 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1999 2000 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 2001 if (rc) { 2002 *bad_wr = wr; 2003 break; 2004 } 2005 wr = wr->next; 2006 } 2007 spin_unlock_irqrestore(&srq->lock, flags); 2008 2009 return rc; 2010 } 2011 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 2012 struct bnxt_re_qp *qp1_qp, 2013 int qp_attr_mask) 2014 { 2015 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp; 2016 int rc; 2017 2018 if (qp_attr_mask & IB_QP_STATE) { 2019 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 2020 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 2021 } 2022 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 2023 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 2024 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 2025 } 2026 2027 if (qp_attr_mask & IB_QP_QKEY) { 2028 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 2029 /* Using a Random QKEY */ 2030 qp->qplib_qp.qkey = 0x81818181; 2031 } 2032 if (qp_attr_mask & IB_QP_SQ_PSN) { 2033 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2034 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 2035 } 2036 2037 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2038 if (rc) 2039 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1"); 2040 return rc; 2041 } 2042 2043 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2044 int qp_attr_mask, struct ib_udata *udata) 2045 { 2046 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2047 struct bnxt_re_dev *rdev = qp->rdev; 2048 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 2049 enum ib_qp_state curr_qp_state, new_qp_state; 2050 int rc, entries; 2051 unsigned int flags; 2052 u8 nw_type; 2053 2054 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 2055 return -EOPNOTSUPP; 2056 2057 qp->qplib_qp.modify_flags = 0; 2058 if (qp_attr_mask & IB_QP_STATE) { 2059 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 2060 new_qp_state = qp_attr->qp_state; 2061 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 2062 ib_qp->qp_type, qp_attr_mask)) { 2063 ibdev_err(&rdev->ibdev, 2064 "Invalid attribute mask: %#x specified ", 2065 qp_attr_mask); 2066 ibdev_err(&rdev->ibdev, 2067 "for qpn: %#x type: %#x", 2068 ib_qp->qp_num, ib_qp->qp_type); 2069 ibdev_err(&rdev->ibdev, 2070 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 2071 curr_qp_state, new_qp_state); 2072 return -EINVAL; 2073 } 2074 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 2075 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 2076 2077 if (!qp->sumem && 2078 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 2079 ibdev_dbg(&rdev->ibdev, 2080 "Move QP = %p to flush list\n", qp); 2081 flags = bnxt_re_lock_cqs(qp); 2082 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 2083 bnxt_re_unlock_cqs(qp, flags); 2084 } 2085 if (!qp->sumem && 2086 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 2087 ibdev_dbg(&rdev->ibdev, 2088 "Move QP = %p out of flush list\n", qp); 2089 flags = bnxt_re_lock_cqs(qp); 2090 bnxt_qplib_clean_qp(&qp->qplib_qp); 2091 bnxt_re_unlock_cqs(qp, flags); 2092 } 2093 } 2094 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 2095 qp->qplib_qp.modify_flags |= 2096 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 2097 qp->qplib_qp.en_sqd_async_notify = true; 2098 } 2099 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 2100 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 2101 qp->qplib_qp.access = 2102 __qp_access_flags_from_ib(qp->qplib_qp.cctx, 2103 qp_attr->qp_access_flags); 2104 /* LOCAL_WRITE access must be set to allow RC receive */ 2105 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE; 2106 } 2107 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 2108 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 2109 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 2110 } 2111 if (qp_attr_mask & IB_QP_QKEY) { 2112 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 2113 qp->qplib_qp.qkey = qp_attr->qkey; 2114 } 2115 if (qp_attr_mask & IB_QP_AV) { 2116 const struct ib_global_route *grh = 2117 rdma_ah_read_grh(&qp_attr->ah_attr); 2118 const struct ib_gid_attr *sgid_attr; 2119 struct bnxt_re_gid_ctx *ctx; 2120 2121 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 2122 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 2123 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 2124 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 2125 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 2126 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 2127 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 2128 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 2129 sizeof(qp->qplib_qp.ah.dgid.data)); 2130 qp->qplib_qp.ah.flow_label = grh->flow_label; 2131 sgid_attr = grh->sgid_attr; 2132 /* Get the HW context of the GID. The reference 2133 * of GID table entry is already taken by the caller. 2134 */ 2135 ctx = rdma_read_gid_hw_context(sgid_attr); 2136 qp->qplib_qp.ah.sgid_index = ctx->idx; 2137 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 2138 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 2139 qp->qplib_qp.ah.traffic_class = grh->traffic_class >> 2; 2140 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 2141 ether_addr_copy(qp->qplib_qp.ah.dmac, 2142 qp_attr->ah_attr.roce.dmac); 2143 2144 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 2145 &qp->qplib_qp.smac[0]); 2146 if (rc) 2147 return rc; 2148 2149 nw_type = rdma_gid_attr_network_type(sgid_attr); 2150 switch (nw_type) { 2151 case RDMA_NETWORK_IPV4: 2152 qp->qplib_qp.nw_type = 2153 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 2154 break; 2155 case RDMA_NETWORK_IPV6: 2156 qp->qplib_qp.nw_type = 2157 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 2158 break; 2159 default: 2160 qp->qplib_qp.nw_type = 2161 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 2162 break; 2163 } 2164 } 2165 2166 if (qp_attr->qp_state == IB_QPS_RTR) { 2167 enum ib_mtu qpmtu; 2168 2169 qpmtu = iboe_get_mtu(rdev->netdev->mtu); 2170 if (qp_attr_mask & IB_QP_PATH_MTU) { 2171 if (ib_mtu_enum_to_int(qp_attr->path_mtu) > 2172 ib_mtu_enum_to_int(qpmtu)) 2173 return -EINVAL; 2174 qpmtu = qp_attr->path_mtu; 2175 } 2176 2177 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2178 qp->qplib_qp.path_mtu = __from_ib_mtu(qpmtu); 2179 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qpmtu); 2180 } 2181 2182 if (qp_attr_mask & IB_QP_TIMEOUT) { 2183 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 2184 qp->qplib_qp.timeout = qp_attr->timeout; 2185 } 2186 if (qp_attr_mask & IB_QP_RETRY_CNT) { 2187 qp->qplib_qp.modify_flags |= 2188 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 2189 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 2190 } 2191 if (qp_attr_mask & IB_QP_RNR_RETRY) { 2192 qp->qplib_qp.modify_flags |= 2193 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 2194 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 2195 } 2196 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 2197 qp->qplib_qp.modify_flags |= 2198 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 2199 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 2200 } 2201 if (qp_attr_mask & IB_QP_RQ_PSN) { 2202 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 2203 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 2204 } 2205 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2206 qp->qplib_qp.modify_flags |= 2207 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 2208 /* Cap the max_rd_atomic to device max */ 2209 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 2210 dev_attr->max_qp_rd_atom); 2211 } 2212 if (qp_attr_mask & IB_QP_SQ_PSN) { 2213 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2214 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 2215 } 2216 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2217 if (qp_attr->max_dest_rd_atomic > 2218 dev_attr->max_qp_init_rd_atom) { 2219 ibdev_err(&rdev->ibdev, 2220 "max_dest_rd_atomic requested%d is > dev_max%d", 2221 qp_attr->max_dest_rd_atomic, 2222 dev_attr->max_qp_init_rd_atom); 2223 return -EINVAL; 2224 } 2225 2226 qp->qplib_qp.modify_flags |= 2227 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 2228 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 2229 } 2230 if (qp_attr_mask & IB_QP_CAP) { 2231 struct bnxt_re_ucontext *uctx = 2232 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2233 2234 qp->qplib_qp.modify_flags |= 2235 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 2236 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 2237 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 2238 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 2239 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 2240 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 2241 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 2242 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 2243 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 2244 (qp_attr->cap.max_inline_data >= 2245 dev_attr->max_inline_data)) { 2246 ibdev_err(&rdev->ibdev, 2247 "Create QP failed - max exceeded"); 2248 return -EINVAL; 2249 } 2250 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx); 2251 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 2252 dev_attr->max_qp_wqes + 1); 2253 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 2254 qp_attr->cap.max_send_wr; 2255 /* 2256 * Reserving one slot for Phantom WQE. Some application can 2257 * post one extra entry in this case. Allowing this to avoid 2258 * unexpected Queue full condition 2259 */ 2260 qp->qplib_qp.sq.q_full_delta -= 1; 2261 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 2262 if (qp->qplib_qp.rq.max_wqe) { 2263 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx); 2264 qp->qplib_qp.rq.max_wqe = 2265 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 2266 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe; 2267 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 2268 qp_attr->cap.max_recv_wr; 2269 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 2270 } else { 2271 /* SRQ was used prior, just ignore the RQ caps */ 2272 } 2273 } 2274 if (qp_attr_mask & IB_QP_DEST_QPN) { 2275 qp->qplib_qp.modify_flags |= 2276 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 2277 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 2278 } 2279 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2280 if (rc) { 2281 ibdev_err(&rdev->ibdev, "Failed to modify HW QP"); 2282 return rc; 2283 } 2284 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 2285 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 2286 return rc; 2287 } 2288 2289 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2290 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 2291 { 2292 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2293 struct bnxt_re_dev *rdev = qp->rdev; 2294 struct bnxt_qplib_qp *qplib_qp; 2295 int rc; 2296 2297 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 2298 if (!qplib_qp) 2299 return -ENOMEM; 2300 2301 qplib_qp->id = qp->qplib_qp.id; 2302 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 2303 2304 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 2305 if (rc) { 2306 ibdev_err(&rdev->ibdev, "Failed to query HW QP"); 2307 goto out; 2308 } 2309 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 2310 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state); 2311 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 2312 qp_attr->qp_access_flags = __qp_access_flags_to_ib(qp->qplib_qp.cctx, 2313 qplib_qp->access); 2314 qp_attr->pkey_index = qplib_qp->pkey_index; 2315 qp_attr->qkey = qplib_qp->qkey; 2316 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2317 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 2318 qplib_qp->ah.host_sgid_index, 2319 qplib_qp->ah.hop_limit, 2320 qplib_qp->ah.traffic_class); 2321 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 2322 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 2323 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 2324 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 2325 qp_attr->timeout = qplib_qp->timeout; 2326 qp_attr->retry_cnt = qplib_qp->retry_cnt; 2327 qp_attr->rnr_retry = qplib_qp->rnr_retry; 2328 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 2329 qp_attr->port_num = __to_ib_port_num(qplib_qp->port_id); 2330 qp_attr->rq_psn = qplib_qp->rq.psn; 2331 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 2332 qp_attr->sq_psn = qplib_qp->sq.psn; 2333 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 2334 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 2335 IB_SIGNAL_REQ_WR; 2336 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 2337 2338 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 2339 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 2340 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 2341 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 2342 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 2343 qp_init_attr->cap = qp_attr->cap; 2344 2345 out: 2346 kfree(qplib_qp); 2347 return rc; 2348 } 2349 2350 /* Routine for sending QP1 packets for RoCE V1 an V2 2351 */ 2352 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 2353 const struct ib_send_wr *wr, 2354 struct bnxt_qplib_swqe *wqe, 2355 int payload_size) 2356 { 2357 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 2358 ib_ah); 2359 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 2360 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 2361 struct bnxt_qplib_sge sge; 2362 u8 nw_type; 2363 u16 ether_type; 2364 union ib_gid dgid; 2365 bool is_eth = false; 2366 bool is_vlan = false; 2367 bool is_grh = false; 2368 bool is_udp = false; 2369 u8 ip_version = 0; 2370 u16 vlan_id = 0xFFFF; 2371 void *buf; 2372 int i, rc; 2373 2374 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 2375 2376 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 2377 if (rc) 2378 return rc; 2379 2380 /* Get network header type for this GID */ 2381 nw_type = rdma_gid_attr_network_type(sgid_attr); 2382 switch (nw_type) { 2383 case RDMA_NETWORK_IPV4: 2384 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 2385 break; 2386 case RDMA_NETWORK_IPV6: 2387 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 2388 break; 2389 default: 2390 nw_type = BNXT_RE_ROCE_V1_PACKET; 2391 break; 2392 } 2393 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 2394 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2395 if (is_udp) { 2396 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 2397 ip_version = 4; 2398 ether_type = ETH_P_IP; 2399 } else { 2400 ip_version = 6; 2401 ether_type = ETH_P_IPV6; 2402 } 2403 is_grh = false; 2404 } else { 2405 ether_type = ETH_P_IBOE; 2406 is_grh = true; 2407 } 2408 2409 is_eth = true; 2410 is_vlan = vlan_id && (vlan_id < 0x1000); 2411 2412 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 2413 ip_version, is_udp, 0, &qp->qp1_hdr); 2414 2415 /* ETH */ 2416 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 2417 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 2418 2419 /* For vlan, check the sgid for vlan existence */ 2420 2421 if (!is_vlan) { 2422 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 2423 } else { 2424 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 2425 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 2426 } 2427 2428 if (is_grh || (ip_version == 6)) { 2429 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 2430 sizeof(sgid_attr->gid)); 2431 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 2432 sizeof(sgid_attr->gid)); 2433 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 2434 } 2435 2436 if (ip_version == 4) { 2437 qp->qp1_hdr.ip4.tos = 0; 2438 qp->qp1_hdr.ip4.id = 0; 2439 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 2440 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 2441 2442 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 2443 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 2444 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 2445 } 2446 2447 if (is_udp) { 2448 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 2449 qp->qp1_hdr.udp.sport = htons(0x8CD1); 2450 qp->qp1_hdr.udp.csum = 0; 2451 } 2452 2453 /* BTH */ 2454 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 2455 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2456 qp->qp1_hdr.immediate_present = 1; 2457 } else { 2458 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2459 } 2460 if (wr->send_flags & IB_SEND_SOLICITED) 2461 qp->qp1_hdr.bth.solicited_event = 1; 2462 /* pad_count */ 2463 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 2464 2465 /* P_key for QP1 is for all members */ 2466 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 2467 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 2468 qp->qp1_hdr.bth.ack_req = 0; 2469 qp->send_psn++; 2470 qp->send_psn &= BTH_PSN_MASK; 2471 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 2472 /* DETH */ 2473 /* Use the priviledged Q_Key for QP1 */ 2474 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 2475 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2476 2477 /* Pack the QP1 to the transmit buffer */ 2478 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2479 if (buf) { 2480 ib_ud_header_pack(&qp->qp1_hdr, buf); 2481 for (i = wqe->num_sge; i; i--) { 2482 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2483 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2484 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2485 } 2486 2487 /* 2488 * Max Header buf size for IPV6 RoCE V2 is 86, 2489 * which is same as the QP1 SQ header buffer. 2490 * Header buf size for IPV4 RoCE V2 can be 66. 2491 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2492 * Subtract 20 bytes from QP1 SQ header buf size 2493 */ 2494 if (is_udp && ip_version == 4) 2495 sge.size -= 20; 2496 /* 2497 * Max Header buf size for RoCE V1 is 78. 2498 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2499 * Subtract 8 bytes from QP1 SQ header buf size 2500 */ 2501 if (!is_udp) 2502 sge.size -= 8; 2503 2504 /* Subtract 4 bytes for non vlan packets */ 2505 if (!is_vlan) 2506 sge.size -= 4; 2507 2508 wqe->sg_list[0].addr = sge.addr; 2509 wqe->sg_list[0].lkey = sge.lkey; 2510 wqe->sg_list[0].size = sge.size; 2511 wqe->num_sge++; 2512 2513 } else { 2514 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!"); 2515 rc = -ENOMEM; 2516 } 2517 return rc; 2518 } 2519 2520 /* For the MAD layer, it only provides the recv SGE the size of 2521 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2522 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2523 * receive packet (334 bytes) with no VLAN and then copy the GRH 2524 * and the MAD datagram out to the provided SGE. 2525 */ 2526 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2527 const struct ib_recv_wr *wr, 2528 struct bnxt_qplib_swqe *wqe, 2529 int payload_size) 2530 { 2531 struct bnxt_re_sqp_entries *sqp_entry; 2532 struct bnxt_qplib_sge ref, sge; 2533 struct bnxt_re_dev *rdev; 2534 u32 rq_prod_index; 2535 2536 rdev = qp->rdev; 2537 2538 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2539 2540 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2541 return -ENOMEM; 2542 2543 /* Create 1 SGE to receive the entire 2544 * ethernet packet 2545 */ 2546 /* Save the reference from ULP */ 2547 ref.addr = wqe->sg_list[0].addr; 2548 ref.lkey = wqe->sg_list[0].lkey; 2549 ref.size = wqe->sg_list[0].size; 2550 2551 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index]; 2552 2553 /* SGE 1 */ 2554 wqe->sg_list[0].addr = sge.addr; 2555 wqe->sg_list[0].lkey = sge.lkey; 2556 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2557 sge.size -= wqe->sg_list[0].size; 2558 2559 sqp_entry->sge.addr = ref.addr; 2560 sqp_entry->sge.lkey = ref.lkey; 2561 sqp_entry->sge.size = ref.size; 2562 /* Store the wrid for reporting completion */ 2563 sqp_entry->wrid = wqe->wr_id; 2564 /* change the wqe->wrid to table index */ 2565 wqe->wr_id = rq_prod_index; 2566 return 0; 2567 } 2568 2569 static int is_ud_qp(struct bnxt_re_qp *qp) 2570 { 2571 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2572 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2573 } 2574 2575 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2576 const struct ib_send_wr *wr, 2577 struct bnxt_qplib_swqe *wqe) 2578 { 2579 struct bnxt_re_ah *ah = NULL; 2580 2581 if (is_ud_qp(qp)) { 2582 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2583 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2584 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2585 wqe->send.avid = ah->qplib_ah.id; 2586 } 2587 switch (wr->opcode) { 2588 case IB_WR_SEND: 2589 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2590 break; 2591 case IB_WR_SEND_WITH_IMM: 2592 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2593 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data); 2594 break; 2595 case IB_WR_SEND_WITH_INV: 2596 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2597 wqe->send.inv_key = wr->ex.invalidate_rkey; 2598 break; 2599 default: 2600 return -EINVAL; 2601 } 2602 if (wr->send_flags & IB_SEND_SIGNALED) 2603 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2604 if (wr->send_flags & IB_SEND_FENCE) 2605 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2606 if (wr->send_flags & IB_SEND_SOLICITED) 2607 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2608 if (wr->send_flags & IB_SEND_INLINE) 2609 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2610 2611 return 0; 2612 } 2613 2614 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2615 struct bnxt_qplib_swqe *wqe) 2616 { 2617 switch (wr->opcode) { 2618 case IB_WR_RDMA_WRITE: 2619 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2620 break; 2621 case IB_WR_RDMA_WRITE_WITH_IMM: 2622 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2623 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data); 2624 break; 2625 case IB_WR_RDMA_READ: 2626 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2627 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2628 break; 2629 default: 2630 return -EINVAL; 2631 } 2632 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2633 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2634 if (wr->send_flags & IB_SEND_SIGNALED) 2635 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2636 if (wr->send_flags & IB_SEND_FENCE) 2637 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2638 if (wr->send_flags & IB_SEND_SOLICITED) 2639 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2640 if (wr->send_flags & IB_SEND_INLINE) 2641 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2642 2643 return 0; 2644 } 2645 2646 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2647 struct bnxt_qplib_swqe *wqe) 2648 { 2649 switch (wr->opcode) { 2650 case IB_WR_ATOMIC_CMP_AND_SWP: 2651 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2652 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2653 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2654 break; 2655 case IB_WR_ATOMIC_FETCH_AND_ADD: 2656 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2657 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2658 break; 2659 default: 2660 return -EINVAL; 2661 } 2662 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2663 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2664 if (wr->send_flags & IB_SEND_SIGNALED) 2665 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2666 if (wr->send_flags & IB_SEND_FENCE) 2667 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2668 if (wr->send_flags & IB_SEND_SOLICITED) 2669 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2670 return 0; 2671 } 2672 2673 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2674 struct bnxt_qplib_swqe *wqe) 2675 { 2676 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2677 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2678 2679 if (wr->send_flags & IB_SEND_SIGNALED) 2680 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2681 if (wr->send_flags & IB_SEND_SOLICITED) 2682 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2683 2684 return 0; 2685 } 2686 2687 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2688 struct bnxt_qplib_swqe *wqe) 2689 { 2690 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2691 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2692 int access = wr->access; 2693 2694 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2695 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2696 wqe->frmr.page_list = mr->pages; 2697 wqe->frmr.page_list_len = mr->npages; 2698 wqe->frmr.levels = qplib_frpl->hwq.level; 2699 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2700 2701 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2702 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2703 2704 if (access & IB_ACCESS_LOCAL_WRITE) 2705 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2706 if (access & IB_ACCESS_REMOTE_READ) 2707 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2708 if (access & IB_ACCESS_REMOTE_WRITE) 2709 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2710 if (access & IB_ACCESS_REMOTE_ATOMIC) 2711 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2712 if (access & IB_ACCESS_MW_BIND) 2713 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2714 2715 wqe->frmr.l_key = wr->key; 2716 wqe->frmr.length = wr->mr->length; 2717 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K); 2718 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K); 2719 wqe->frmr.va = wr->mr->iova; 2720 return 0; 2721 } 2722 2723 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2724 const struct ib_send_wr *wr, 2725 struct bnxt_qplib_swqe *wqe) 2726 { 2727 /* Copy the inline data to the data field */ 2728 u8 *in_data; 2729 u32 i, sge_len; 2730 void *sge_addr; 2731 2732 in_data = wqe->inline_data; 2733 for (i = 0; i < wr->num_sge; i++) { 2734 sge_addr = (void *)(unsigned long) 2735 wr->sg_list[i].addr; 2736 sge_len = wr->sg_list[i].length; 2737 2738 if ((sge_len + wqe->inline_len) > 2739 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2740 ibdev_err(&rdev->ibdev, 2741 "Inline data size requested > supported value"); 2742 return -EINVAL; 2743 } 2744 sge_len = wr->sg_list[i].length; 2745 2746 memcpy(in_data, sge_addr, sge_len); 2747 in_data += wr->sg_list[i].length; 2748 wqe->inline_len += wr->sg_list[i].length; 2749 } 2750 return wqe->inline_len; 2751 } 2752 2753 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2754 const struct ib_send_wr *wr, 2755 struct bnxt_qplib_swqe *wqe) 2756 { 2757 int payload_sz = 0; 2758 2759 if (wr->send_flags & IB_SEND_INLINE) 2760 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2761 else 2762 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2763 wqe->num_sge); 2764 2765 return payload_sz; 2766 } 2767 2768 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2769 { 2770 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2771 qp->ib_qp.qp_type == IB_QPT_GSI || 2772 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2773 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2774 int qp_attr_mask; 2775 struct ib_qp_attr qp_attr; 2776 2777 qp_attr_mask = IB_QP_STATE; 2778 qp_attr.qp_state = IB_QPS_RTS; 2779 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2780 qp->qplib_qp.wqe_cnt = 0; 2781 } 2782 } 2783 2784 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2785 struct bnxt_re_qp *qp, 2786 const struct ib_send_wr *wr) 2787 { 2788 int rc = 0, payload_sz = 0; 2789 unsigned long flags; 2790 2791 spin_lock_irqsave(&qp->sq_lock, flags); 2792 while (wr) { 2793 struct bnxt_qplib_swqe wqe = {}; 2794 2795 /* Common */ 2796 wqe.num_sge = wr->num_sge; 2797 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2798 ibdev_err(&rdev->ibdev, 2799 "Limit exceeded for Send SGEs"); 2800 rc = -EINVAL; 2801 goto bad; 2802 } 2803 2804 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2805 if (payload_sz < 0) { 2806 rc = -EINVAL; 2807 goto bad; 2808 } 2809 wqe.wr_id = wr->wr_id; 2810 2811 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2812 2813 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2814 if (!rc) 2815 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2816 bad: 2817 if (rc) { 2818 ibdev_err(&rdev->ibdev, 2819 "Post send failed opcode = %#x rc = %d", 2820 wr->opcode, rc); 2821 break; 2822 } 2823 wr = wr->next; 2824 } 2825 bnxt_qplib_post_send_db(&qp->qplib_qp); 2826 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2827 bnxt_ud_qp_hw_stall_workaround(qp); 2828 spin_unlock_irqrestore(&qp->sq_lock, flags); 2829 return rc; 2830 } 2831 2832 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe) 2833 { 2834 /* Need unconditional fence for non-wire memory opcode 2835 * to work as expected. 2836 */ 2837 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV || 2838 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR || 2839 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR || 2840 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW) 2841 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2842 } 2843 2844 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2845 const struct ib_send_wr **bad_wr) 2846 { 2847 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2848 struct bnxt_qplib_swqe wqe; 2849 int rc = 0, payload_sz = 0; 2850 unsigned long flags; 2851 2852 spin_lock_irqsave(&qp->sq_lock, flags); 2853 while (wr) { 2854 /* House keeping */ 2855 memset(&wqe, 0, sizeof(wqe)); 2856 2857 /* Common */ 2858 wqe.num_sge = wr->num_sge; 2859 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2860 ibdev_err(&qp->rdev->ibdev, 2861 "Limit exceeded for Send SGEs"); 2862 rc = -EINVAL; 2863 goto bad; 2864 } 2865 2866 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2867 if (payload_sz < 0) { 2868 rc = -EINVAL; 2869 goto bad; 2870 } 2871 wqe.wr_id = wr->wr_id; 2872 2873 switch (wr->opcode) { 2874 case IB_WR_SEND: 2875 case IB_WR_SEND_WITH_IMM: 2876 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2877 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2878 payload_sz); 2879 if (rc) 2880 goto bad; 2881 wqe.rawqp1.lflags |= 2882 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2883 } 2884 switch (wr->send_flags) { 2885 case IB_SEND_IP_CSUM: 2886 wqe.rawqp1.lflags |= 2887 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2888 break; 2889 default: 2890 break; 2891 } 2892 fallthrough; 2893 case IB_WR_SEND_WITH_INV: 2894 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2895 break; 2896 case IB_WR_RDMA_WRITE: 2897 case IB_WR_RDMA_WRITE_WITH_IMM: 2898 case IB_WR_RDMA_READ: 2899 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2900 break; 2901 case IB_WR_ATOMIC_CMP_AND_SWP: 2902 case IB_WR_ATOMIC_FETCH_AND_ADD: 2903 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2904 break; 2905 case IB_WR_RDMA_READ_WITH_INV: 2906 ibdev_err(&qp->rdev->ibdev, 2907 "RDMA Read with Invalidate is not supported"); 2908 rc = -EINVAL; 2909 goto bad; 2910 case IB_WR_LOCAL_INV: 2911 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2912 break; 2913 case IB_WR_REG_MR: 2914 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2915 break; 2916 default: 2917 /* Unsupported WRs */ 2918 ibdev_err(&qp->rdev->ibdev, 2919 "WR (%#x) is not supported", wr->opcode); 2920 rc = -EINVAL; 2921 goto bad; 2922 } 2923 if (!rc) { 2924 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2925 bnxt_re_legacy_set_uc_fence(&wqe); 2926 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2927 } 2928 bad: 2929 if (rc) { 2930 ibdev_err(&qp->rdev->ibdev, 2931 "post_send failed op:%#x qps = %#x rc = %d\n", 2932 wr->opcode, qp->qplib_qp.state, rc); 2933 *bad_wr = wr; 2934 break; 2935 } 2936 wr = wr->next; 2937 } 2938 bnxt_qplib_post_send_db(&qp->qplib_qp); 2939 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2940 bnxt_ud_qp_hw_stall_workaround(qp); 2941 spin_unlock_irqrestore(&qp->sq_lock, flags); 2942 2943 return rc; 2944 } 2945 2946 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2947 struct bnxt_re_qp *qp, 2948 const struct ib_recv_wr *wr) 2949 { 2950 struct bnxt_qplib_swqe wqe; 2951 int rc = 0; 2952 2953 while (wr) { 2954 /* House keeping */ 2955 memset(&wqe, 0, sizeof(wqe)); 2956 2957 /* Common */ 2958 wqe.num_sge = wr->num_sge; 2959 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2960 ibdev_err(&rdev->ibdev, 2961 "Limit exceeded for Receive SGEs"); 2962 rc = -EINVAL; 2963 break; 2964 } 2965 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2966 wqe.wr_id = wr->wr_id; 2967 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2968 2969 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2970 if (rc) 2971 break; 2972 2973 wr = wr->next; 2974 } 2975 if (!rc) 2976 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2977 return rc; 2978 } 2979 2980 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2981 const struct ib_recv_wr **bad_wr) 2982 { 2983 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2984 struct bnxt_qplib_swqe wqe; 2985 int rc = 0, payload_sz = 0; 2986 unsigned long flags; 2987 u32 count = 0; 2988 2989 spin_lock_irqsave(&qp->rq_lock, flags); 2990 while (wr) { 2991 /* House keeping */ 2992 memset(&wqe, 0, sizeof(wqe)); 2993 2994 /* Common */ 2995 wqe.num_sge = wr->num_sge; 2996 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2997 ibdev_err(&qp->rdev->ibdev, 2998 "Limit exceeded for Receive SGEs"); 2999 rc = -EINVAL; 3000 *bad_wr = wr; 3001 break; 3002 } 3003 3004 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 3005 wr->num_sge); 3006 wqe.wr_id = wr->wr_id; 3007 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 3008 3009 if (ib_qp->qp_type == IB_QPT_GSI && 3010 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 3011 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 3012 payload_sz); 3013 if (!rc) 3014 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 3015 if (rc) { 3016 *bad_wr = wr; 3017 break; 3018 } 3019 3020 /* Ring DB if the RQEs posted reaches a threshold value */ 3021 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 3022 bnxt_qplib_post_recv_db(&qp->qplib_qp); 3023 count = 0; 3024 } 3025 3026 wr = wr->next; 3027 } 3028 3029 if (count) 3030 bnxt_qplib_post_recv_db(&qp->qplib_qp); 3031 3032 spin_unlock_irqrestore(&qp->rq_lock, flags); 3033 3034 return rc; 3035 } 3036 3037 static struct bnxt_qplib_nq *bnxt_re_get_nq(struct bnxt_re_dev *rdev) 3038 { 3039 int min, indx; 3040 3041 mutex_lock(&rdev->nqr->load_lock); 3042 for (indx = 0, min = 0; indx < (rdev->nqr->num_msix - 1); indx++) { 3043 if (rdev->nqr->nq[min].load > rdev->nqr->nq[indx].load) 3044 min = indx; 3045 } 3046 rdev->nqr->nq[min].load++; 3047 mutex_unlock(&rdev->nqr->load_lock); 3048 3049 return &rdev->nqr->nq[min]; 3050 } 3051 3052 static void bnxt_re_put_nq(struct bnxt_re_dev *rdev, struct bnxt_qplib_nq *nq) 3053 { 3054 mutex_lock(&rdev->nqr->load_lock); 3055 nq->load--; 3056 mutex_unlock(&rdev->nqr->load_lock); 3057 } 3058 3059 /* Completion Queues */ 3060 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 3061 { 3062 struct bnxt_qplib_chip_ctx *cctx; 3063 struct bnxt_qplib_nq *nq; 3064 struct bnxt_re_dev *rdev; 3065 struct bnxt_re_cq *cq; 3066 3067 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3068 rdev = cq->rdev; 3069 nq = cq->qplib_cq.nq; 3070 cctx = rdev->chip_ctx; 3071 3072 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 3073 free_page((unsigned long)cq->uctx_cq_page); 3074 hash_del(&cq->hash_entry); 3075 } 3076 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3077 3078 bnxt_re_put_nq(rdev, nq); 3079 ib_umem_release(cq->umem); 3080 3081 atomic_dec(&rdev->stats.res.cq_count); 3082 nq->budget--; 3083 kfree(cq->cql); 3084 return 0; 3085 } 3086 3087 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 3088 struct uverbs_attr_bundle *attrs) 3089 { 3090 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3091 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 3092 struct ib_udata *udata = &attrs->driver_udata; 3093 struct bnxt_re_ucontext *uctx = 3094 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3095 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 3096 struct bnxt_qplib_chip_ctx *cctx; 3097 int cqe = attr->cqe; 3098 int rc, entries; 3099 u32 active_cqs; 3100 3101 if (attr->flags) 3102 return -EOPNOTSUPP; 3103 3104 /* Validate CQ fields */ 3105 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3106 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded"); 3107 return -EINVAL; 3108 } 3109 3110 cq->rdev = rdev; 3111 cctx = rdev->chip_ctx; 3112 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 3113 3114 entries = bnxt_re_init_depth(cqe + 1, uctx); 3115 if (entries > dev_attr->max_cq_wqes + 1) 3116 entries = dev_attr->max_cq_wqes + 1; 3117 3118 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3119 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3120 if (udata) { 3121 struct bnxt_re_cq_req req; 3122 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3123 rc = -EFAULT; 3124 goto fail; 3125 } 3126 3127 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3128 entries * sizeof(struct cq_base), 3129 IB_ACCESS_LOCAL_WRITE); 3130 if (IS_ERR(cq->umem)) { 3131 rc = PTR_ERR(cq->umem); 3132 goto fail; 3133 } 3134 cq->qplib_cq.sg_info.umem = cq->umem; 3135 cq->qplib_cq.dpi = &uctx->dpi; 3136 } else { 3137 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 3138 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 3139 GFP_KERNEL); 3140 if (!cq->cql) { 3141 rc = -ENOMEM; 3142 goto fail; 3143 } 3144 3145 cq->qplib_cq.dpi = &rdev->dpi_privileged; 3146 } 3147 cq->qplib_cq.max_wqe = entries; 3148 cq->qplib_cq.coalescing = &rdev->cq_coalescing; 3149 cq->qplib_cq.nq = bnxt_re_get_nq(rdev); 3150 cq->qplib_cq.cnq_hw_ring_id = cq->qplib_cq.nq->ring_id; 3151 3152 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 3153 if (rc) { 3154 ibdev_err(&rdev->ibdev, "Failed to create HW CQ"); 3155 goto fail; 3156 } 3157 3158 cq->ib_cq.cqe = entries; 3159 cq->cq_period = cq->qplib_cq.period; 3160 3161 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count); 3162 if (active_cqs > rdev->stats.res.cq_watermark) 3163 rdev->stats.res.cq_watermark = active_cqs; 3164 spin_lock_init(&cq->cq_lock); 3165 3166 if (udata) { 3167 struct bnxt_re_cq_resp resp = {}; 3168 3169 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 3170 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id); 3171 /* Allocate a page */ 3172 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL); 3173 if (!cq->uctx_cq_page) { 3174 rc = -ENOMEM; 3175 goto c2fail; 3176 } 3177 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT; 3178 } 3179 resp.cqid = cq->qplib_cq.id; 3180 resp.tail = cq->qplib_cq.hwq.cons; 3181 resp.phase = cq->qplib_cq.period; 3182 resp.rsvd = 0; 3183 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 3184 if (rc) { 3185 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata"); 3186 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3187 goto free_mem; 3188 } 3189 } 3190 3191 return 0; 3192 3193 free_mem: 3194 free_page((unsigned long)cq->uctx_cq_page); 3195 c2fail: 3196 ib_umem_release(cq->umem); 3197 fail: 3198 kfree(cq->cql); 3199 return rc; 3200 } 3201 3202 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq) 3203 { 3204 struct bnxt_re_dev *rdev = cq->rdev; 3205 3206 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq); 3207 3208 cq->qplib_cq.max_wqe = cq->resize_cqe; 3209 if (cq->resize_umem) { 3210 ib_umem_release(cq->umem); 3211 cq->umem = cq->resize_umem; 3212 cq->resize_umem = NULL; 3213 cq->resize_cqe = 0; 3214 } 3215 } 3216 3217 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata) 3218 { 3219 struct bnxt_qplib_sg_info sg_info = {}; 3220 struct bnxt_qplib_dpi *orig_dpi = NULL; 3221 struct bnxt_qplib_dev_attr *dev_attr; 3222 struct bnxt_re_ucontext *uctx = NULL; 3223 struct bnxt_re_resize_cq_req req; 3224 struct bnxt_re_dev *rdev; 3225 struct bnxt_re_cq *cq; 3226 int rc, entries; 3227 3228 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3229 rdev = cq->rdev; 3230 dev_attr = rdev->dev_attr; 3231 if (!ibcq->uobject) { 3232 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported"); 3233 return -EOPNOTSUPP; 3234 } 3235 3236 if (cq->resize_umem) { 3237 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy", 3238 cq->qplib_cq.id); 3239 return -EBUSY; 3240 } 3241 3242 /* Check the requested cq depth out of supported depth */ 3243 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3244 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d", 3245 cq->qplib_cq.id, cqe); 3246 return -EINVAL; 3247 } 3248 3249 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3250 entries = bnxt_re_init_depth(cqe + 1, uctx); 3251 if (entries > dev_attr->max_cq_wqes + 1) 3252 entries = dev_attr->max_cq_wqes + 1; 3253 3254 /* uverbs consumer */ 3255 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3256 rc = -EFAULT; 3257 goto fail; 3258 } 3259 3260 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3261 entries * sizeof(struct cq_base), 3262 IB_ACCESS_LOCAL_WRITE); 3263 if (IS_ERR(cq->resize_umem)) { 3264 rc = PTR_ERR(cq->resize_umem); 3265 cq->resize_umem = NULL; 3266 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n", 3267 __func__, rc); 3268 goto fail; 3269 } 3270 cq->resize_cqe = entries; 3271 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info)); 3272 orig_dpi = cq->qplib_cq.dpi; 3273 3274 cq->qplib_cq.sg_info.umem = cq->resize_umem; 3275 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3276 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3277 cq->qplib_cq.dpi = &uctx->dpi; 3278 3279 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries); 3280 if (rc) { 3281 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!", 3282 cq->qplib_cq.id); 3283 goto fail; 3284 } 3285 3286 cq->ib_cq.cqe = cq->resize_cqe; 3287 atomic_inc(&rdev->stats.res.resize_count); 3288 3289 return 0; 3290 3291 fail: 3292 if (cq->resize_umem) { 3293 ib_umem_release(cq->resize_umem); 3294 cq->resize_umem = NULL; 3295 cq->resize_cqe = 0; 3296 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info)); 3297 cq->qplib_cq.dpi = orig_dpi; 3298 } 3299 return rc; 3300 } 3301 3302 static u8 __req_to_ib_wc_status(u8 qstatus) 3303 { 3304 switch (qstatus) { 3305 case CQ_REQ_STATUS_OK: 3306 return IB_WC_SUCCESS; 3307 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 3308 return IB_WC_BAD_RESP_ERR; 3309 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 3310 return IB_WC_LOC_LEN_ERR; 3311 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 3312 return IB_WC_LOC_QP_OP_ERR; 3313 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 3314 return IB_WC_LOC_PROT_ERR; 3315 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 3316 return IB_WC_GENERAL_ERR; 3317 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 3318 return IB_WC_REM_INV_REQ_ERR; 3319 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 3320 return IB_WC_REM_ACCESS_ERR; 3321 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 3322 return IB_WC_REM_OP_ERR; 3323 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 3324 return IB_WC_RNR_RETRY_EXC_ERR; 3325 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 3326 return IB_WC_RETRY_EXC_ERR; 3327 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 3328 return IB_WC_WR_FLUSH_ERR; 3329 default: 3330 return IB_WC_GENERAL_ERR; 3331 } 3332 return 0; 3333 } 3334 3335 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 3336 { 3337 switch (qstatus) { 3338 case CQ_RES_RAWETH_QP1_STATUS_OK: 3339 return IB_WC_SUCCESS; 3340 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 3341 return IB_WC_LOC_ACCESS_ERR; 3342 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 3343 return IB_WC_LOC_LEN_ERR; 3344 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 3345 return IB_WC_LOC_PROT_ERR; 3346 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 3347 return IB_WC_LOC_QP_OP_ERR; 3348 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 3349 return IB_WC_GENERAL_ERR; 3350 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 3351 return IB_WC_WR_FLUSH_ERR; 3352 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 3353 return IB_WC_WR_FLUSH_ERR; 3354 default: 3355 return IB_WC_GENERAL_ERR; 3356 } 3357 } 3358 3359 static u8 __rc_to_ib_wc_status(u8 qstatus) 3360 { 3361 switch (qstatus) { 3362 case CQ_RES_RC_STATUS_OK: 3363 return IB_WC_SUCCESS; 3364 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 3365 return IB_WC_LOC_ACCESS_ERR; 3366 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 3367 return IB_WC_LOC_LEN_ERR; 3368 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 3369 return IB_WC_LOC_PROT_ERR; 3370 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 3371 return IB_WC_LOC_QP_OP_ERR; 3372 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 3373 return IB_WC_GENERAL_ERR; 3374 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 3375 return IB_WC_REM_INV_REQ_ERR; 3376 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 3377 return IB_WC_WR_FLUSH_ERR; 3378 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 3379 return IB_WC_WR_FLUSH_ERR; 3380 default: 3381 return IB_WC_GENERAL_ERR; 3382 } 3383 } 3384 3385 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 3386 { 3387 switch (cqe->type) { 3388 case BNXT_QPLIB_SWQE_TYPE_SEND: 3389 wc->opcode = IB_WC_SEND; 3390 break; 3391 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 3392 wc->opcode = IB_WC_SEND; 3393 wc->wc_flags |= IB_WC_WITH_IMM; 3394 break; 3395 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 3396 wc->opcode = IB_WC_SEND; 3397 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3398 break; 3399 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 3400 wc->opcode = IB_WC_RDMA_WRITE; 3401 break; 3402 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 3403 wc->opcode = IB_WC_RDMA_WRITE; 3404 wc->wc_flags |= IB_WC_WITH_IMM; 3405 break; 3406 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 3407 wc->opcode = IB_WC_RDMA_READ; 3408 break; 3409 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 3410 wc->opcode = IB_WC_COMP_SWAP; 3411 break; 3412 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 3413 wc->opcode = IB_WC_FETCH_ADD; 3414 break; 3415 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 3416 wc->opcode = IB_WC_LOCAL_INV; 3417 break; 3418 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 3419 wc->opcode = IB_WC_REG_MR; 3420 break; 3421 default: 3422 wc->opcode = IB_WC_SEND; 3423 break; 3424 } 3425 3426 wc->status = __req_to_ib_wc_status(cqe->status); 3427 } 3428 3429 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 3430 u16 raweth_qp1_flags2) 3431 { 3432 bool is_ipv6 = false, is_ipv4 = false; 3433 3434 /* raweth_qp1_flags Bit 9-6 indicates itype */ 3435 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3436 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3437 return -1; 3438 3439 if (raweth_qp1_flags2 & 3440 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 3441 raweth_qp1_flags2 & 3442 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 3443 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 3444 (raweth_qp1_flags2 & 3445 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 3446 (is_ipv6 = true) : (is_ipv4 = true); 3447 return ((is_ipv6) ? 3448 BNXT_RE_ROCEV2_IPV6_PACKET : 3449 BNXT_RE_ROCEV2_IPV4_PACKET); 3450 } else { 3451 return BNXT_RE_ROCE_V1_PACKET; 3452 } 3453 } 3454 3455 static int bnxt_re_to_ib_nw_type(int nw_type) 3456 { 3457 u8 nw_hdr_type = 0xFF; 3458 3459 switch (nw_type) { 3460 case BNXT_RE_ROCE_V1_PACKET: 3461 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 3462 break; 3463 case BNXT_RE_ROCEV2_IPV4_PACKET: 3464 nw_hdr_type = RDMA_NETWORK_IPV4; 3465 break; 3466 case BNXT_RE_ROCEV2_IPV6_PACKET: 3467 nw_hdr_type = RDMA_NETWORK_IPV6; 3468 break; 3469 } 3470 return nw_hdr_type; 3471 } 3472 3473 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 3474 void *rq_hdr_buf) 3475 { 3476 u8 *tmp_buf = NULL; 3477 struct ethhdr *eth_hdr; 3478 u16 eth_type; 3479 bool rc = false; 3480 3481 tmp_buf = (u8 *)rq_hdr_buf; 3482 /* 3483 * If dest mac is not same as I/F mac, this could be a 3484 * loopback address or multicast address, check whether 3485 * it is a loopback packet 3486 */ 3487 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 3488 tmp_buf += 4; 3489 /* Check the ether type */ 3490 eth_hdr = (struct ethhdr *)tmp_buf; 3491 eth_type = ntohs(eth_hdr->h_proto); 3492 switch (eth_type) { 3493 case ETH_P_IBOE: 3494 rc = true; 3495 break; 3496 case ETH_P_IP: 3497 case ETH_P_IPV6: { 3498 u32 len; 3499 struct udphdr *udp_hdr; 3500 3501 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 3502 sizeof(struct ipv6hdr)); 3503 tmp_buf += sizeof(struct ethhdr) + len; 3504 udp_hdr = (struct udphdr *)tmp_buf; 3505 if (ntohs(udp_hdr->dest) == 3506 ROCE_V2_UDP_DPORT) 3507 rc = true; 3508 break; 3509 } 3510 default: 3511 break; 3512 } 3513 } 3514 3515 return rc; 3516 } 3517 3518 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp, 3519 struct bnxt_qplib_cqe *cqe) 3520 { 3521 struct bnxt_re_dev *rdev = gsi_qp->rdev; 3522 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3523 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp; 3524 dma_addr_t shrq_hdr_buf_map; 3525 struct ib_sge s_sge[2] = {}; 3526 struct ib_sge r_sge[2] = {}; 3527 struct bnxt_re_ah *gsi_sah; 3528 struct ib_recv_wr rwr = {}; 3529 dma_addr_t rq_hdr_buf_map; 3530 struct ib_ud_wr udwr = {}; 3531 struct ib_send_wr *swr; 3532 u32 skip_bytes = 0; 3533 int pkt_type = 0; 3534 void *rq_hdr_buf; 3535 u32 offset = 0; 3536 u32 tbl_idx; 3537 int rc; 3538 3539 swr = &udwr.wr; 3540 tbl_idx = cqe->wr_id; 3541 3542 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf + 3543 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size); 3544 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3545 tbl_idx); 3546 3547 /* Shadow QP header buffer */ 3548 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3549 tbl_idx); 3550 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3551 3552 /* Store this cqe */ 3553 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 3554 sqp_entry->qp1_qp = gsi_qp; 3555 3556 /* Find packet type from the cqe */ 3557 3558 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 3559 cqe->raweth_qp1_flags2); 3560 if (pkt_type < 0) { 3561 ibdev_err(&rdev->ibdev, "Invalid packet\n"); 3562 return -EINVAL; 3563 } 3564 3565 /* Adjust the offset for the user buffer and post in the rq */ 3566 3567 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 3568 offset = 20; 3569 3570 /* 3571 * QP1 loopback packet has 4 bytes of internal header before 3572 * ether header. Skip these four bytes. 3573 */ 3574 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 3575 skip_bytes = 4; 3576 3577 /* First send SGE . Skip the ether header*/ 3578 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 3579 + skip_bytes; 3580 s_sge[0].lkey = 0xFFFFFFFF; 3581 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 3582 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 3583 3584 /* Second Send SGE */ 3585 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 3586 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 3587 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 3588 s_sge[1].addr += 8; 3589 s_sge[1].lkey = 0xFFFFFFFF; 3590 s_sge[1].length = 256; 3591 3592 /* First recv SGE */ 3593 3594 r_sge[0].addr = shrq_hdr_buf_map; 3595 r_sge[0].lkey = 0xFFFFFFFF; 3596 r_sge[0].length = 40; 3597 3598 r_sge[1].addr = sqp_entry->sge.addr + offset; 3599 r_sge[1].lkey = sqp_entry->sge.lkey; 3600 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 3601 3602 /* Create receive work request */ 3603 rwr.num_sge = 2; 3604 rwr.sg_list = r_sge; 3605 rwr.wr_id = tbl_idx; 3606 rwr.next = NULL; 3607 3608 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr); 3609 if (rc) { 3610 ibdev_err(&rdev->ibdev, 3611 "Failed to post Rx buffers to shadow QP"); 3612 return -ENOMEM; 3613 } 3614 3615 swr->num_sge = 2; 3616 swr->sg_list = s_sge; 3617 swr->wr_id = tbl_idx; 3618 swr->opcode = IB_WR_SEND; 3619 swr->next = NULL; 3620 gsi_sah = rdev->gsi_ctx.gsi_sah; 3621 udwr.ah = &gsi_sah->ib_ah; 3622 udwr.remote_qpn = gsi_sqp->qplib_qp.id; 3623 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey; 3624 3625 /* post data received in the send queue */ 3626 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr); 3627 } 3628 3629 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 3630 struct bnxt_qplib_cqe *cqe) 3631 { 3632 wc->opcode = IB_WC_RECV; 3633 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 3634 wc->wc_flags |= IB_WC_GRH; 3635 } 3636 3637 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev, 3638 u16 vlan_id) 3639 { 3640 /* 3641 * Check if the vlan is configured in the host. If not configured, it 3642 * can be a transparent VLAN. So dont report the vlan id. 3643 */ 3644 if (!__vlan_find_dev_deep_rcu(rdev->netdev, 3645 htons(ETH_P_8021Q), vlan_id)) 3646 return false; 3647 return true; 3648 } 3649 3650 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 3651 u16 *vid, u8 *sl) 3652 { 3653 bool ret = false; 3654 u32 metadata; 3655 u16 tpid; 3656 3657 metadata = orig_cqe->raweth_qp1_metadata; 3658 if (orig_cqe->raweth_qp1_flags2 & 3659 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3660 tpid = ((metadata & 3661 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3662 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3663 if (tpid == ETH_P_8021Q) { 3664 *vid = metadata & 3665 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3666 *sl = (metadata & 3667 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3668 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3669 ret = true; 3670 } 3671 } 3672 3673 return ret; 3674 } 3675 3676 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3677 struct bnxt_qplib_cqe *cqe) 3678 { 3679 wc->opcode = IB_WC_RECV; 3680 wc->status = __rc_to_ib_wc_status(cqe->status); 3681 3682 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3683 wc->wc_flags |= IB_WC_WITH_IMM; 3684 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3685 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3686 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3687 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3688 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3689 } 3690 3691 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp, 3692 struct ib_wc *wc, 3693 struct bnxt_qplib_cqe *cqe) 3694 { 3695 struct bnxt_re_dev *rdev = gsi_sqp->rdev; 3696 struct bnxt_re_qp *gsi_qp = NULL; 3697 struct bnxt_qplib_cqe *orig_cqe = NULL; 3698 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3699 int nw_type; 3700 u32 tbl_idx; 3701 u16 vlan_id; 3702 u8 sl; 3703 3704 tbl_idx = cqe->wr_id; 3705 3706 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3707 gsi_qp = sqp_entry->qp1_qp; 3708 orig_cqe = &sqp_entry->cqe; 3709 3710 wc->wr_id = sqp_entry->wrid; 3711 wc->byte_len = orig_cqe->length; 3712 wc->qp = &gsi_qp->ib_qp; 3713 3714 wc->ex.imm_data = cpu_to_be32(orig_cqe->immdata); 3715 wc->src_qp = orig_cqe->src_qp; 3716 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3717 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3718 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3719 wc->vlan_id = vlan_id; 3720 wc->sl = sl; 3721 wc->wc_flags |= IB_WC_WITH_VLAN; 3722 } 3723 } 3724 wc->port_num = 1; 3725 wc->vendor_err = orig_cqe->status; 3726 3727 wc->opcode = IB_WC_RECV; 3728 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3729 wc->wc_flags |= IB_WC_GRH; 3730 3731 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3732 orig_cqe->raweth_qp1_flags2); 3733 if (nw_type >= 0) { 3734 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3735 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3736 } 3737 } 3738 3739 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3740 struct ib_wc *wc, 3741 struct bnxt_qplib_cqe *cqe) 3742 { 3743 struct bnxt_re_dev *rdev; 3744 u16 vlan_id = 0; 3745 u8 nw_type; 3746 3747 rdev = qp->rdev; 3748 wc->opcode = IB_WC_RECV; 3749 wc->status = __rc_to_ib_wc_status(cqe->status); 3750 3751 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3752 wc->wc_flags |= IB_WC_WITH_IMM; 3753 /* report only on GSI QP for Thor */ 3754 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3755 wc->wc_flags |= IB_WC_GRH; 3756 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3757 wc->wc_flags |= IB_WC_WITH_SMAC; 3758 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3759 vlan_id = (cqe->cfa_meta & 0xFFF); 3760 } 3761 /* Mark only if vlan_id is non zero */ 3762 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3763 wc->vlan_id = vlan_id; 3764 wc->wc_flags |= IB_WC_WITH_VLAN; 3765 } 3766 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3767 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3768 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3769 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3770 } 3771 3772 } 3773 3774 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3775 { 3776 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3777 unsigned long flags; 3778 int rc; 3779 3780 spin_lock_irqsave(&qp->sq_lock, flags); 3781 3782 rc = bnxt_re_bind_fence_mw(lib_qp); 3783 if (!rc) { 3784 lib_qp->sq.phantom_wqe_cnt++; 3785 ibdev_dbg(&qp->rdev->ibdev, 3786 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3787 lib_qp->id, lib_qp->sq.hwq.prod, 3788 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3789 lib_qp->sq.phantom_wqe_cnt); 3790 } 3791 3792 spin_unlock_irqrestore(&qp->sq_lock, flags); 3793 return rc; 3794 } 3795 3796 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3797 { 3798 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3799 struct bnxt_re_qp *qp, *sh_qp; 3800 struct bnxt_qplib_cqe *cqe; 3801 int i, ncqe, budget; 3802 struct bnxt_qplib_q *sq; 3803 struct bnxt_qplib_qp *lib_qp; 3804 u32 tbl_idx; 3805 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3806 unsigned long flags; 3807 3808 /* User CQ; the only processing we do is to 3809 * complete any pending CQ resize operation. 3810 */ 3811 if (cq->umem) { 3812 if (cq->resize_umem) 3813 bnxt_re_resize_cq_complete(cq); 3814 return 0; 3815 } 3816 3817 spin_lock_irqsave(&cq->cq_lock, flags); 3818 budget = min_t(u32, num_entries, cq->max_cql); 3819 num_entries = budget; 3820 if (!cq->cql) { 3821 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use"); 3822 goto exit; 3823 } 3824 cqe = &cq->cql[0]; 3825 while (budget) { 3826 lib_qp = NULL; 3827 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3828 if (lib_qp) { 3829 sq = &lib_qp->sq; 3830 if (sq->send_phantom) { 3831 qp = container_of(lib_qp, 3832 struct bnxt_re_qp, qplib_qp); 3833 if (send_phantom_wqe(qp) == -ENOMEM) 3834 ibdev_err(&cq->rdev->ibdev, 3835 "Phantom failed! Scheduled to send again\n"); 3836 else 3837 sq->send_phantom = false; 3838 } 3839 } 3840 if (ncqe < budget) 3841 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3842 cqe + ncqe, 3843 budget - ncqe); 3844 3845 if (!ncqe) 3846 break; 3847 3848 for (i = 0; i < ncqe; i++, cqe++) { 3849 /* Transcribe each qplib_wqe back to ib_wc */ 3850 memset(wc, 0, sizeof(*wc)); 3851 3852 wc->wr_id = cqe->wr_id; 3853 wc->byte_len = cqe->length; 3854 qp = container_of 3855 ((struct bnxt_qplib_qp *) 3856 (unsigned long)(cqe->qp_handle), 3857 struct bnxt_re_qp, qplib_qp); 3858 wc->qp = &qp->ib_qp; 3859 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3860 wc->ex.imm_data = cpu_to_be32(cqe->immdata); 3861 else 3862 wc->ex.invalidate_rkey = cqe->invrkey; 3863 wc->src_qp = cqe->src_qp; 3864 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3865 wc->port_num = 1; 3866 wc->vendor_err = cqe->status; 3867 3868 switch (cqe->opcode) { 3869 case CQ_BASE_CQE_TYPE_REQ: 3870 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3871 if (sh_qp && 3872 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3873 /* Handle this completion with 3874 * the stored completion 3875 */ 3876 memset(wc, 0, sizeof(*wc)); 3877 continue; 3878 } 3879 bnxt_re_process_req_wc(wc, cqe); 3880 break; 3881 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3882 if (!cqe->status) { 3883 int rc = 0; 3884 3885 rc = bnxt_re_process_raw_qp_pkt_rx 3886 (qp, cqe); 3887 if (!rc) { 3888 memset(wc, 0, sizeof(*wc)); 3889 continue; 3890 } 3891 cqe->status = -1; 3892 } 3893 /* Errors need not be looped back. 3894 * But change the wr_id to the one 3895 * stored in the table 3896 */ 3897 tbl_idx = cqe->wr_id; 3898 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3899 wc->wr_id = sqp_entry->wrid; 3900 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3901 break; 3902 case CQ_BASE_CQE_TYPE_RES_RC: 3903 bnxt_re_process_res_rc_wc(wc, cqe); 3904 break; 3905 case CQ_BASE_CQE_TYPE_RES_UD: 3906 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3907 if (sh_qp && 3908 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3909 /* Handle this completion with 3910 * the stored completion 3911 */ 3912 if (cqe->status) { 3913 continue; 3914 } else { 3915 bnxt_re_process_res_shadow_qp_wc 3916 (qp, wc, cqe); 3917 break; 3918 } 3919 } 3920 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3921 break; 3922 default: 3923 ibdev_err(&cq->rdev->ibdev, 3924 "POLL CQ : type 0x%x not handled", 3925 cqe->opcode); 3926 continue; 3927 } 3928 wc++; 3929 budget--; 3930 } 3931 } 3932 exit: 3933 spin_unlock_irqrestore(&cq->cq_lock, flags); 3934 return num_entries - budget; 3935 } 3936 3937 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3938 enum ib_cq_notify_flags ib_cqn_flags) 3939 { 3940 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3941 int type = 0, rc = 0; 3942 unsigned long flags; 3943 3944 spin_lock_irqsave(&cq->cq_lock, flags); 3945 /* Trigger on the very next completion */ 3946 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3947 type = DBC_DBC_TYPE_CQ_ARMALL; 3948 /* Trigger on the next solicited completion */ 3949 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3950 type = DBC_DBC_TYPE_CQ_ARMSE; 3951 3952 /* Poll to see if there are missed events */ 3953 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3954 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3955 rc = 1; 3956 goto exit; 3957 } 3958 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3959 3960 exit: 3961 spin_unlock_irqrestore(&cq->cq_lock, flags); 3962 return rc; 3963 } 3964 3965 /* Memory Regions */ 3966 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3967 { 3968 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3969 struct bnxt_re_dev *rdev = pd->rdev; 3970 struct bnxt_re_mr *mr; 3971 u32 active_mrs; 3972 int rc; 3973 3974 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3975 if (!mr) 3976 return ERR_PTR(-ENOMEM); 3977 3978 mr->rdev = rdev; 3979 mr->qplib_mr.pd = &pd->qplib_pd; 3980 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 3981 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3982 3983 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING) 3984 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr); 3985 3986 /* Allocate and register 0 as the address */ 3987 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3988 if (rc) 3989 goto fail; 3990 3991 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3992 mr->qplib_mr.total_size = -1; /* Infinte length */ 3993 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0, 3994 PAGE_SIZE); 3995 if (rc) 3996 goto fail_mr; 3997 3998 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3999 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 4000 IB_ACCESS_REMOTE_ATOMIC)) 4001 mr->ib_mr.rkey = mr->ib_mr.lkey; 4002 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4003 if (active_mrs > rdev->stats.res.mr_watermark) 4004 rdev->stats.res.mr_watermark = active_mrs; 4005 4006 return &mr->ib_mr; 4007 4008 fail_mr: 4009 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4010 fail: 4011 kfree(mr); 4012 return ERR_PTR(rc); 4013 } 4014 4015 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 4016 { 4017 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 4018 struct bnxt_re_dev *rdev = mr->rdev; 4019 int rc; 4020 4021 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4022 if (rc) { 4023 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc); 4024 return rc; 4025 } 4026 4027 if (mr->pages) { 4028 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 4029 &mr->qplib_frpl); 4030 kfree(mr->pages); 4031 mr->npages = 0; 4032 mr->pages = NULL; 4033 } 4034 ib_umem_release(mr->ib_umem); 4035 4036 kfree(mr); 4037 atomic_dec(&rdev->stats.res.mr_count); 4038 return rc; 4039 } 4040 4041 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 4042 { 4043 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 4044 4045 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 4046 return -ENOMEM; 4047 4048 mr->pages[mr->npages++] = addr; 4049 return 0; 4050 } 4051 4052 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 4053 unsigned int *sg_offset) 4054 { 4055 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 4056 4057 mr->npages = 0; 4058 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 4059 } 4060 4061 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 4062 u32 max_num_sg) 4063 { 4064 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4065 struct bnxt_re_dev *rdev = pd->rdev; 4066 struct bnxt_re_mr *mr = NULL; 4067 u32 active_mrs; 4068 int rc; 4069 4070 if (type != IB_MR_TYPE_MEM_REG) { 4071 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type); 4072 return ERR_PTR(-EINVAL); 4073 } 4074 if (max_num_sg > MAX_PBL_LVL_1_PGS) 4075 return ERR_PTR(-EINVAL); 4076 4077 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 4078 if (!mr) 4079 return ERR_PTR(-ENOMEM); 4080 4081 mr->rdev = rdev; 4082 mr->qplib_mr.pd = &pd->qplib_pd; 4083 mr->qplib_mr.access_flags = BNXT_QPLIB_FR_PMR; 4084 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 4085 4086 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4087 if (rc) 4088 goto bail; 4089 4090 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4091 mr->ib_mr.rkey = mr->ib_mr.lkey; 4092 4093 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 4094 if (!mr->pages) { 4095 rc = -ENOMEM; 4096 goto fail; 4097 } 4098 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 4099 &mr->qplib_frpl, max_num_sg); 4100 if (rc) { 4101 ibdev_err(&rdev->ibdev, 4102 "Failed to allocate HW FR page list"); 4103 goto fail_mr; 4104 } 4105 4106 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4107 if (active_mrs > rdev->stats.res.mr_watermark) 4108 rdev->stats.res.mr_watermark = active_mrs; 4109 return &mr->ib_mr; 4110 4111 fail_mr: 4112 kfree(mr->pages); 4113 fail: 4114 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4115 bail: 4116 kfree(mr); 4117 return ERR_PTR(rc); 4118 } 4119 4120 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 4121 struct ib_udata *udata) 4122 { 4123 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4124 struct bnxt_re_dev *rdev = pd->rdev; 4125 struct bnxt_re_mw *mw; 4126 u32 active_mws; 4127 int rc; 4128 4129 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 4130 if (!mw) 4131 return ERR_PTR(-ENOMEM); 4132 mw->rdev = rdev; 4133 mw->qplib_mw.pd = &pd->qplib_pd; 4134 4135 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 4136 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 4137 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 4138 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 4139 if (rc) { 4140 ibdev_err(&rdev->ibdev, "Allocate MW failed!"); 4141 goto fail; 4142 } 4143 mw->ib_mw.rkey = mw->qplib_mw.rkey; 4144 4145 active_mws = atomic_inc_return(&rdev->stats.res.mw_count); 4146 if (active_mws > rdev->stats.res.mw_watermark) 4147 rdev->stats.res.mw_watermark = active_mws; 4148 return &mw->ib_mw; 4149 4150 fail: 4151 kfree(mw); 4152 return ERR_PTR(rc); 4153 } 4154 4155 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 4156 { 4157 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 4158 struct bnxt_re_dev *rdev = mw->rdev; 4159 int rc; 4160 4161 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 4162 if (rc) { 4163 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc); 4164 return rc; 4165 } 4166 4167 kfree(mw); 4168 atomic_dec(&rdev->stats.res.mw_count); 4169 return rc; 4170 } 4171 4172 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr, 4173 int mr_access_flags, struct ib_umem *umem) 4174 { 4175 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4176 struct bnxt_re_dev *rdev = pd->rdev; 4177 unsigned long page_size; 4178 struct bnxt_re_mr *mr; 4179 int umem_pgs, rc; 4180 u32 active_mrs; 4181 4182 if (length > BNXT_RE_MAX_MR_SIZE) { 4183 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n", 4184 length, BNXT_RE_MAX_MR_SIZE); 4185 return ERR_PTR(-ENOMEM); 4186 } 4187 4188 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr); 4189 if (!page_size) { 4190 ibdev_err(&rdev->ibdev, "umem page size unsupported!"); 4191 return ERR_PTR(-EINVAL); 4192 } 4193 4194 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 4195 if (!mr) 4196 return ERR_PTR(-ENOMEM); 4197 4198 mr->rdev = rdev; 4199 mr->qplib_mr.pd = &pd->qplib_pd; 4200 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 4201 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 4202 4203 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) { 4204 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4205 if (rc) { 4206 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc); 4207 rc = -EIO; 4208 goto free_mr; 4209 } 4210 /* The fixed portion of the rkey is the same as the lkey */ 4211 mr->ib_mr.rkey = mr->qplib_mr.rkey; 4212 } else { 4213 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR; 4214 } 4215 mr->ib_umem = umem; 4216 mr->qplib_mr.va = virt_addr; 4217 mr->qplib_mr.total_size = length; 4218 4219 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING) 4220 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr); 4221 4222 umem_pgs = ib_umem_num_dma_blocks(umem, page_size); 4223 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem, 4224 umem_pgs, page_size); 4225 if (rc) { 4226 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc); 4227 rc = -EIO; 4228 goto free_mrw; 4229 } 4230 4231 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4232 mr->ib_mr.rkey = mr->qplib_mr.lkey; 4233 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4234 if (active_mrs > rdev->stats.res.mr_watermark) 4235 rdev->stats.res.mr_watermark = active_mrs; 4236 4237 return &mr->ib_mr; 4238 4239 free_mrw: 4240 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4241 free_mr: 4242 kfree(mr); 4243 return ERR_PTR(rc); 4244 } 4245 4246 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 4247 u64 virt_addr, int mr_access_flags, 4248 struct ib_udata *udata) 4249 { 4250 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4251 struct bnxt_re_dev *rdev = pd->rdev; 4252 struct ib_umem *umem; 4253 struct ib_mr *ib_mr; 4254 4255 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags); 4256 if (IS_ERR(umem)) 4257 return ERR_CAST(umem); 4258 4259 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4260 if (IS_ERR(ib_mr)) 4261 ib_umem_release(umem); 4262 return ib_mr; 4263 } 4264 4265 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start, 4266 u64 length, u64 virt_addr, int fd, 4267 int mr_access_flags, 4268 struct uverbs_attr_bundle *attrs) 4269 { 4270 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4271 struct bnxt_re_dev *rdev = pd->rdev; 4272 struct ib_umem_dmabuf *umem_dmabuf; 4273 struct ib_umem *umem; 4274 struct ib_mr *ib_mr; 4275 4276 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length, 4277 fd, mr_access_flags); 4278 if (IS_ERR(umem_dmabuf)) 4279 return ERR_CAST(umem_dmabuf); 4280 4281 umem = &umem_dmabuf->umem; 4282 4283 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4284 if (IS_ERR(ib_mr)) 4285 ib_umem_release(umem); 4286 return ib_mr; 4287 } 4288 4289 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 4290 { 4291 struct ib_device *ibdev = ctx->device; 4292 struct bnxt_re_ucontext *uctx = 4293 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 4294 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4295 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 4296 struct bnxt_re_user_mmap_entry *entry; 4297 struct bnxt_re_uctx_resp resp = {}; 4298 struct bnxt_re_uctx_req ureq = {}; 4299 u32 chip_met_rev_num = 0; 4300 int rc; 4301 4302 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver); 4303 4304 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 4305 ibdev_dbg(ibdev, " is different from the device %d ", 4306 BNXT_RE_ABI_VERSION); 4307 return -EPERM; 4308 } 4309 4310 uctx->rdev = rdev; 4311 4312 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 4313 if (!uctx->shpg) { 4314 rc = -ENOMEM; 4315 goto fail; 4316 } 4317 spin_lock_init(&uctx->sh_lock); 4318 4319 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 4320 chip_met_rev_num = rdev->chip_ctx->chip_num; 4321 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) << 4322 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 4323 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) << 4324 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 4325 resp.chip_id0 = chip_met_rev_num; 4326 /*Temp, Use xa_alloc instead */ 4327 resp.dev_id = rdev->en_dev->pdev->devfn; 4328 resp.max_qp = rdev->qplib_ctx.qpc_count; 4329 resp.pg_size = PAGE_SIZE; 4330 resp.cqe_sz = sizeof(struct cq_base); 4331 resp.max_cqd = dev_attr->max_cq_wqes; 4332 4333 if (rdev->chip_ctx->modes.db_push) 4334 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED; 4335 4336 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL); 4337 if (!entry) { 4338 rc = -ENOMEM; 4339 goto cfail; 4340 } 4341 uctx->shpage_mmap = &entry->rdma_entry; 4342 if (rdev->pacing.dbr_pacing) 4343 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED; 4344 4345 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 4346 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED; 4347 4348 if (udata->inlen >= sizeof(ureq)) { 4349 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))); 4350 if (rc) 4351 goto cfail; 4352 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) { 4353 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4354 uctx->cmask |= BNXT_RE_UCNTX_CAP_POW2_DISABLED; 4355 } 4356 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT) { 4357 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE; 4358 resp.mode = rdev->chip_ctx->modes.wqe_mode; 4359 if (resp.mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 4360 uctx->cmask |= BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED; 4361 } 4362 } 4363 4364 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 4365 if (rc) { 4366 ibdev_err(ibdev, "Failed to copy user context"); 4367 rc = -EFAULT; 4368 goto cfail; 4369 } 4370 4371 return 0; 4372 cfail: 4373 free_page((unsigned long)uctx->shpg); 4374 uctx->shpg = NULL; 4375 fail: 4376 return rc; 4377 } 4378 4379 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 4380 { 4381 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4382 struct bnxt_re_ucontext, 4383 ib_uctx); 4384 4385 struct bnxt_re_dev *rdev = uctx->rdev; 4386 4387 rdma_user_mmap_entry_remove(uctx->shpage_mmap); 4388 uctx->shpage_mmap = NULL; 4389 if (uctx->shpg) 4390 free_page((unsigned long)uctx->shpg); 4391 4392 if (uctx->dpi.dbr) { 4393 /* Free DPI only if this is the first PD allocated by the 4394 * application and mark the context dpi as NULL 4395 */ 4396 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi); 4397 uctx->dpi.dbr = NULL; 4398 } 4399 } 4400 4401 static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id) 4402 { 4403 struct bnxt_re_cq *cq = NULL, *tmp_cq; 4404 4405 hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) { 4406 if (tmp_cq->qplib_cq.id == cq_id) { 4407 cq = tmp_cq; 4408 break; 4409 } 4410 } 4411 return cq; 4412 } 4413 4414 static struct bnxt_re_srq *bnxt_re_search_for_srq(struct bnxt_re_dev *rdev, u32 srq_id) 4415 { 4416 struct bnxt_re_srq *srq = NULL, *tmp_srq; 4417 4418 hash_for_each_possible(rdev->srq_hash, tmp_srq, hash_entry, srq_id) { 4419 if (tmp_srq->qplib_srq.id == srq_id) { 4420 srq = tmp_srq; 4421 break; 4422 } 4423 } 4424 return srq; 4425 } 4426 4427 /* Helper function to mmap the virtual memory from user app */ 4428 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 4429 { 4430 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4431 struct bnxt_re_ucontext, 4432 ib_uctx); 4433 struct bnxt_re_user_mmap_entry *bnxt_entry; 4434 struct rdma_user_mmap_entry *rdma_entry; 4435 int ret = 0; 4436 u64 pfn; 4437 4438 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma); 4439 if (!rdma_entry) 4440 return -EINVAL; 4441 4442 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4443 rdma_entry); 4444 4445 switch (bnxt_entry->mmap_flag) { 4446 case BNXT_RE_MMAP_WC_DB: 4447 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4448 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4449 pgprot_writecombine(vma->vm_page_prot), 4450 rdma_entry); 4451 break; 4452 case BNXT_RE_MMAP_UC_DB: 4453 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4454 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4455 pgprot_noncached(vma->vm_page_prot), 4456 rdma_entry); 4457 break; 4458 case BNXT_RE_MMAP_SH_PAGE: 4459 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg)); 4460 break; 4461 case BNXT_RE_MMAP_DBR_BAR: 4462 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4463 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4464 pgprot_noncached(vma->vm_page_prot), 4465 rdma_entry); 4466 break; 4467 case BNXT_RE_MMAP_DBR_PAGE: 4468 case BNXT_RE_MMAP_TOGGLE_PAGE: 4469 /* Driver doesn't expect write access for user space */ 4470 if (vma->vm_flags & VM_WRITE) 4471 ret = -EFAULT; 4472 else 4473 ret = vm_insert_page(vma, vma->vm_start, 4474 virt_to_page((void *)bnxt_entry->mem_offset)); 4475 break; 4476 default: 4477 ret = -EINVAL; 4478 break; 4479 } 4480 4481 rdma_user_mmap_entry_put(rdma_entry); 4482 return ret; 4483 } 4484 4485 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 4486 { 4487 struct bnxt_re_user_mmap_entry *bnxt_entry; 4488 4489 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4490 rdma_entry); 4491 4492 kfree(bnxt_entry); 4493 } 4494 4495 int bnxt_re_process_mad(struct ib_device *ibdev, int mad_flags, 4496 u32 port_num, const struct ib_wc *in_wc, 4497 const struct ib_grh *in_grh, 4498 const struct ib_mad *in_mad, struct ib_mad *out_mad, 4499 size_t *out_mad_size, u16 *out_mad_pkey_index) 4500 { 4501 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4502 struct ib_class_port_info cpi = {}; 4503 int ret = IB_MAD_RESULT_SUCCESS; 4504 int rc = 0; 4505 4506 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT) 4507 return ret; 4508 4509 switch (in_mad->mad_hdr.attr_id) { 4510 case IB_PMA_CLASS_PORT_INFO: 4511 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH; 4512 memcpy((out_mad->data + 40), &cpi, sizeof(cpi)); 4513 break; 4514 case IB_PMA_PORT_COUNTERS_EXT: 4515 rc = bnxt_re_assign_pma_port_ext_counters(rdev, out_mad); 4516 break; 4517 case IB_PMA_PORT_COUNTERS: 4518 rc = bnxt_re_assign_pma_port_counters(rdev, out_mad); 4519 break; 4520 default: 4521 rc = -EINVAL; 4522 break; 4523 } 4524 if (rc) 4525 return IB_MAD_RESULT_FAILURE; 4526 ret |= IB_MAD_RESULT_REPLY; 4527 return ret; 4528 } 4529 4530 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs) 4531 { 4532 struct bnxt_re_ucontext *uctx; 4533 4534 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4535 bnxt_re_pacing_alert(uctx->rdev); 4536 return 0; 4537 } 4538 4539 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs) 4540 { 4541 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4542 enum bnxt_re_alloc_page_type alloc_type; 4543 struct bnxt_re_user_mmap_entry *entry; 4544 enum bnxt_re_mmap_flag mmap_flag; 4545 struct bnxt_qplib_chip_ctx *cctx; 4546 struct bnxt_re_ucontext *uctx; 4547 struct bnxt_re_dev *rdev; 4548 u64 mmap_offset; 4549 u32 length; 4550 u32 dpi; 4551 u64 addr; 4552 int err; 4553 4554 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4555 if (IS_ERR(uctx)) 4556 return PTR_ERR(uctx); 4557 4558 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE); 4559 if (err) 4560 return err; 4561 4562 rdev = uctx->rdev; 4563 cctx = rdev->chip_ctx; 4564 4565 switch (alloc_type) { 4566 case BNXT_RE_ALLOC_WC_PAGE: 4567 if (cctx->modes.db_push) { 4568 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi, 4569 uctx, BNXT_QPLIB_DPI_TYPE_WC)) 4570 return -ENOMEM; 4571 length = PAGE_SIZE; 4572 dpi = uctx->wcdpi.dpi; 4573 addr = (u64)uctx->wcdpi.umdbr; 4574 mmap_flag = BNXT_RE_MMAP_WC_DB; 4575 } else { 4576 return -EINVAL; 4577 } 4578 4579 break; 4580 case BNXT_RE_ALLOC_DBR_BAR_PAGE: 4581 length = PAGE_SIZE; 4582 addr = (u64)rdev->pacing.dbr_bar_addr; 4583 mmap_flag = BNXT_RE_MMAP_DBR_BAR; 4584 break; 4585 4586 case BNXT_RE_ALLOC_DBR_PAGE: 4587 length = PAGE_SIZE; 4588 addr = (u64)rdev->pacing.dbr_page; 4589 mmap_flag = BNXT_RE_MMAP_DBR_PAGE; 4590 break; 4591 4592 default: 4593 return -EOPNOTSUPP; 4594 } 4595 4596 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset); 4597 if (!entry) 4598 return -ENOMEM; 4599 4600 uobj->object = entry; 4601 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4602 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4603 &mmap_offset, sizeof(mmap_offset)); 4604 if (err) 4605 return err; 4606 4607 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4608 &length, sizeof(length)); 4609 if (err) 4610 return err; 4611 4612 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI, 4613 &dpi, sizeof(length)); 4614 if (err) 4615 return err; 4616 4617 return 0; 4618 } 4619 4620 static int alloc_page_obj_cleanup(struct ib_uobject *uobject, 4621 enum rdma_remove_reason why, 4622 struct uverbs_attr_bundle *attrs) 4623 { 4624 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4625 struct bnxt_re_ucontext *uctx = entry->uctx; 4626 4627 switch (entry->mmap_flag) { 4628 case BNXT_RE_MMAP_WC_DB: 4629 if (uctx && uctx->wcdpi.dbr) { 4630 struct bnxt_re_dev *rdev = uctx->rdev; 4631 4632 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi); 4633 uctx->wcdpi.dbr = NULL; 4634 } 4635 break; 4636 case BNXT_RE_MMAP_DBR_BAR: 4637 case BNXT_RE_MMAP_DBR_PAGE: 4638 break; 4639 default: 4640 goto exit; 4641 } 4642 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4643 exit: 4644 return 0; 4645 } 4646 4647 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE, 4648 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE, 4649 BNXT_RE_OBJECT_ALLOC_PAGE, 4650 UVERBS_ACCESS_NEW, 4651 UA_MANDATORY), 4652 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE, 4653 enum bnxt_re_alloc_page_type, 4654 UA_MANDATORY), 4655 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4656 UVERBS_ATTR_TYPE(u64), 4657 UA_MANDATORY), 4658 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4659 UVERBS_ATTR_TYPE(u32), 4660 UA_MANDATORY), 4661 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI, 4662 UVERBS_ATTR_TYPE(u32), 4663 UA_MANDATORY)); 4664 4665 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE, 4666 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE, 4667 BNXT_RE_OBJECT_ALLOC_PAGE, 4668 UVERBS_ACCESS_DESTROY, 4669 UA_MANDATORY)); 4670 4671 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE, 4672 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup), 4673 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE), 4674 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE)); 4675 4676 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV); 4677 4678 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV, 4679 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV)); 4680 4681 /* Toggle MEM */ 4682 static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs) 4683 { 4684 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4685 enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE; 4686 enum bnxt_re_get_toggle_mem_type res_type; 4687 struct bnxt_re_user_mmap_entry *entry; 4688 struct bnxt_re_ucontext *uctx; 4689 struct ib_ucontext *ib_uctx; 4690 struct bnxt_re_dev *rdev; 4691 struct bnxt_re_srq *srq; 4692 u32 length = PAGE_SIZE; 4693 struct bnxt_re_cq *cq; 4694 u64 mem_offset; 4695 u32 offset = 0; 4696 u64 addr = 0; 4697 u32 res_id; 4698 int err; 4699 4700 ib_uctx = ib_uverbs_get_ucontext(attrs); 4701 if (IS_ERR(ib_uctx)) 4702 return PTR_ERR(ib_uctx); 4703 4704 err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE); 4705 if (err) 4706 return err; 4707 4708 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx); 4709 rdev = uctx->rdev; 4710 err = uverbs_copy_from(&res_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID); 4711 if (err) 4712 return err; 4713 4714 switch (res_type) { 4715 case BNXT_RE_CQ_TOGGLE_MEM: 4716 cq = bnxt_re_search_for_cq(rdev, res_id); 4717 if (!cq) 4718 return -EINVAL; 4719 4720 addr = (u64)cq->uctx_cq_page; 4721 break; 4722 case BNXT_RE_SRQ_TOGGLE_MEM: 4723 srq = bnxt_re_search_for_srq(rdev, res_id); 4724 if (!srq) 4725 return -EINVAL; 4726 4727 addr = (u64)srq->uctx_srq_page; 4728 break; 4729 4730 default: 4731 return -EOPNOTSUPP; 4732 } 4733 4734 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset); 4735 if (!entry) 4736 return -ENOMEM; 4737 4738 uobj->object = entry; 4739 uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4740 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4741 &mem_offset, sizeof(mem_offset)); 4742 if (err) 4743 return err; 4744 4745 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4746 &length, sizeof(length)); 4747 if (err) 4748 return err; 4749 4750 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4751 &offset, sizeof(length)); 4752 if (err) 4753 return err; 4754 4755 return 0; 4756 } 4757 4758 static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject, 4759 enum rdma_remove_reason why, 4760 struct uverbs_attr_bundle *attrs) 4761 { 4762 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4763 4764 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4765 return 0; 4766 } 4767 4768 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM, 4769 UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE, 4770 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4771 UVERBS_ACCESS_NEW, 4772 UA_MANDATORY), 4773 UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE, 4774 enum bnxt_re_get_toggle_mem_type, 4775 UA_MANDATORY), 4776 UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID, 4777 UVERBS_ATTR_TYPE(u32), 4778 UA_MANDATORY), 4779 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4780 UVERBS_ATTR_TYPE(u64), 4781 UA_MANDATORY), 4782 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4783 UVERBS_ATTR_TYPE(u32), 4784 UA_MANDATORY), 4785 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4786 UVERBS_ATTR_TYPE(u32), 4787 UA_MANDATORY)); 4788 4789 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM, 4790 UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE, 4791 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4792 UVERBS_ACCESS_DESTROY, 4793 UA_MANDATORY)); 4794 4795 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4796 UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup), 4797 &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM), 4798 &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM)); 4799 4800 const struct uapi_definition bnxt_re_uapi_defs[] = { 4801 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE), 4802 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV), 4803 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM), 4804 {} 4805 }; 4806