1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 #include <net/addrconf.h> 45 46 #include <rdma/ib_verbs.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_umem.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_mad.h> 51 #include <rdma/ib_cache.h> 52 #include <rdma/uverbs_ioctl.h> 53 #include <linux/hashtable.h> 54 55 #include "bnxt_ulp.h" 56 57 #include "roce_hsi.h" 58 #include "qplib_res.h" 59 #include "qplib_sp.h" 60 #include "qplib_fp.h" 61 #include "qplib_rcfw.h" 62 63 #include "bnxt_re.h" 64 #include "ib_verbs.h" 65 66 #include <rdma/uverbs_types.h> 67 #include <rdma/uverbs_std_types.h> 68 69 #include <rdma/ib_user_ioctl_cmds.h> 70 71 #define UVERBS_MODULE_NAME bnxt_re 72 #include <rdma/uverbs_named_ioctl.h> 73 74 #include <rdma/bnxt_re-abi.h> 75 76 static int __from_ib_access_flags(int iflags) 77 { 78 int qflags = 0; 79 80 if (iflags & IB_ACCESS_LOCAL_WRITE) 81 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 82 if (iflags & IB_ACCESS_REMOTE_READ) 83 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 84 if (iflags & IB_ACCESS_REMOTE_WRITE) 85 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 86 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 87 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 88 if (iflags & IB_ACCESS_MW_BIND) 89 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 90 if (iflags & IB_ZERO_BASED) 91 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 92 if (iflags & IB_ACCESS_ON_DEMAND) 93 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 94 return qflags; 95 }; 96 97 static enum ib_access_flags __to_ib_access_flags(int qflags) 98 { 99 enum ib_access_flags iflags = 0; 100 101 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 102 iflags |= IB_ACCESS_LOCAL_WRITE; 103 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 104 iflags |= IB_ACCESS_REMOTE_WRITE; 105 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 106 iflags |= IB_ACCESS_REMOTE_READ; 107 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 108 iflags |= IB_ACCESS_REMOTE_ATOMIC; 109 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 110 iflags |= IB_ACCESS_MW_BIND; 111 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 112 iflags |= IB_ZERO_BASED; 113 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 114 iflags |= IB_ACCESS_ON_DEMAND; 115 return iflags; 116 }; 117 118 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 119 struct bnxt_qplib_sge *sg_list, int num) 120 { 121 int i, total = 0; 122 123 for (i = 0; i < num; i++) { 124 sg_list[i].addr = ib_sg_list[i].addr; 125 sg_list[i].lkey = ib_sg_list[i].lkey; 126 sg_list[i].size = ib_sg_list[i].length; 127 total += sg_list[i].size; 128 } 129 return total; 130 } 131 132 /* Device */ 133 int bnxt_re_query_device(struct ib_device *ibdev, 134 struct ib_device_attr *ib_attr, 135 struct ib_udata *udata) 136 { 137 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 138 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 139 140 memset(ib_attr, 0, sizeof(*ib_attr)); 141 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 142 min(sizeof(dev_attr->fw_ver), 143 sizeof(ib_attr->fw_ver))); 144 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid, 145 rdev->netdev->dev_addr); 146 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 147 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED; 148 149 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 150 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 151 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 152 ib_attr->max_qp = dev_attr->max_qp; 153 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 154 ib_attr->device_cap_flags = 155 IB_DEVICE_CURR_QP_STATE_MOD 156 | IB_DEVICE_RC_RNR_NAK_GEN 157 | IB_DEVICE_SHUTDOWN_PORT 158 | IB_DEVICE_SYS_IMAGE_GUID 159 | IB_DEVICE_RESIZE_MAX_WR 160 | IB_DEVICE_PORT_ACTIVE_EVENT 161 | IB_DEVICE_N_NOTIFY_CQ 162 | IB_DEVICE_MEM_WINDOW 163 | IB_DEVICE_MEM_WINDOW_TYPE_2B 164 | IB_DEVICE_MEM_MGT_EXTENSIONS; 165 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY; 166 ib_attr->max_send_sge = dev_attr->max_qp_sges; 167 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 168 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 169 ib_attr->max_cq = dev_attr->max_cq; 170 ib_attr->max_cqe = dev_attr->max_cq_wqes; 171 ib_attr->max_mr = dev_attr->max_mr; 172 ib_attr->max_pd = dev_attr->max_pd; 173 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 174 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 175 ib_attr->atomic_cap = IB_ATOMIC_NONE; 176 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 177 if (dev_attr->is_atomic) { 178 ib_attr->atomic_cap = IB_ATOMIC_GLOB; 179 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; 180 } 181 182 ib_attr->max_ee_rd_atom = 0; 183 ib_attr->max_res_rd_atom = 0; 184 ib_attr->max_ee_init_rd_atom = 0; 185 ib_attr->max_ee = 0; 186 ib_attr->max_rdd = 0; 187 ib_attr->max_mw = dev_attr->max_mw; 188 ib_attr->max_raw_ipv6_qp = 0; 189 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 190 ib_attr->max_mcast_grp = 0; 191 ib_attr->max_mcast_qp_attach = 0; 192 ib_attr->max_total_mcast_qp_attach = 0; 193 ib_attr->max_ah = dev_attr->max_ah; 194 195 ib_attr->max_srq = dev_attr->max_srq; 196 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 197 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 198 199 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 200 201 ib_attr->max_pkeys = 1; 202 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 203 return 0; 204 } 205 206 /* Port */ 207 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num, 208 struct ib_port_attr *port_attr) 209 { 210 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 211 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 212 int rc; 213 214 memset(port_attr, 0, sizeof(*port_attr)); 215 216 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 217 port_attr->state = IB_PORT_ACTIVE; 218 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 219 } else { 220 port_attr->state = IB_PORT_DOWN; 221 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 222 } 223 port_attr->max_mtu = IB_MTU_4096; 224 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 225 port_attr->gid_tbl_len = dev_attr->max_sgid; 226 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 227 IB_PORT_DEVICE_MGMT_SUP | 228 IB_PORT_VENDOR_CLASS_SUP; 229 port_attr->ip_gids = true; 230 231 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 232 port_attr->bad_pkey_cntr = 0; 233 port_attr->qkey_viol_cntr = 0; 234 port_attr->pkey_tbl_len = dev_attr->max_pkey; 235 port_attr->lid = 0; 236 port_attr->sm_lid = 0; 237 port_attr->lmc = 0; 238 port_attr->max_vl_num = 4; 239 port_attr->sm_sl = 0; 240 port_attr->subnet_timeout = 0; 241 port_attr->init_type_reply = 0; 242 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed, 243 &port_attr->active_width); 244 245 return rc; 246 } 247 248 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num, 249 struct ib_port_immutable *immutable) 250 { 251 struct ib_port_attr port_attr; 252 253 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 254 return -EINVAL; 255 256 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 257 immutable->gid_tbl_len = port_attr.gid_tbl_len; 258 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 259 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 260 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 261 return 0; 262 } 263 264 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 265 { 266 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 267 268 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 269 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 270 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 271 } 272 273 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num, 274 u16 index, u16 *pkey) 275 { 276 if (index > 0) 277 return -EINVAL; 278 279 *pkey = IB_DEFAULT_PKEY_FULL; 280 281 return 0; 282 } 283 284 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num, 285 int index, union ib_gid *gid) 286 { 287 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 288 int rc; 289 290 /* Ignore port_num */ 291 memset(gid, 0, sizeof(*gid)); 292 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 293 &rdev->qplib_res.sgid_tbl, index, 294 (struct bnxt_qplib_gid *)gid); 295 return rc; 296 } 297 298 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 299 { 300 int rc = 0; 301 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 302 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 303 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 304 struct bnxt_qplib_gid *gid_to_del; 305 u16 vlan_id = 0xFFFF; 306 307 /* Delete the entry from the hardware */ 308 ctx = *context; 309 if (!ctx) 310 return -EINVAL; 311 312 if (sgid_tbl && sgid_tbl->active) { 313 if (ctx->idx >= sgid_tbl->max) 314 return -EINVAL; 315 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 316 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 317 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 318 * or via the ib_unregister_device path. In the former case QP1 319 * may not be destroyed yet, in which case just return as FW 320 * needs that entry to be present and will fail it's deletion. 321 * We could get invoked again after QP1 is destroyed OR get an 322 * ADD_GID call with a different GID value for the same index 323 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 324 */ 325 if (ctx->idx == 0 && 326 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 327 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) { 328 ibdev_dbg(&rdev->ibdev, 329 "Trying to delete GID0 while QP1 is alive\n"); 330 return -EFAULT; 331 } 332 ctx->refcnt--; 333 if (!ctx->refcnt) { 334 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 335 vlan_id, true); 336 if (rc) { 337 ibdev_err(&rdev->ibdev, 338 "Failed to remove GID: %#x", rc); 339 } else { 340 ctx_tbl = sgid_tbl->ctx; 341 ctx_tbl[ctx->idx] = NULL; 342 kfree(ctx); 343 } 344 } 345 } else { 346 return -EINVAL; 347 } 348 return rc; 349 } 350 351 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 352 { 353 int rc; 354 u32 tbl_idx = 0; 355 u16 vlan_id = 0xFFFF; 356 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 357 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 358 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 359 360 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 361 if (rc) 362 return rc; 363 364 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 365 rdev->qplib_res.netdev->dev_addr, 366 vlan_id, true, &tbl_idx); 367 if (rc == -EALREADY) { 368 ctx_tbl = sgid_tbl->ctx; 369 ctx_tbl[tbl_idx]->refcnt++; 370 *context = ctx_tbl[tbl_idx]; 371 return 0; 372 } 373 374 if (rc < 0) { 375 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc); 376 return rc; 377 } 378 379 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 380 if (!ctx) 381 return -ENOMEM; 382 ctx_tbl = sgid_tbl->ctx; 383 ctx->idx = tbl_idx; 384 ctx->refcnt = 1; 385 ctx_tbl[tbl_idx] = ctx; 386 *context = ctx; 387 388 return rc; 389 } 390 391 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 392 u32 port_num) 393 { 394 return IB_LINK_LAYER_ETHERNET; 395 } 396 397 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 398 399 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 400 { 401 struct bnxt_re_fence_data *fence = &pd->fence; 402 struct ib_mr *ib_mr = &fence->mr->ib_mr; 403 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 404 struct bnxt_re_dev *rdev = pd->rdev; 405 406 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 407 return; 408 409 memset(wqe, 0, sizeof(*wqe)); 410 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 411 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 412 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 413 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 414 wqe->bind.zero_based = false; 415 wqe->bind.parent_l_key = ib_mr->lkey; 416 wqe->bind.va = (u64)(unsigned long)fence->va; 417 wqe->bind.length = fence->size; 418 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 419 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 420 421 /* Save the initial rkey in fence structure for now; 422 * wqe->bind.r_key will be set at (re)bind time. 423 */ 424 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 425 } 426 427 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 428 { 429 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 430 qplib_qp); 431 struct ib_pd *ib_pd = qp->ib_qp.pd; 432 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 433 struct bnxt_re_fence_data *fence = &pd->fence; 434 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 435 struct bnxt_qplib_swqe wqe; 436 int rc; 437 438 memcpy(&wqe, fence_wqe, sizeof(wqe)); 439 wqe.bind.r_key = fence->bind_rkey; 440 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 441 442 ibdev_dbg(&qp->rdev->ibdev, 443 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 444 wqe.bind.r_key, qp->qplib_qp.id, pd); 445 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 446 if (rc) { 447 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n"); 448 return rc; 449 } 450 bnxt_qplib_post_send_db(&qp->qplib_qp); 451 452 return rc; 453 } 454 455 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 456 { 457 struct bnxt_re_fence_data *fence = &pd->fence; 458 struct bnxt_re_dev *rdev = pd->rdev; 459 struct device *dev = &rdev->en_dev->pdev->dev; 460 struct bnxt_re_mr *mr = fence->mr; 461 462 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 463 return; 464 465 if (fence->mw) { 466 bnxt_re_dealloc_mw(fence->mw); 467 fence->mw = NULL; 468 } 469 if (mr) { 470 if (mr->ib_mr.rkey) 471 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 472 true); 473 if (mr->ib_mr.lkey) 474 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 475 kfree(mr); 476 fence->mr = NULL; 477 } 478 if (fence->dma_addr) { 479 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 480 DMA_BIDIRECTIONAL); 481 fence->dma_addr = 0; 482 } 483 } 484 485 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 486 { 487 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 488 struct bnxt_re_fence_data *fence = &pd->fence; 489 struct bnxt_re_dev *rdev = pd->rdev; 490 struct device *dev = &rdev->en_dev->pdev->dev; 491 struct bnxt_re_mr *mr = NULL; 492 dma_addr_t dma_addr = 0; 493 struct ib_mw *mw; 494 int rc; 495 496 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 497 return 0; 498 499 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 500 DMA_BIDIRECTIONAL); 501 rc = dma_mapping_error(dev, dma_addr); 502 if (rc) { 503 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n"); 504 rc = -EIO; 505 fence->dma_addr = 0; 506 goto fail; 507 } 508 fence->dma_addr = dma_addr; 509 510 /* Allocate a MR */ 511 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 512 if (!mr) { 513 rc = -ENOMEM; 514 goto fail; 515 } 516 fence->mr = mr; 517 mr->rdev = rdev; 518 mr->qplib_mr.pd = &pd->qplib_pd; 519 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 520 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 521 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 522 if (rc) { 523 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); 524 goto fail; 525 } 526 527 /* Register MR */ 528 mr->ib_mr.lkey = mr->qplib_mr.lkey; 529 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 530 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 531 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 532 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE); 533 if (rc) { 534 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n"); 535 goto fail; 536 } 537 mr->ib_mr.rkey = mr->qplib_mr.rkey; 538 539 /* Create a fence MW only for kernel consumers */ 540 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 541 if (IS_ERR(mw)) { 542 ibdev_err(&rdev->ibdev, 543 "Failed to create fence-MW for PD: %p\n", pd); 544 rc = PTR_ERR(mw); 545 goto fail; 546 } 547 fence->mw = mw; 548 549 bnxt_re_create_fence_wqe(pd); 550 return 0; 551 552 fail: 553 bnxt_re_destroy_fence_mr(pd); 554 return rc; 555 } 556 557 static struct bnxt_re_user_mmap_entry* 558 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset, 559 enum bnxt_re_mmap_flag mmap_flag, u64 *offset) 560 { 561 struct bnxt_re_user_mmap_entry *entry; 562 int ret; 563 564 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 565 if (!entry) 566 return NULL; 567 568 entry->mem_offset = mem_offset; 569 entry->mmap_flag = mmap_flag; 570 entry->uctx = uctx; 571 572 switch (mmap_flag) { 573 case BNXT_RE_MMAP_SH_PAGE: 574 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx, 575 &entry->rdma_entry, PAGE_SIZE, 0); 576 break; 577 case BNXT_RE_MMAP_UC_DB: 578 case BNXT_RE_MMAP_WC_DB: 579 case BNXT_RE_MMAP_DBR_BAR: 580 case BNXT_RE_MMAP_DBR_PAGE: 581 case BNXT_RE_MMAP_TOGGLE_PAGE: 582 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx, 583 &entry->rdma_entry, PAGE_SIZE); 584 break; 585 default: 586 ret = -EINVAL; 587 break; 588 } 589 590 if (ret) { 591 kfree(entry); 592 return NULL; 593 } 594 if (offset) 595 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 596 597 return entry; 598 } 599 600 /* Protection Domains */ 601 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 602 { 603 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 604 struct bnxt_re_dev *rdev = pd->rdev; 605 606 if (udata) { 607 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 608 pd->pd_db_mmap = NULL; 609 } 610 611 bnxt_re_destroy_fence_mr(pd); 612 613 if (pd->qplib_pd.id) { 614 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res, 615 &rdev->qplib_res.pd_tbl, 616 &pd->qplib_pd)) 617 atomic_dec(&rdev->stats.res.pd_count); 618 } 619 return 0; 620 } 621 622 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 623 { 624 struct ib_device *ibdev = ibpd->device; 625 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 626 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 627 udata, struct bnxt_re_ucontext, ib_uctx); 628 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 629 struct bnxt_re_user_mmap_entry *entry = NULL; 630 u32 active_pds; 631 int rc = 0; 632 633 pd->rdev = rdev; 634 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) { 635 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD"); 636 rc = -ENOMEM; 637 goto fail; 638 } 639 640 if (udata) { 641 struct bnxt_re_pd_resp resp = {}; 642 643 if (!ucntx->dpi.dbr) { 644 /* Allocate DPI in alloc_pd to avoid failing of 645 * ibv_devinfo and family of application when DPIs 646 * are depleted. 647 */ 648 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, 649 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) { 650 rc = -ENOMEM; 651 goto dbfail; 652 } 653 } 654 655 resp.pdid = pd->qplib_pd.id; 656 /* Still allow mapping this DBR to the new user PD. */ 657 resp.dpi = ucntx->dpi.dpi; 658 659 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr, 660 BNXT_RE_MMAP_UC_DB, &resp.dbr); 661 662 if (!entry) { 663 rc = -ENOMEM; 664 goto dbfail; 665 } 666 667 pd->pd_db_mmap = &entry->rdma_entry; 668 669 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 670 if (rc) { 671 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 672 rc = -EFAULT; 673 goto dbfail; 674 } 675 } 676 677 if (!udata) 678 if (bnxt_re_create_fence_mr(pd)) 679 ibdev_warn(&rdev->ibdev, 680 "Failed to create Fence-MR\n"); 681 active_pds = atomic_inc_return(&rdev->stats.res.pd_count); 682 if (active_pds > rdev->stats.res.pd_watermark) 683 rdev->stats.res.pd_watermark = active_pds; 684 685 return 0; 686 dbfail: 687 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 688 &pd->qplib_pd); 689 fail: 690 return rc; 691 } 692 693 /* Address Handles */ 694 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 695 { 696 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 697 struct bnxt_re_dev *rdev = ah->rdev; 698 bool block = true; 699 int rc; 700 701 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE); 702 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block); 703 if (BNXT_RE_CHECK_RC(rc)) { 704 if (rc == -ETIMEDOUT) 705 rc = 0; 706 else 707 goto fail; 708 } 709 atomic_dec(&rdev->stats.res.ah_count); 710 fail: 711 return rc; 712 } 713 714 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 715 { 716 u8 nw_type; 717 718 switch (ntype) { 719 case RDMA_NETWORK_IPV4: 720 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 721 break; 722 case RDMA_NETWORK_IPV6: 723 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 724 break; 725 default: 726 nw_type = CMDQ_CREATE_AH_TYPE_V1; 727 break; 728 } 729 return nw_type; 730 } 731 732 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr, 733 struct ib_udata *udata) 734 { 735 struct ib_pd *ib_pd = ib_ah->pd; 736 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 737 struct rdma_ah_attr *ah_attr = init_attr->ah_attr; 738 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 739 struct bnxt_re_dev *rdev = pd->rdev; 740 const struct ib_gid_attr *sgid_attr; 741 struct bnxt_re_gid_ctx *ctx; 742 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 743 u32 active_ahs; 744 u8 nw_type; 745 int rc; 746 747 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 748 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set"); 749 return -EINVAL; 750 } 751 752 ah->rdev = rdev; 753 ah->qplib_ah.pd = &pd->qplib_pd; 754 755 /* Supply the configuration for the HW */ 756 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 757 sizeof(union ib_gid)); 758 sgid_attr = grh->sgid_attr; 759 /* Get the HW context of the GID. The reference 760 * of GID table entry is already taken by the caller. 761 */ 762 ctx = rdma_read_gid_hw_context(sgid_attr); 763 ah->qplib_ah.sgid_index = ctx->idx; 764 ah->qplib_ah.host_sgid_index = grh->sgid_index; 765 ah->qplib_ah.traffic_class = grh->traffic_class; 766 ah->qplib_ah.flow_label = grh->flow_label; 767 ah->qplib_ah.hop_limit = grh->hop_limit; 768 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 769 770 /* Get network header type for this GID */ 771 nw_type = rdma_gid_attr_network_type(sgid_attr); 772 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 773 774 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 775 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 776 !(init_attr->flags & 777 RDMA_CREATE_AH_SLEEPABLE)); 778 if (rc) { 779 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH"); 780 return rc; 781 } 782 783 /* Write AVID to shared page. */ 784 if (udata) { 785 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 786 udata, struct bnxt_re_ucontext, ib_uctx); 787 unsigned long flag; 788 u32 *wrptr; 789 790 spin_lock_irqsave(&uctx->sh_lock, flag); 791 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 792 *wrptr = ah->qplib_ah.id; 793 wmb(); /* make sure cache is updated. */ 794 spin_unlock_irqrestore(&uctx->sh_lock, flag); 795 } 796 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count); 797 if (active_ahs > rdev->stats.res.ah_watermark) 798 rdev->stats.res.ah_watermark = active_ahs; 799 800 return 0; 801 } 802 803 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 804 { 805 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 806 807 ah_attr->type = ib_ah->type; 808 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 809 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 810 rdma_ah_set_grh(ah_attr, NULL, 0, 811 ah->qplib_ah.host_sgid_index, 812 0, ah->qplib_ah.traffic_class); 813 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 814 rdma_ah_set_port_num(ah_attr, 1); 815 rdma_ah_set_static_rate(ah_attr, 0); 816 return 0; 817 } 818 819 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 820 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 821 { 822 unsigned long flags; 823 824 spin_lock_irqsave(&qp->scq->cq_lock, flags); 825 if (qp->rcq != qp->scq) 826 spin_lock(&qp->rcq->cq_lock); 827 else 828 __acquire(&qp->rcq->cq_lock); 829 830 return flags; 831 } 832 833 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 834 unsigned long flags) 835 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 836 { 837 if (qp->rcq != qp->scq) 838 spin_unlock(&qp->rcq->cq_lock); 839 else 840 __release(&qp->rcq->cq_lock); 841 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 842 } 843 844 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp) 845 { 846 struct bnxt_re_qp *gsi_sqp; 847 struct bnxt_re_ah *gsi_sah; 848 struct bnxt_re_dev *rdev; 849 int rc; 850 851 rdev = qp->rdev; 852 gsi_sqp = rdev->gsi_ctx.gsi_sqp; 853 gsi_sah = rdev->gsi_ctx.gsi_sah; 854 855 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n"); 856 bnxt_qplib_destroy_ah(&rdev->qplib_res, 857 &gsi_sah->qplib_ah, 858 true); 859 atomic_dec(&rdev->stats.res.ah_count); 860 bnxt_qplib_clean_qp(&qp->qplib_qp); 861 862 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n"); 863 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp); 864 if (rc) { 865 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed"); 866 goto fail; 867 } 868 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp); 869 870 /* remove from active qp list */ 871 mutex_lock(&rdev->qp_lock); 872 list_del(&gsi_sqp->list); 873 mutex_unlock(&rdev->qp_lock); 874 atomic_dec(&rdev->stats.res.qp_count); 875 876 kfree(rdev->gsi_ctx.sqp_tbl); 877 kfree(gsi_sah); 878 kfree(gsi_sqp); 879 rdev->gsi_ctx.gsi_sqp = NULL; 880 rdev->gsi_ctx.gsi_sah = NULL; 881 rdev->gsi_ctx.sqp_tbl = NULL; 882 883 return 0; 884 fail: 885 return rc; 886 } 887 888 /* Queue Pairs */ 889 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 890 { 891 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 892 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 893 struct bnxt_re_dev *rdev = qp->rdev; 894 struct bnxt_qplib_nq *scq_nq = NULL; 895 struct bnxt_qplib_nq *rcq_nq = NULL; 896 unsigned int flags; 897 int rc; 898 899 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 900 901 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 902 if (rc) { 903 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP"); 904 return rc; 905 } 906 907 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 908 flags = bnxt_re_lock_cqs(qp); 909 bnxt_qplib_clean_qp(&qp->qplib_qp); 910 bnxt_re_unlock_cqs(qp, flags); 911 } 912 913 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 914 915 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) { 916 rc = bnxt_re_destroy_gsi_sqp(qp); 917 if (rc) 918 return rc; 919 } 920 921 mutex_lock(&rdev->qp_lock); 922 list_del(&qp->list); 923 mutex_unlock(&rdev->qp_lock); 924 atomic_dec(&rdev->stats.res.qp_count); 925 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC) 926 atomic_dec(&rdev->stats.res.rc_qp_count); 927 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD) 928 atomic_dec(&rdev->stats.res.ud_qp_count); 929 930 ib_umem_release(qp->rumem); 931 ib_umem_release(qp->sumem); 932 933 /* Flush all the entries of notification queue associated with 934 * given qp. 935 */ 936 scq_nq = qplib_qp->scq->nq; 937 rcq_nq = qplib_qp->rcq->nq; 938 bnxt_re_synchronize_nq(scq_nq); 939 if (scq_nq != rcq_nq) 940 bnxt_re_synchronize_nq(rcq_nq); 941 942 return 0; 943 } 944 945 static u8 __from_ib_qp_type(enum ib_qp_type type) 946 { 947 switch (type) { 948 case IB_QPT_GSI: 949 return CMDQ_CREATE_QP1_TYPE_GSI; 950 case IB_QPT_RC: 951 return CMDQ_CREATE_QP_TYPE_RC; 952 case IB_QPT_UD: 953 return CMDQ_CREATE_QP_TYPE_UD; 954 default: 955 return IB_QPT_MAX; 956 } 957 } 958 959 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp, 960 int rsge, int max) 961 { 962 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 963 rsge = max; 964 return bnxt_re_get_rwqe_size(rsge); 965 } 966 967 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge) 968 { 969 u16 wqe_size, calc_ils; 970 971 wqe_size = bnxt_re_get_swqe_size(nsge); 972 if (ilsize) { 973 calc_ils = sizeof(struct sq_send_hdr) + ilsize; 974 wqe_size = max_t(u16, calc_ils, wqe_size); 975 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr)); 976 } 977 return wqe_size; 978 } 979 980 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp, 981 struct ib_qp_init_attr *init_attr) 982 { 983 struct bnxt_qplib_dev_attr *dev_attr; 984 struct bnxt_qplib_qp *qplqp; 985 struct bnxt_re_dev *rdev; 986 struct bnxt_qplib_q *sq; 987 int align, ilsize; 988 989 rdev = qp->rdev; 990 qplqp = &qp->qplib_qp; 991 sq = &qplqp->sq; 992 dev_attr = &rdev->dev_attr; 993 994 align = sizeof(struct sq_send_hdr); 995 ilsize = ALIGN(init_attr->cap.max_inline_data, align); 996 997 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge); 998 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges)) 999 return -EINVAL; 1000 /* For gen p4 and gen p5 backward compatibility mode 1001 * wqe size is fixed to 128 bytes 1002 */ 1003 if (sq->wqe_size < bnxt_re_get_swqe_size(dev_attr->max_qp_sges) && 1004 qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 1005 sq->wqe_size = bnxt_re_get_swqe_size(dev_attr->max_qp_sges); 1006 1007 if (init_attr->cap.max_inline_data) { 1008 qplqp->max_inline_data = sq->wqe_size - 1009 sizeof(struct sq_send_hdr); 1010 init_attr->cap.max_inline_data = qplqp->max_inline_data; 1011 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 1012 sq->max_sge = qplqp->max_inline_data / 1013 sizeof(struct sq_sge); 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 1020 struct bnxt_re_qp *qp, struct ib_udata *udata) 1021 { 1022 struct bnxt_qplib_qp *qplib_qp; 1023 struct bnxt_re_ucontext *cntx; 1024 struct bnxt_re_qp_req ureq; 1025 int bytes = 0, psn_sz; 1026 struct ib_umem *umem; 1027 int psn_nume; 1028 1029 qplib_qp = &qp->qplib_qp; 1030 cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, 1031 ib_uctx); 1032 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1033 return -EFAULT; 1034 1035 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size); 1036 /* Consider mapping PSN search memory only for RC QPs. */ 1037 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 1038 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 1039 sizeof(struct sq_psn_search_ext) : 1040 sizeof(struct sq_psn_search); 1041 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 1042 qplib_qp->sq.max_wqe : 1043 ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) / 1044 sizeof(struct bnxt_qplib_sge)); 1045 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 1046 psn_nume = roundup_pow_of_two(psn_nume); 1047 bytes += (psn_nume * psn_sz); 1048 } 1049 1050 bytes = PAGE_ALIGN(bytes); 1051 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes, 1052 IB_ACCESS_LOCAL_WRITE); 1053 if (IS_ERR(umem)) 1054 return PTR_ERR(umem); 1055 1056 qp->sumem = umem; 1057 qplib_qp->sq.sg_info.umem = umem; 1058 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE; 1059 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT; 1060 qplib_qp->qp_handle = ureq.qp_handle; 1061 1062 if (!qp->qplib_qp.srq) { 1063 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size); 1064 bytes = PAGE_ALIGN(bytes); 1065 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes, 1066 IB_ACCESS_LOCAL_WRITE); 1067 if (IS_ERR(umem)) 1068 goto rqfail; 1069 qp->rumem = umem; 1070 qplib_qp->rq.sg_info.umem = umem; 1071 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE; 1072 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT; 1073 } 1074 1075 qplib_qp->dpi = &cntx->dpi; 1076 return 0; 1077 rqfail: 1078 ib_umem_release(qp->sumem); 1079 qp->sumem = NULL; 1080 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 1081 1082 return PTR_ERR(umem); 1083 } 1084 1085 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 1086 (struct bnxt_re_pd *pd, 1087 struct bnxt_qplib_res *qp1_res, 1088 struct bnxt_qplib_qp *qp1_qp) 1089 { 1090 struct bnxt_re_dev *rdev = pd->rdev; 1091 struct bnxt_re_ah *ah; 1092 union ib_gid sgid; 1093 int rc; 1094 1095 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 1096 if (!ah) 1097 return NULL; 1098 1099 ah->rdev = rdev; 1100 ah->qplib_ah.pd = &pd->qplib_pd; 1101 1102 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 1103 if (rc) 1104 goto fail; 1105 1106 /* supply the dgid data same as sgid */ 1107 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 1108 sizeof(union ib_gid)); 1109 ah->qplib_ah.sgid_index = 0; 1110 1111 ah->qplib_ah.traffic_class = 0; 1112 ah->qplib_ah.flow_label = 0; 1113 ah->qplib_ah.hop_limit = 1; 1114 ah->qplib_ah.sl = 0; 1115 /* Have DMAC same as SMAC */ 1116 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 1117 1118 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 1119 if (rc) { 1120 ibdev_err(&rdev->ibdev, 1121 "Failed to allocate HW AH for Shadow QP"); 1122 goto fail; 1123 } 1124 atomic_inc(&rdev->stats.res.ah_count); 1125 1126 return ah; 1127 1128 fail: 1129 kfree(ah); 1130 return NULL; 1131 } 1132 1133 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 1134 (struct bnxt_re_pd *pd, 1135 struct bnxt_qplib_res *qp1_res, 1136 struct bnxt_qplib_qp *qp1_qp) 1137 { 1138 struct bnxt_re_dev *rdev = pd->rdev; 1139 struct bnxt_re_qp *qp; 1140 int rc; 1141 1142 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1143 if (!qp) 1144 return NULL; 1145 1146 qp->rdev = rdev; 1147 1148 /* Initialize the shadow QP structure from the QP1 values */ 1149 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1150 1151 qp->qplib_qp.pd = &pd->qplib_pd; 1152 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1153 qp->qplib_qp.type = IB_QPT_UD; 1154 1155 qp->qplib_qp.max_inline_data = 0; 1156 qp->qplib_qp.sig_type = true; 1157 1158 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 1159 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6); 1160 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1161 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe; 1162 qp->qplib_qp.sq.max_sge = 2; 1163 /* Q full delta can be 1 since it is internal QP */ 1164 qp->qplib_qp.sq.q_full_delta = 1; 1165 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE; 1166 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT; 1167 1168 qp->qplib_qp.scq = qp1_qp->scq; 1169 qp->qplib_qp.rcq = qp1_qp->rcq; 1170 1171 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6); 1172 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1173 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe; 1174 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1175 /* Q full delta can be 1 since it is internal QP */ 1176 qp->qplib_qp.rq.q_full_delta = 1; 1177 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE; 1178 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT; 1179 1180 qp->qplib_qp.mtu = qp1_qp->mtu; 1181 1182 qp->qplib_qp.sq_hdr_buf_size = 0; 1183 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1184 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1185 1186 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1187 if (rc) 1188 goto fail; 1189 1190 spin_lock_init(&qp->sq_lock); 1191 INIT_LIST_HEAD(&qp->list); 1192 mutex_lock(&rdev->qp_lock); 1193 list_add_tail(&qp->list, &rdev->qp_list); 1194 atomic_inc(&rdev->stats.res.qp_count); 1195 mutex_unlock(&rdev->qp_lock); 1196 return qp; 1197 fail: 1198 kfree(qp); 1199 return NULL; 1200 } 1201 1202 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 1203 struct ib_qp_init_attr *init_attr, 1204 struct bnxt_re_ucontext *uctx) 1205 { 1206 struct bnxt_qplib_dev_attr *dev_attr; 1207 struct bnxt_qplib_qp *qplqp; 1208 struct bnxt_re_dev *rdev; 1209 struct bnxt_qplib_q *rq; 1210 int entries; 1211 1212 rdev = qp->rdev; 1213 qplqp = &qp->qplib_qp; 1214 rq = &qplqp->rq; 1215 dev_attr = &rdev->dev_attr; 1216 1217 if (init_attr->srq) { 1218 struct bnxt_re_srq *srq; 1219 1220 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq); 1221 qplqp->srq = &srq->qplib_srq; 1222 rq->max_wqe = 0; 1223 } else { 1224 rq->max_sge = init_attr->cap.max_recv_sge; 1225 if (rq->max_sge > dev_attr->max_qp_sges) 1226 rq->max_sge = dev_attr->max_qp_sges; 1227 init_attr->cap.max_recv_sge = rq->max_sge; 1228 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge, 1229 dev_attr->max_qp_sges); 1230 /* Allocate 1 more than what's provided so posting max doesn't 1231 * mean empty. 1232 */ 1233 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx); 1234 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1235 rq->max_sw_wqe = rq->max_wqe; 1236 rq->q_full_delta = 0; 1237 rq->sg_info.pgsize = PAGE_SIZE; 1238 rq->sg_info.pgshft = PAGE_SHIFT; 1239 } 1240 1241 return 0; 1242 } 1243 1244 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 1245 { 1246 struct bnxt_qplib_dev_attr *dev_attr; 1247 struct bnxt_qplib_qp *qplqp; 1248 struct bnxt_re_dev *rdev; 1249 1250 rdev = qp->rdev; 1251 qplqp = &qp->qplib_qp; 1252 dev_attr = &rdev->dev_attr; 1253 1254 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1255 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1256 if (qplqp->rq.max_sge > dev_attr->max_qp_sges) 1257 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1258 qplqp->rq.max_sge = 6; 1259 } 1260 } 1261 1262 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 1263 struct ib_qp_init_attr *init_attr, 1264 struct bnxt_re_ucontext *uctx) 1265 { 1266 struct bnxt_qplib_dev_attr *dev_attr; 1267 struct bnxt_qplib_qp *qplqp; 1268 struct bnxt_re_dev *rdev; 1269 struct bnxt_qplib_q *sq; 1270 int entries; 1271 int diff; 1272 int rc; 1273 1274 rdev = qp->rdev; 1275 qplqp = &qp->qplib_qp; 1276 sq = &qplqp->sq; 1277 dev_attr = &rdev->dev_attr; 1278 1279 sq->max_sge = init_attr->cap.max_send_sge; 1280 if (sq->max_sge > dev_attr->max_qp_sges) { 1281 sq->max_sge = dev_attr->max_qp_sges; 1282 init_attr->cap.max_send_sge = sq->max_sge; 1283 } 1284 1285 rc = bnxt_re_setup_swqe_size(qp, init_attr); 1286 if (rc) 1287 return rc; 1288 1289 entries = init_attr->cap.max_send_wr; 1290 /* Allocate 128 + 1 more than what's provided */ 1291 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ? 1292 0 : BNXT_QPLIB_RESERVED_QP_WRS; 1293 entries = bnxt_re_init_depth(entries + diff + 1, uctx); 1294 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1); 1295 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true); 1296 sq->q_full_delta = diff + 1; 1297 /* 1298 * Reserving one slot for Phantom WQE. Application can 1299 * post one extra entry in this case. But allowing this to avoid 1300 * unexpected Queue full condition 1301 */ 1302 qplqp->sq.q_full_delta -= 1; 1303 qplqp->sq.sg_info.pgsize = PAGE_SIZE; 1304 qplqp->sq.sg_info.pgshft = PAGE_SHIFT; 1305 1306 return 0; 1307 } 1308 1309 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 1310 struct ib_qp_init_attr *init_attr, 1311 struct bnxt_re_ucontext *uctx) 1312 { 1313 struct bnxt_qplib_dev_attr *dev_attr; 1314 struct bnxt_qplib_qp *qplqp; 1315 struct bnxt_re_dev *rdev; 1316 int entries; 1317 1318 rdev = qp->rdev; 1319 qplqp = &qp->qplib_qp; 1320 dev_attr = &rdev->dev_attr; 1321 1322 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1323 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx); 1324 qplqp->sq.max_wqe = min_t(u32, entries, 1325 dev_attr->max_qp_wqes + 1); 1326 qplqp->sq.q_full_delta = qplqp->sq.max_wqe - 1327 init_attr->cap.max_send_wr; 1328 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ 1329 if (qplqp->sq.max_sge > dev_attr->max_qp_sges) 1330 qplqp->sq.max_sge = dev_attr->max_qp_sges; 1331 } 1332 } 1333 1334 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 1335 struct ib_qp_init_attr *init_attr) 1336 { 1337 struct bnxt_qplib_chip_ctx *chip_ctx; 1338 int qptype; 1339 1340 chip_ctx = rdev->chip_ctx; 1341 1342 qptype = __from_ib_qp_type(init_attr->qp_type); 1343 if (qptype == IB_QPT_MAX) { 1344 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype); 1345 qptype = -EOPNOTSUPP; 1346 goto out; 1347 } 1348 1349 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) && 1350 init_attr->qp_type == IB_QPT_GSI) 1351 qptype = CMDQ_CREATE_QP_TYPE_GSI; 1352 out: 1353 return qptype; 1354 } 1355 1356 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1357 struct ib_qp_init_attr *init_attr, 1358 struct ib_udata *udata) 1359 { 1360 struct bnxt_qplib_dev_attr *dev_attr; 1361 struct bnxt_re_ucontext *uctx; 1362 struct bnxt_qplib_qp *qplqp; 1363 struct bnxt_re_dev *rdev; 1364 struct bnxt_re_cq *cq; 1365 int rc = 0, qptype; 1366 1367 rdev = qp->rdev; 1368 qplqp = &qp->qplib_qp; 1369 dev_attr = &rdev->dev_attr; 1370 1371 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1372 /* Setup misc params */ 1373 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); 1374 qplqp->pd = &pd->qplib_pd; 1375 qplqp->qp_handle = (u64)qplqp; 1376 qplqp->max_inline_data = init_attr->cap.max_inline_data; 1377 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR; 1378 qptype = bnxt_re_init_qp_type(rdev, init_attr); 1379 if (qptype < 0) { 1380 rc = qptype; 1381 goto out; 1382 } 1383 qplqp->type = (u8)qptype; 1384 qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode; 1385 1386 if (init_attr->qp_type == IB_QPT_RC) { 1387 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom; 1388 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1389 } 1390 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1391 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */ 1392 if (init_attr->create_flags) { 1393 ibdev_dbg(&rdev->ibdev, 1394 "QP create flags 0x%x not supported", 1395 init_attr->create_flags); 1396 return -EOPNOTSUPP; 1397 } 1398 1399 /* Setup CQs */ 1400 if (init_attr->send_cq) { 1401 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq); 1402 qplqp->scq = &cq->qplib_cq; 1403 qp->scq = cq; 1404 } 1405 1406 if (init_attr->recv_cq) { 1407 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq); 1408 qplqp->rcq = &cq->qplib_cq; 1409 qp->rcq = cq; 1410 } 1411 1412 /* Setup RQ/SRQ */ 1413 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx); 1414 if (rc) 1415 goto out; 1416 if (init_attr->qp_type == IB_QPT_GSI) 1417 bnxt_re_adjust_gsi_rq_attr(qp); 1418 1419 /* Setup SQ */ 1420 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx); 1421 if (rc) 1422 goto out; 1423 if (init_attr->qp_type == IB_QPT_GSI) 1424 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx); 1425 1426 if (udata) /* This will update DPI and qp_handle */ 1427 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1428 out: 1429 return rc; 1430 } 1431 1432 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp, 1433 struct bnxt_re_pd *pd) 1434 { 1435 struct bnxt_re_sqp_entries *sqp_tbl; 1436 struct bnxt_re_dev *rdev; 1437 struct bnxt_re_qp *sqp; 1438 struct bnxt_re_ah *sah; 1439 int rc = 0; 1440 1441 rdev = qp->rdev; 1442 /* Create a shadow QP to handle the QP1 traffic */ 1443 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl), 1444 GFP_KERNEL); 1445 if (!sqp_tbl) 1446 return -ENOMEM; 1447 rdev->gsi_ctx.sqp_tbl = sqp_tbl; 1448 1449 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp); 1450 if (!sqp) { 1451 rc = -ENODEV; 1452 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1"); 1453 goto out; 1454 } 1455 rdev->gsi_ctx.gsi_sqp = sqp; 1456 1457 sqp->rcq = qp->rcq; 1458 sqp->scq = qp->scq; 1459 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1460 &qp->qplib_qp); 1461 if (!sah) { 1462 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1463 &sqp->qplib_qp); 1464 rc = -ENODEV; 1465 ibdev_err(&rdev->ibdev, 1466 "Failed to create AH entry for ShadowQP"); 1467 goto out; 1468 } 1469 rdev->gsi_ctx.gsi_sah = sah; 1470 1471 return 0; 1472 out: 1473 kfree(sqp_tbl); 1474 return rc; 1475 } 1476 1477 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1478 struct ib_qp_init_attr *init_attr) 1479 { 1480 struct bnxt_re_dev *rdev; 1481 struct bnxt_qplib_qp *qplqp; 1482 int rc; 1483 1484 rdev = qp->rdev; 1485 qplqp = &qp->qplib_qp; 1486 1487 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1488 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1489 1490 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp); 1491 if (rc) { 1492 ibdev_err(&rdev->ibdev, "create HW QP1 failed!"); 1493 goto out; 1494 } 1495 1496 rc = bnxt_re_create_shadow_gsi(qp, pd); 1497 out: 1498 return rc; 1499 } 1500 1501 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev, 1502 struct ib_qp_init_attr *init_attr, 1503 struct bnxt_qplib_dev_attr *dev_attr) 1504 { 1505 bool rc = true; 1506 1507 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes || 1508 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes || 1509 init_attr->cap.max_send_sge > dev_attr->max_qp_sges || 1510 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges || 1511 init_attr->cap.max_inline_data > dev_attr->max_inline_data) { 1512 ibdev_err(&rdev->ibdev, 1513 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x", 1514 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes, 1515 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes, 1516 init_attr->cap.max_send_sge, dev_attr->max_qp_sges, 1517 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges, 1518 init_attr->cap.max_inline_data, 1519 dev_attr->max_inline_data); 1520 rc = false; 1521 } 1522 return rc; 1523 } 1524 1525 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr, 1526 struct ib_udata *udata) 1527 { 1528 struct ib_pd *ib_pd = ib_qp->pd; 1529 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1530 struct bnxt_re_dev *rdev = pd->rdev; 1531 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1532 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1533 u32 active_qps; 1534 int rc; 1535 1536 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr); 1537 if (!rc) { 1538 rc = -EINVAL; 1539 goto fail; 1540 } 1541 1542 qp->rdev = rdev; 1543 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata); 1544 if (rc) 1545 goto fail; 1546 1547 if (qp_init_attr->qp_type == IB_QPT_GSI && 1548 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) { 1549 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr); 1550 if (rc == -ENODEV) 1551 goto qp_destroy; 1552 if (rc) 1553 goto fail; 1554 } else { 1555 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1556 if (rc) { 1557 ibdev_err(&rdev->ibdev, "Failed to create HW QP"); 1558 goto free_umem; 1559 } 1560 if (udata) { 1561 struct bnxt_re_qp_resp resp; 1562 1563 resp.qpid = qp->qplib_qp.id; 1564 resp.rsvd = 0; 1565 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1566 if (rc) { 1567 ibdev_err(&rdev->ibdev, "Failed to copy QP udata"); 1568 goto qp_destroy; 1569 } 1570 } 1571 } 1572 1573 qp->ib_qp.qp_num = qp->qplib_qp.id; 1574 if (qp_init_attr->qp_type == IB_QPT_GSI) 1575 rdev->gsi_ctx.gsi_qp = qp; 1576 spin_lock_init(&qp->sq_lock); 1577 spin_lock_init(&qp->rq_lock); 1578 INIT_LIST_HEAD(&qp->list); 1579 mutex_lock(&rdev->qp_lock); 1580 list_add_tail(&qp->list, &rdev->qp_list); 1581 mutex_unlock(&rdev->qp_lock); 1582 active_qps = atomic_inc_return(&rdev->stats.res.qp_count); 1583 if (active_qps > rdev->stats.res.qp_watermark) 1584 rdev->stats.res.qp_watermark = active_qps; 1585 if (qp_init_attr->qp_type == IB_QPT_RC) { 1586 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count); 1587 if (active_qps > rdev->stats.res.rc_qp_watermark) 1588 rdev->stats.res.rc_qp_watermark = active_qps; 1589 } else if (qp_init_attr->qp_type == IB_QPT_UD) { 1590 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count); 1591 if (active_qps > rdev->stats.res.ud_qp_watermark) 1592 rdev->stats.res.ud_qp_watermark = active_qps; 1593 } 1594 1595 return 0; 1596 qp_destroy: 1597 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1598 free_umem: 1599 ib_umem_release(qp->rumem); 1600 ib_umem_release(qp->sumem); 1601 fail: 1602 return rc; 1603 } 1604 1605 static u8 __from_ib_qp_state(enum ib_qp_state state) 1606 { 1607 switch (state) { 1608 case IB_QPS_RESET: 1609 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1610 case IB_QPS_INIT: 1611 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1612 case IB_QPS_RTR: 1613 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1614 case IB_QPS_RTS: 1615 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1616 case IB_QPS_SQD: 1617 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1618 case IB_QPS_SQE: 1619 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1620 case IB_QPS_ERR: 1621 default: 1622 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1623 } 1624 } 1625 1626 static enum ib_qp_state __to_ib_qp_state(u8 state) 1627 { 1628 switch (state) { 1629 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1630 return IB_QPS_RESET; 1631 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1632 return IB_QPS_INIT; 1633 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1634 return IB_QPS_RTR; 1635 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1636 return IB_QPS_RTS; 1637 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1638 return IB_QPS_SQD; 1639 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1640 return IB_QPS_SQE; 1641 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1642 default: 1643 return IB_QPS_ERR; 1644 } 1645 } 1646 1647 static u32 __from_ib_mtu(enum ib_mtu mtu) 1648 { 1649 switch (mtu) { 1650 case IB_MTU_256: 1651 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1652 case IB_MTU_512: 1653 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1654 case IB_MTU_1024: 1655 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1656 case IB_MTU_2048: 1657 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1658 case IB_MTU_4096: 1659 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1660 default: 1661 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1662 } 1663 } 1664 1665 static enum ib_mtu __to_ib_mtu(u32 mtu) 1666 { 1667 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1668 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1669 return IB_MTU_256; 1670 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1671 return IB_MTU_512; 1672 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1673 return IB_MTU_1024; 1674 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1675 return IB_MTU_2048; 1676 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1677 return IB_MTU_4096; 1678 default: 1679 return IB_MTU_2048; 1680 } 1681 } 1682 1683 /* Shared Receive Queues */ 1684 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1685 { 1686 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1687 ib_srq); 1688 struct bnxt_re_dev *rdev = srq->rdev; 1689 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1690 struct bnxt_qplib_nq *nq = NULL; 1691 1692 if (qplib_srq->cq) 1693 nq = qplib_srq->cq->nq; 1694 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1695 ib_umem_release(srq->umem); 1696 atomic_dec(&rdev->stats.res.srq_count); 1697 if (nq) 1698 nq->budget--; 1699 return 0; 1700 } 1701 1702 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1703 struct bnxt_re_pd *pd, 1704 struct bnxt_re_srq *srq, 1705 struct ib_udata *udata) 1706 { 1707 struct bnxt_re_srq_req ureq; 1708 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1709 struct ib_umem *umem; 1710 int bytes = 0; 1711 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1712 udata, struct bnxt_re_ucontext, ib_uctx); 1713 1714 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1715 return -EFAULT; 1716 1717 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size); 1718 bytes = PAGE_ALIGN(bytes); 1719 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes, 1720 IB_ACCESS_LOCAL_WRITE); 1721 if (IS_ERR(umem)) 1722 return PTR_ERR(umem); 1723 1724 srq->umem = umem; 1725 qplib_srq->sg_info.umem = umem; 1726 qplib_srq->sg_info.pgsize = PAGE_SIZE; 1727 qplib_srq->sg_info.pgshft = PAGE_SHIFT; 1728 qplib_srq->srq_handle = ureq.srq_handle; 1729 qplib_srq->dpi = &cntx->dpi; 1730 1731 return 0; 1732 } 1733 1734 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1735 struct ib_srq_init_attr *srq_init_attr, 1736 struct ib_udata *udata) 1737 { 1738 struct bnxt_qplib_dev_attr *dev_attr; 1739 struct bnxt_qplib_nq *nq = NULL; 1740 struct bnxt_re_ucontext *uctx; 1741 struct bnxt_re_dev *rdev; 1742 struct bnxt_re_srq *srq; 1743 struct bnxt_re_pd *pd; 1744 struct ib_pd *ib_pd; 1745 u32 active_srqs; 1746 int rc, entries; 1747 1748 ib_pd = ib_srq->pd; 1749 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1750 rdev = pd->rdev; 1751 dev_attr = &rdev->dev_attr; 1752 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1753 1754 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1755 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded"); 1756 rc = -EINVAL; 1757 goto exit; 1758 } 1759 1760 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1761 rc = -EOPNOTSUPP; 1762 goto exit; 1763 } 1764 1765 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1766 srq->rdev = rdev; 1767 srq->qplib_srq.pd = &pd->qplib_pd; 1768 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1769 /* Allocate 1 more than what's provided so posting max doesn't 1770 * mean empty 1771 */ 1772 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx); 1773 if (entries > dev_attr->max_srq_wqes + 1) 1774 entries = dev_attr->max_srq_wqes + 1; 1775 srq->qplib_srq.max_wqe = entries; 1776 1777 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1778 /* 128 byte wqe size for SRQ . So use max sges */ 1779 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges); 1780 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1781 srq->srq_limit = srq_init_attr->attr.srq_limit; 1782 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1783 nq = &rdev->nq[0]; 1784 1785 if (udata) { 1786 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1787 if (rc) 1788 goto fail; 1789 } 1790 1791 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1792 if (rc) { 1793 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!"); 1794 goto fail; 1795 } 1796 1797 if (udata) { 1798 struct bnxt_re_srq_resp resp; 1799 1800 resp.srqid = srq->qplib_srq.id; 1801 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1802 if (rc) { 1803 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!"); 1804 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1805 &srq->qplib_srq); 1806 goto fail; 1807 } 1808 } 1809 if (nq) 1810 nq->budget++; 1811 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count); 1812 if (active_srqs > rdev->stats.res.srq_watermark) 1813 rdev->stats.res.srq_watermark = active_srqs; 1814 spin_lock_init(&srq->lock); 1815 1816 return 0; 1817 1818 fail: 1819 ib_umem_release(srq->umem); 1820 exit: 1821 return rc; 1822 } 1823 1824 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1825 enum ib_srq_attr_mask srq_attr_mask, 1826 struct ib_udata *udata) 1827 { 1828 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1829 ib_srq); 1830 struct bnxt_re_dev *rdev = srq->rdev; 1831 int rc; 1832 1833 switch (srq_attr_mask) { 1834 case IB_SRQ_MAX_WR: 1835 /* SRQ resize is not supported */ 1836 return -EINVAL; 1837 case IB_SRQ_LIMIT: 1838 /* Change the SRQ threshold */ 1839 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1840 return -EINVAL; 1841 1842 srq->qplib_srq.threshold = srq_attr->srq_limit; 1843 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1844 if (rc) { 1845 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!"); 1846 return rc; 1847 } 1848 /* On success, update the shadow */ 1849 srq->srq_limit = srq_attr->srq_limit; 1850 /* No need to Build and send response back to udata */ 1851 return 0; 1852 default: 1853 ibdev_err(&rdev->ibdev, 1854 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1855 return -EINVAL; 1856 } 1857 } 1858 1859 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1860 { 1861 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1862 ib_srq); 1863 struct bnxt_re_srq tsrq; 1864 struct bnxt_re_dev *rdev = srq->rdev; 1865 int rc; 1866 1867 /* Get live SRQ attr */ 1868 tsrq.qplib_srq.id = srq->qplib_srq.id; 1869 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1870 if (rc) { 1871 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!"); 1872 return rc; 1873 } 1874 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1875 srq_attr->max_sge = srq->qplib_srq.max_sge; 1876 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1877 1878 return 0; 1879 } 1880 1881 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1882 const struct ib_recv_wr **bad_wr) 1883 { 1884 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1885 ib_srq); 1886 struct bnxt_qplib_swqe wqe; 1887 unsigned long flags; 1888 int rc = 0; 1889 1890 spin_lock_irqsave(&srq->lock, flags); 1891 while (wr) { 1892 /* Transcribe each ib_recv_wr to qplib_swqe */ 1893 wqe.num_sge = wr->num_sge; 1894 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1895 wqe.wr_id = wr->wr_id; 1896 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1897 1898 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1899 if (rc) { 1900 *bad_wr = wr; 1901 break; 1902 } 1903 wr = wr->next; 1904 } 1905 spin_unlock_irqrestore(&srq->lock, flags); 1906 1907 return rc; 1908 } 1909 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1910 struct bnxt_re_qp *qp1_qp, 1911 int qp_attr_mask) 1912 { 1913 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp; 1914 int rc; 1915 1916 if (qp_attr_mask & IB_QP_STATE) { 1917 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1918 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1919 } 1920 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1921 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1922 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1923 } 1924 1925 if (qp_attr_mask & IB_QP_QKEY) { 1926 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1927 /* Using a Random QKEY */ 1928 qp->qplib_qp.qkey = 0x81818181; 1929 } 1930 if (qp_attr_mask & IB_QP_SQ_PSN) { 1931 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1932 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1933 } 1934 1935 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1936 if (rc) 1937 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1"); 1938 return rc; 1939 } 1940 1941 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1942 int qp_attr_mask, struct ib_udata *udata) 1943 { 1944 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1945 struct bnxt_re_dev *rdev = qp->rdev; 1946 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1947 enum ib_qp_state curr_qp_state, new_qp_state; 1948 int rc, entries; 1949 unsigned int flags; 1950 u8 nw_type; 1951 1952 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 1953 return -EOPNOTSUPP; 1954 1955 qp->qplib_qp.modify_flags = 0; 1956 if (qp_attr_mask & IB_QP_STATE) { 1957 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1958 new_qp_state = qp_attr->qp_state; 1959 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1960 ib_qp->qp_type, qp_attr_mask)) { 1961 ibdev_err(&rdev->ibdev, 1962 "Invalid attribute mask: %#x specified ", 1963 qp_attr_mask); 1964 ibdev_err(&rdev->ibdev, 1965 "for qpn: %#x type: %#x", 1966 ib_qp->qp_num, ib_qp->qp_type); 1967 ibdev_err(&rdev->ibdev, 1968 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1969 curr_qp_state, new_qp_state); 1970 return -EINVAL; 1971 } 1972 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1973 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1974 1975 if (!qp->sumem && 1976 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1977 ibdev_dbg(&rdev->ibdev, 1978 "Move QP = %p to flush list\n", qp); 1979 flags = bnxt_re_lock_cqs(qp); 1980 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1981 bnxt_re_unlock_cqs(qp, flags); 1982 } 1983 if (!qp->sumem && 1984 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1985 ibdev_dbg(&rdev->ibdev, 1986 "Move QP = %p out of flush list\n", qp); 1987 flags = bnxt_re_lock_cqs(qp); 1988 bnxt_qplib_clean_qp(&qp->qplib_qp); 1989 bnxt_re_unlock_cqs(qp, flags); 1990 } 1991 } 1992 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1993 qp->qplib_qp.modify_flags |= 1994 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1995 qp->qplib_qp.en_sqd_async_notify = true; 1996 } 1997 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1998 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1999 qp->qplib_qp.access = 2000 __from_ib_access_flags(qp_attr->qp_access_flags); 2001 /* LOCAL_WRITE access must be set to allow RC receive */ 2002 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 2003 /* Temp: Set all params on QP as of now */ 2004 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 2005 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 2006 } 2007 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 2008 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 2009 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 2010 } 2011 if (qp_attr_mask & IB_QP_QKEY) { 2012 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 2013 qp->qplib_qp.qkey = qp_attr->qkey; 2014 } 2015 if (qp_attr_mask & IB_QP_AV) { 2016 const struct ib_global_route *grh = 2017 rdma_ah_read_grh(&qp_attr->ah_attr); 2018 const struct ib_gid_attr *sgid_attr; 2019 struct bnxt_re_gid_ctx *ctx; 2020 2021 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 2022 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 2023 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 2024 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 2025 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 2026 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 2027 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 2028 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 2029 sizeof(qp->qplib_qp.ah.dgid.data)); 2030 qp->qplib_qp.ah.flow_label = grh->flow_label; 2031 sgid_attr = grh->sgid_attr; 2032 /* Get the HW context of the GID. The reference 2033 * of GID table entry is already taken by the caller. 2034 */ 2035 ctx = rdma_read_gid_hw_context(sgid_attr); 2036 qp->qplib_qp.ah.sgid_index = ctx->idx; 2037 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 2038 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 2039 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 2040 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 2041 ether_addr_copy(qp->qplib_qp.ah.dmac, 2042 qp_attr->ah_attr.roce.dmac); 2043 2044 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 2045 &qp->qplib_qp.smac[0]); 2046 if (rc) 2047 return rc; 2048 2049 nw_type = rdma_gid_attr_network_type(sgid_attr); 2050 switch (nw_type) { 2051 case RDMA_NETWORK_IPV4: 2052 qp->qplib_qp.nw_type = 2053 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 2054 break; 2055 case RDMA_NETWORK_IPV6: 2056 qp->qplib_qp.nw_type = 2057 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 2058 break; 2059 default: 2060 qp->qplib_qp.nw_type = 2061 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 2062 break; 2063 } 2064 } 2065 2066 if (qp_attr_mask & IB_QP_PATH_MTU) { 2067 qp->qplib_qp.modify_flags |= 2068 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2069 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 2070 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 2071 } else if (qp_attr->qp_state == IB_QPS_RTR) { 2072 qp->qplib_qp.modify_flags |= 2073 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2074 qp->qplib_qp.path_mtu = 2075 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 2076 qp->qplib_qp.mtu = 2077 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 2078 } 2079 2080 if (qp_attr_mask & IB_QP_TIMEOUT) { 2081 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 2082 qp->qplib_qp.timeout = qp_attr->timeout; 2083 } 2084 if (qp_attr_mask & IB_QP_RETRY_CNT) { 2085 qp->qplib_qp.modify_flags |= 2086 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 2087 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 2088 } 2089 if (qp_attr_mask & IB_QP_RNR_RETRY) { 2090 qp->qplib_qp.modify_flags |= 2091 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 2092 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 2093 } 2094 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 2095 qp->qplib_qp.modify_flags |= 2096 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 2097 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 2098 } 2099 if (qp_attr_mask & IB_QP_RQ_PSN) { 2100 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 2101 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 2102 } 2103 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2104 qp->qplib_qp.modify_flags |= 2105 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 2106 /* Cap the max_rd_atomic to device max */ 2107 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 2108 dev_attr->max_qp_rd_atom); 2109 } 2110 if (qp_attr_mask & IB_QP_SQ_PSN) { 2111 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2112 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 2113 } 2114 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2115 if (qp_attr->max_dest_rd_atomic > 2116 dev_attr->max_qp_init_rd_atom) { 2117 ibdev_err(&rdev->ibdev, 2118 "max_dest_rd_atomic requested%d is > dev_max%d", 2119 qp_attr->max_dest_rd_atomic, 2120 dev_attr->max_qp_init_rd_atom); 2121 return -EINVAL; 2122 } 2123 2124 qp->qplib_qp.modify_flags |= 2125 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 2126 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 2127 } 2128 if (qp_attr_mask & IB_QP_CAP) { 2129 struct bnxt_re_ucontext *uctx = 2130 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2131 2132 qp->qplib_qp.modify_flags |= 2133 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 2134 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 2135 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 2136 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 2137 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 2138 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 2139 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 2140 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 2141 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 2142 (qp_attr->cap.max_inline_data >= 2143 dev_attr->max_inline_data)) { 2144 ibdev_err(&rdev->ibdev, 2145 "Create QP failed - max exceeded"); 2146 return -EINVAL; 2147 } 2148 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx); 2149 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 2150 dev_attr->max_qp_wqes + 1); 2151 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 2152 qp_attr->cap.max_send_wr; 2153 /* 2154 * Reserving one slot for Phantom WQE. Some application can 2155 * post one extra entry in this case. Allowing this to avoid 2156 * unexpected Queue full condition 2157 */ 2158 qp->qplib_qp.sq.q_full_delta -= 1; 2159 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 2160 if (qp->qplib_qp.rq.max_wqe) { 2161 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx); 2162 qp->qplib_qp.rq.max_wqe = 2163 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 2164 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe; 2165 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 2166 qp_attr->cap.max_recv_wr; 2167 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 2168 } else { 2169 /* SRQ was used prior, just ignore the RQ caps */ 2170 } 2171 } 2172 if (qp_attr_mask & IB_QP_DEST_QPN) { 2173 qp->qplib_qp.modify_flags |= 2174 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 2175 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 2176 } 2177 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2178 if (rc) { 2179 ibdev_err(&rdev->ibdev, "Failed to modify HW QP"); 2180 return rc; 2181 } 2182 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 2183 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 2184 return rc; 2185 } 2186 2187 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2188 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 2189 { 2190 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2191 struct bnxt_re_dev *rdev = qp->rdev; 2192 struct bnxt_qplib_qp *qplib_qp; 2193 int rc; 2194 2195 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 2196 if (!qplib_qp) 2197 return -ENOMEM; 2198 2199 qplib_qp->id = qp->qplib_qp.id; 2200 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 2201 2202 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 2203 if (rc) { 2204 ibdev_err(&rdev->ibdev, "Failed to query HW QP"); 2205 goto out; 2206 } 2207 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 2208 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state); 2209 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 2210 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 2211 qp_attr->pkey_index = qplib_qp->pkey_index; 2212 qp_attr->qkey = qplib_qp->qkey; 2213 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2214 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 2215 qplib_qp->ah.host_sgid_index, 2216 qplib_qp->ah.hop_limit, 2217 qplib_qp->ah.traffic_class); 2218 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 2219 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 2220 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 2221 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 2222 qp_attr->timeout = qplib_qp->timeout; 2223 qp_attr->retry_cnt = qplib_qp->retry_cnt; 2224 qp_attr->rnr_retry = qplib_qp->rnr_retry; 2225 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 2226 qp_attr->rq_psn = qplib_qp->rq.psn; 2227 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 2228 qp_attr->sq_psn = qplib_qp->sq.psn; 2229 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 2230 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 2231 IB_SIGNAL_REQ_WR; 2232 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 2233 2234 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 2235 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 2236 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 2237 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 2238 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 2239 qp_init_attr->cap = qp_attr->cap; 2240 2241 out: 2242 kfree(qplib_qp); 2243 return rc; 2244 } 2245 2246 /* Routine for sending QP1 packets for RoCE V1 an V2 2247 */ 2248 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 2249 const struct ib_send_wr *wr, 2250 struct bnxt_qplib_swqe *wqe, 2251 int payload_size) 2252 { 2253 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 2254 ib_ah); 2255 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 2256 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 2257 struct bnxt_qplib_sge sge; 2258 u8 nw_type; 2259 u16 ether_type; 2260 union ib_gid dgid; 2261 bool is_eth = false; 2262 bool is_vlan = false; 2263 bool is_grh = false; 2264 bool is_udp = false; 2265 u8 ip_version = 0; 2266 u16 vlan_id = 0xFFFF; 2267 void *buf; 2268 int i, rc; 2269 2270 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 2271 2272 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 2273 if (rc) 2274 return rc; 2275 2276 /* Get network header type for this GID */ 2277 nw_type = rdma_gid_attr_network_type(sgid_attr); 2278 switch (nw_type) { 2279 case RDMA_NETWORK_IPV4: 2280 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 2281 break; 2282 case RDMA_NETWORK_IPV6: 2283 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 2284 break; 2285 default: 2286 nw_type = BNXT_RE_ROCE_V1_PACKET; 2287 break; 2288 } 2289 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 2290 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2291 if (is_udp) { 2292 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 2293 ip_version = 4; 2294 ether_type = ETH_P_IP; 2295 } else { 2296 ip_version = 6; 2297 ether_type = ETH_P_IPV6; 2298 } 2299 is_grh = false; 2300 } else { 2301 ether_type = ETH_P_IBOE; 2302 is_grh = true; 2303 } 2304 2305 is_eth = true; 2306 is_vlan = vlan_id && (vlan_id < 0x1000); 2307 2308 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 2309 ip_version, is_udp, 0, &qp->qp1_hdr); 2310 2311 /* ETH */ 2312 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 2313 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 2314 2315 /* For vlan, check the sgid for vlan existence */ 2316 2317 if (!is_vlan) { 2318 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 2319 } else { 2320 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 2321 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 2322 } 2323 2324 if (is_grh || (ip_version == 6)) { 2325 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 2326 sizeof(sgid_attr->gid)); 2327 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 2328 sizeof(sgid_attr->gid)); 2329 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 2330 } 2331 2332 if (ip_version == 4) { 2333 qp->qp1_hdr.ip4.tos = 0; 2334 qp->qp1_hdr.ip4.id = 0; 2335 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 2336 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 2337 2338 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 2339 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 2340 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 2341 } 2342 2343 if (is_udp) { 2344 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 2345 qp->qp1_hdr.udp.sport = htons(0x8CD1); 2346 qp->qp1_hdr.udp.csum = 0; 2347 } 2348 2349 /* BTH */ 2350 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 2351 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2352 qp->qp1_hdr.immediate_present = 1; 2353 } else { 2354 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2355 } 2356 if (wr->send_flags & IB_SEND_SOLICITED) 2357 qp->qp1_hdr.bth.solicited_event = 1; 2358 /* pad_count */ 2359 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 2360 2361 /* P_key for QP1 is for all members */ 2362 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 2363 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 2364 qp->qp1_hdr.bth.ack_req = 0; 2365 qp->send_psn++; 2366 qp->send_psn &= BTH_PSN_MASK; 2367 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 2368 /* DETH */ 2369 /* Use the priviledged Q_Key for QP1 */ 2370 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 2371 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2372 2373 /* Pack the QP1 to the transmit buffer */ 2374 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2375 if (buf) { 2376 ib_ud_header_pack(&qp->qp1_hdr, buf); 2377 for (i = wqe->num_sge; i; i--) { 2378 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2379 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2380 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2381 } 2382 2383 /* 2384 * Max Header buf size for IPV6 RoCE V2 is 86, 2385 * which is same as the QP1 SQ header buffer. 2386 * Header buf size for IPV4 RoCE V2 can be 66. 2387 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2388 * Subtract 20 bytes from QP1 SQ header buf size 2389 */ 2390 if (is_udp && ip_version == 4) 2391 sge.size -= 20; 2392 /* 2393 * Max Header buf size for RoCE V1 is 78. 2394 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2395 * Subtract 8 bytes from QP1 SQ header buf size 2396 */ 2397 if (!is_udp) 2398 sge.size -= 8; 2399 2400 /* Subtract 4 bytes for non vlan packets */ 2401 if (!is_vlan) 2402 sge.size -= 4; 2403 2404 wqe->sg_list[0].addr = sge.addr; 2405 wqe->sg_list[0].lkey = sge.lkey; 2406 wqe->sg_list[0].size = sge.size; 2407 wqe->num_sge++; 2408 2409 } else { 2410 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!"); 2411 rc = -ENOMEM; 2412 } 2413 return rc; 2414 } 2415 2416 /* For the MAD layer, it only provides the recv SGE the size of 2417 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2418 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2419 * receive packet (334 bytes) with no VLAN and then copy the GRH 2420 * and the MAD datagram out to the provided SGE. 2421 */ 2422 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2423 const struct ib_recv_wr *wr, 2424 struct bnxt_qplib_swqe *wqe, 2425 int payload_size) 2426 { 2427 struct bnxt_re_sqp_entries *sqp_entry; 2428 struct bnxt_qplib_sge ref, sge; 2429 struct bnxt_re_dev *rdev; 2430 u32 rq_prod_index; 2431 2432 rdev = qp->rdev; 2433 2434 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2435 2436 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2437 return -ENOMEM; 2438 2439 /* Create 1 SGE to receive the entire 2440 * ethernet packet 2441 */ 2442 /* Save the reference from ULP */ 2443 ref.addr = wqe->sg_list[0].addr; 2444 ref.lkey = wqe->sg_list[0].lkey; 2445 ref.size = wqe->sg_list[0].size; 2446 2447 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index]; 2448 2449 /* SGE 1 */ 2450 wqe->sg_list[0].addr = sge.addr; 2451 wqe->sg_list[0].lkey = sge.lkey; 2452 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2453 sge.size -= wqe->sg_list[0].size; 2454 2455 sqp_entry->sge.addr = ref.addr; 2456 sqp_entry->sge.lkey = ref.lkey; 2457 sqp_entry->sge.size = ref.size; 2458 /* Store the wrid for reporting completion */ 2459 sqp_entry->wrid = wqe->wr_id; 2460 /* change the wqe->wrid to table index */ 2461 wqe->wr_id = rq_prod_index; 2462 return 0; 2463 } 2464 2465 static int is_ud_qp(struct bnxt_re_qp *qp) 2466 { 2467 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2468 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2469 } 2470 2471 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2472 const struct ib_send_wr *wr, 2473 struct bnxt_qplib_swqe *wqe) 2474 { 2475 struct bnxt_re_ah *ah = NULL; 2476 2477 if (is_ud_qp(qp)) { 2478 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2479 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2480 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2481 wqe->send.avid = ah->qplib_ah.id; 2482 } 2483 switch (wr->opcode) { 2484 case IB_WR_SEND: 2485 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2486 break; 2487 case IB_WR_SEND_WITH_IMM: 2488 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2489 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data); 2490 break; 2491 case IB_WR_SEND_WITH_INV: 2492 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2493 wqe->send.inv_key = wr->ex.invalidate_rkey; 2494 break; 2495 default: 2496 return -EINVAL; 2497 } 2498 if (wr->send_flags & IB_SEND_SIGNALED) 2499 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2500 if (wr->send_flags & IB_SEND_FENCE) 2501 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2502 if (wr->send_flags & IB_SEND_SOLICITED) 2503 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2504 if (wr->send_flags & IB_SEND_INLINE) 2505 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2506 2507 return 0; 2508 } 2509 2510 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2511 struct bnxt_qplib_swqe *wqe) 2512 { 2513 switch (wr->opcode) { 2514 case IB_WR_RDMA_WRITE: 2515 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2516 break; 2517 case IB_WR_RDMA_WRITE_WITH_IMM: 2518 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2519 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data); 2520 break; 2521 case IB_WR_RDMA_READ: 2522 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2523 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2524 break; 2525 default: 2526 return -EINVAL; 2527 } 2528 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2529 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2530 if (wr->send_flags & IB_SEND_SIGNALED) 2531 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2532 if (wr->send_flags & IB_SEND_FENCE) 2533 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2534 if (wr->send_flags & IB_SEND_SOLICITED) 2535 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2536 if (wr->send_flags & IB_SEND_INLINE) 2537 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2538 2539 return 0; 2540 } 2541 2542 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2543 struct bnxt_qplib_swqe *wqe) 2544 { 2545 switch (wr->opcode) { 2546 case IB_WR_ATOMIC_CMP_AND_SWP: 2547 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2548 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2549 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2550 break; 2551 case IB_WR_ATOMIC_FETCH_AND_ADD: 2552 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2553 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2554 break; 2555 default: 2556 return -EINVAL; 2557 } 2558 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2559 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2560 if (wr->send_flags & IB_SEND_SIGNALED) 2561 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2562 if (wr->send_flags & IB_SEND_FENCE) 2563 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2564 if (wr->send_flags & IB_SEND_SOLICITED) 2565 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2566 return 0; 2567 } 2568 2569 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2570 struct bnxt_qplib_swqe *wqe) 2571 { 2572 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2573 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2574 2575 if (wr->send_flags & IB_SEND_SIGNALED) 2576 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2577 if (wr->send_flags & IB_SEND_SOLICITED) 2578 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2579 2580 return 0; 2581 } 2582 2583 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2584 struct bnxt_qplib_swqe *wqe) 2585 { 2586 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2587 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2588 int access = wr->access; 2589 2590 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2591 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2592 wqe->frmr.page_list = mr->pages; 2593 wqe->frmr.page_list_len = mr->npages; 2594 wqe->frmr.levels = qplib_frpl->hwq.level; 2595 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2596 2597 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2598 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2599 2600 if (access & IB_ACCESS_LOCAL_WRITE) 2601 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2602 if (access & IB_ACCESS_REMOTE_READ) 2603 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2604 if (access & IB_ACCESS_REMOTE_WRITE) 2605 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2606 if (access & IB_ACCESS_REMOTE_ATOMIC) 2607 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2608 if (access & IB_ACCESS_MW_BIND) 2609 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2610 2611 wqe->frmr.l_key = wr->key; 2612 wqe->frmr.length = wr->mr->length; 2613 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K); 2614 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K); 2615 wqe->frmr.va = wr->mr->iova; 2616 return 0; 2617 } 2618 2619 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2620 const struct ib_send_wr *wr, 2621 struct bnxt_qplib_swqe *wqe) 2622 { 2623 /* Copy the inline data to the data field */ 2624 u8 *in_data; 2625 u32 i, sge_len; 2626 void *sge_addr; 2627 2628 in_data = wqe->inline_data; 2629 for (i = 0; i < wr->num_sge; i++) { 2630 sge_addr = (void *)(unsigned long) 2631 wr->sg_list[i].addr; 2632 sge_len = wr->sg_list[i].length; 2633 2634 if ((sge_len + wqe->inline_len) > 2635 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2636 ibdev_err(&rdev->ibdev, 2637 "Inline data size requested > supported value"); 2638 return -EINVAL; 2639 } 2640 sge_len = wr->sg_list[i].length; 2641 2642 memcpy(in_data, sge_addr, sge_len); 2643 in_data += wr->sg_list[i].length; 2644 wqe->inline_len += wr->sg_list[i].length; 2645 } 2646 return wqe->inline_len; 2647 } 2648 2649 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2650 const struct ib_send_wr *wr, 2651 struct bnxt_qplib_swqe *wqe) 2652 { 2653 int payload_sz = 0; 2654 2655 if (wr->send_flags & IB_SEND_INLINE) 2656 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2657 else 2658 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2659 wqe->num_sge); 2660 2661 return payload_sz; 2662 } 2663 2664 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2665 { 2666 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2667 qp->ib_qp.qp_type == IB_QPT_GSI || 2668 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2669 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2670 int qp_attr_mask; 2671 struct ib_qp_attr qp_attr; 2672 2673 qp_attr_mask = IB_QP_STATE; 2674 qp_attr.qp_state = IB_QPS_RTS; 2675 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2676 qp->qplib_qp.wqe_cnt = 0; 2677 } 2678 } 2679 2680 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2681 struct bnxt_re_qp *qp, 2682 const struct ib_send_wr *wr) 2683 { 2684 int rc = 0, payload_sz = 0; 2685 unsigned long flags; 2686 2687 spin_lock_irqsave(&qp->sq_lock, flags); 2688 while (wr) { 2689 struct bnxt_qplib_swqe wqe = {}; 2690 2691 /* Common */ 2692 wqe.num_sge = wr->num_sge; 2693 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2694 ibdev_err(&rdev->ibdev, 2695 "Limit exceeded for Send SGEs"); 2696 rc = -EINVAL; 2697 goto bad; 2698 } 2699 2700 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2701 if (payload_sz < 0) { 2702 rc = -EINVAL; 2703 goto bad; 2704 } 2705 wqe.wr_id = wr->wr_id; 2706 2707 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2708 2709 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2710 if (!rc) 2711 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2712 bad: 2713 if (rc) { 2714 ibdev_err(&rdev->ibdev, 2715 "Post send failed opcode = %#x rc = %d", 2716 wr->opcode, rc); 2717 break; 2718 } 2719 wr = wr->next; 2720 } 2721 bnxt_qplib_post_send_db(&qp->qplib_qp); 2722 bnxt_ud_qp_hw_stall_workaround(qp); 2723 spin_unlock_irqrestore(&qp->sq_lock, flags); 2724 return rc; 2725 } 2726 2727 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe) 2728 { 2729 /* Need unconditional fence for non-wire memory opcode 2730 * to work as expected. 2731 */ 2732 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV || 2733 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR || 2734 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR || 2735 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW) 2736 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2737 } 2738 2739 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2740 const struct ib_send_wr **bad_wr) 2741 { 2742 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2743 struct bnxt_qplib_swqe wqe; 2744 int rc = 0, payload_sz = 0; 2745 unsigned long flags; 2746 2747 spin_lock_irqsave(&qp->sq_lock, flags); 2748 while (wr) { 2749 /* House keeping */ 2750 memset(&wqe, 0, sizeof(wqe)); 2751 2752 /* Common */ 2753 wqe.num_sge = wr->num_sge; 2754 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2755 ibdev_err(&qp->rdev->ibdev, 2756 "Limit exceeded for Send SGEs"); 2757 rc = -EINVAL; 2758 goto bad; 2759 } 2760 2761 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2762 if (payload_sz < 0) { 2763 rc = -EINVAL; 2764 goto bad; 2765 } 2766 wqe.wr_id = wr->wr_id; 2767 2768 switch (wr->opcode) { 2769 case IB_WR_SEND: 2770 case IB_WR_SEND_WITH_IMM: 2771 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2772 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2773 payload_sz); 2774 if (rc) 2775 goto bad; 2776 wqe.rawqp1.lflags |= 2777 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2778 } 2779 switch (wr->send_flags) { 2780 case IB_SEND_IP_CSUM: 2781 wqe.rawqp1.lflags |= 2782 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2783 break; 2784 default: 2785 break; 2786 } 2787 fallthrough; 2788 case IB_WR_SEND_WITH_INV: 2789 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2790 break; 2791 case IB_WR_RDMA_WRITE: 2792 case IB_WR_RDMA_WRITE_WITH_IMM: 2793 case IB_WR_RDMA_READ: 2794 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2795 break; 2796 case IB_WR_ATOMIC_CMP_AND_SWP: 2797 case IB_WR_ATOMIC_FETCH_AND_ADD: 2798 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2799 break; 2800 case IB_WR_RDMA_READ_WITH_INV: 2801 ibdev_err(&qp->rdev->ibdev, 2802 "RDMA Read with Invalidate is not supported"); 2803 rc = -EINVAL; 2804 goto bad; 2805 case IB_WR_LOCAL_INV: 2806 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2807 break; 2808 case IB_WR_REG_MR: 2809 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2810 break; 2811 default: 2812 /* Unsupported WRs */ 2813 ibdev_err(&qp->rdev->ibdev, 2814 "WR (%#x) is not supported", wr->opcode); 2815 rc = -EINVAL; 2816 goto bad; 2817 } 2818 if (!rc) { 2819 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2820 bnxt_re_legacy_set_uc_fence(&wqe); 2821 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2822 } 2823 bad: 2824 if (rc) { 2825 ibdev_err(&qp->rdev->ibdev, 2826 "post_send failed op:%#x qps = %#x rc = %d\n", 2827 wr->opcode, qp->qplib_qp.state, rc); 2828 *bad_wr = wr; 2829 break; 2830 } 2831 wr = wr->next; 2832 } 2833 bnxt_qplib_post_send_db(&qp->qplib_qp); 2834 bnxt_ud_qp_hw_stall_workaround(qp); 2835 spin_unlock_irqrestore(&qp->sq_lock, flags); 2836 2837 return rc; 2838 } 2839 2840 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2841 struct bnxt_re_qp *qp, 2842 const struct ib_recv_wr *wr) 2843 { 2844 struct bnxt_qplib_swqe wqe; 2845 int rc = 0; 2846 2847 while (wr) { 2848 /* House keeping */ 2849 memset(&wqe, 0, sizeof(wqe)); 2850 2851 /* Common */ 2852 wqe.num_sge = wr->num_sge; 2853 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2854 ibdev_err(&rdev->ibdev, 2855 "Limit exceeded for Receive SGEs"); 2856 rc = -EINVAL; 2857 break; 2858 } 2859 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2860 wqe.wr_id = wr->wr_id; 2861 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2862 2863 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2864 if (rc) 2865 break; 2866 2867 wr = wr->next; 2868 } 2869 if (!rc) 2870 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2871 return rc; 2872 } 2873 2874 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2875 const struct ib_recv_wr **bad_wr) 2876 { 2877 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2878 struct bnxt_qplib_swqe wqe; 2879 int rc = 0, payload_sz = 0; 2880 unsigned long flags; 2881 u32 count = 0; 2882 2883 spin_lock_irqsave(&qp->rq_lock, flags); 2884 while (wr) { 2885 /* House keeping */ 2886 memset(&wqe, 0, sizeof(wqe)); 2887 2888 /* Common */ 2889 wqe.num_sge = wr->num_sge; 2890 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2891 ibdev_err(&qp->rdev->ibdev, 2892 "Limit exceeded for Receive SGEs"); 2893 rc = -EINVAL; 2894 *bad_wr = wr; 2895 break; 2896 } 2897 2898 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2899 wr->num_sge); 2900 wqe.wr_id = wr->wr_id; 2901 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2902 2903 if (ib_qp->qp_type == IB_QPT_GSI && 2904 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 2905 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2906 payload_sz); 2907 if (!rc) 2908 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2909 if (rc) { 2910 *bad_wr = wr; 2911 break; 2912 } 2913 2914 /* Ring DB if the RQEs posted reaches a threshold value */ 2915 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2916 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2917 count = 0; 2918 } 2919 2920 wr = wr->next; 2921 } 2922 2923 if (count) 2924 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2925 2926 spin_unlock_irqrestore(&qp->rq_lock, flags); 2927 2928 return rc; 2929 } 2930 2931 /* Completion Queues */ 2932 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 2933 { 2934 struct bnxt_qplib_chip_ctx *cctx; 2935 struct bnxt_qplib_nq *nq; 2936 struct bnxt_re_dev *rdev; 2937 struct bnxt_re_cq *cq; 2938 2939 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2940 rdev = cq->rdev; 2941 nq = cq->qplib_cq.nq; 2942 cctx = rdev->chip_ctx; 2943 2944 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 2945 free_page((unsigned long)cq->uctx_cq_page); 2946 hash_del(&cq->hash_entry); 2947 } 2948 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2949 ib_umem_release(cq->umem); 2950 2951 atomic_dec(&rdev->stats.res.cq_count); 2952 nq->budget--; 2953 kfree(cq->cql); 2954 return 0; 2955 } 2956 2957 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 2958 struct uverbs_attr_bundle *attrs) 2959 { 2960 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 2961 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 2962 struct ib_udata *udata = &attrs->driver_udata; 2963 struct bnxt_re_ucontext *uctx = 2964 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2965 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2966 struct bnxt_qplib_chip_ctx *cctx; 2967 struct bnxt_qplib_nq *nq = NULL; 2968 unsigned int nq_alloc_cnt; 2969 int cqe = attr->cqe; 2970 int rc, entries; 2971 u32 active_cqs; 2972 2973 if (attr->flags) 2974 return -EOPNOTSUPP; 2975 2976 /* Validate CQ fields */ 2977 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2978 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded"); 2979 return -EINVAL; 2980 } 2981 2982 cq->rdev = rdev; 2983 cctx = rdev->chip_ctx; 2984 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2985 2986 entries = bnxt_re_init_depth(cqe + 1, uctx); 2987 if (entries > dev_attr->max_cq_wqes + 1) 2988 entries = dev_attr->max_cq_wqes + 1; 2989 2990 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 2991 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 2992 if (udata) { 2993 struct bnxt_re_cq_req req; 2994 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2995 rc = -EFAULT; 2996 goto fail; 2997 } 2998 2999 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3000 entries * sizeof(struct cq_base), 3001 IB_ACCESS_LOCAL_WRITE); 3002 if (IS_ERR(cq->umem)) { 3003 rc = PTR_ERR(cq->umem); 3004 goto fail; 3005 } 3006 cq->qplib_cq.sg_info.umem = cq->umem; 3007 cq->qplib_cq.dpi = &uctx->dpi; 3008 } else { 3009 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 3010 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 3011 GFP_KERNEL); 3012 if (!cq->cql) { 3013 rc = -ENOMEM; 3014 goto fail; 3015 } 3016 3017 cq->qplib_cq.dpi = &rdev->dpi_privileged; 3018 } 3019 /* 3020 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 3021 * used for getting the NQ index. 3022 */ 3023 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 3024 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 3025 cq->qplib_cq.max_wqe = entries; 3026 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 3027 cq->qplib_cq.nq = nq; 3028 3029 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 3030 if (rc) { 3031 ibdev_err(&rdev->ibdev, "Failed to create HW CQ"); 3032 goto fail; 3033 } 3034 3035 cq->ib_cq.cqe = entries; 3036 cq->cq_period = cq->qplib_cq.period; 3037 nq->budget++; 3038 3039 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count); 3040 if (active_cqs > rdev->stats.res.cq_watermark) 3041 rdev->stats.res.cq_watermark = active_cqs; 3042 spin_lock_init(&cq->cq_lock); 3043 3044 if (udata) { 3045 struct bnxt_re_cq_resp resp = {}; 3046 3047 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 3048 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id); 3049 /* Allocate a page */ 3050 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL); 3051 if (!cq->uctx_cq_page) { 3052 rc = -ENOMEM; 3053 goto c2fail; 3054 } 3055 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT; 3056 } 3057 resp.cqid = cq->qplib_cq.id; 3058 resp.tail = cq->qplib_cq.hwq.cons; 3059 resp.phase = cq->qplib_cq.period; 3060 resp.rsvd = 0; 3061 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 3062 if (rc) { 3063 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata"); 3064 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3065 goto free_mem; 3066 } 3067 } 3068 3069 return 0; 3070 3071 free_mem: 3072 free_page((unsigned long)cq->uctx_cq_page); 3073 c2fail: 3074 ib_umem_release(cq->umem); 3075 fail: 3076 kfree(cq->cql); 3077 return rc; 3078 } 3079 3080 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq) 3081 { 3082 struct bnxt_re_dev *rdev = cq->rdev; 3083 3084 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq); 3085 3086 cq->qplib_cq.max_wqe = cq->resize_cqe; 3087 if (cq->resize_umem) { 3088 ib_umem_release(cq->umem); 3089 cq->umem = cq->resize_umem; 3090 cq->resize_umem = NULL; 3091 cq->resize_cqe = 0; 3092 } 3093 } 3094 3095 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata) 3096 { 3097 struct bnxt_qplib_sg_info sg_info = {}; 3098 struct bnxt_qplib_dpi *orig_dpi = NULL; 3099 struct bnxt_qplib_dev_attr *dev_attr; 3100 struct bnxt_re_ucontext *uctx = NULL; 3101 struct bnxt_re_resize_cq_req req; 3102 struct bnxt_re_dev *rdev; 3103 struct bnxt_re_cq *cq; 3104 int rc, entries; 3105 3106 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3107 rdev = cq->rdev; 3108 dev_attr = &rdev->dev_attr; 3109 if (!ibcq->uobject) { 3110 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported"); 3111 return -EOPNOTSUPP; 3112 } 3113 3114 if (cq->resize_umem) { 3115 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy", 3116 cq->qplib_cq.id); 3117 return -EBUSY; 3118 } 3119 3120 /* Check the requested cq depth out of supported depth */ 3121 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3122 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d", 3123 cq->qplib_cq.id, cqe); 3124 return -EINVAL; 3125 } 3126 3127 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3128 entries = bnxt_re_init_depth(cqe + 1, uctx); 3129 if (entries > dev_attr->max_cq_wqes + 1) 3130 entries = dev_attr->max_cq_wqes + 1; 3131 3132 /* uverbs consumer */ 3133 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3134 rc = -EFAULT; 3135 goto fail; 3136 } 3137 3138 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3139 entries * sizeof(struct cq_base), 3140 IB_ACCESS_LOCAL_WRITE); 3141 if (IS_ERR(cq->resize_umem)) { 3142 rc = PTR_ERR(cq->resize_umem); 3143 cq->resize_umem = NULL; 3144 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n", 3145 __func__, rc); 3146 goto fail; 3147 } 3148 cq->resize_cqe = entries; 3149 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info)); 3150 orig_dpi = cq->qplib_cq.dpi; 3151 3152 cq->qplib_cq.sg_info.umem = cq->resize_umem; 3153 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3154 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3155 cq->qplib_cq.dpi = &uctx->dpi; 3156 3157 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries); 3158 if (rc) { 3159 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!", 3160 cq->qplib_cq.id); 3161 goto fail; 3162 } 3163 3164 cq->ib_cq.cqe = cq->resize_cqe; 3165 atomic_inc(&rdev->stats.res.resize_count); 3166 3167 return 0; 3168 3169 fail: 3170 if (cq->resize_umem) { 3171 ib_umem_release(cq->resize_umem); 3172 cq->resize_umem = NULL; 3173 cq->resize_cqe = 0; 3174 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info)); 3175 cq->qplib_cq.dpi = orig_dpi; 3176 } 3177 return rc; 3178 } 3179 3180 static u8 __req_to_ib_wc_status(u8 qstatus) 3181 { 3182 switch (qstatus) { 3183 case CQ_REQ_STATUS_OK: 3184 return IB_WC_SUCCESS; 3185 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 3186 return IB_WC_BAD_RESP_ERR; 3187 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 3188 return IB_WC_LOC_LEN_ERR; 3189 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 3190 return IB_WC_LOC_QP_OP_ERR; 3191 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 3192 return IB_WC_LOC_PROT_ERR; 3193 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 3194 return IB_WC_GENERAL_ERR; 3195 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 3196 return IB_WC_REM_INV_REQ_ERR; 3197 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 3198 return IB_WC_REM_ACCESS_ERR; 3199 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 3200 return IB_WC_REM_OP_ERR; 3201 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 3202 return IB_WC_RNR_RETRY_EXC_ERR; 3203 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 3204 return IB_WC_RETRY_EXC_ERR; 3205 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 3206 return IB_WC_WR_FLUSH_ERR; 3207 default: 3208 return IB_WC_GENERAL_ERR; 3209 } 3210 return 0; 3211 } 3212 3213 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 3214 { 3215 switch (qstatus) { 3216 case CQ_RES_RAWETH_QP1_STATUS_OK: 3217 return IB_WC_SUCCESS; 3218 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 3219 return IB_WC_LOC_ACCESS_ERR; 3220 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 3221 return IB_WC_LOC_LEN_ERR; 3222 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 3223 return IB_WC_LOC_PROT_ERR; 3224 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 3225 return IB_WC_LOC_QP_OP_ERR; 3226 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 3227 return IB_WC_GENERAL_ERR; 3228 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 3229 return IB_WC_WR_FLUSH_ERR; 3230 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 3231 return IB_WC_WR_FLUSH_ERR; 3232 default: 3233 return IB_WC_GENERAL_ERR; 3234 } 3235 } 3236 3237 static u8 __rc_to_ib_wc_status(u8 qstatus) 3238 { 3239 switch (qstatus) { 3240 case CQ_RES_RC_STATUS_OK: 3241 return IB_WC_SUCCESS; 3242 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 3243 return IB_WC_LOC_ACCESS_ERR; 3244 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 3245 return IB_WC_LOC_LEN_ERR; 3246 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 3247 return IB_WC_LOC_PROT_ERR; 3248 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 3249 return IB_WC_LOC_QP_OP_ERR; 3250 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 3251 return IB_WC_GENERAL_ERR; 3252 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 3253 return IB_WC_REM_INV_REQ_ERR; 3254 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 3255 return IB_WC_WR_FLUSH_ERR; 3256 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 3257 return IB_WC_WR_FLUSH_ERR; 3258 default: 3259 return IB_WC_GENERAL_ERR; 3260 } 3261 } 3262 3263 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 3264 { 3265 switch (cqe->type) { 3266 case BNXT_QPLIB_SWQE_TYPE_SEND: 3267 wc->opcode = IB_WC_SEND; 3268 break; 3269 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 3270 wc->opcode = IB_WC_SEND; 3271 wc->wc_flags |= IB_WC_WITH_IMM; 3272 break; 3273 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 3274 wc->opcode = IB_WC_SEND; 3275 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3276 break; 3277 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 3278 wc->opcode = IB_WC_RDMA_WRITE; 3279 break; 3280 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 3281 wc->opcode = IB_WC_RDMA_WRITE; 3282 wc->wc_flags |= IB_WC_WITH_IMM; 3283 break; 3284 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 3285 wc->opcode = IB_WC_RDMA_READ; 3286 break; 3287 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 3288 wc->opcode = IB_WC_COMP_SWAP; 3289 break; 3290 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 3291 wc->opcode = IB_WC_FETCH_ADD; 3292 break; 3293 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 3294 wc->opcode = IB_WC_LOCAL_INV; 3295 break; 3296 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 3297 wc->opcode = IB_WC_REG_MR; 3298 break; 3299 default: 3300 wc->opcode = IB_WC_SEND; 3301 break; 3302 } 3303 3304 wc->status = __req_to_ib_wc_status(cqe->status); 3305 } 3306 3307 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 3308 u16 raweth_qp1_flags2) 3309 { 3310 bool is_ipv6 = false, is_ipv4 = false; 3311 3312 /* raweth_qp1_flags Bit 9-6 indicates itype */ 3313 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3314 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3315 return -1; 3316 3317 if (raweth_qp1_flags2 & 3318 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 3319 raweth_qp1_flags2 & 3320 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 3321 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 3322 (raweth_qp1_flags2 & 3323 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 3324 (is_ipv6 = true) : (is_ipv4 = true); 3325 return ((is_ipv6) ? 3326 BNXT_RE_ROCEV2_IPV6_PACKET : 3327 BNXT_RE_ROCEV2_IPV4_PACKET); 3328 } else { 3329 return BNXT_RE_ROCE_V1_PACKET; 3330 } 3331 } 3332 3333 static int bnxt_re_to_ib_nw_type(int nw_type) 3334 { 3335 u8 nw_hdr_type = 0xFF; 3336 3337 switch (nw_type) { 3338 case BNXT_RE_ROCE_V1_PACKET: 3339 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 3340 break; 3341 case BNXT_RE_ROCEV2_IPV4_PACKET: 3342 nw_hdr_type = RDMA_NETWORK_IPV4; 3343 break; 3344 case BNXT_RE_ROCEV2_IPV6_PACKET: 3345 nw_hdr_type = RDMA_NETWORK_IPV6; 3346 break; 3347 } 3348 return nw_hdr_type; 3349 } 3350 3351 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 3352 void *rq_hdr_buf) 3353 { 3354 u8 *tmp_buf = NULL; 3355 struct ethhdr *eth_hdr; 3356 u16 eth_type; 3357 bool rc = false; 3358 3359 tmp_buf = (u8 *)rq_hdr_buf; 3360 /* 3361 * If dest mac is not same as I/F mac, this could be a 3362 * loopback address or multicast address, check whether 3363 * it is a loopback packet 3364 */ 3365 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 3366 tmp_buf += 4; 3367 /* Check the ether type */ 3368 eth_hdr = (struct ethhdr *)tmp_buf; 3369 eth_type = ntohs(eth_hdr->h_proto); 3370 switch (eth_type) { 3371 case ETH_P_IBOE: 3372 rc = true; 3373 break; 3374 case ETH_P_IP: 3375 case ETH_P_IPV6: { 3376 u32 len; 3377 struct udphdr *udp_hdr; 3378 3379 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 3380 sizeof(struct ipv6hdr)); 3381 tmp_buf += sizeof(struct ethhdr) + len; 3382 udp_hdr = (struct udphdr *)tmp_buf; 3383 if (ntohs(udp_hdr->dest) == 3384 ROCE_V2_UDP_DPORT) 3385 rc = true; 3386 break; 3387 } 3388 default: 3389 break; 3390 } 3391 } 3392 3393 return rc; 3394 } 3395 3396 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp, 3397 struct bnxt_qplib_cqe *cqe) 3398 { 3399 struct bnxt_re_dev *rdev = gsi_qp->rdev; 3400 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3401 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp; 3402 dma_addr_t shrq_hdr_buf_map; 3403 struct ib_sge s_sge[2] = {}; 3404 struct ib_sge r_sge[2] = {}; 3405 struct bnxt_re_ah *gsi_sah; 3406 struct ib_recv_wr rwr = {}; 3407 dma_addr_t rq_hdr_buf_map; 3408 struct ib_ud_wr udwr = {}; 3409 struct ib_send_wr *swr; 3410 u32 skip_bytes = 0; 3411 int pkt_type = 0; 3412 void *rq_hdr_buf; 3413 u32 offset = 0; 3414 u32 tbl_idx; 3415 int rc; 3416 3417 swr = &udwr.wr; 3418 tbl_idx = cqe->wr_id; 3419 3420 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf + 3421 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size); 3422 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3423 tbl_idx); 3424 3425 /* Shadow QP header buffer */ 3426 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3427 tbl_idx); 3428 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3429 3430 /* Store this cqe */ 3431 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 3432 sqp_entry->qp1_qp = gsi_qp; 3433 3434 /* Find packet type from the cqe */ 3435 3436 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 3437 cqe->raweth_qp1_flags2); 3438 if (pkt_type < 0) { 3439 ibdev_err(&rdev->ibdev, "Invalid packet\n"); 3440 return -EINVAL; 3441 } 3442 3443 /* Adjust the offset for the user buffer and post in the rq */ 3444 3445 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 3446 offset = 20; 3447 3448 /* 3449 * QP1 loopback packet has 4 bytes of internal header before 3450 * ether header. Skip these four bytes. 3451 */ 3452 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 3453 skip_bytes = 4; 3454 3455 /* First send SGE . Skip the ether header*/ 3456 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 3457 + skip_bytes; 3458 s_sge[0].lkey = 0xFFFFFFFF; 3459 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 3460 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 3461 3462 /* Second Send SGE */ 3463 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 3464 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 3465 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 3466 s_sge[1].addr += 8; 3467 s_sge[1].lkey = 0xFFFFFFFF; 3468 s_sge[1].length = 256; 3469 3470 /* First recv SGE */ 3471 3472 r_sge[0].addr = shrq_hdr_buf_map; 3473 r_sge[0].lkey = 0xFFFFFFFF; 3474 r_sge[0].length = 40; 3475 3476 r_sge[1].addr = sqp_entry->sge.addr + offset; 3477 r_sge[1].lkey = sqp_entry->sge.lkey; 3478 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 3479 3480 /* Create receive work request */ 3481 rwr.num_sge = 2; 3482 rwr.sg_list = r_sge; 3483 rwr.wr_id = tbl_idx; 3484 rwr.next = NULL; 3485 3486 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr); 3487 if (rc) { 3488 ibdev_err(&rdev->ibdev, 3489 "Failed to post Rx buffers to shadow QP"); 3490 return -ENOMEM; 3491 } 3492 3493 swr->num_sge = 2; 3494 swr->sg_list = s_sge; 3495 swr->wr_id = tbl_idx; 3496 swr->opcode = IB_WR_SEND; 3497 swr->next = NULL; 3498 gsi_sah = rdev->gsi_ctx.gsi_sah; 3499 udwr.ah = &gsi_sah->ib_ah; 3500 udwr.remote_qpn = gsi_sqp->qplib_qp.id; 3501 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey; 3502 3503 /* post data received in the send queue */ 3504 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr); 3505 } 3506 3507 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 3508 struct bnxt_qplib_cqe *cqe) 3509 { 3510 wc->opcode = IB_WC_RECV; 3511 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 3512 wc->wc_flags |= IB_WC_GRH; 3513 } 3514 3515 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev, 3516 u16 vlan_id) 3517 { 3518 /* 3519 * Check if the vlan is configured in the host. If not configured, it 3520 * can be a transparent VLAN. So dont report the vlan id. 3521 */ 3522 if (!__vlan_find_dev_deep_rcu(rdev->netdev, 3523 htons(ETH_P_8021Q), vlan_id)) 3524 return false; 3525 return true; 3526 } 3527 3528 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 3529 u16 *vid, u8 *sl) 3530 { 3531 bool ret = false; 3532 u32 metadata; 3533 u16 tpid; 3534 3535 metadata = orig_cqe->raweth_qp1_metadata; 3536 if (orig_cqe->raweth_qp1_flags2 & 3537 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3538 tpid = ((metadata & 3539 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3540 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3541 if (tpid == ETH_P_8021Q) { 3542 *vid = metadata & 3543 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3544 *sl = (metadata & 3545 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3546 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3547 ret = true; 3548 } 3549 } 3550 3551 return ret; 3552 } 3553 3554 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3555 struct bnxt_qplib_cqe *cqe) 3556 { 3557 wc->opcode = IB_WC_RECV; 3558 wc->status = __rc_to_ib_wc_status(cqe->status); 3559 3560 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3561 wc->wc_flags |= IB_WC_WITH_IMM; 3562 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3563 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3564 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3565 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3566 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3567 } 3568 3569 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp, 3570 struct ib_wc *wc, 3571 struct bnxt_qplib_cqe *cqe) 3572 { 3573 struct bnxt_re_dev *rdev = gsi_sqp->rdev; 3574 struct bnxt_re_qp *gsi_qp = NULL; 3575 struct bnxt_qplib_cqe *orig_cqe = NULL; 3576 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3577 int nw_type; 3578 u32 tbl_idx; 3579 u16 vlan_id; 3580 u8 sl; 3581 3582 tbl_idx = cqe->wr_id; 3583 3584 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3585 gsi_qp = sqp_entry->qp1_qp; 3586 orig_cqe = &sqp_entry->cqe; 3587 3588 wc->wr_id = sqp_entry->wrid; 3589 wc->byte_len = orig_cqe->length; 3590 wc->qp = &gsi_qp->ib_qp; 3591 3592 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(orig_cqe->immdata)); 3593 wc->src_qp = orig_cqe->src_qp; 3594 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3595 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3596 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3597 wc->vlan_id = vlan_id; 3598 wc->sl = sl; 3599 wc->wc_flags |= IB_WC_WITH_VLAN; 3600 } 3601 } 3602 wc->port_num = 1; 3603 wc->vendor_err = orig_cqe->status; 3604 3605 wc->opcode = IB_WC_RECV; 3606 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3607 wc->wc_flags |= IB_WC_GRH; 3608 3609 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3610 orig_cqe->raweth_qp1_flags2); 3611 if (nw_type >= 0) { 3612 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3613 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3614 } 3615 } 3616 3617 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3618 struct ib_wc *wc, 3619 struct bnxt_qplib_cqe *cqe) 3620 { 3621 struct bnxt_re_dev *rdev; 3622 u16 vlan_id = 0; 3623 u8 nw_type; 3624 3625 rdev = qp->rdev; 3626 wc->opcode = IB_WC_RECV; 3627 wc->status = __rc_to_ib_wc_status(cqe->status); 3628 3629 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3630 wc->wc_flags |= IB_WC_WITH_IMM; 3631 /* report only on GSI QP for Thor */ 3632 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3633 wc->wc_flags |= IB_WC_GRH; 3634 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3635 wc->wc_flags |= IB_WC_WITH_SMAC; 3636 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3637 vlan_id = (cqe->cfa_meta & 0xFFF); 3638 } 3639 /* Mark only if vlan_id is non zero */ 3640 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3641 wc->vlan_id = vlan_id; 3642 wc->wc_flags |= IB_WC_WITH_VLAN; 3643 } 3644 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3645 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3646 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3647 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3648 } 3649 3650 } 3651 3652 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3653 { 3654 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3655 unsigned long flags; 3656 int rc; 3657 3658 spin_lock_irqsave(&qp->sq_lock, flags); 3659 3660 rc = bnxt_re_bind_fence_mw(lib_qp); 3661 if (!rc) { 3662 lib_qp->sq.phantom_wqe_cnt++; 3663 ibdev_dbg(&qp->rdev->ibdev, 3664 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3665 lib_qp->id, lib_qp->sq.hwq.prod, 3666 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3667 lib_qp->sq.phantom_wqe_cnt); 3668 } 3669 3670 spin_unlock_irqrestore(&qp->sq_lock, flags); 3671 return rc; 3672 } 3673 3674 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3675 { 3676 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3677 struct bnxt_re_qp *qp, *sh_qp; 3678 struct bnxt_qplib_cqe *cqe; 3679 int i, ncqe, budget; 3680 struct bnxt_qplib_q *sq; 3681 struct bnxt_qplib_qp *lib_qp; 3682 u32 tbl_idx; 3683 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3684 unsigned long flags; 3685 3686 /* User CQ; the only processing we do is to 3687 * complete any pending CQ resize operation. 3688 */ 3689 if (cq->umem) { 3690 if (cq->resize_umem) 3691 bnxt_re_resize_cq_complete(cq); 3692 return 0; 3693 } 3694 3695 spin_lock_irqsave(&cq->cq_lock, flags); 3696 budget = min_t(u32, num_entries, cq->max_cql); 3697 num_entries = budget; 3698 if (!cq->cql) { 3699 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use"); 3700 goto exit; 3701 } 3702 cqe = &cq->cql[0]; 3703 while (budget) { 3704 lib_qp = NULL; 3705 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3706 if (lib_qp) { 3707 sq = &lib_qp->sq; 3708 if (sq->send_phantom) { 3709 qp = container_of(lib_qp, 3710 struct bnxt_re_qp, qplib_qp); 3711 if (send_phantom_wqe(qp) == -ENOMEM) 3712 ibdev_err(&cq->rdev->ibdev, 3713 "Phantom failed! Scheduled to send again\n"); 3714 else 3715 sq->send_phantom = false; 3716 } 3717 } 3718 if (ncqe < budget) 3719 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3720 cqe + ncqe, 3721 budget - ncqe); 3722 3723 if (!ncqe) 3724 break; 3725 3726 for (i = 0; i < ncqe; i++, cqe++) { 3727 /* Transcribe each qplib_wqe back to ib_wc */ 3728 memset(wc, 0, sizeof(*wc)); 3729 3730 wc->wr_id = cqe->wr_id; 3731 wc->byte_len = cqe->length; 3732 qp = container_of 3733 ((struct bnxt_qplib_qp *) 3734 (unsigned long)(cqe->qp_handle), 3735 struct bnxt_re_qp, qplib_qp); 3736 wc->qp = &qp->ib_qp; 3737 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immdata)); 3738 wc->src_qp = cqe->src_qp; 3739 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3740 wc->port_num = 1; 3741 wc->vendor_err = cqe->status; 3742 3743 switch (cqe->opcode) { 3744 case CQ_BASE_CQE_TYPE_REQ: 3745 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3746 if (sh_qp && 3747 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3748 /* Handle this completion with 3749 * the stored completion 3750 */ 3751 memset(wc, 0, sizeof(*wc)); 3752 continue; 3753 } 3754 bnxt_re_process_req_wc(wc, cqe); 3755 break; 3756 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3757 if (!cqe->status) { 3758 int rc = 0; 3759 3760 rc = bnxt_re_process_raw_qp_pkt_rx 3761 (qp, cqe); 3762 if (!rc) { 3763 memset(wc, 0, sizeof(*wc)); 3764 continue; 3765 } 3766 cqe->status = -1; 3767 } 3768 /* Errors need not be looped back. 3769 * But change the wr_id to the one 3770 * stored in the table 3771 */ 3772 tbl_idx = cqe->wr_id; 3773 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3774 wc->wr_id = sqp_entry->wrid; 3775 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3776 break; 3777 case CQ_BASE_CQE_TYPE_RES_RC: 3778 bnxt_re_process_res_rc_wc(wc, cqe); 3779 break; 3780 case CQ_BASE_CQE_TYPE_RES_UD: 3781 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3782 if (sh_qp && 3783 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3784 /* Handle this completion with 3785 * the stored completion 3786 */ 3787 if (cqe->status) { 3788 continue; 3789 } else { 3790 bnxt_re_process_res_shadow_qp_wc 3791 (qp, wc, cqe); 3792 break; 3793 } 3794 } 3795 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3796 break; 3797 default: 3798 ibdev_err(&cq->rdev->ibdev, 3799 "POLL CQ : type 0x%x not handled", 3800 cqe->opcode); 3801 continue; 3802 } 3803 wc++; 3804 budget--; 3805 } 3806 } 3807 exit: 3808 spin_unlock_irqrestore(&cq->cq_lock, flags); 3809 return num_entries - budget; 3810 } 3811 3812 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3813 enum ib_cq_notify_flags ib_cqn_flags) 3814 { 3815 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3816 int type = 0, rc = 0; 3817 unsigned long flags; 3818 3819 spin_lock_irqsave(&cq->cq_lock, flags); 3820 /* Trigger on the very next completion */ 3821 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3822 type = DBC_DBC_TYPE_CQ_ARMALL; 3823 /* Trigger on the next solicited completion */ 3824 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3825 type = DBC_DBC_TYPE_CQ_ARMSE; 3826 3827 /* Poll to see if there are missed events */ 3828 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3829 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3830 rc = 1; 3831 goto exit; 3832 } 3833 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3834 3835 exit: 3836 spin_unlock_irqrestore(&cq->cq_lock, flags); 3837 return rc; 3838 } 3839 3840 /* Memory Regions */ 3841 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3842 { 3843 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3844 struct bnxt_re_dev *rdev = pd->rdev; 3845 struct bnxt_re_mr *mr; 3846 u32 active_mrs; 3847 int rc; 3848 3849 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3850 if (!mr) 3851 return ERR_PTR(-ENOMEM); 3852 3853 mr->rdev = rdev; 3854 mr->qplib_mr.pd = &pd->qplib_pd; 3855 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3856 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3857 3858 /* Allocate and register 0 as the address */ 3859 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3860 if (rc) 3861 goto fail; 3862 3863 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3864 mr->qplib_mr.total_size = -1; /* Infinte length */ 3865 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0, 3866 PAGE_SIZE); 3867 if (rc) 3868 goto fail_mr; 3869 3870 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3871 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3872 IB_ACCESS_REMOTE_ATOMIC)) 3873 mr->ib_mr.rkey = mr->ib_mr.lkey; 3874 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 3875 if (active_mrs > rdev->stats.res.mr_watermark) 3876 rdev->stats.res.mr_watermark = active_mrs; 3877 3878 return &mr->ib_mr; 3879 3880 fail_mr: 3881 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3882 fail: 3883 kfree(mr); 3884 return ERR_PTR(rc); 3885 } 3886 3887 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3888 { 3889 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3890 struct bnxt_re_dev *rdev = mr->rdev; 3891 int rc; 3892 3893 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3894 if (rc) { 3895 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc); 3896 return rc; 3897 } 3898 3899 if (mr->pages) { 3900 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3901 &mr->qplib_frpl); 3902 kfree(mr->pages); 3903 mr->npages = 0; 3904 mr->pages = NULL; 3905 } 3906 ib_umem_release(mr->ib_umem); 3907 3908 kfree(mr); 3909 atomic_dec(&rdev->stats.res.mr_count); 3910 return rc; 3911 } 3912 3913 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3914 { 3915 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3916 3917 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3918 return -ENOMEM; 3919 3920 mr->pages[mr->npages++] = addr; 3921 return 0; 3922 } 3923 3924 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3925 unsigned int *sg_offset) 3926 { 3927 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3928 3929 mr->npages = 0; 3930 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3931 } 3932 3933 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3934 u32 max_num_sg) 3935 { 3936 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3937 struct bnxt_re_dev *rdev = pd->rdev; 3938 struct bnxt_re_mr *mr = NULL; 3939 u32 active_mrs; 3940 int rc; 3941 3942 if (type != IB_MR_TYPE_MEM_REG) { 3943 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type); 3944 return ERR_PTR(-EINVAL); 3945 } 3946 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3947 return ERR_PTR(-EINVAL); 3948 3949 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3950 if (!mr) 3951 return ERR_PTR(-ENOMEM); 3952 3953 mr->rdev = rdev; 3954 mr->qplib_mr.pd = &pd->qplib_pd; 3955 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3956 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3957 3958 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3959 if (rc) 3960 goto bail; 3961 3962 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3963 mr->ib_mr.rkey = mr->ib_mr.lkey; 3964 3965 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3966 if (!mr->pages) { 3967 rc = -ENOMEM; 3968 goto fail; 3969 } 3970 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3971 &mr->qplib_frpl, max_num_sg); 3972 if (rc) { 3973 ibdev_err(&rdev->ibdev, 3974 "Failed to allocate HW FR page list"); 3975 goto fail_mr; 3976 } 3977 3978 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 3979 if (active_mrs > rdev->stats.res.mr_watermark) 3980 rdev->stats.res.mr_watermark = active_mrs; 3981 return &mr->ib_mr; 3982 3983 fail_mr: 3984 kfree(mr->pages); 3985 fail: 3986 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3987 bail: 3988 kfree(mr); 3989 return ERR_PTR(rc); 3990 } 3991 3992 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3993 struct ib_udata *udata) 3994 { 3995 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3996 struct bnxt_re_dev *rdev = pd->rdev; 3997 struct bnxt_re_mw *mw; 3998 u32 active_mws; 3999 int rc; 4000 4001 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 4002 if (!mw) 4003 return ERR_PTR(-ENOMEM); 4004 mw->rdev = rdev; 4005 mw->qplib_mw.pd = &pd->qplib_pd; 4006 4007 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 4008 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 4009 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 4010 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 4011 if (rc) { 4012 ibdev_err(&rdev->ibdev, "Allocate MW failed!"); 4013 goto fail; 4014 } 4015 mw->ib_mw.rkey = mw->qplib_mw.rkey; 4016 4017 active_mws = atomic_inc_return(&rdev->stats.res.mw_count); 4018 if (active_mws > rdev->stats.res.mw_watermark) 4019 rdev->stats.res.mw_watermark = active_mws; 4020 return &mw->ib_mw; 4021 4022 fail: 4023 kfree(mw); 4024 return ERR_PTR(rc); 4025 } 4026 4027 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 4028 { 4029 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 4030 struct bnxt_re_dev *rdev = mw->rdev; 4031 int rc; 4032 4033 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 4034 if (rc) { 4035 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc); 4036 return rc; 4037 } 4038 4039 kfree(mw); 4040 atomic_dec(&rdev->stats.res.mw_count); 4041 return rc; 4042 } 4043 4044 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr, 4045 int mr_access_flags, struct ib_umem *umem) 4046 { 4047 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4048 struct bnxt_re_dev *rdev = pd->rdev; 4049 unsigned long page_size; 4050 struct bnxt_re_mr *mr; 4051 int umem_pgs, rc; 4052 u32 active_mrs; 4053 4054 if (length > BNXT_RE_MAX_MR_SIZE) { 4055 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n", 4056 length, BNXT_RE_MAX_MR_SIZE); 4057 return ERR_PTR(-ENOMEM); 4058 } 4059 4060 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr); 4061 if (!page_size) { 4062 ibdev_err(&rdev->ibdev, "umem page size unsupported!"); 4063 return ERR_PTR(-EINVAL); 4064 } 4065 4066 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 4067 if (!mr) 4068 return ERR_PTR(-ENOMEM); 4069 4070 mr->rdev = rdev; 4071 mr->qplib_mr.pd = &pd->qplib_pd; 4072 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 4073 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 4074 4075 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4076 if (rc) { 4077 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc); 4078 rc = -EIO; 4079 goto free_mr; 4080 } 4081 /* The fixed portion of the rkey is the same as the lkey */ 4082 mr->ib_mr.rkey = mr->qplib_mr.rkey; 4083 mr->ib_umem = umem; 4084 mr->qplib_mr.va = virt_addr; 4085 mr->qplib_mr.total_size = length; 4086 4087 umem_pgs = ib_umem_num_dma_blocks(umem, page_size); 4088 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem, 4089 umem_pgs, page_size); 4090 if (rc) { 4091 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc); 4092 rc = -EIO; 4093 goto free_mrw; 4094 } 4095 4096 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4097 mr->ib_mr.rkey = mr->qplib_mr.lkey; 4098 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4099 if (active_mrs > rdev->stats.res.mr_watermark) 4100 rdev->stats.res.mr_watermark = active_mrs; 4101 4102 return &mr->ib_mr; 4103 4104 free_mrw: 4105 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4106 free_mr: 4107 kfree(mr); 4108 return ERR_PTR(rc); 4109 } 4110 4111 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 4112 u64 virt_addr, int mr_access_flags, 4113 struct ib_udata *udata) 4114 { 4115 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4116 struct bnxt_re_dev *rdev = pd->rdev; 4117 struct ib_umem *umem; 4118 struct ib_mr *ib_mr; 4119 4120 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags); 4121 if (IS_ERR(umem)) 4122 return ERR_CAST(umem); 4123 4124 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4125 if (IS_ERR(ib_mr)) 4126 ib_umem_release(umem); 4127 return ib_mr; 4128 } 4129 4130 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start, 4131 u64 length, u64 virt_addr, int fd, 4132 int mr_access_flags, struct ib_udata *udata) 4133 { 4134 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4135 struct bnxt_re_dev *rdev = pd->rdev; 4136 struct ib_umem_dmabuf *umem_dmabuf; 4137 struct ib_umem *umem; 4138 struct ib_mr *ib_mr; 4139 4140 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length, 4141 fd, mr_access_flags); 4142 if (IS_ERR(umem_dmabuf)) 4143 return ERR_CAST(umem_dmabuf); 4144 4145 umem = &umem_dmabuf->umem; 4146 4147 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4148 if (IS_ERR(ib_mr)) 4149 ib_umem_release(umem); 4150 return ib_mr; 4151 } 4152 4153 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 4154 { 4155 struct ib_device *ibdev = ctx->device; 4156 struct bnxt_re_ucontext *uctx = 4157 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 4158 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4159 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 4160 struct bnxt_re_user_mmap_entry *entry; 4161 struct bnxt_re_uctx_resp resp = {}; 4162 struct bnxt_re_uctx_req ureq = {}; 4163 u32 chip_met_rev_num = 0; 4164 int rc; 4165 4166 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver); 4167 4168 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 4169 ibdev_dbg(ibdev, " is different from the device %d ", 4170 BNXT_RE_ABI_VERSION); 4171 return -EPERM; 4172 } 4173 4174 uctx->rdev = rdev; 4175 4176 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 4177 if (!uctx->shpg) { 4178 rc = -ENOMEM; 4179 goto fail; 4180 } 4181 spin_lock_init(&uctx->sh_lock); 4182 4183 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 4184 chip_met_rev_num = rdev->chip_ctx->chip_num; 4185 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) << 4186 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 4187 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) << 4188 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 4189 resp.chip_id0 = chip_met_rev_num; 4190 /*Temp, Use xa_alloc instead */ 4191 resp.dev_id = rdev->en_dev->pdev->devfn; 4192 resp.max_qp = rdev->qplib_ctx.qpc_count; 4193 resp.pg_size = PAGE_SIZE; 4194 resp.cqe_sz = sizeof(struct cq_base); 4195 resp.max_cqd = dev_attr->max_cq_wqes; 4196 4197 if (rdev->chip_ctx->modes.db_push) 4198 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED; 4199 4200 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL); 4201 if (!entry) { 4202 rc = -ENOMEM; 4203 goto cfail; 4204 } 4205 uctx->shpage_mmap = &entry->rdma_entry; 4206 if (rdev->pacing.dbr_pacing) 4207 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED; 4208 4209 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 4210 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED; 4211 4212 if (udata->inlen >= sizeof(ureq)) { 4213 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))); 4214 if (rc) 4215 goto cfail; 4216 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) { 4217 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4218 uctx->cmask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4219 } 4220 } 4221 4222 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 4223 if (rc) { 4224 ibdev_err(ibdev, "Failed to copy user context"); 4225 rc = -EFAULT; 4226 goto cfail; 4227 } 4228 4229 return 0; 4230 cfail: 4231 free_page((unsigned long)uctx->shpg); 4232 uctx->shpg = NULL; 4233 fail: 4234 return rc; 4235 } 4236 4237 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 4238 { 4239 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4240 struct bnxt_re_ucontext, 4241 ib_uctx); 4242 4243 struct bnxt_re_dev *rdev = uctx->rdev; 4244 4245 rdma_user_mmap_entry_remove(uctx->shpage_mmap); 4246 uctx->shpage_mmap = NULL; 4247 if (uctx->shpg) 4248 free_page((unsigned long)uctx->shpg); 4249 4250 if (uctx->dpi.dbr) { 4251 /* Free DPI only if this is the first PD allocated by the 4252 * application and mark the context dpi as NULL 4253 */ 4254 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi); 4255 uctx->dpi.dbr = NULL; 4256 } 4257 } 4258 4259 static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id) 4260 { 4261 struct bnxt_re_cq *cq = NULL, *tmp_cq; 4262 4263 hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) { 4264 if (tmp_cq->qplib_cq.id == cq_id) { 4265 cq = tmp_cq; 4266 break; 4267 } 4268 } 4269 return cq; 4270 } 4271 4272 /* Helper function to mmap the virtual memory from user app */ 4273 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 4274 { 4275 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4276 struct bnxt_re_ucontext, 4277 ib_uctx); 4278 struct bnxt_re_user_mmap_entry *bnxt_entry; 4279 struct rdma_user_mmap_entry *rdma_entry; 4280 int ret = 0; 4281 u64 pfn; 4282 4283 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma); 4284 if (!rdma_entry) 4285 return -EINVAL; 4286 4287 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4288 rdma_entry); 4289 4290 switch (bnxt_entry->mmap_flag) { 4291 case BNXT_RE_MMAP_WC_DB: 4292 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4293 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4294 pgprot_writecombine(vma->vm_page_prot), 4295 rdma_entry); 4296 break; 4297 case BNXT_RE_MMAP_UC_DB: 4298 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4299 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4300 pgprot_noncached(vma->vm_page_prot), 4301 rdma_entry); 4302 break; 4303 case BNXT_RE_MMAP_SH_PAGE: 4304 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg)); 4305 break; 4306 case BNXT_RE_MMAP_DBR_BAR: 4307 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4308 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4309 pgprot_noncached(vma->vm_page_prot), 4310 rdma_entry); 4311 break; 4312 case BNXT_RE_MMAP_DBR_PAGE: 4313 case BNXT_RE_MMAP_TOGGLE_PAGE: 4314 /* Driver doesn't expect write access for user space */ 4315 if (vma->vm_flags & VM_WRITE) 4316 return -EFAULT; 4317 ret = vm_insert_page(vma, vma->vm_start, 4318 virt_to_page((void *)bnxt_entry->mem_offset)); 4319 break; 4320 default: 4321 ret = -EINVAL; 4322 break; 4323 } 4324 4325 rdma_user_mmap_entry_put(rdma_entry); 4326 return ret; 4327 } 4328 4329 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 4330 { 4331 struct bnxt_re_user_mmap_entry *bnxt_entry; 4332 4333 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4334 rdma_entry); 4335 4336 kfree(bnxt_entry); 4337 } 4338 4339 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs) 4340 { 4341 struct bnxt_re_ucontext *uctx; 4342 4343 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4344 bnxt_re_pacing_alert(uctx->rdev); 4345 return 0; 4346 } 4347 4348 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs) 4349 { 4350 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4351 enum bnxt_re_alloc_page_type alloc_type; 4352 struct bnxt_re_user_mmap_entry *entry; 4353 enum bnxt_re_mmap_flag mmap_flag; 4354 struct bnxt_qplib_chip_ctx *cctx; 4355 struct bnxt_re_ucontext *uctx; 4356 struct bnxt_re_dev *rdev; 4357 u64 mmap_offset; 4358 u32 length; 4359 u32 dpi; 4360 u64 addr; 4361 int err; 4362 4363 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4364 if (IS_ERR(uctx)) 4365 return PTR_ERR(uctx); 4366 4367 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE); 4368 if (err) 4369 return err; 4370 4371 rdev = uctx->rdev; 4372 cctx = rdev->chip_ctx; 4373 4374 switch (alloc_type) { 4375 case BNXT_RE_ALLOC_WC_PAGE: 4376 if (cctx->modes.db_push) { 4377 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi, 4378 uctx, BNXT_QPLIB_DPI_TYPE_WC)) 4379 return -ENOMEM; 4380 length = PAGE_SIZE; 4381 dpi = uctx->wcdpi.dpi; 4382 addr = (u64)uctx->wcdpi.umdbr; 4383 mmap_flag = BNXT_RE_MMAP_WC_DB; 4384 } else { 4385 return -EINVAL; 4386 } 4387 4388 break; 4389 case BNXT_RE_ALLOC_DBR_BAR_PAGE: 4390 length = PAGE_SIZE; 4391 addr = (u64)rdev->pacing.dbr_bar_addr; 4392 mmap_flag = BNXT_RE_MMAP_DBR_BAR; 4393 break; 4394 4395 case BNXT_RE_ALLOC_DBR_PAGE: 4396 length = PAGE_SIZE; 4397 addr = (u64)rdev->pacing.dbr_page; 4398 mmap_flag = BNXT_RE_MMAP_DBR_PAGE; 4399 break; 4400 4401 default: 4402 return -EOPNOTSUPP; 4403 } 4404 4405 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset); 4406 if (!entry) 4407 return -ENOMEM; 4408 4409 uobj->object = entry; 4410 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4411 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4412 &mmap_offset, sizeof(mmap_offset)); 4413 if (err) 4414 return err; 4415 4416 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4417 &length, sizeof(length)); 4418 if (err) 4419 return err; 4420 4421 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI, 4422 &dpi, sizeof(length)); 4423 if (err) 4424 return err; 4425 4426 return 0; 4427 } 4428 4429 static int alloc_page_obj_cleanup(struct ib_uobject *uobject, 4430 enum rdma_remove_reason why, 4431 struct uverbs_attr_bundle *attrs) 4432 { 4433 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4434 struct bnxt_re_ucontext *uctx = entry->uctx; 4435 4436 switch (entry->mmap_flag) { 4437 case BNXT_RE_MMAP_WC_DB: 4438 if (uctx && uctx->wcdpi.dbr) { 4439 struct bnxt_re_dev *rdev = uctx->rdev; 4440 4441 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi); 4442 uctx->wcdpi.dbr = NULL; 4443 } 4444 break; 4445 case BNXT_RE_MMAP_DBR_BAR: 4446 case BNXT_RE_MMAP_DBR_PAGE: 4447 break; 4448 default: 4449 goto exit; 4450 } 4451 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4452 exit: 4453 return 0; 4454 } 4455 4456 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE, 4457 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE, 4458 BNXT_RE_OBJECT_ALLOC_PAGE, 4459 UVERBS_ACCESS_NEW, 4460 UA_MANDATORY), 4461 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE, 4462 enum bnxt_re_alloc_page_type, 4463 UA_MANDATORY), 4464 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4465 UVERBS_ATTR_TYPE(u64), 4466 UA_MANDATORY), 4467 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4468 UVERBS_ATTR_TYPE(u32), 4469 UA_MANDATORY), 4470 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI, 4471 UVERBS_ATTR_TYPE(u32), 4472 UA_MANDATORY)); 4473 4474 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE, 4475 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE, 4476 BNXT_RE_OBJECT_ALLOC_PAGE, 4477 UVERBS_ACCESS_DESTROY, 4478 UA_MANDATORY)); 4479 4480 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE, 4481 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup), 4482 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE), 4483 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE)); 4484 4485 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV); 4486 4487 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV, 4488 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV)); 4489 4490 /* Toggle MEM */ 4491 static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs) 4492 { 4493 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4494 enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE; 4495 enum bnxt_re_get_toggle_mem_type res_type; 4496 struct bnxt_re_user_mmap_entry *entry; 4497 struct bnxt_re_ucontext *uctx; 4498 struct ib_ucontext *ib_uctx; 4499 struct bnxt_re_dev *rdev; 4500 struct bnxt_re_cq *cq; 4501 u64 mem_offset; 4502 u64 addr = 0; 4503 u32 length; 4504 u32 offset; 4505 u32 cq_id; 4506 int err; 4507 4508 ib_uctx = ib_uverbs_get_ucontext(attrs); 4509 if (IS_ERR(ib_uctx)) 4510 return PTR_ERR(ib_uctx); 4511 4512 err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE); 4513 if (err) 4514 return err; 4515 4516 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx); 4517 rdev = uctx->rdev; 4518 4519 switch (res_type) { 4520 case BNXT_RE_CQ_TOGGLE_MEM: 4521 err = uverbs_copy_from(&cq_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID); 4522 if (err) 4523 return err; 4524 4525 cq = bnxt_re_search_for_cq(rdev, cq_id); 4526 if (!cq) 4527 return -EINVAL; 4528 4529 length = PAGE_SIZE; 4530 addr = (u64)cq->uctx_cq_page; 4531 mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE; 4532 offset = 0; 4533 break; 4534 case BNXT_RE_SRQ_TOGGLE_MEM: 4535 break; 4536 4537 default: 4538 return -EOPNOTSUPP; 4539 } 4540 4541 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset); 4542 if (!entry) 4543 return -ENOMEM; 4544 4545 uobj->object = entry; 4546 uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4547 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4548 &mem_offset, sizeof(mem_offset)); 4549 if (err) 4550 return err; 4551 4552 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4553 &length, sizeof(length)); 4554 if (err) 4555 return err; 4556 4557 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4558 &offset, sizeof(length)); 4559 if (err) 4560 return err; 4561 4562 return 0; 4563 } 4564 4565 static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject, 4566 enum rdma_remove_reason why, 4567 struct uverbs_attr_bundle *attrs) 4568 { 4569 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4570 4571 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4572 return 0; 4573 } 4574 4575 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM, 4576 UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE, 4577 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4578 UVERBS_ACCESS_NEW, 4579 UA_MANDATORY), 4580 UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE, 4581 enum bnxt_re_get_toggle_mem_type, 4582 UA_MANDATORY), 4583 UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID, 4584 UVERBS_ATTR_TYPE(u32), 4585 UA_MANDATORY), 4586 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4587 UVERBS_ATTR_TYPE(u64), 4588 UA_MANDATORY), 4589 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4590 UVERBS_ATTR_TYPE(u32), 4591 UA_MANDATORY), 4592 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4593 UVERBS_ATTR_TYPE(u32), 4594 UA_MANDATORY)); 4595 4596 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM, 4597 UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE, 4598 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4599 UVERBS_ACCESS_DESTROY, 4600 UA_MANDATORY)); 4601 4602 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4603 UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup), 4604 &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM), 4605 &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM)); 4606 4607 const struct uapi_definition bnxt_re_uapi_defs[] = { 4608 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE), 4609 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV), 4610 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM), 4611 {} 4612 }; 4613