1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 #include <net/addrconf.h> 45 46 #include <rdma/ib_verbs.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_umem.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_mad.h> 51 #include <rdma/ib_cache.h> 52 #include <rdma/uverbs_ioctl.h> 53 #include <linux/hashtable.h> 54 55 #include "bnxt_ulp.h" 56 57 #include "roce_hsi.h" 58 #include "qplib_res.h" 59 #include "qplib_sp.h" 60 #include "qplib_fp.h" 61 #include "qplib_rcfw.h" 62 63 #include "bnxt_re.h" 64 #include "ib_verbs.h" 65 66 #include <rdma/uverbs_types.h> 67 #include <rdma/uverbs_std_types.h> 68 69 #include <rdma/ib_user_ioctl_cmds.h> 70 71 #define UVERBS_MODULE_NAME bnxt_re 72 #include <rdma/uverbs_named_ioctl.h> 73 74 #include <rdma/bnxt_re-abi.h> 75 76 static int __from_ib_access_flags(int iflags) 77 { 78 int qflags = 0; 79 80 if (iflags & IB_ACCESS_LOCAL_WRITE) 81 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 82 if (iflags & IB_ACCESS_REMOTE_READ) 83 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 84 if (iflags & IB_ACCESS_REMOTE_WRITE) 85 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 86 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 87 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 88 if (iflags & IB_ACCESS_MW_BIND) 89 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 90 if (iflags & IB_ZERO_BASED) 91 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 92 if (iflags & IB_ACCESS_ON_DEMAND) 93 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 94 return qflags; 95 }; 96 97 static enum ib_access_flags __to_ib_access_flags(int qflags) 98 { 99 enum ib_access_flags iflags = 0; 100 101 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 102 iflags |= IB_ACCESS_LOCAL_WRITE; 103 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 104 iflags |= IB_ACCESS_REMOTE_WRITE; 105 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 106 iflags |= IB_ACCESS_REMOTE_READ; 107 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 108 iflags |= IB_ACCESS_REMOTE_ATOMIC; 109 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 110 iflags |= IB_ACCESS_MW_BIND; 111 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 112 iflags |= IB_ZERO_BASED; 113 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 114 iflags |= IB_ACCESS_ON_DEMAND; 115 return iflags; 116 }; 117 118 static void bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev *rdev, 119 struct bnxt_qplib_mrw *qplib_mr) 120 { 121 if (_is_relaxed_ordering_supported(rdev->dev_attr.dev_cap_flags2) && 122 pcie_relaxed_ordering_enabled(rdev->en_dev->pdev)) 123 qplib_mr->flags |= CMDQ_REGISTER_MR_FLAGS_ENABLE_RO; 124 } 125 126 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 127 struct bnxt_qplib_sge *sg_list, int num) 128 { 129 int i, total = 0; 130 131 for (i = 0; i < num; i++) { 132 sg_list[i].addr = ib_sg_list[i].addr; 133 sg_list[i].lkey = ib_sg_list[i].lkey; 134 sg_list[i].size = ib_sg_list[i].length; 135 total += sg_list[i].size; 136 } 137 return total; 138 } 139 140 /* Device */ 141 int bnxt_re_query_device(struct ib_device *ibdev, 142 struct ib_device_attr *ib_attr, 143 struct ib_udata *udata) 144 { 145 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 146 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 147 148 memset(ib_attr, 0, sizeof(*ib_attr)); 149 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 150 min(sizeof(dev_attr->fw_ver), 151 sizeof(ib_attr->fw_ver))); 152 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid, 153 rdev->netdev->dev_addr); 154 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 155 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED; 156 157 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 158 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 159 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 160 ib_attr->max_qp = dev_attr->max_qp; 161 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 162 ib_attr->device_cap_flags = 163 IB_DEVICE_CURR_QP_STATE_MOD 164 | IB_DEVICE_RC_RNR_NAK_GEN 165 | IB_DEVICE_SHUTDOWN_PORT 166 | IB_DEVICE_SYS_IMAGE_GUID 167 | IB_DEVICE_RESIZE_MAX_WR 168 | IB_DEVICE_PORT_ACTIVE_EVENT 169 | IB_DEVICE_N_NOTIFY_CQ 170 | IB_DEVICE_MEM_WINDOW 171 | IB_DEVICE_MEM_WINDOW_TYPE_2B 172 | IB_DEVICE_MEM_MGT_EXTENSIONS; 173 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY; 174 ib_attr->max_send_sge = dev_attr->max_qp_sges; 175 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 176 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 177 ib_attr->max_cq = dev_attr->max_cq; 178 ib_attr->max_cqe = dev_attr->max_cq_wqes; 179 ib_attr->max_mr = dev_attr->max_mr; 180 ib_attr->max_pd = dev_attr->max_pd; 181 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 182 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 183 ib_attr->atomic_cap = IB_ATOMIC_NONE; 184 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 185 if (dev_attr->is_atomic) { 186 ib_attr->atomic_cap = IB_ATOMIC_GLOB; 187 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; 188 } 189 190 ib_attr->max_ee_rd_atom = 0; 191 ib_attr->max_res_rd_atom = 0; 192 ib_attr->max_ee_init_rd_atom = 0; 193 ib_attr->max_ee = 0; 194 ib_attr->max_rdd = 0; 195 ib_attr->max_mw = dev_attr->max_mw; 196 ib_attr->max_raw_ipv6_qp = 0; 197 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 198 ib_attr->max_mcast_grp = 0; 199 ib_attr->max_mcast_qp_attach = 0; 200 ib_attr->max_total_mcast_qp_attach = 0; 201 ib_attr->max_ah = dev_attr->max_ah; 202 203 ib_attr->max_srq = dev_attr->max_srq; 204 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 205 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 206 207 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 208 209 ib_attr->max_pkeys = 1; 210 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 211 return 0; 212 } 213 214 /* Port */ 215 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num, 216 struct ib_port_attr *port_attr) 217 { 218 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 219 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 220 int rc; 221 222 memset(port_attr, 0, sizeof(*port_attr)); 223 224 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 225 port_attr->state = IB_PORT_ACTIVE; 226 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 227 } else { 228 port_attr->state = IB_PORT_DOWN; 229 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 230 } 231 port_attr->max_mtu = IB_MTU_4096; 232 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 233 port_attr->gid_tbl_len = dev_attr->max_sgid; 234 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 235 IB_PORT_DEVICE_MGMT_SUP | 236 IB_PORT_VENDOR_CLASS_SUP; 237 port_attr->ip_gids = true; 238 239 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 240 port_attr->bad_pkey_cntr = 0; 241 port_attr->qkey_viol_cntr = 0; 242 port_attr->pkey_tbl_len = dev_attr->max_pkey; 243 port_attr->lid = 0; 244 port_attr->sm_lid = 0; 245 port_attr->lmc = 0; 246 port_attr->max_vl_num = 4; 247 port_attr->sm_sl = 0; 248 port_attr->subnet_timeout = 0; 249 port_attr->init_type_reply = 0; 250 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed, 251 &port_attr->active_width); 252 253 return rc; 254 } 255 256 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num, 257 struct ib_port_immutable *immutable) 258 { 259 struct ib_port_attr port_attr; 260 261 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 262 return -EINVAL; 263 264 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 265 immutable->gid_tbl_len = port_attr.gid_tbl_len; 266 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 267 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 268 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 269 return 0; 270 } 271 272 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 273 { 274 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 275 276 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 277 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 278 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 279 } 280 281 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num, 282 u16 index, u16 *pkey) 283 { 284 if (index > 0) 285 return -EINVAL; 286 287 *pkey = IB_DEFAULT_PKEY_FULL; 288 289 return 0; 290 } 291 292 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num, 293 int index, union ib_gid *gid) 294 { 295 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 296 int rc; 297 298 /* Ignore port_num */ 299 memset(gid, 0, sizeof(*gid)); 300 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 301 &rdev->qplib_res.sgid_tbl, index, 302 (struct bnxt_qplib_gid *)gid); 303 return rc; 304 } 305 306 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 307 { 308 int rc = 0; 309 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 310 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 311 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 312 struct bnxt_qplib_gid *gid_to_del; 313 u16 vlan_id = 0xFFFF; 314 315 /* Delete the entry from the hardware */ 316 ctx = *context; 317 if (!ctx) 318 return -EINVAL; 319 320 if (sgid_tbl && sgid_tbl->active) { 321 if (ctx->idx >= sgid_tbl->max) 322 return -EINVAL; 323 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 324 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 325 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 326 * or via the ib_unregister_device path. In the former case QP1 327 * may not be destroyed yet, in which case just return as FW 328 * needs that entry to be present and will fail it's deletion. 329 * We could get invoked again after QP1 is destroyed OR get an 330 * ADD_GID call with a different GID value for the same index 331 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 332 */ 333 if (ctx->idx == 0 && 334 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 335 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) { 336 ibdev_dbg(&rdev->ibdev, 337 "Trying to delete GID0 while QP1 is alive\n"); 338 return -EFAULT; 339 } 340 ctx->refcnt--; 341 if (!ctx->refcnt) { 342 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 343 vlan_id, true); 344 if (rc) { 345 ibdev_err(&rdev->ibdev, 346 "Failed to remove GID: %#x", rc); 347 } else { 348 ctx_tbl = sgid_tbl->ctx; 349 ctx_tbl[ctx->idx] = NULL; 350 kfree(ctx); 351 } 352 } 353 } else { 354 return -EINVAL; 355 } 356 return rc; 357 } 358 359 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 360 { 361 int rc; 362 u32 tbl_idx = 0; 363 u16 vlan_id = 0xFFFF; 364 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 365 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 366 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 367 368 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 369 if (rc) 370 return rc; 371 372 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 373 rdev->qplib_res.netdev->dev_addr, 374 vlan_id, true, &tbl_idx); 375 if (rc == -EALREADY) { 376 ctx_tbl = sgid_tbl->ctx; 377 ctx_tbl[tbl_idx]->refcnt++; 378 *context = ctx_tbl[tbl_idx]; 379 return 0; 380 } 381 382 if (rc < 0) { 383 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc); 384 return rc; 385 } 386 387 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 388 if (!ctx) 389 return -ENOMEM; 390 ctx_tbl = sgid_tbl->ctx; 391 ctx->idx = tbl_idx; 392 ctx->refcnt = 1; 393 ctx_tbl[tbl_idx] = ctx; 394 *context = ctx; 395 396 return rc; 397 } 398 399 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 400 u32 port_num) 401 { 402 return IB_LINK_LAYER_ETHERNET; 403 } 404 405 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 406 407 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 408 { 409 struct bnxt_re_fence_data *fence = &pd->fence; 410 struct ib_mr *ib_mr = &fence->mr->ib_mr; 411 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 412 struct bnxt_re_dev *rdev = pd->rdev; 413 414 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 415 return; 416 417 memset(wqe, 0, sizeof(*wqe)); 418 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 419 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 420 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 421 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 422 wqe->bind.zero_based = false; 423 wqe->bind.parent_l_key = ib_mr->lkey; 424 wqe->bind.va = (u64)(unsigned long)fence->va; 425 wqe->bind.length = fence->size; 426 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 427 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 428 429 /* Save the initial rkey in fence structure for now; 430 * wqe->bind.r_key will be set at (re)bind time. 431 */ 432 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 433 } 434 435 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 436 { 437 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 438 qplib_qp); 439 struct ib_pd *ib_pd = qp->ib_qp.pd; 440 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 441 struct bnxt_re_fence_data *fence = &pd->fence; 442 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 443 struct bnxt_qplib_swqe wqe; 444 int rc; 445 446 memcpy(&wqe, fence_wqe, sizeof(wqe)); 447 wqe.bind.r_key = fence->bind_rkey; 448 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 449 450 ibdev_dbg(&qp->rdev->ibdev, 451 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 452 wqe.bind.r_key, qp->qplib_qp.id, pd); 453 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 454 if (rc) { 455 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n"); 456 return rc; 457 } 458 bnxt_qplib_post_send_db(&qp->qplib_qp); 459 460 return rc; 461 } 462 463 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 464 { 465 struct bnxt_re_fence_data *fence = &pd->fence; 466 struct bnxt_re_dev *rdev = pd->rdev; 467 struct device *dev = &rdev->en_dev->pdev->dev; 468 struct bnxt_re_mr *mr = fence->mr; 469 470 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 471 return; 472 473 if (fence->mw) { 474 bnxt_re_dealloc_mw(fence->mw); 475 fence->mw = NULL; 476 } 477 if (mr) { 478 if (mr->ib_mr.rkey) 479 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 480 true); 481 if (mr->ib_mr.lkey) 482 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 483 kfree(mr); 484 fence->mr = NULL; 485 } 486 if (fence->dma_addr) { 487 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 488 DMA_BIDIRECTIONAL); 489 fence->dma_addr = 0; 490 } 491 } 492 493 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 494 { 495 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 496 struct bnxt_re_fence_data *fence = &pd->fence; 497 struct bnxt_re_dev *rdev = pd->rdev; 498 struct device *dev = &rdev->en_dev->pdev->dev; 499 struct bnxt_re_mr *mr = NULL; 500 dma_addr_t dma_addr = 0; 501 struct ib_mw *mw; 502 int rc; 503 504 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 505 return 0; 506 507 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 508 DMA_BIDIRECTIONAL); 509 rc = dma_mapping_error(dev, dma_addr); 510 if (rc) { 511 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n"); 512 rc = -EIO; 513 fence->dma_addr = 0; 514 goto fail; 515 } 516 fence->dma_addr = dma_addr; 517 518 /* Allocate a MR */ 519 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 520 if (!mr) { 521 rc = -ENOMEM; 522 goto fail; 523 } 524 fence->mr = mr; 525 mr->rdev = rdev; 526 mr->qplib_mr.pd = &pd->qplib_pd; 527 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 528 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 529 if (!_is_alloc_mr_unified(rdev->dev_attr.dev_cap_flags)) { 530 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 531 if (rc) { 532 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); 533 goto fail; 534 } 535 536 /* Register MR */ 537 mr->ib_mr.lkey = mr->qplib_mr.lkey; 538 } else { 539 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR; 540 } 541 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 542 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 543 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 544 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE); 545 if (rc) { 546 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n"); 547 goto fail; 548 } 549 mr->ib_mr.rkey = mr->qplib_mr.rkey; 550 551 /* Create a fence MW only for kernel consumers */ 552 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 553 if (IS_ERR(mw)) { 554 ibdev_err(&rdev->ibdev, 555 "Failed to create fence-MW for PD: %p\n", pd); 556 rc = PTR_ERR(mw); 557 goto fail; 558 } 559 fence->mw = mw; 560 561 bnxt_re_create_fence_wqe(pd); 562 return 0; 563 564 fail: 565 bnxt_re_destroy_fence_mr(pd); 566 return rc; 567 } 568 569 static struct bnxt_re_user_mmap_entry* 570 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset, 571 enum bnxt_re_mmap_flag mmap_flag, u64 *offset) 572 { 573 struct bnxt_re_user_mmap_entry *entry; 574 int ret; 575 576 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 577 if (!entry) 578 return NULL; 579 580 entry->mem_offset = mem_offset; 581 entry->mmap_flag = mmap_flag; 582 entry->uctx = uctx; 583 584 switch (mmap_flag) { 585 case BNXT_RE_MMAP_SH_PAGE: 586 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx, 587 &entry->rdma_entry, PAGE_SIZE, 0); 588 break; 589 case BNXT_RE_MMAP_UC_DB: 590 case BNXT_RE_MMAP_WC_DB: 591 case BNXT_RE_MMAP_DBR_BAR: 592 case BNXT_RE_MMAP_DBR_PAGE: 593 case BNXT_RE_MMAP_TOGGLE_PAGE: 594 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx, 595 &entry->rdma_entry, PAGE_SIZE); 596 break; 597 default: 598 ret = -EINVAL; 599 break; 600 } 601 602 if (ret) { 603 kfree(entry); 604 return NULL; 605 } 606 if (offset) 607 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 608 609 return entry; 610 } 611 612 /* Protection Domains */ 613 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 614 { 615 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 616 struct bnxt_re_dev *rdev = pd->rdev; 617 618 if (udata) { 619 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 620 pd->pd_db_mmap = NULL; 621 } 622 623 bnxt_re_destroy_fence_mr(pd); 624 625 if (pd->qplib_pd.id) { 626 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res, 627 &rdev->qplib_res.pd_tbl, 628 &pd->qplib_pd)) 629 atomic_dec(&rdev->stats.res.pd_count); 630 } 631 return 0; 632 } 633 634 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 635 { 636 struct ib_device *ibdev = ibpd->device; 637 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 638 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 639 udata, struct bnxt_re_ucontext, ib_uctx); 640 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 641 struct bnxt_re_user_mmap_entry *entry = NULL; 642 u32 active_pds; 643 int rc = 0; 644 645 pd->rdev = rdev; 646 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) { 647 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD"); 648 rc = -ENOMEM; 649 goto fail; 650 } 651 652 if (udata) { 653 struct bnxt_re_pd_resp resp = {}; 654 655 if (!ucntx->dpi.dbr) { 656 /* Allocate DPI in alloc_pd to avoid failing of 657 * ibv_devinfo and family of application when DPIs 658 * are depleted. 659 */ 660 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, 661 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) { 662 rc = -ENOMEM; 663 goto dbfail; 664 } 665 } 666 667 resp.pdid = pd->qplib_pd.id; 668 /* Still allow mapping this DBR to the new user PD. */ 669 resp.dpi = ucntx->dpi.dpi; 670 671 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr, 672 BNXT_RE_MMAP_UC_DB, &resp.dbr); 673 674 if (!entry) { 675 rc = -ENOMEM; 676 goto dbfail; 677 } 678 679 pd->pd_db_mmap = &entry->rdma_entry; 680 681 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 682 if (rc) { 683 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 684 rc = -EFAULT; 685 goto dbfail; 686 } 687 } 688 689 if (!udata) 690 if (bnxt_re_create_fence_mr(pd)) 691 ibdev_warn(&rdev->ibdev, 692 "Failed to create Fence-MR\n"); 693 active_pds = atomic_inc_return(&rdev->stats.res.pd_count); 694 if (active_pds > rdev->stats.res.pd_watermark) 695 rdev->stats.res.pd_watermark = active_pds; 696 697 return 0; 698 dbfail: 699 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 700 &pd->qplib_pd); 701 fail: 702 return rc; 703 } 704 705 /* Address Handles */ 706 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 707 { 708 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 709 struct bnxt_re_dev *rdev = ah->rdev; 710 bool block = true; 711 int rc; 712 713 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE); 714 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block); 715 if (BNXT_RE_CHECK_RC(rc)) { 716 if (rc == -ETIMEDOUT) 717 rc = 0; 718 else 719 goto fail; 720 } 721 atomic_dec(&rdev->stats.res.ah_count); 722 fail: 723 return rc; 724 } 725 726 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 727 { 728 u8 nw_type; 729 730 switch (ntype) { 731 case RDMA_NETWORK_IPV4: 732 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 733 break; 734 case RDMA_NETWORK_IPV6: 735 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 736 break; 737 default: 738 nw_type = CMDQ_CREATE_AH_TYPE_V1; 739 break; 740 } 741 return nw_type; 742 } 743 744 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr, 745 struct ib_udata *udata) 746 { 747 struct ib_pd *ib_pd = ib_ah->pd; 748 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 749 struct rdma_ah_attr *ah_attr = init_attr->ah_attr; 750 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 751 struct bnxt_re_dev *rdev = pd->rdev; 752 const struct ib_gid_attr *sgid_attr; 753 struct bnxt_re_gid_ctx *ctx; 754 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 755 u32 active_ahs; 756 u8 nw_type; 757 int rc; 758 759 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 760 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set"); 761 return -EINVAL; 762 } 763 764 ah->rdev = rdev; 765 ah->qplib_ah.pd = &pd->qplib_pd; 766 767 /* Supply the configuration for the HW */ 768 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 769 sizeof(union ib_gid)); 770 sgid_attr = grh->sgid_attr; 771 /* Get the HW context of the GID. The reference 772 * of GID table entry is already taken by the caller. 773 */ 774 ctx = rdma_read_gid_hw_context(sgid_attr); 775 ah->qplib_ah.sgid_index = ctx->idx; 776 ah->qplib_ah.host_sgid_index = grh->sgid_index; 777 ah->qplib_ah.traffic_class = grh->traffic_class; 778 ah->qplib_ah.flow_label = grh->flow_label; 779 ah->qplib_ah.hop_limit = grh->hop_limit; 780 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 781 782 /* Get network header type for this GID */ 783 nw_type = rdma_gid_attr_network_type(sgid_attr); 784 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 785 786 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 787 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 788 !(init_attr->flags & 789 RDMA_CREATE_AH_SLEEPABLE)); 790 if (rc) { 791 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH"); 792 return rc; 793 } 794 795 /* Write AVID to shared page. */ 796 if (udata) { 797 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 798 udata, struct bnxt_re_ucontext, ib_uctx); 799 unsigned long flag; 800 u32 *wrptr; 801 802 spin_lock_irqsave(&uctx->sh_lock, flag); 803 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 804 *wrptr = ah->qplib_ah.id; 805 wmb(); /* make sure cache is updated. */ 806 spin_unlock_irqrestore(&uctx->sh_lock, flag); 807 } 808 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count); 809 if (active_ahs > rdev->stats.res.ah_watermark) 810 rdev->stats.res.ah_watermark = active_ahs; 811 812 return 0; 813 } 814 815 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 816 { 817 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 818 819 ah_attr->type = ib_ah->type; 820 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 821 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 822 rdma_ah_set_grh(ah_attr, NULL, 0, 823 ah->qplib_ah.host_sgid_index, 824 0, ah->qplib_ah.traffic_class); 825 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 826 rdma_ah_set_port_num(ah_attr, 1); 827 rdma_ah_set_static_rate(ah_attr, 0); 828 return 0; 829 } 830 831 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 832 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 833 { 834 unsigned long flags; 835 836 spin_lock_irqsave(&qp->scq->cq_lock, flags); 837 if (qp->rcq != qp->scq) 838 spin_lock(&qp->rcq->cq_lock); 839 else 840 __acquire(&qp->rcq->cq_lock); 841 842 return flags; 843 } 844 845 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 846 unsigned long flags) 847 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 848 { 849 if (qp->rcq != qp->scq) 850 spin_unlock(&qp->rcq->cq_lock); 851 else 852 __release(&qp->rcq->cq_lock); 853 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 854 } 855 856 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp) 857 { 858 struct bnxt_re_qp *gsi_sqp; 859 struct bnxt_re_ah *gsi_sah; 860 struct bnxt_re_dev *rdev; 861 int rc; 862 863 rdev = qp->rdev; 864 gsi_sqp = rdev->gsi_ctx.gsi_sqp; 865 gsi_sah = rdev->gsi_ctx.gsi_sah; 866 867 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n"); 868 bnxt_qplib_destroy_ah(&rdev->qplib_res, 869 &gsi_sah->qplib_ah, 870 true); 871 atomic_dec(&rdev->stats.res.ah_count); 872 bnxt_qplib_clean_qp(&qp->qplib_qp); 873 874 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n"); 875 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp); 876 if (rc) { 877 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed"); 878 goto fail; 879 } 880 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp); 881 882 /* remove from active qp list */ 883 mutex_lock(&rdev->qp_lock); 884 list_del(&gsi_sqp->list); 885 mutex_unlock(&rdev->qp_lock); 886 atomic_dec(&rdev->stats.res.qp_count); 887 888 kfree(rdev->gsi_ctx.sqp_tbl); 889 kfree(gsi_sah); 890 kfree(gsi_sqp); 891 rdev->gsi_ctx.gsi_sqp = NULL; 892 rdev->gsi_ctx.gsi_sah = NULL; 893 rdev->gsi_ctx.sqp_tbl = NULL; 894 895 return 0; 896 fail: 897 return rc; 898 } 899 900 /* Queue Pairs */ 901 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 902 { 903 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 904 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 905 struct bnxt_re_dev *rdev = qp->rdev; 906 struct bnxt_qplib_nq *scq_nq = NULL; 907 struct bnxt_qplib_nq *rcq_nq = NULL; 908 unsigned int flags; 909 int rc; 910 911 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 912 913 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 914 if (rc) { 915 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP"); 916 return rc; 917 } 918 919 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 920 flags = bnxt_re_lock_cqs(qp); 921 bnxt_qplib_clean_qp(&qp->qplib_qp); 922 bnxt_re_unlock_cqs(qp, flags); 923 } 924 925 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 926 927 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) { 928 rc = bnxt_re_destroy_gsi_sqp(qp); 929 if (rc) 930 return rc; 931 } 932 933 mutex_lock(&rdev->qp_lock); 934 list_del(&qp->list); 935 mutex_unlock(&rdev->qp_lock); 936 atomic_dec(&rdev->stats.res.qp_count); 937 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC) 938 atomic_dec(&rdev->stats.res.rc_qp_count); 939 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD) 940 atomic_dec(&rdev->stats.res.ud_qp_count); 941 942 ib_umem_release(qp->rumem); 943 ib_umem_release(qp->sumem); 944 945 /* Flush all the entries of notification queue associated with 946 * given qp. 947 */ 948 scq_nq = qplib_qp->scq->nq; 949 rcq_nq = qplib_qp->rcq->nq; 950 bnxt_re_synchronize_nq(scq_nq); 951 if (scq_nq != rcq_nq) 952 bnxt_re_synchronize_nq(rcq_nq); 953 954 return 0; 955 } 956 957 static u8 __from_ib_qp_type(enum ib_qp_type type) 958 { 959 switch (type) { 960 case IB_QPT_GSI: 961 return CMDQ_CREATE_QP1_TYPE_GSI; 962 case IB_QPT_RC: 963 return CMDQ_CREATE_QP_TYPE_RC; 964 case IB_QPT_UD: 965 return CMDQ_CREATE_QP_TYPE_UD; 966 default: 967 return IB_QPT_MAX; 968 } 969 } 970 971 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp, 972 int rsge, int max) 973 { 974 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 975 rsge = max; 976 return bnxt_re_get_rwqe_size(rsge); 977 } 978 979 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge) 980 { 981 u16 wqe_size, calc_ils; 982 983 wqe_size = bnxt_re_get_swqe_size(nsge); 984 if (ilsize) { 985 calc_ils = sizeof(struct sq_send_hdr) + ilsize; 986 wqe_size = max_t(u16, calc_ils, wqe_size); 987 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr)); 988 } 989 return wqe_size; 990 } 991 992 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp, 993 struct ib_qp_init_attr *init_attr) 994 { 995 struct bnxt_qplib_dev_attr *dev_attr; 996 struct bnxt_qplib_qp *qplqp; 997 struct bnxt_re_dev *rdev; 998 struct bnxt_qplib_q *sq; 999 int align, ilsize; 1000 1001 rdev = qp->rdev; 1002 qplqp = &qp->qplib_qp; 1003 sq = &qplqp->sq; 1004 dev_attr = &rdev->dev_attr; 1005 1006 align = sizeof(struct sq_send_hdr); 1007 ilsize = ALIGN(init_attr->cap.max_inline_data, align); 1008 1009 /* For gen p4 and gen p5 fixed wqe compatibility mode 1010 * wqe size is fixed to 128 bytes - ie 6 SGEs 1011 */ 1012 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) { 1013 sq->wqe_size = bnxt_re_get_swqe_size(BNXT_STATIC_MAX_SGE); 1014 sq->max_sge = BNXT_STATIC_MAX_SGE; 1015 } else { 1016 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge); 1017 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges)) 1018 return -EINVAL; 1019 } 1020 1021 if (init_attr->cap.max_inline_data) { 1022 qplqp->max_inline_data = sq->wqe_size - 1023 sizeof(struct sq_send_hdr); 1024 init_attr->cap.max_inline_data = qplqp->max_inline_data; 1025 } 1026 1027 return 0; 1028 } 1029 1030 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 1031 struct bnxt_re_qp *qp, struct bnxt_re_ucontext *cntx, 1032 struct bnxt_re_qp_req *ureq) 1033 { 1034 struct bnxt_qplib_qp *qplib_qp; 1035 int bytes = 0, psn_sz; 1036 struct ib_umem *umem; 1037 int psn_nume; 1038 1039 qplib_qp = &qp->qplib_qp; 1040 1041 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size); 1042 /* Consider mapping PSN search memory only for RC QPs. */ 1043 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 1044 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 1045 sizeof(struct sq_psn_search_ext) : 1046 sizeof(struct sq_psn_search); 1047 if (cntx && bnxt_re_is_var_size_supported(rdev, cntx)) { 1048 psn_nume = ureq->sq_slots; 1049 } else { 1050 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 1051 qplib_qp->sq.max_wqe : ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) / 1052 sizeof(struct bnxt_qplib_sge)); 1053 } 1054 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 1055 psn_nume = roundup_pow_of_two(psn_nume); 1056 bytes += (psn_nume * psn_sz); 1057 } 1058 1059 bytes = PAGE_ALIGN(bytes); 1060 umem = ib_umem_get(&rdev->ibdev, ureq->qpsva, bytes, 1061 IB_ACCESS_LOCAL_WRITE); 1062 if (IS_ERR(umem)) 1063 return PTR_ERR(umem); 1064 1065 qp->sumem = umem; 1066 qplib_qp->sq.sg_info.umem = umem; 1067 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE; 1068 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT; 1069 qplib_qp->qp_handle = ureq->qp_handle; 1070 1071 if (!qp->qplib_qp.srq) { 1072 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size); 1073 bytes = PAGE_ALIGN(bytes); 1074 umem = ib_umem_get(&rdev->ibdev, ureq->qprva, bytes, 1075 IB_ACCESS_LOCAL_WRITE); 1076 if (IS_ERR(umem)) 1077 goto rqfail; 1078 qp->rumem = umem; 1079 qplib_qp->rq.sg_info.umem = umem; 1080 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE; 1081 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT; 1082 } 1083 1084 qplib_qp->dpi = &cntx->dpi; 1085 return 0; 1086 rqfail: 1087 ib_umem_release(qp->sumem); 1088 qp->sumem = NULL; 1089 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 1090 1091 return PTR_ERR(umem); 1092 } 1093 1094 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 1095 (struct bnxt_re_pd *pd, 1096 struct bnxt_qplib_res *qp1_res, 1097 struct bnxt_qplib_qp *qp1_qp) 1098 { 1099 struct bnxt_re_dev *rdev = pd->rdev; 1100 struct bnxt_re_ah *ah; 1101 union ib_gid sgid; 1102 int rc; 1103 1104 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 1105 if (!ah) 1106 return NULL; 1107 1108 ah->rdev = rdev; 1109 ah->qplib_ah.pd = &pd->qplib_pd; 1110 1111 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 1112 if (rc) 1113 goto fail; 1114 1115 /* supply the dgid data same as sgid */ 1116 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 1117 sizeof(union ib_gid)); 1118 ah->qplib_ah.sgid_index = 0; 1119 1120 ah->qplib_ah.traffic_class = 0; 1121 ah->qplib_ah.flow_label = 0; 1122 ah->qplib_ah.hop_limit = 1; 1123 ah->qplib_ah.sl = 0; 1124 /* Have DMAC same as SMAC */ 1125 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 1126 1127 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 1128 if (rc) { 1129 ibdev_err(&rdev->ibdev, 1130 "Failed to allocate HW AH for Shadow QP"); 1131 goto fail; 1132 } 1133 atomic_inc(&rdev->stats.res.ah_count); 1134 1135 return ah; 1136 1137 fail: 1138 kfree(ah); 1139 return NULL; 1140 } 1141 1142 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 1143 (struct bnxt_re_pd *pd, 1144 struct bnxt_qplib_res *qp1_res, 1145 struct bnxt_qplib_qp *qp1_qp) 1146 { 1147 struct bnxt_re_dev *rdev = pd->rdev; 1148 struct bnxt_re_qp *qp; 1149 int rc; 1150 1151 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1152 if (!qp) 1153 return NULL; 1154 1155 qp->rdev = rdev; 1156 1157 /* Initialize the shadow QP structure from the QP1 values */ 1158 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1159 1160 qp->qplib_qp.pd = &pd->qplib_pd; 1161 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1162 qp->qplib_qp.type = IB_QPT_UD; 1163 1164 qp->qplib_qp.max_inline_data = 0; 1165 qp->qplib_qp.sig_type = true; 1166 1167 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 1168 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6); 1169 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1170 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe; 1171 qp->qplib_qp.sq.max_sge = 2; 1172 /* Q full delta can be 1 since it is internal QP */ 1173 qp->qplib_qp.sq.q_full_delta = 1; 1174 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE; 1175 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT; 1176 1177 qp->qplib_qp.scq = qp1_qp->scq; 1178 qp->qplib_qp.rcq = qp1_qp->rcq; 1179 1180 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6); 1181 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1182 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe; 1183 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1184 /* Q full delta can be 1 since it is internal QP */ 1185 qp->qplib_qp.rq.q_full_delta = 1; 1186 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE; 1187 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT; 1188 1189 qp->qplib_qp.mtu = qp1_qp->mtu; 1190 1191 qp->qplib_qp.sq_hdr_buf_size = 0; 1192 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1193 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1194 1195 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1196 if (rc) 1197 goto fail; 1198 1199 spin_lock_init(&qp->sq_lock); 1200 INIT_LIST_HEAD(&qp->list); 1201 mutex_lock(&rdev->qp_lock); 1202 list_add_tail(&qp->list, &rdev->qp_list); 1203 atomic_inc(&rdev->stats.res.qp_count); 1204 mutex_unlock(&rdev->qp_lock); 1205 return qp; 1206 fail: 1207 kfree(qp); 1208 return NULL; 1209 } 1210 1211 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 1212 struct ib_qp_init_attr *init_attr, 1213 struct bnxt_re_ucontext *uctx) 1214 { 1215 struct bnxt_qplib_dev_attr *dev_attr; 1216 struct bnxt_qplib_qp *qplqp; 1217 struct bnxt_re_dev *rdev; 1218 struct bnxt_qplib_q *rq; 1219 int entries; 1220 1221 rdev = qp->rdev; 1222 qplqp = &qp->qplib_qp; 1223 rq = &qplqp->rq; 1224 dev_attr = &rdev->dev_attr; 1225 1226 if (init_attr->srq) { 1227 struct bnxt_re_srq *srq; 1228 1229 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq); 1230 qplqp->srq = &srq->qplib_srq; 1231 rq->max_wqe = 0; 1232 } else { 1233 rq->max_sge = init_attr->cap.max_recv_sge; 1234 if (rq->max_sge > dev_attr->max_qp_sges) 1235 rq->max_sge = dev_attr->max_qp_sges; 1236 init_attr->cap.max_recv_sge = rq->max_sge; 1237 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge, 1238 dev_attr->max_qp_sges); 1239 /* Allocate 1 more than what's provided so posting max doesn't 1240 * mean empty. 1241 */ 1242 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx); 1243 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1244 rq->max_sw_wqe = rq->max_wqe; 1245 rq->q_full_delta = 0; 1246 rq->sg_info.pgsize = PAGE_SIZE; 1247 rq->sg_info.pgshft = PAGE_SHIFT; 1248 } 1249 1250 return 0; 1251 } 1252 1253 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 1254 { 1255 struct bnxt_qplib_dev_attr *dev_attr; 1256 struct bnxt_qplib_qp *qplqp; 1257 struct bnxt_re_dev *rdev; 1258 1259 rdev = qp->rdev; 1260 qplqp = &qp->qplib_qp; 1261 dev_attr = &rdev->dev_attr; 1262 1263 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1264 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1265 if (qplqp->rq.max_sge > dev_attr->max_qp_sges) 1266 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1267 qplqp->rq.max_sge = 6; 1268 } 1269 } 1270 1271 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 1272 struct ib_qp_init_attr *init_attr, 1273 struct bnxt_re_ucontext *uctx, 1274 struct bnxt_re_qp_req *ureq) 1275 { 1276 struct bnxt_qplib_dev_attr *dev_attr; 1277 struct bnxt_qplib_qp *qplqp; 1278 struct bnxt_re_dev *rdev; 1279 struct bnxt_qplib_q *sq; 1280 int diff = 0; 1281 int entries; 1282 int rc; 1283 1284 rdev = qp->rdev; 1285 qplqp = &qp->qplib_qp; 1286 sq = &qplqp->sq; 1287 dev_attr = &rdev->dev_attr; 1288 1289 sq->max_sge = init_attr->cap.max_send_sge; 1290 entries = init_attr->cap.max_send_wr; 1291 if (uctx && qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) { 1292 sq->max_wqe = ureq->sq_slots; 1293 sq->max_sw_wqe = ureq->sq_slots; 1294 sq->wqe_size = sizeof(struct sq_sge); 1295 } else { 1296 if (sq->max_sge > dev_attr->max_qp_sges) { 1297 sq->max_sge = dev_attr->max_qp_sges; 1298 init_attr->cap.max_send_sge = sq->max_sge; 1299 } 1300 1301 rc = bnxt_re_setup_swqe_size(qp, init_attr); 1302 if (rc) 1303 return rc; 1304 1305 /* Allocate 128 + 1 more than what's provided */ 1306 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ? 1307 0 : BNXT_QPLIB_RESERVED_QP_WRS; 1308 entries = bnxt_re_init_depth(entries + diff + 1, uctx); 1309 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1); 1310 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true); 1311 } 1312 sq->q_full_delta = diff + 1; 1313 /* 1314 * Reserving one slot for Phantom WQE. Application can 1315 * post one extra entry in this case. But allowing this to avoid 1316 * unexpected Queue full condition 1317 */ 1318 qplqp->sq.q_full_delta -= 1; 1319 qplqp->sq.sg_info.pgsize = PAGE_SIZE; 1320 qplqp->sq.sg_info.pgshft = PAGE_SHIFT; 1321 1322 return 0; 1323 } 1324 1325 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 1326 struct ib_qp_init_attr *init_attr, 1327 struct bnxt_re_ucontext *uctx) 1328 { 1329 struct bnxt_qplib_dev_attr *dev_attr; 1330 struct bnxt_qplib_qp *qplqp; 1331 struct bnxt_re_dev *rdev; 1332 int entries; 1333 1334 rdev = qp->rdev; 1335 qplqp = &qp->qplib_qp; 1336 dev_attr = &rdev->dev_attr; 1337 1338 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1339 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx); 1340 qplqp->sq.max_wqe = min_t(u32, entries, 1341 dev_attr->max_qp_wqes + 1); 1342 qplqp->sq.q_full_delta = qplqp->sq.max_wqe - 1343 init_attr->cap.max_send_wr; 1344 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ 1345 if (qplqp->sq.max_sge > dev_attr->max_qp_sges) 1346 qplqp->sq.max_sge = dev_attr->max_qp_sges; 1347 } 1348 } 1349 1350 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 1351 struct ib_qp_init_attr *init_attr) 1352 { 1353 struct bnxt_qplib_chip_ctx *chip_ctx; 1354 int qptype; 1355 1356 chip_ctx = rdev->chip_ctx; 1357 1358 qptype = __from_ib_qp_type(init_attr->qp_type); 1359 if (qptype == IB_QPT_MAX) { 1360 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype); 1361 qptype = -EOPNOTSUPP; 1362 goto out; 1363 } 1364 1365 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) && 1366 init_attr->qp_type == IB_QPT_GSI) 1367 qptype = CMDQ_CREATE_QP_TYPE_GSI; 1368 out: 1369 return qptype; 1370 } 1371 1372 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1373 struct ib_qp_init_attr *init_attr, 1374 struct bnxt_re_ucontext *uctx, 1375 struct bnxt_re_qp_req *ureq) 1376 { 1377 struct bnxt_qplib_dev_attr *dev_attr; 1378 struct bnxt_qplib_qp *qplqp; 1379 struct bnxt_re_dev *rdev; 1380 struct bnxt_re_cq *cq; 1381 int rc = 0, qptype; 1382 1383 rdev = qp->rdev; 1384 qplqp = &qp->qplib_qp; 1385 dev_attr = &rdev->dev_attr; 1386 1387 /* Setup misc params */ 1388 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); 1389 qplqp->pd = &pd->qplib_pd; 1390 qplqp->qp_handle = (u64)qplqp; 1391 qplqp->max_inline_data = init_attr->cap.max_inline_data; 1392 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR; 1393 qptype = bnxt_re_init_qp_type(rdev, init_attr); 1394 if (qptype < 0) { 1395 rc = qptype; 1396 goto out; 1397 } 1398 qplqp->type = (u8)qptype; 1399 qplqp->wqe_mode = bnxt_re_is_var_size_supported(rdev, uctx); 1400 if (init_attr->qp_type == IB_QPT_RC) { 1401 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom; 1402 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1403 } 1404 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1405 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */ 1406 if (init_attr->create_flags) { 1407 ibdev_dbg(&rdev->ibdev, 1408 "QP create flags 0x%x not supported", 1409 init_attr->create_flags); 1410 return -EOPNOTSUPP; 1411 } 1412 1413 /* Setup CQs */ 1414 if (init_attr->send_cq) { 1415 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq); 1416 qplqp->scq = &cq->qplib_cq; 1417 qp->scq = cq; 1418 } 1419 1420 if (init_attr->recv_cq) { 1421 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq); 1422 qplqp->rcq = &cq->qplib_cq; 1423 qp->rcq = cq; 1424 } 1425 1426 /* Setup RQ/SRQ */ 1427 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx); 1428 if (rc) 1429 goto out; 1430 if (init_attr->qp_type == IB_QPT_GSI) 1431 bnxt_re_adjust_gsi_rq_attr(qp); 1432 1433 /* Setup SQ */ 1434 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx, ureq); 1435 if (rc) 1436 goto out; 1437 if (init_attr->qp_type == IB_QPT_GSI) 1438 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx); 1439 1440 if (uctx) /* This will update DPI and qp_handle */ 1441 rc = bnxt_re_init_user_qp(rdev, pd, qp, uctx, ureq); 1442 out: 1443 return rc; 1444 } 1445 1446 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp, 1447 struct bnxt_re_pd *pd) 1448 { 1449 struct bnxt_re_sqp_entries *sqp_tbl; 1450 struct bnxt_re_dev *rdev; 1451 struct bnxt_re_qp *sqp; 1452 struct bnxt_re_ah *sah; 1453 int rc = 0; 1454 1455 rdev = qp->rdev; 1456 /* Create a shadow QP to handle the QP1 traffic */ 1457 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl), 1458 GFP_KERNEL); 1459 if (!sqp_tbl) 1460 return -ENOMEM; 1461 rdev->gsi_ctx.sqp_tbl = sqp_tbl; 1462 1463 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp); 1464 if (!sqp) { 1465 rc = -ENODEV; 1466 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1"); 1467 goto out; 1468 } 1469 rdev->gsi_ctx.gsi_sqp = sqp; 1470 1471 sqp->rcq = qp->rcq; 1472 sqp->scq = qp->scq; 1473 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1474 &qp->qplib_qp); 1475 if (!sah) { 1476 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1477 &sqp->qplib_qp); 1478 rc = -ENODEV; 1479 ibdev_err(&rdev->ibdev, 1480 "Failed to create AH entry for ShadowQP"); 1481 goto out; 1482 } 1483 rdev->gsi_ctx.gsi_sah = sah; 1484 1485 return 0; 1486 out: 1487 kfree(sqp_tbl); 1488 return rc; 1489 } 1490 1491 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1492 struct ib_qp_init_attr *init_attr) 1493 { 1494 struct bnxt_re_dev *rdev; 1495 struct bnxt_qplib_qp *qplqp; 1496 int rc; 1497 1498 rdev = qp->rdev; 1499 qplqp = &qp->qplib_qp; 1500 1501 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1502 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1503 1504 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp); 1505 if (rc) { 1506 ibdev_err(&rdev->ibdev, "create HW QP1 failed!"); 1507 goto out; 1508 } 1509 1510 rc = bnxt_re_create_shadow_gsi(qp, pd); 1511 out: 1512 return rc; 1513 } 1514 1515 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev, 1516 struct ib_qp_init_attr *init_attr, 1517 struct bnxt_qplib_dev_attr *dev_attr) 1518 { 1519 bool rc = true; 1520 1521 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes || 1522 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes || 1523 init_attr->cap.max_send_sge > dev_attr->max_qp_sges || 1524 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges || 1525 init_attr->cap.max_inline_data > dev_attr->max_inline_data) { 1526 ibdev_err(&rdev->ibdev, 1527 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x", 1528 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes, 1529 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes, 1530 init_attr->cap.max_send_sge, dev_attr->max_qp_sges, 1531 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges, 1532 init_attr->cap.max_inline_data, 1533 dev_attr->max_inline_data); 1534 rc = false; 1535 } 1536 return rc; 1537 } 1538 1539 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr, 1540 struct ib_udata *udata) 1541 { 1542 struct bnxt_qplib_dev_attr *dev_attr; 1543 struct bnxt_re_ucontext *uctx; 1544 struct bnxt_re_qp_req ureq; 1545 struct bnxt_re_dev *rdev; 1546 struct bnxt_re_pd *pd; 1547 struct bnxt_re_qp *qp; 1548 struct ib_pd *ib_pd; 1549 u32 active_qps; 1550 int rc; 1551 1552 ib_pd = ib_qp->pd; 1553 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1554 rdev = pd->rdev; 1555 dev_attr = &rdev->dev_attr; 1556 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1557 1558 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1559 if (udata) 1560 if (ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)))) 1561 return -EFAULT; 1562 1563 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr); 1564 if (!rc) { 1565 rc = -EINVAL; 1566 goto fail; 1567 } 1568 1569 qp->rdev = rdev; 1570 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, uctx, &ureq); 1571 if (rc) 1572 goto fail; 1573 1574 if (qp_init_attr->qp_type == IB_QPT_GSI && 1575 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) { 1576 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr); 1577 if (rc == -ENODEV) 1578 goto qp_destroy; 1579 if (rc) 1580 goto fail; 1581 } else { 1582 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1583 if (rc) { 1584 ibdev_err(&rdev->ibdev, "Failed to create HW QP"); 1585 goto free_umem; 1586 } 1587 if (udata) { 1588 struct bnxt_re_qp_resp resp; 1589 1590 resp.qpid = qp->qplib_qp.id; 1591 resp.rsvd = 0; 1592 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1593 if (rc) { 1594 ibdev_err(&rdev->ibdev, "Failed to copy QP udata"); 1595 goto qp_destroy; 1596 } 1597 } 1598 } 1599 1600 qp->ib_qp.qp_num = qp->qplib_qp.id; 1601 if (qp_init_attr->qp_type == IB_QPT_GSI) 1602 rdev->gsi_ctx.gsi_qp = qp; 1603 spin_lock_init(&qp->sq_lock); 1604 spin_lock_init(&qp->rq_lock); 1605 INIT_LIST_HEAD(&qp->list); 1606 mutex_lock(&rdev->qp_lock); 1607 list_add_tail(&qp->list, &rdev->qp_list); 1608 mutex_unlock(&rdev->qp_lock); 1609 active_qps = atomic_inc_return(&rdev->stats.res.qp_count); 1610 if (active_qps > rdev->stats.res.qp_watermark) 1611 rdev->stats.res.qp_watermark = active_qps; 1612 if (qp_init_attr->qp_type == IB_QPT_RC) { 1613 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count); 1614 if (active_qps > rdev->stats.res.rc_qp_watermark) 1615 rdev->stats.res.rc_qp_watermark = active_qps; 1616 } else if (qp_init_attr->qp_type == IB_QPT_UD) { 1617 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count); 1618 if (active_qps > rdev->stats.res.ud_qp_watermark) 1619 rdev->stats.res.ud_qp_watermark = active_qps; 1620 } 1621 1622 return 0; 1623 qp_destroy: 1624 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1625 free_umem: 1626 ib_umem_release(qp->rumem); 1627 ib_umem_release(qp->sumem); 1628 fail: 1629 return rc; 1630 } 1631 1632 static u8 __from_ib_qp_state(enum ib_qp_state state) 1633 { 1634 switch (state) { 1635 case IB_QPS_RESET: 1636 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1637 case IB_QPS_INIT: 1638 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1639 case IB_QPS_RTR: 1640 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1641 case IB_QPS_RTS: 1642 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1643 case IB_QPS_SQD: 1644 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1645 case IB_QPS_SQE: 1646 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1647 case IB_QPS_ERR: 1648 default: 1649 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1650 } 1651 } 1652 1653 static enum ib_qp_state __to_ib_qp_state(u8 state) 1654 { 1655 switch (state) { 1656 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1657 return IB_QPS_RESET; 1658 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1659 return IB_QPS_INIT; 1660 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1661 return IB_QPS_RTR; 1662 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1663 return IB_QPS_RTS; 1664 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1665 return IB_QPS_SQD; 1666 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1667 return IB_QPS_SQE; 1668 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1669 default: 1670 return IB_QPS_ERR; 1671 } 1672 } 1673 1674 static u32 __from_ib_mtu(enum ib_mtu mtu) 1675 { 1676 switch (mtu) { 1677 case IB_MTU_256: 1678 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1679 case IB_MTU_512: 1680 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1681 case IB_MTU_1024: 1682 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1683 case IB_MTU_2048: 1684 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1685 case IB_MTU_4096: 1686 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1687 default: 1688 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1689 } 1690 } 1691 1692 static enum ib_mtu __to_ib_mtu(u32 mtu) 1693 { 1694 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1695 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1696 return IB_MTU_256; 1697 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1698 return IB_MTU_512; 1699 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1700 return IB_MTU_1024; 1701 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1702 return IB_MTU_2048; 1703 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1704 return IB_MTU_4096; 1705 default: 1706 return IB_MTU_2048; 1707 } 1708 } 1709 1710 /* Shared Receive Queues */ 1711 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1712 { 1713 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1714 ib_srq); 1715 struct bnxt_re_dev *rdev = srq->rdev; 1716 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1717 struct bnxt_qplib_nq *nq = NULL; 1718 1719 if (qplib_srq->cq) 1720 nq = qplib_srq->cq->nq; 1721 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) { 1722 free_page((unsigned long)srq->uctx_srq_page); 1723 hash_del(&srq->hash_entry); 1724 } 1725 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1726 ib_umem_release(srq->umem); 1727 atomic_dec(&rdev->stats.res.srq_count); 1728 if (nq) 1729 nq->budget--; 1730 return 0; 1731 } 1732 1733 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1734 struct bnxt_re_pd *pd, 1735 struct bnxt_re_srq *srq, 1736 struct ib_udata *udata) 1737 { 1738 struct bnxt_re_srq_req ureq; 1739 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1740 struct ib_umem *umem; 1741 int bytes = 0; 1742 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1743 udata, struct bnxt_re_ucontext, ib_uctx); 1744 1745 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1746 return -EFAULT; 1747 1748 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size); 1749 bytes = PAGE_ALIGN(bytes); 1750 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes, 1751 IB_ACCESS_LOCAL_WRITE); 1752 if (IS_ERR(umem)) 1753 return PTR_ERR(umem); 1754 1755 srq->umem = umem; 1756 qplib_srq->sg_info.umem = umem; 1757 qplib_srq->sg_info.pgsize = PAGE_SIZE; 1758 qplib_srq->sg_info.pgshft = PAGE_SHIFT; 1759 qplib_srq->srq_handle = ureq.srq_handle; 1760 qplib_srq->dpi = &cntx->dpi; 1761 1762 return 0; 1763 } 1764 1765 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1766 struct ib_srq_init_attr *srq_init_attr, 1767 struct ib_udata *udata) 1768 { 1769 struct bnxt_qplib_dev_attr *dev_attr; 1770 struct bnxt_qplib_nq *nq = NULL; 1771 struct bnxt_re_ucontext *uctx; 1772 struct bnxt_re_dev *rdev; 1773 struct bnxt_re_srq *srq; 1774 struct bnxt_re_pd *pd; 1775 struct ib_pd *ib_pd; 1776 u32 active_srqs; 1777 int rc, entries; 1778 1779 ib_pd = ib_srq->pd; 1780 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1781 rdev = pd->rdev; 1782 dev_attr = &rdev->dev_attr; 1783 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1784 1785 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1786 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded"); 1787 rc = -EINVAL; 1788 goto exit; 1789 } 1790 1791 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1792 rc = -EOPNOTSUPP; 1793 goto exit; 1794 } 1795 1796 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1797 srq->rdev = rdev; 1798 srq->qplib_srq.pd = &pd->qplib_pd; 1799 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1800 /* Allocate 1 more than what's provided so posting max doesn't 1801 * mean empty 1802 */ 1803 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx); 1804 if (entries > dev_attr->max_srq_wqes + 1) 1805 entries = dev_attr->max_srq_wqes + 1; 1806 srq->qplib_srq.max_wqe = entries; 1807 1808 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1809 /* 128 byte wqe size for SRQ . So use max sges */ 1810 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges); 1811 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1812 srq->srq_limit = srq_init_attr->attr.srq_limit; 1813 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1814 nq = &rdev->nq[0]; 1815 1816 if (udata) { 1817 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1818 if (rc) 1819 goto fail; 1820 } 1821 1822 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1823 if (rc) { 1824 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!"); 1825 goto fail; 1826 } 1827 1828 if (udata) { 1829 struct bnxt_re_srq_resp resp = {}; 1830 1831 resp.srqid = srq->qplib_srq.id; 1832 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) { 1833 hash_add(rdev->srq_hash, &srq->hash_entry, srq->qplib_srq.id); 1834 srq->uctx_srq_page = (void *)get_zeroed_page(GFP_KERNEL); 1835 if (!srq->uctx_srq_page) { 1836 rc = -ENOMEM; 1837 goto fail; 1838 } 1839 resp.comp_mask |= BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT; 1840 } 1841 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1842 if (rc) { 1843 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!"); 1844 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1845 &srq->qplib_srq); 1846 goto fail; 1847 } 1848 } 1849 if (nq) 1850 nq->budget++; 1851 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count); 1852 if (active_srqs > rdev->stats.res.srq_watermark) 1853 rdev->stats.res.srq_watermark = active_srqs; 1854 spin_lock_init(&srq->lock); 1855 1856 return 0; 1857 1858 fail: 1859 ib_umem_release(srq->umem); 1860 exit: 1861 return rc; 1862 } 1863 1864 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1865 enum ib_srq_attr_mask srq_attr_mask, 1866 struct ib_udata *udata) 1867 { 1868 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1869 ib_srq); 1870 struct bnxt_re_dev *rdev = srq->rdev; 1871 int rc; 1872 1873 switch (srq_attr_mask) { 1874 case IB_SRQ_MAX_WR: 1875 /* SRQ resize is not supported */ 1876 return -EINVAL; 1877 case IB_SRQ_LIMIT: 1878 /* Change the SRQ threshold */ 1879 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1880 return -EINVAL; 1881 1882 srq->qplib_srq.threshold = srq_attr->srq_limit; 1883 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1884 if (rc) { 1885 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!"); 1886 return rc; 1887 } 1888 /* On success, update the shadow */ 1889 srq->srq_limit = srq_attr->srq_limit; 1890 /* No need to Build and send response back to udata */ 1891 return 0; 1892 default: 1893 ibdev_err(&rdev->ibdev, 1894 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1895 return -EINVAL; 1896 } 1897 } 1898 1899 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1900 { 1901 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1902 ib_srq); 1903 struct bnxt_re_srq tsrq; 1904 struct bnxt_re_dev *rdev = srq->rdev; 1905 int rc; 1906 1907 /* Get live SRQ attr */ 1908 tsrq.qplib_srq.id = srq->qplib_srq.id; 1909 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1910 if (rc) { 1911 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!"); 1912 return rc; 1913 } 1914 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1915 srq_attr->max_sge = srq->qplib_srq.max_sge; 1916 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1917 1918 return 0; 1919 } 1920 1921 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1922 const struct ib_recv_wr **bad_wr) 1923 { 1924 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1925 ib_srq); 1926 struct bnxt_qplib_swqe wqe; 1927 unsigned long flags; 1928 int rc = 0; 1929 1930 spin_lock_irqsave(&srq->lock, flags); 1931 while (wr) { 1932 /* Transcribe each ib_recv_wr to qplib_swqe */ 1933 wqe.num_sge = wr->num_sge; 1934 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1935 wqe.wr_id = wr->wr_id; 1936 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1937 1938 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1939 if (rc) { 1940 *bad_wr = wr; 1941 break; 1942 } 1943 wr = wr->next; 1944 } 1945 spin_unlock_irqrestore(&srq->lock, flags); 1946 1947 return rc; 1948 } 1949 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1950 struct bnxt_re_qp *qp1_qp, 1951 int qp_attr_mask) 1952 { 1953 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp; 1954 int rc; 1955 1956 if (qp_attr_mask & IB_QP_STATE) { 1957 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1958 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1959 } 1960 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1961 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1962 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1963 } 1964 1965 if (qp_attr_mask & IB_QP_QKEY) { 1966 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1967 /* Using a Random QKEY */ 1968 qp->qplib_qp.qkey = 0x81818181; 1969 } 1970 if (qp_attr_mask & IB_QP_SQ_PSN) { 1971 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1972 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1973 } 1974 1975 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1976 if (rc) 1977 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1"); 1978 return rc; 1979 } 1980 1981 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1982 int qp_attr_mask, struct ib_udata *udata) 1983 { 1984 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1985 struct bnxt_re_dev *rdev = qp->rdev; 1986 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1987 enum ib_qp_state curr_qp_state, new_qp_state; 1988 int rc, entries; 1989 unsigned int flags; 1990 u8 nw_type; 1991 1992 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 1993 return -EOPNOTSUPP; 1994 1995 qp->qplib_qp.modify_flags = 0; 1996 if (qp_attr_mask & IB_QP_STATE) { 1997 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1998 new_qp_state = qp_attr->qp_state; 1999 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 2000 ib_qp->qp_type, qp_attr_mask)) { 2001 ibdev_err(&rdev->ibdev, 2002 "Invalid attribute mask: %#x specified ", 2003 qp_attr_mask); 2004 ibdev_err(&rdev->ibdev, 2005 "for qpn: %#x type: %#x", 2006 ib_qp->qp_num, ib_qp->qp_type); 2007 ibdev_err(&rdev->ibdev, 2008 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 2009 curr_qp_state, new_qp_state); 2010 return -EINVAL; 2011 } 2012 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 2013 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 2014 2015 if (!qp->sumem && 2016 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 2017 ibdev_dbg(&rdev->ibdev, 2018 "Move QP = %p to flush list\n", qp); 2019 flags = bnxt_re_lock_cqs(qp); 2020 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 2021 bnxt_re_unlock_cqs(qp, flags); 2022 } 2023 if (!qp->sumem && 2024 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 2025 ibdev_dbg(&rdev->ibdev, 2026 "Move QP = %p out of flush list\n", qp); 2027 flags = bnxt_re_lock_cqs(qp); 2028 bnxt_qplib_clean_qp(&qp->qplib_qp); 2029 bnxt_re_unlock_cqs(qp, flags); 2030 } 2031 } 2032 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 2033 qp->qplib_qp.modify_flags |= 2034 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 2035 qp->qplib_qp.en_sqd_async_notify = true; 2036 } 2037 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 2038 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 2039 qp->qplib_qp.access = 2040 __from_ib_access_flags(qp_attr->qp_access_flags); 2041 /* LOCAL_WRITE access must be set to allow RC receive */ 2042 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 2043 /* Temp: Set all params on QP as of now */ 2044 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 2045 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 2046 } 2047 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 2048 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 2049 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 2050 } 2051 if (qp_attr_mask & IB_QP_QKEY) { 2052 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 2053 qp->qplib_qp.qkey = qp_attr->qkey; 2054 } 2055 if (qp_attr_mask & IB_QP_AV) { 2056 const struct ib_global_route *grh = 2057 rdma_ah_read_grh(&qp_attr->ah_attr); 2058 const struct ib_gid_attr *sgid_attr; 2059 struct bnxt_re_gid_ctx *ctx; 2060 2061 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 2062 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 2063 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 2064 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 2065 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 2066 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 2067 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 2068 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 2069 sizeof(qp->qplib_qp.ah.dgid.data)); 2070 qp->qplib_qp.ah.flow_label = grh->flow_label; 2071 sgid_attr = grh->sgid_attr; 2072 /* Get the HW context of the GID. The reference 2073 * of GID table entry is already taken by the caller. 2074 */ 2075 ctx = rdma_read_gid_hw_context(sgid_attr); 2076 qp->qplib_qp.ah.sgid_index = ctx->idx; 2077 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 2078 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 2079 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 2080 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 2081 ether_addr_copy(qp->qplib_qp.ah.dmac, 2082 qp_attr->ah_attr.roce.dmac); 2083 2084 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 2085 &qp->qplib_qp.smac[0]); 2086 if (rc) 2087 return rc; 2088 2089 nw_type = rdma_gid_attr_network_type(sgid_attr); 2090 switch (nw_type) { 2091 case RDMA_NETWORK_IPV4: 2092 qp->qplib_qp.nw_type = 2093 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 2094 break; 2095 case RDMA_NETWORK_IPV6: 2096 qp->qplib_qp.nw_type = 2097 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 2098 break; 2099 default: 2100 qp->qplib_qp.nw_type = 2101 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 2102 break; 2103 } 2104 } 2105 2106 if (qp_attr_mask & IB_QP_PATH_MTU) { 2107 qp->qplib_qp.modify_flags |= 2108 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2109 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 2110 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 2111 } else if (qp_attr->qp_state == IB_QPS_RTR) { 2112 qp->qplib_qp.modify_flags |= 2113 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2114 qp->qplib_qp.path_mtu = 2115 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 2116 qp->qplib_qp.mtu = 2117 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 2118 } 2119 2120 if (qp_attr_mask & IB_QP_TIMEOUT) { 2121 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 2122 qp->qplib_qp.timeout = qp_attr->timeout; 2123 } 2124 if (qp_attr_mask & IB_QP_RETRY_CNT) { 2125 qp->qplib_qp.modify_flags |= 2126 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 2127 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 2128 } 2129 if (qp_attr_mask & IB_QP_RNR_RETRY) { 2130 qp->qplib_qp.modify_flags |= 2131 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 2132 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 2133 } 2134 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 2135 qp->qplib_qp.modify_flags |= 2136 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 2137 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 2138 } 2139 if (qp_attr_mask & IB_QP_RQ_PSN) { 2140 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 2141 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 2142 } 2143 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2144 qp->qplib_qp.modify_flags |= 2145 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 2146 /* Cap the max_rd_atomic to device max */ 2147 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 2148 dev_attr->max_qp_rd_atom); 2149 } 2150 if (qp_attr_mask & IB_QP_SQ_PSN) { 2151 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2152 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 2153 } 2154 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2155 if (qp_attr->max_dest_rd_atomic > 2156 dev_attr->max_qp_init_rd_atom) { 2157 ibdev_err(&rdev->ibdev, 2158 "max_dest_rd_atomic requested%d is > dev_max%d", 2159 qp_attr->max_dest_rd_atomic, 2160 dev_attr->max_qp_init_rd_atom); 2161 return -EINVAL; 2162 } 2163 2164 qp->qplib_qp.modify_flags |= 2165 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 2166 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 2167 } 2168 if (qp_attr_mask & IB_QP_CAP) { 2169 struct bnxt_re_ucontext *uctx = 2170 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2171 2172 qp->qplib_qp.modify_flags |= 2173 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 2174 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 2175 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 2176 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 2177 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 2178 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 2179 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 2180 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 2181 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 2182 (qp_attr->cap.max_inline_data >= 2183 dev_attr->max_inline_data)) { 2184 ibdev_err(&rdev->ibdev, 2185 "Create QP failed - max exceeded"); 2186 return -EINVAL; 2187 } 2188 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx); 2189 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 2190 dev_attr->max_qp_wqes + 1); 2191 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 2192 qp_attr->cap.max_send_wr; 2193 /* 2194 * Reserving one slot for Phantom WQE. Some application can 2195 * post one extra entry in this case. Allowing this to avoid 2196 * unexpected Queue full condition 2197 */ 2198 qp->qplib_qp.sq.q_full_delta -= 1; 2199 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 2200 if (qp->qplib_qp.rq.max_wqe) { 2201 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx); 2202 qp->qplib_qp.rq.max_wqe = 2203 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 2204 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe; 2205 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 2206 qp_attr->cap.max_recv_wr; 2207 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 2208 } else { 2209 /* SRQ was used prior, just ignore the RQ caps */ 2210 } 2211 } 2212 if (qp_attr_mask & IB_QP_DEST_QPN) { 2213 qp->qplib_qp.modify_flags |= 2214 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 2215 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 2216 } 2217 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2218 if (rc) { 2219 ibdev_err(&rdev->ibdev, "Failed to modify HW QP"); 2220 return rc; 2221 } 2222 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 2223 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 2224 return rc; 2225 } 2226 2227 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2228 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 2229 { 2230 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2231 struct bnxt_re_dev *rdev = qp->rdev; 2232 struct bnxt_qplib_qp *qplib_qp; 2233 int rc; 2234 2235 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 2236 if (!qplib_qp) 2237 return -ENOMEM; 2238 2239 qplib_qp->id = qp->qplib_qp.id; 2240 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 2241 2242 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 2243 if (rc) { 2244 ibdev_err(&rdev->ibdev, "Failed to query HW QP"); 2245 goto out; 2246 } 2247 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 2248 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state); 2249 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 2250 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 2251 qp_attr->pkey_index = qplib_qp->pkey_index; 2252 qp_attr->qkey = qplib_qp->qkey; 2253 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2254 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 2255 qplib_qp->ah.host_sgid_index, 2256 qplib_qp->ah.hop_limit, 2257 qplib_qp->ah.traffic_class); 2258 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 2259 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 2260 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 2261 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 2262 qp_attr->timeout = qplib_qp->timeout; 2263 qp_attr->retry_cnt = qplib_qp->retry_cnt; 2264 qp_attr->rnr_retry = qplib_qp->rnr_retry; 2265 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 2266 qp_attr->rq_psn = qplib_qp->rq.psn; 2267 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 2268 qp_attr->sq_psn = qplib_qp->sq.psn; 2269 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 2270 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 2271 IB_SIGNAL_REQ_WR; 2272 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 2273 2274 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 2275 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 2276 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 2277 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 2278 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 2279 qp_init_attr->cap = qp_attr->cap; 2280 2281 out: 2282 kfree(qplib_qp); 2283 return rc; 2284 } 2285 2286 /* Routine for sending QP1 packets for RoCE V1 an V2 2287 */ 2288 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 2289 const struct ib_send_wr *wr, 2290 struct bnxt_qplib_swqe *wqe, 2291 int payload_size) 2292 { 2293 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 2294 ib_ah); 2295 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 2296 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 2297 struct bnxt_qplib_sge sge; 2298 u8 nw_type; 2299 u16 ether_type; 2300 union ib_gid dgid; 2301 bool is_eth = false; 2302 bool is_vlan = false; 2303 bool is_grh = false; 2304 bool is_udp = false; 2305 u8 ip_version = 0; 2306 u16 vlan_id = 0xFFFF; 2307 void *buf; 2308 int i, rc; 2309 2310 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 2311 2312 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 2313 if (rc) 2314 return rc; 2315 2316 /* Get network header type for this GID */ 2317 nw_type = rdma_gid_attr_network_type(sgid_attr); 2318 switch (nw_type) { 2319 case RDMA_NETWORK_IPV4: 2320 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 2321 break; 2322 case RDMA_NETWORK_IPV6: 2323 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 2324 break; 2325 default: 2326 nw_type = BNXT_RE_ROCE_V1_PACKET; 2327 break; 2328 } 2329 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 2330 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2331 if (is_udp) { 2332 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 2333 ip_version = 4; 2334 ether_type = ETH_P_IP; 2335 } else { 2336 ip_version = 6; 2337 ether_type = ETH_P_IPV6; 2338 } 2339 is_grh = false; 2340 } else { 2341 ether_type = ETH_P_IBOE; 2342 is_grh = true; 2343 } 2344 2345 is_eth = true; 2346 is_vlan = vlan_id && (vlan_id < 0x1000); 2347 2348 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 2349 ip_version, is_udp, 0, &qp->qp1_hdr); 2350 2351 /* ETH */ 2352 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 2353 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 2354 2355 /* For vlan, check the sgid for vlan existence */ 2356 2357 if (!is_vlan) { 2358 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 2359 } else { 2360 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 2361 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 2362 } 2363 2364 if (is_grh || (ip_version == 6)) { 2365 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 2366 sizeof(sgid_attr->gid)); 2367 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 2368 sizeof(sgid_attr->gid)); 2369 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 2370 } 2371 2372 if (ip_version == 4) { 2373 qp->qp1_hdr.ip4.tos = 0; 2374 qp->qp1_hdr.ip4.id = 0; 2375 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 2376 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 2377 2378 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 2379 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 2380 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 2381 } 2382 2383 if (is_udp) { 2384 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 2385 qp->qp1_hdr.udp.sport = htons(0x8CD1); 2386 qp->qp1_hdr.udp.csum = 0; 2387 } 2388 2389 /* BTH */ 2390 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 2391 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2392 qp->qp1_hdr.immediate_present = 1; 2393 } else { 2394 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2395 } 2396 if (wr->send_flags & IB_SEND_SOLICITED) 2397 qp->qp1_hdr.bth.solicited_event = 1; 2398 /* pad_count */ 2399 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 2400 2401 /* P_key for QP1 is for all members */ 2402 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 2403 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 2404 qp->qp1_hdr.bth.ack_req = 0; 2405 qp->send_psn++; 2406 qp->send_psn &= BTH_PSN_MASK; 2407 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 2408 /* DETH */ 2409 /* Use the priviledged Q_Key for QP1 */ 2410 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 2411 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2412 2413 /* Pack the QP1 to the transmit buffer */ 2414 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2415 if (buf) { 2416 ib_ud_header_pack(&qp->qp1_hdr, buf); 2417 for (i = wqe->num_sge; i; i--) { 2418 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2419 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2420 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2421 } 2422 2423 /* 2424 * Max Header buf size for IPV6 RoCE V2 is 86, 2425 * which is same as the QP1 SQ header buffer. 2426 * Header buf size for IPV4 RoCE V2 can be 66. 2427 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2428 * Subtract 20 bytes from QP1 SQ header buf size 2429 */ 2430 if (is_udp && ip_version == 4) 2431 sge.size -= 20; 2432 /* 2433 * Max Header buf size for RoCE V1 is 78. 2434 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2435 * Subtract 8 bytes from QP1 SQ header buf size 2436 */ 2437 if (!is_udp) 2438 sge.size -= 8; 2439 2440 /* Subtract 4 bytes for non vlan packets */ 2441 if (!is_vlan) 2442 sge.size -= 4; 2443 2444 wqe->sg_list[0].addr = sge.addr; 2445 wqe->sg_list[0].lkey = sge.lkey; 2446 wqe->sg_list[0].size = sge.size; 2447 wqe->num_sge++; 2448 2449 } else { 2450 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!"); 2451 rc = -ENOMEM; 2452 } 2453 return rc; 2454 } 2455 2456 /* For the MAD layer, it only provides the recv SGE the size of 2457 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2458 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2459 * receive packet (334 bytes) with no VLAN and then copy the GRH 2460 * and the MAD datagram out to the provided SGE. 2461 */ 2462 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2463 const struct ib_recv_wr *wr, 2464 struct bnxt_qplib_swqe *wqe, 2465 int payload_size) 2466 { 2467 struct bnxt_re_sqp_entries *sqp_entry; 2468 struct bnxt_qplib_sge ref, sge; 2469 struct bnxt_re_dev *rdev; 2470 u32 rq_prod_index; 2471 2472 rdev = qp->rdev; 2473 2474 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2475 2476 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2477 return -ENOMEM; 2478 2479 /* Create 1 SGE to receive the entire 2480 * ethernet packet 2481 */ 2482 /* Save the reference from ULP */ 2483 ref.addr = wqe->sg_list[0].addr; 2484 ref.lkey = wqe->sg_list[0].lkey; 2485 ref.size = wqe->sg_list[0].size; 2486 2487 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index]; 2488 2489 /* SGE 1 */ 2490 wqe->sg_list[0].addr = sge.addr; 2491 wqe->sg_list[0].lkey = sge.lkey; 2492 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2493 sge.size -= wqe->sg_list[0].size; 2494 2495 sqp_entry->sge.addr = ref.addr; 2496 sqp_entry->sge.lkey = ref.lkey; 2497 sqp_entry->sge.size = ref.size; 2498 /* Store the wrid for reporting completion */ 2499 sqp_entry->wrid = wqe->wr_id; 2500 /* change the wqe->wrid to table index */ 2501 wqe->wr_id = rq_prod_index; 2502 return 0; 2503 } 2504 2505 static int is_ud_qp(struct bnxt_re_qp *qp) 2506 { 2507 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2508 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2509 } 2510 2511 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2512 const struct ib_send_wr *wr, 2513 struct bnxt_qplib_swqe *wqe) 2514 { 2515 struct bnxt_re_ah *ah = NULL; 2516 2517 if (is_ud_qp(qp)) { 2518 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2519 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2520 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2521 wqe->send.avid = ah->qplib_ah.id; 2522 } 2523 switch (wr->opcode) { 2524 case IB_WR_SEND: 2525 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2526 break; 2527 case IB_WR_SEND_WITH_IMM: 2528 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2529 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data); 2530 break; 2531 case IB_WR_SEND_WITH_INV: 2532 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2533 wqe->send.inv_key = wr->ex.invalidate_rkey; 2534 break; 2535 default: 2536 return -EINVAL; 2537 } 2538 if (wr->send_flags & IB_SEND_SIGNALED) 2539 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2540 if (wr->send_flags & IB_SEND_FENCE) 2541 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2542 if (wr->send_flags & IB_SEND_SOLICITED) 2543 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2544 if (wr->send_flags & IB_SEND_INLINE) 2545 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2546 2547 return 0; 2548 } 2549 2550 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2551 struct bnxt_qplib_swqe *wqe) 2552 { 2553 switch (wr->opcode) { 2554 case IB_WR_RDMA_WRITE: 2555 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2556 break; 2557 case IB_WR_RDMA_WRITE_WITH_IMM: 2558 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2559 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data); 2560 break; 2561 case IB_WR_RDMA_READ: 2562 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2563 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2564 break; 2565 default: 2566 return -EINVAL; 2567 } 2568 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2569 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2570 if (wr->send_flags & IB_SEND_SIGNALED) 2571 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2572 if (wr->send_flags & IB_SEND_FENCE) 2573 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2574 if (wr->send_flags & IB_SEND_SOLICITED) 2575 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2576 if (wr->send_flags & IB_SEND_INLINE) 2577 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2578 2579 return 0; 2580 } 2581 2582 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2583 struct bnxt_qplib_swqe *wqe) 2584 { 2585 switch (wr->opcode) { 2586 case IB_WR_ATOMIC_CMP_AND_SWP: 2587 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2588 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2589 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2590 break; 2591 case IB_WR_ATOMIC_FETCH_AND_ADD: 2592 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2593 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2594 break; 2595 default: 2596 return -EINVAL; 2597 } 2598 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2599 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2600 if (wr->send_flags & IB_SEND_SIGNALED) 2601 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2602 if (wr->send_flags & IB_SEND_FENCE) 2603 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2604 if (wr->send_flags & IB_SEND_SOLICITED) 2605 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2606 return 0; 2607 } 2608 2609 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2610 struct bnxt_qplib_swqe *wqe) 2611 { 2612 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2613 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2614 2615 if (wr->send_flags & IB_SEND_SIGNALED) 2616 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2617 if (wr->send_flags & IB_SEND_SOLICITED) 2618 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2619 2620 return 0; 2621 } 2622 2623 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2624 struct bnxt_qplib_swqe *wqe) 2625 { 2626 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2627 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2628 int access = wr->access; 2629 2630 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2631 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2632 wqe->frmr.page_list = mr->pages; 2633 wqe->frmr.page_list_len = mr->npages; 2634 wqe->frmr.levels = qplib_frpl->hwq.level; 2635 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2636 2637 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2638 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2639 2640 if (access & IB_ACCESS_LOCAL_WRITE) 2641 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2642 if (access & IB_ACCESS_REMOTE_READ) 2643 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2644 if (access & IB_ACCESS_REMOTE_WRITE) 2645 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2646 if (access & IB_ACCESS_REMOTE_ATOMIC) 2647 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2648 if (access & IB_ACCESS_MW_BIND) 2649 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2650 2651 wqe->frmr.l_key = wr->key; 2652 wqe->frmr.length = wr->mr->length; 2653 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K); 2654 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K); 2655 wqe->frmr.va = wr->mr->iova; 2656 return 0; 2657 } 2658 2659 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2660 const struct ib_send_wr *wr, 2661 struct bnxt_qplib_swqe *wqe) 2662 { 2663 /* Copy the inline data to the data field */ 2664 u8 *in_data; 2665 u32 i, sge_len; 2666 void *sge_addr; 2667 2668 in_data = wqe->inline_data; 2669 for (i = 0; i < wr->num_sge; i++) { 2670 sge_addr = (void *)(unsigned long) 2671 wr->sg_list[i].addr; 2672 sge_len = wr->sg_list[i].length; 2673 2674 if ((sge_len + wqe->inline_len) > 2675 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2676 ibdev_err(&rdev->ibdev, 2677 "Inline data size requested > supported value"); 2678 return -EINVAL; 2679 } 2680 sge_len = wr->sg_list[i].length; 2681 2682 memcpy(in_data, sge_addr, sge_len); 2683 in_data += wr->sg_list[i].length; 2684 wqe->inline_len += wr->sg_list[i].length; 2685 } 2686 return wqe->inline_len; 2687 } 2688 2689 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2690 const struct ib_send_wr *wr, 2691 struct bnxt_qplib_swqe *wqe) 2692 { 2693 int payload_sz = 0; 2694 2695 if (wr->send_flags & IB_SEND_INLINE) 2696 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2697 else 2698 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2699 wqe->num_sge); 2700 2701 return payload_sz; 2702 } 2703 2704 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2705 { 2706 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2707 qp->ib_qp.qp_type == IB_QPT_GSI || 2708 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2709 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2710 int qp_attr_mask; 2711 struct ib_qp_attr qp_attr; 2712 2713 qp_attr_mask = IB_QP_STATE; 2714 qp_attr.qp_state = IB_QPS_RTS; 2715 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2716 qp->qplib_qp.wqe_cnt = 0; 2717 } 2718 } 2719 2720 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2721 struct bnxt_re_qp *qp, 2722 const struct ib_send_wr *wr) 2723 { 2724 int rc = 0, payload_sz = 0; 2725 unsigned long flags; 2726 2727 spin_lock_irqsave(&qp->sq_lock, flags); 2728 while (wr) { 2729 struct bnxt_qplib_swqe wqe = {}; 2730 2731 /* Common */ 2732 wqe.num_sge = wr->num_sge; 2733 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2734 ibdev_err(&rdev->ibdev, 2735 "Limit exceeded for Send SGEs"); 2736 rc = -EINVAL; 2737 goto bad; 2738 } 2739 2740 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2741 if (payload_sz < 0) { 2742 rc = -EINVAL; 2743 goto bad; 2744 } 2745 wqe.wr_id = wr->wr_id; 2746 2747 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2748 2749 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2750 if (!rc) 2751 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2752 bad: 2753 if (rc) { 2754 ibdev_err(&rdev->ibdev, 2755 "Post send failed opcode = %#x rc = %d", 2756 wr->opcode, rc); 2757 break; 2758 } 2759 wr = wr->next; 2760 } 2761 bnxt_qplib_post_send_db(&qp->qplib_qp); 2762 bnxt_ud_qp_hw_stall_workaround(qp); 2763 spin_unlock_irqrestore(&qp->sq_lock, flags); 2764 return rc; 2765 } 2766 2767 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe) 2768 { 2769 /* Need unconditional fence for non-wire memory opcode 2770 * to work as expected. 2771 */ 2772 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV || 2773 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR || 2774 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR || 2775 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW) 2776 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2777 } 2778 2779 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2780 const struct ib_send_wr **bad_wr) 2781 { 2782 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2783 struct bnxt_qplib_swqe wqe; 2784 int rc = 0, payload_sz = 0; 2785 unsigned long flags; 2786 2787 spin_lock_irqsave(&qp->sq_lock, flags); 2788 while (wr) { 2789 /* House keeping */ 2790 memset(&wqe, 0, sizeof(wqe)); 2791 2792 /* Common */ 2793 wqe.num_sge = wr->num_sge; 2794 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2795 ibdev_err(&qp->rdev->ibdev, 2796 "Limit exceeded for Send SGEs"); 2797 rc = -EINVAL; 2798 goto bad; 2799 } 2800 2801 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2802 if (payload_sz < 0) { 2803 rc = -EINVAL; 2804 goto bad; 2805 } 2806 wqe.wr_id = wr->wr_id; 2807 2808 switch (wr->opcode) { 2809 case IB_WR_SEND: 2810 case IB_WR_SEND_WITH_IMM: 2811 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2812 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2813 payload_sz); 2814 if (rc) 2815 goto bad; 2816 wqe.rawqp1.lflags |= 2817 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2818 } 2819 switch (wr->send_flags) { 2820 case IB_SEND_IP_CSUM: 2821 wqe.rawqp1.lflags |= 2822 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2823 break; 2824 default: 2825 break; 2826 } 2827 fallthrough; 2828 case IB_WR_SEND_WITH_INV: 2829 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2830 break; 2831 case IB_WR_RDMA_WRITE: 2832 case IB_WR_RDMA_WRITE_WITH_IMM: 2833 case IB_WR_RDMA_READ: 2834 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2835 break; 2836 case IB_WR_ATOMIC_CMP_AND_SWP: 2837 case IB_WR_ATOMIC_FETCH_AND_ADD: 2838 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2839 break; 2840 case IB_WR_RDMA_READ_WITH_INV: 2841 ibdev_err(&qp->rdev->ibdev, 2842 "RDMA Read with Invalidate is not supported"); 2843 rc = -EINVAL; 2844 goto bad; 2845 case IB_WR_LOCAL_INV: 2846 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2847 break; 2848 case IB_WR_REG_MR: 2849 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2850 break; 2851 default: 2852 /* Unsupported WRs */ 2853 ibdev_err(&qp->rdev->ibdev, 2854 "WR (%#x) is not supported", wr->opcode); 2855 rc = -EINVAL; 2856 goto bad; 2857 } 2858 if (!rc) { 2859 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2860 bnxt_re_legacy_set_uc_fence(&wqe); 2861 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2862 } 2863 bad: 2864 if (rc) { 2865 ibdev_err(&qp->rdev->ibdev, 2866 "post_send failed op:%#x qps = %#x rc = %d\n", 2867 wr->opcode, qp->qplib_qp.state, rc); 2868 *bad_wr = wr; 2869 break; 2870 } 2871 wr = wr->next; 2872 } 2873 bnxt_qplib_post_send_db(&qp->qplib_qp); 2874 bnxt_ud_qp_hw_stall_workaround(qp); 2875 spin_unlock_irqrestore(&qp->sq_lock, flags); 2876 2877 return rc; 2878 } 2879 2880 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2881 struct bnxt_re_qp *qp, 2882 const struct ib_recv_wr *wr) 2883 { 2884 struct bnxt_qplib_swqe wqe; 2885 int rc = 0; 2886 2887 while (wr) { 2888 /* House keeping */ 2889 memset(&wqe, 0, sizeof(wqe)); 2890 2891 /* Common */ 2892 wqe.num_sge = wr->num_sge; 2893 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2894 ibdev_err(&rdev->ibdev, 2895 "Limit exceeded for Receive SGEs"); 2896 rc = -EINVAL; 2897 break; 2898 } 2899 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2900 wqe.wr_id = wr->wr_id; 2901 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2902 2903 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2904 if (rc) 2905 break; 2906 2907 wr = wr->next; 2908 } 2909 if (!rc) 2910 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2911 return rc; 2912 } 2913 2914 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2915 const struct ib_recv_wr **bad_wr) 2916 { 2917 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2918 struct bnxt_qplib_swqe wqe; 2919 int rc = 0, payload_sz = 0; 2920 unsigned long flags; 2921 u32 count = 0; 2922 2923 spin_lock_irqsave(&qp->rq_lock, flags); 2924 while (wr) { 2925 /* House keeping */ 2926 memset(&wqe, 0, sizeof(wqe)); 2927 2928 /* Common */ 2929 wqe.num_sge = wr->num_sge; 2930 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2931 ibdev_err(&qp->rdev->ibdev, 2932 "Limit exceeded for Receive SGEs"); 2933 rc = -EINVAL; 2934 *bad_wr = wr; 2935 break; 2936 } 2937 2938 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2939 wr->num_sge); 2940 wqe.wr_id = wr->wr_id; 2941 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2942 2943 if (ib_qp->qp_type == IB_QPT_GSI && 2944 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 2945 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2946 payload_sz); 2947 if (!rc) 2948 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2949 if (rc) { 2950 *bad_wr = wr; 2951 break; 2952 } 2953 2954 /* Ring DB if the RQEs posted reaches a threshold value */ 2955 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2956 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2957 count = 0; 2958 } 2959 2960 wr = wr->next; 2961 } 2962 2963 if (count) 2964 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2965 2966 spin_unlock_irqrestore(&qp->rq_lock, flags); 2967 2968 return rc; 2969 } 2970 2971 /* Completion Queues */ 2972 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 2973 { 2974 struct bnxt_qplib_chip_ctx *cctx; 2975 struct bnxt_qplib_nq *nq; 2976 struct bnxt_re_dev *rdev; 2977 struct bnxt_re_cq *cq; 2978 2979 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2980 rdev = cq->rdev; 2981 nq = cq->qplib_cq.nq; 2982 cctx = rdev->chip_ctx; 2983 2984 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 2985 free_page((unsigned long)cq->uctx_cq_page); 2986 hash_del(&cq->hash_entry); 2987 } 2988 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2989 ib_umem_release(cq->umem); 2990 2991 atomic_dec(&rdev->stats.res.cq_count); 2992 nq->budget--; 2993 kfree(cq->cql); 2994 return 0; 2995 } 2996 2997 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 2998 struct uverbs_attr_bundle *attrs) 2999 { 3000 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3001 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 3002 struct ib_udata *udata = &attrs->driver_udata; 3003 struct bnxt_re_ucontext *uctx = 3004 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3005 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 3006 struct bnxt_qplib_chip_ctx *cctx; 3007 struct bnxt_qplib_nq *nq = NULL; 3008 unsigned int nq_alloc_cnt; 3009 int cqe = attr->cqe; 3010 int rc, entries; 3011 u32 active_cqs; 3012 3013 if (attr->flags) 3014 return -EOPNOTSUPP; 3015 3016 /* Validate CQ fields */ 3017 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3018 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded"); 3019 return -EINVAL; 3020 } 3021 3022 cq->rdev = rdev; 3023 cctx = rdev->chip_ctx; 3024 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 3025 3026 entries = bnxt_re_init_depth(cqe + 1, uctx); 3027 if (entries > dev_attr->max_cq_wqes + 1) 3028 entries = dev_attr->max_cq_wqes + 1; 3029 3030 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3031 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3032 if (udata) { 3033 struct bnxt_re_cq_req req; 3034 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3035 rc = -EFAULT; 3036 goto fail; 3037 } 3038 3039 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3040 entries * sizeof(struct cq_base), 3041 IB_ACCESS_LOCAL_WRITE); 3042 if (IS_ERR(cq->umem)) { 3043 rc = PTR_ERR(cq->umem); 3044 goto fail; 3045 } 3046 cq->qplib_cq.sg_info.umem = cq->umem; 3047 cq->qplib_cq.dpi = &uctx->dpi; 3048 } else { 3049 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 3050 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 3051 GFP_KERNEL); 3052 if (!cq->cql) { 3053 rc = -ENOMEM; 3054 goto fail; 3055 } 3056 3057 cq->qplib_cq.dpi = &rdev->dpi_privileged; 3058 } 3059 /* 3060 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 3061 * used for getting the NQ index. 3062 */ 3063 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 3064 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 3065 cq->qplib_cq.max_wqe = entries; 3066 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 3067 cq->qplib_cq.nq = nq; 3068 3069 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 3070 if (rc) { 3071 ibdev_err(&rdev->ibdev, "Failed to create HW CQ"); 3072 goto fail; 3073 } 3074 3075 cq->ib_cq.cqe = entries; 3076 cq->cq_period = cq->qplib_cq.period; 3077 nq->budget++; 3078 3079 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count); 3080 if (active_cqs > rdev->stats.res.cq_watermark) 3081 rdev->stats.res.cq_watermark = active_cqs; 3082 spin_lock_init(&cq->cq_lock); 3083 3084 if (udata) { 3085 struct bnxt_re_cq_resp resp = {}; 3086 3087 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 3088 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id); 3089 /* Allocate a page */ 3090 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL); 3091 if (!cq->uctx_cq_page) { 3092 rc = -ENOMEM; 3093 goto c2fail; 3094 } 3095 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT; 3096 } 3097 resp.cqid = cq->qplib_cq.id; 3098 resp.tail = cq->qplib_cq.hwq.cons; 3099 resp.phase = cq->qplib_cq.period; 3100 resp.rsvd = 0; 3101 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 3102 if (rc) { 3103 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata"); 3104 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3105 goto free_mem; 3106 } 3107 } 3108 3109 return 0; 3110 3111 free_mem: 3112 free_page((unsigned long)cq->uctx_cq_page); 3113 c2fail: 3114 ib_umem_release(cq->umem); 3115 fail: 3116 kfree(cq->cql); 3117 return rc; 3118 } 3119 3120 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq) 3121 { 3122 struct bnxt_re_dev *rdev = cq->rdev; 3123 3124 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq); 3125 3126 cq->qplib_cq.max_wqe = cq->resize_cqe; 3127 if (cq->resize_umem) { 3128 ib_umem_release(cq->umem); 3129 cq->umem = cq->resize_umem; 3130 cq->resize_umem = NULL; 3131 cq->resize_cqe = 0; 3132 } 3133 } 3134 3135 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata) 3136 { 3137 struct bnxt_qplib_sg_info sg_info = {}; 3138 struct bnxt_qplib_dpi *orig_dpi = NULL; 3139 struct bnxt_qplib_dev_attr *dev_attr; 3140 struct bnxt_re_ucontext *uctx = NULL; 3141 struct bnxt_re_resize_cq_req req; 3142 struct bnxt_re_dev *rdev; 3143 struct bnxt_re_cq *cq; 3144 int rc, entries; 3145 3146 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3147 rdev = cq->rdev; 3148 dev_attr = &rdev->dev_attr; 3149 if (!ibcq->uobject) { 3150 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported"); 3151 return -EOPNOTSUPP; 3152 } 3153 3154 if (cq->resize_umem) { 3155 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy", 3156 cq->qplib_cq.id); 3157 return -EBUSY; 3158 } 3159 3160 /* Check the requested cq depth out of supported depth */ 3161 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3162 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d", 3163 cq->qplib_cq.id, cqe); 3164 return -EINVAL; 3165 } 3166 3167 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3168 entries = bnxt_re_init_depth(cqe + 1, uctx); 3169 if (entries > dev_attr->max_cq_wqes + 1) 3170 entries = dev_attr->max_cq_wqes + 1; 3171 3172 /* uverbs consumer */ 3173 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3174 rc = -EFAULT; 3175 goto fail; 3176 } 3177 3178 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3179 entries * sizeof(struct cq_base), 3180 IB_ACCESS_LOCAL_WRITE); 3181 if (IS_ERR(cq->resize_umem)) { 3182 rc = PTR_ERR(cq->resize_umem); 3183 cq->resize_umem = NULL; 3184 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n", 3185 __func__, rc); 3186 goto fail; 3187 } 3188 cq->resize_cqe = entries; 3189 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info)); 3190 orig_dpi = cq->qplib_cq.dpi; 3191 3192 cq->qplib_cq.sg_info.umem = cq->resize_umem; 3193 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3194 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3195 cq->qplib_cq.dpi = &uctx->dpi; 3196 3197 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries); 3198 if (rc) { 3199 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!", 3200 cq->qplib_cq.id); 3201 goto fail; 3202 } 3203 3204 cq->ib_cq.cqe = cq->resize_cqe; 3205 atomic_inc(&rdev->stats.res.resize_count); 3206 3207 return 0; 3208 3209 fail: 3210 if (cq->resize_umem) { 3211 ib_umem_release(cq->resize_umem); 3212 cq->resize_umem = NULL; 3213 cq->resize_cqe = 0; 3214 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info)); 3215 cq->qplib_cq.dpi = orig_dpi; 3216 } 3217 return rc; 3218 } 3219 3220 static u8 __req_to_ib_wc_status(u8 qstatus) 3221 { 3222 switch (qstatus) { 3223 case CQ_REQ_STATUS_OK: 3224 return IB_WC_SUCCESS; 3225 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 3226 return IB_WC_BAD_RESP_ERR; 3227 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 3228 return IB_WC_LOC_LEN_ERR; 3229 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 3230 return IB_WC_LOC_QP_OP_ERR; 3231 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 3232 return IB_WC_LOC_PROT_ERR; 3233 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 3234 return IB_WC_GENERAL_ERR; 3235 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 3236 return IB_WC_REM_INV_REQ_ERR; 3237 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 3238 return IB_WC_REM_ACCESS_ERR; 3239 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 3240 return IB_WC_REM_OP_ERR; 3241 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 3242 return IB_WC_RNR_RETRY_EXC_ERR; 3243 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 3244 return IB_WC_RETRY_EXC_ERR; 3245 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 3246 return IB_WC_WR_FLUSH_ERR; 3247 default: 3248 return IB_WC_GENERAL_ERR; 3249 } 3250 return 0; 3251 } 3252 3253 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 3254 { 3255 switch (qstatus) { 3256 case CQ_RES_RAWETH_QP1_STATUS_OK: 3257 return IB_WC_SUCCESS; 3258 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 3259 return IB_WC_LOC_ACCESS_ERR; 3260 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 3261 return IB_WC_LOC_LEN_ERR; 3262 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 3263 return IB_WC_LOC_PROT_ERR; 3264 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 3265 return IB_WC_LOC_QP_OP_ERR; 3266 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 3267 return IB_WC_GENERAL_ERR; 3268 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 3269 return IB_WC_WR_FLUSH_ERR; 3270 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 3271 return IB_WC_WR_FLUSH_ERR; 3272 default: 3273 return IB_WC_GENERAL_ERR; 3274 } 3275 } 3276 3277 static u8 __rc_to_ib_wc_status(u8 qstatus) 3278 { 3279 switch (qstatus) { 3280 case CQ_RES_RC_STATUS_OK: 3281 return IB_WC_SUCCESS; 3282 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 3283 return IB_WC_LOC_ACCESS_ERR; 3284 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 3285 return IB_WC_LOC_LEN_ERR; 3286 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 3287 return IB_WC_LOC_PROT_ERR; 3288 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 3289 return IB_WC_LOC_QP_OP_ERR; 3290 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 3291 return IB_WC_GENERAL_ERR; 3292 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 3293 return IB_WC_REM_INV_REQ_ERR; 3294 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 3295 return IB_WC_WR_FLUSH_ERR; 3296 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 3297 return IB_WC_WR_FLUSH_ERR; 3298 default: 3299 return IB_WC_GENERAL_ERR; 3300 } 3301 } 3302 3303 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 3304 { 3305 switch (cqe->type) { 3306 case BNXT_QPLIB_SWQE_TYPE_SEND: 3307 wc->opcode = IB_WC_SEND; 3308 break; 3309 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 3310 wc->opcode = IB_WC_SEND; 3311 wc->wc_flags |= IB_WC_WITH_IMM; 3312 break; 3313 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 3314 wc->opcode = IB_WC_SEND; 3315 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3316 break; 3317 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 3318 wc->opcode = IB_WC_RDMA_WRITE; 3319 break; 3320 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 3321 wc->opcode = IB_WC_RDMA_WRITE; 3322 wc->wc_flags |= IB_WC_WITH_IMM; 3323 break; 3324 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 3325 wc->opcode = IB_WC_RDMA_READ; 3326 break; 3327 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 3328 wc->opcode = IB_WC_COMP_SWAP; 3329 break; 3330 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 3331 wc->opcode = IB_WC_FETCH_ADD; 3332 break; 3333 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 3334 wc->opcode = IB_WC_LOCAL_INV; 3335 break; 3336 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 3337 wc->opcode = IB_WC_REG_MR; 3338 break; 3339 default: 3340 wc->opcode = IB_WC_SEND; 3341 break; 3342 } 3343 3344 wc->status = __req_to_ib_wc_status(cqe->status); 3345 } 3346 3347 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 3348 u16 raweth_qp1_flags2) 3349 { 3350 bool is_ipv6 = false, is_ipv4 = false; 3351 3352 /* raweth_qp1_flags Bit 9-6 indicates itype */ 3353 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3354 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3355 return -1; 3356 3357 if (raweth_qp1_flags2 & 3358 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 3359 raweth_qp1_flags2 & 3360 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 3361 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 3362 (raweth_qp1_flags2 & 3363 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 3364 (is_ipv6 = true) : (is_ipv4 = true); 3365 return ((is_ipv6) ? 3366 BNXT_RE_ROCEV2_IPV6_PACKET : 3367 BNXT_RE_ROCEV2_IPV4_PACKET); 3368 } else { 3369 return BNXT_RE_ROCE_V1_PACKET; 3370 } 3371 } 3372 3373 static int bnxt_re_to_ib_nw_type(int nw_type) 3374 { 3375 u8 nw_hdr_type = 0xFF; 3376 3377 switch (nw_type) { 3378 case BNXT_RE_ROCE_V1_PACKET: 3379 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 3380 break; 3381 case BNXT_RE_ROCEV2_IPV4_PACKET: 3382 nw_hdr_type = RDMA_NETWORK_IPV4; 3383 break; 3384 case BNXT_RE_ROCEV2_IPV6_PACKET: 3385 nw_hdr_type = RDMA_NETWORK_IPV6; 3386 break; 3387 } 3388 return nw_hdr_type; 3389 } 3390 3391 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 3392 void *rq_hdr_buf) 3393 { 3394 u8 *tmp_buf = NULL; 3395 struct ethhdr *eth_hdr; 3396 u16 eth_type; 3397 bool rc = false; 3398 3399 tmp_buf = (u8 *)rq_hdr_buf; 3400 /* 3401 * If dest mac is not same as I/F mac, this could be a 3402 * loopback address or multicast address, check whether 3403 * it is a loopback packet 3404 */ 3405 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 3406 tmp_buf += 4; 3407 /* Check the ether type */ 3408 eth_hdr = (struct ethhdr *)tmp_buf; 3409 eth_type = ntohs(eth_hdr->h_proto); 3410 switch (eth_type) { 3411 case ETH_P_IBOE: 3412 rc = true; 3413 break; 3414 case ETH_P_IP: 3415 case ETH_P_IPV6: { 3416 u32 len; 3417 struct udphdr *udp_hdr; 3418 3419 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 3420 sizeof(struct ipv6hdr)); 3421 tmp_buf += sizeof(struct ethhdr) + len; 3422 udp_hdr = (struct udphdr *)tmp_buf; 3423 if (ntohs(udp_hdr->dest) == 3424 ROCE_V2_UDP_DPORT) 3425 rc = true; 3426 break; 3427 } 3428 default: 3429 break; 3430 } 3431 } 3432 3433 return rc; 3434 } 3435 3436 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp, 3437 struct bnxt_qplib_cqe *cqe) 3438 { 3439 struct bnxt_re_dev *rdev = gsi_qp->rdev; 3440 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3441 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp; 3442 dma_addr_t shrq_hdr_buf_map; 3443 struct ib_sge s_sge[2] = {}; 3444 struct ib_sge r_sge[2] = {}; 3445 struct bnxt_re_ah *gsi_sah; 3446 struct ib_recv_wr rwr = {}; 3447 dma_addr_t rq_hdr_buf_map; 3448 struct ib_ud_wr udwr = {}; 3449 struct ib_send_wr *swr; 3450 u32 skip_bytes = 0; 3451 int pkt_type = 0; 3452 void *rq_hdr_buf; 3453 u32 offset = 0; 3454 u32 tbl_idx; 3455 int rc; 3456 3457 swr = &udwr.wr; 3458 tbl_idx = cqe->wr_id; 3459 3460 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf + 3461 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size); 3462 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3463 tbl_idx); 3464 3465 /* Shadow QP header buffer */ 3466 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3467 tbl_idx); 3468 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3469 3470 /* Store this cqe */ 3471 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 3472 sqp_entry->qp1_qp = gsi_qp; 3473 3474 /* Find packet type from the cqe */ 3475 3476 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 3477 cqe->raweth_qp1_flags2); 3478 if (pkt_type < 0) { 3479 ibdev_err(&rdev->ibdev, "Invalid packet\n"); 3480 return -EINVAL; 3481 } 3482 3483 /* Adjust the offset for the user buffer and post in the rq */ 3484 3485 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 3486 offset = 20; 3487 3488 /* 3489 * QP1 loopback packet has 4 bytes of internal header before 3490 * ether header. Skip these four bytes. 3491 */ 3492 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 3493 skip_bytes = 4; 3494 3495 /* First send SGE . Skip the ether header*/ 3496 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 3497 + skip_bytes; 3498 s_sge[0].lkey = 0xFFFFFFFF; 3499 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 3500 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 3501 3502 /* Second Send SGE */ 3503 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 3504 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 3505 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 3506 s_sge[1].addr += 8; 3507 s_sge[1].lkey = 0xFFFFFFFF; 3508 s_sge[1].length = 256; 3509 3510 /* First recv SGE */ 3511 3512 r_sge[0].addr = shrq_hdr_buf_map; 3513 r_sge[0].lkey = 0xFFFFFFFF; 3514 r_sge[0].length = 40; 3515 3516 r_sge[1].addr = sqp_entry->sge.addr + offset; 3517 r_sge[1].lkey = sqp_entry->sge.lkey; 3518 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 3519 3520 /* Create receive work request */ 3521 rwr.num_sge = 2; 3522 rwr.sg_list = r_sge; 3523 rwr.wr_id = tbl_idx; 3524 rwr.next = NULL; 3525 3526 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr); 3527 if (rc) { 3528 ibdev_err(&rdev->ibdev, 3529 "Failed to post Rx buffers to shadow QP"); 3530 return -ENOMEM; 3531 } 3532 3533 swr->num_sge = 2; 3534 swr->sg_list = s_sge; 3535 swr->wr_id = tbl_idx; 3536 swr->opcode = IB_WR_SEND; 3537 swr->next = NULL; 3538 gsi_sah = rdev->gsi_ctx.gsi_sah; 3539 udwr.ah = &gsi_sah->ib_ah; 3540 udwr.remote_qpn = gsi_sqp->qplib_qp.id; 3541 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey; 3542 3543 /* post data received in the send queue */ 3544 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr); 3545 } 3546 3547 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 3548 struct bnxt_qplib_cqe *cqe) 3549 { 3550 wc->opcode = IB_WC_RECV; 3551 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 3552 wc->wc_flags |= IB_WC_GRH; 3553 } 3554 3555 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev, 3556 u16 vlan_id) 3557 { 3558 /* 3559 * Check if the vlan is configured in the host. If not configured, it 3560 * can be a transparent VLAN. So dont report the vlan id. 3561 */ 3562 if (!__vlan_find_dev_deep_rcu(rdev->netdev, 3563 htons(ETH_P_8021Q), vlan_id)) 3564 return false; 3565 return true; 3566 } 3567 3568 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 3569 u16 *vid, u8 *sl) 3570 { 3571 bool ret = false; 3572 u32 metadata; 3573 u16 tpid; 3574 3575 metadata = orig_cqe->raweth_qp1_metadata; 3576 if (orig_cqe->raweth_qp1_flags2 & 3577 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3578 tpid = ((metadata & 3579 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3580 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3581 if (tpid == ETH_P_8021Q) { 3582 *vid = metadata & 3583 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3584 *sl = (metadata & 3585 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3586 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3587 ret = true; 3588 } 3589 } 3590 3591 return ret; 3592 } 3593 3594 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3595 struct bnxt_qplib_cqe *cqe) 3596 { 3597 wc->opcode = IB_WC_RECV; 3598 wc->status = __rc_to_ib_wc_status(cqe->status); 3599 3600 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3601 wc->wc_flags |= IB_WC_WITH_IMM; 3602 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3603 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3604 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3605 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3606 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3607 } 3608 3609 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp, 3610 struct ib_wc *wc, 3611 struct bnxt_qplib_cqe *cqe) 3612 { 3613 struct bnxt_re_dev *rdev = gsi_sqp->rdev; 3614 struct bnxt_re_qp *gsi_qp = NULL; 3615 struct bnxt_qplib_cqe *orig_cqe = NULL; 3616 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3617 int nw_type; 3618 u32 tbl_idx; 3619 u16 vlan_id; 3620 u8 sl; 3621 3622 tbl_idx = cqe->wr_id; 3623 3624 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3625 gsi_qp = sqp_entry->qp1_qp; 3626 orig_cqe = &sqp_entry->cqe; 3627 3628 wc->wr_id = sqp_entry->wrid; 3629 wc->byte_len = orig_cqe->length; 3630 wc->qp = &gsi_qp->ib_qp; 3631 3632 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(orig_cqe->immdata)); 3633 wc->src_qp = orig_cqe->src_qp; 3634 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3635 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3636 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3637 wc->vlan_id = vlan_id; 3638 wc->sl = sl; 3639 wc->wc_flags |= IB_WC_WITH_VLAN; 3640 } 3641 } 3642 wc->port_num = 1; 3643 wc->vendor_err = orig_cqe->status; 3644 3645 wc->opcode = IB_WC_RECV; 3646 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3647 wc->wc_flags |= IB_WC_GRH; 3648 3649 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3650 orig_cqe->raweth_qp1_flags2); 3651 if (nw_type >= 0) { 3652 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3653 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3654 } 3655 } 3656 3657 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3658 struct ib_wc *wc, 3659 struct bnxt_qplib_cqe *cqe) 3660 { 3661 struct bnxt_re_dev *rdev; 3662 u16 vlan_id = 0; 3663 u8 nw_type; 3664 3665 rdev = qp->rdev; 3666 wc->opcode = IB_WC_RECV; 3667 wc->status = __rc_to_ib_wc_status(cqe->status); 3668 3669 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3670 wc->wc_flags |= IB_WC_WITH_IMM; 3671 /* report only on GSI QP for Thor */ 3672 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3673 wc->wc_flags |= IB_WC_GRH; 3674 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3675 wc->wc_flags |= IB_WC_WITH_SMAC; 3676 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3677 vlan_id = (cqe->cfa_meta & 0xFFF); 3678 } 3679 /* Mark only if vlan_id is non zero */ 3680 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3681 wc->vlan_id = vlan_id; 3682 wc->wc_flags |= IB_WC_WITH_VLAN; 3683 } 3684 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3685 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3686 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3687 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3688 } 3689 3690 } 3691 3692 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3693 { 3694 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3695 unsigned long flags; 3696 int rc; 3697 3698 spin_lock_irqsave(&qp->sq_lock, flags); 3699 3700 rc = bnxt_re_bind_fence_mw(lib_qp); 3701 if (!rc) { 3702 lib_qp->sq.phantom_wqe_cnt++; 3703 ibdev_dbg(&qp->rdev->ibdev, 3704 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3705 lib_qp->id, lib_qp->sq.hwq.prod, 3706 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3707 lib_qp->sq.phantom_wqe_cnt); 3708 } 3709 3710 spin_unlock_irqrestore(&qp->sq_lock, flags); 3711 return rc; 3712 } 3713 3714 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3715 { 3716 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3717 struct bnxt_re_qp *qp, *sh_qp; 3718 struct bnxt_qplib_cqe *cqe; 3719 int i, ncqe, budget; 3720 struct bnxt_qplib_q *sq; 3721 struct bnxt_qplib_qp *lib_qp; 3722 u32 tbl_idx; 3723 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3724 unsigned long flags; 3725 3726 /* User CQ; the only processing we do is to 3727 * complete any pending CQ resize operation. 3728 */ 3729 if (cq->umem) { 3730 if (cq->resize_umem) 3731 bnxt_re_resize_cq_complete(cq); 3732 return 0; 3733 } 3734 3735 spin_lock_irqsave(&cq->cq_lock, flags); 3736 budget = min_t(u32, num_entries, cq->max_cql); 3737 num_entries = budget; 3738 if (!cq->cql) { 3739 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use"); 3740 goto exit; 3741 } 3742 cqe = &cq->cql[0]; 3743 while (budget) { 3744 lib_qp = NULL; 3745 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3746 if (lib_qp) { 3747 sq = &lib_qp->sq; 3748 if (sq->send_phantom) { 3749 qp = container_of(lib_qp, 3750 struct bnxt_re_qp, qplib_qp); 3751 if (send_phantom_wqe(qp) == -ENOMEM) 3752 ibdev_err(&cq->rdev->ibdev, 3753 "Phantom failed! Scheduled to send again\n"); 3754 else 3755 sq->send_phantom = false; 3756 } 3757 } 3758 if (ncqe < budget) 3759 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3760 cqe + ncqe, 3761 budget - ncqe); 3762 3763 if (!ncqe) 3764 break; 3765 3766 for (i = 0; i < ncqe; i++, cqe++) { 3767 /* Transcribe each qplib_wqe back to ib_wc */ 3768 memset(wc, 0, sizeof(*wc)); 3769 3770 wc->wr_id = cqe->wr_id; 3771 wc->byte_len = cqe->length; 3772 qp = container_of 3773 ((struct bnxt_qplib_qp *) 3774 (unsigned long)(cqe->qp_handle), 3775 struct bnxt_re_qp, qplib_qp); 3776 wc->qp = &qp->ib_qp; 3777 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immdata)); 3778 wc->src_qp = cqe->src_qp; 3779 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3780 wc->port_num = 1; 3781 wc->vendor_err = cqe->status; 3782 3783 switch (cqe->opcode) { 3784 case CQ_BASE_CQE_TYPE_REQ: 3785 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3786 if (sh_qp && 3787 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3788 /* Handle this completion with 3789 * the stored completion 3790 */ 3791 memset(wc, 0, sizeof(*wc)); 3792 continue; 3793 } 3794 bnxt_re_process_req_wc(wc, cqe); 3795 break; 3796 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3797 if (!cqe->status) { 3798 int rc = 0; 3799 3800 rc = bnxt_re_process_raw_qp_pkt_rx 3801 (qp, cqe); 3802 if (!rc) { 3803 memset(wc, 0, sizeof(*wc)); 3804 continue; 3805 } 3806 cqe->status = -1; 3807 } 3808 /* Errors need not be looped back. 3809 * But change the wr_id to the one 3810 * stored in the table 3811 */ 3812 tbl_idx = cqe->wr_id; 3813 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3814 wc->wr_id = sqp_entry->wrid; 3815 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3816 break; 3817 case CQ_BASE_CQE_TYPE_RES_RC: 3818 bnxt_re_process_res_rc_wc(wc, cqe); 3819 break; 3820 case CQ_BASE_CQE_TYPE_RES_UD: 3821 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3822 if (sh_qp && 3823 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3824 /* Handle this completion with 3825 * the stored completion 3826 */ 3827 if (cqe->status) { 3828 continue; 3829 } else { 3830 bnxt_re_process_res_shadow_qp_wc 3831 (qp, wc, cqe); 3832 break; 3833 } 3834 } 3835 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3836 break; 3837 default: 3838 ibdev_err(&cq->rdev->ibdev, 3839 "POLL CQ : type 0x%x not handled", 3840 cqe->opcode); 3841 continue; 3842 } 3843 wc++; 3844 budget--; 3845 } 3846 } 3847 exit: 3848 spin_unlock_irqrestore(&cq->cq_lock, flags); 3849 return num_entries - budget; 3850 } 3851 3852 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3853 enum ib_cq_notify_flags ib_cqn_flags) 3854 { 3855 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3856 int type = 0, rc = 0; 3857 unsigned long flags; 3858 3859 spin_lock_irqsave(&cq->cq_lock, flags); 3860 /* Trigger on the very next completion */ 3861 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3862 type = DBC_DBC_TYPE_CQ_ARMALL; 3863 /* Trigger on the next solicited completion */ 3864 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3865 type = DBC_DBC_TYPE_CQ_ARMSE; 3866 3867 /* Poll to see if there are missed events */ 3868 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3869 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3870 rc = 1; 3871 goto exit; 3872 } 3873 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3874 3875 exit: 3876 spin_unlock_irqrestore(&cq->cq_lock, flags); 3877 return rc; 3878 } 3879 3880 /* Memory Regions */ 3881 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3882 { 3883 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3884 struct bnxt_re_dev *rdev = pd->rdev; 3885 struct bnxt_re_mr *mr; 3886 u32 active_mrs; 3887 int rc; 3888 3889 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3890 if (!mr) 3891 return ERR_PTR(-ENOMEM); 3892 3893 mr->rdev = rdev; 3894 mr->qplib_mr.pd = &pd->qplib_pd; 3895 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 3896 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3897 3898 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING) 3899 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr); 3900 3901 /* Allocate and register 0 as the address */ 3902 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3903 if (rc) 3904 goto fail; 3905 3906 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3907 mr->qplib_mr.total_size = -1; /* Infinte length */ 3908 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0, 3909 PAGE_SIZE); 3910 if (rc) 3911 goto fail_mr; 3912 3913 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3914 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3915 IB_ACCESS_REMOTE_ATOMIC)) 3916 mr->ib_mr.rkey = mr->ib_mr.lkey; 3917 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 3918 if (active_mrs > rdev->stats.res.mr_watermark) 3919 rdev->stats.res.mr_watermark = active_mrs; 3920 3921 return &mr->ib_mr; 3922 3923 fail_mr: 3924 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3925 fail: 3926 kfree(mr); 3927 return ERR_PTR(rc); 3928 } 3929 3930 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3931 { 3932 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3933 struct bnxt_re_dev *rdev = mr->rdev; 3934 int rc; 3935 3936 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3937 if (rc) { 3938 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc); 3939 return rc; 3940 } 3941 3942 if (mr->pages) { 3943 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3944 &mr->qplib_frpl); 3945 kfree(mr->pages); 3946 mr->npages = 0; 3947 mr->pages = NULL; 3948 } 3949 ib_umem_release(mr->ib_umem); 3950 3951 kfree(mr); 3952 atomic_dec(&rdev->stats.res.mr_count); 3953 return rc; 3954 } 3955 3956 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3957 { 3958 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3959 3960 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3961 return -ENOMEM; 3962 3963 mr->pages[mr->npages++] = addr; 3964 return 0; 3965 } 3966 3967 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3968 unsigned int *sg_offset) 3969 { 3970 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3971 3972 mr->npages = 0; 3973 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3974 } 3975 3976 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3977 u32 max_num_sg) 3978 { 3979 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3980 struct bnxt_re_dev *rdev = pd->rdev; 3981 struct bnxt_re_mr *mr = NULL; 3982 u32 active_mrs; 3983 int rc; 3984 3985 if (type != IB_MR_TYPE_MEM_REG) { 3986 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type); 3987 return ERR_PTR(-EINVAL); 3988 } 3989 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3990 return ERR_PTR(-EINVAL); 3991 3992 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3993 if (!mr) 3994 return ERR_PTR(-ENOMEM); 3995 3996 mr->rdev = rdev; 3997 mr->qplib_mr.pd = &pd->qplib_pd; 3998 mr->qplib_mr.access_flags = BNXT_QPLIB_FR_PMR; 3999 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 4000 4001 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4002 if (rc) 4003 goto bail; 4004 4005 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4006 mr->ib_mr.rkey = mr->ib_mr.lkey; 4007 4008 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 4009 if (!mr->pages) { 4010 rc = -ENOMEM; 4011 goto fail; 4012 } 4013 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 4014 &mr->qplib_frpl, max_num_sg); 4015 if (rc) { 4016 ibdev_err(&rdev->ibdev, 4017 "Failed to allocate HW FR page list"); 4018 goto fail_mr; 4019 } 4020 4021 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4022 if (active_mrs > rdev->stats.res.mr_watermark) 4023 rdev->stats.res.mr_watermark = active_mrs; 4024 return &mr->ib_mr; 4025 4026 fail_mr: 4027 kfree(mr->pages); 4028 fail: 4029 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4030 bail: 4031 kfree(mr); 4032 return ERR_PTR(rc); 4033 } 4034 4035 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 4036 struct ib_udata *udata) 4037 { 4038 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4039 struct bnxt_re_dev *rdev = pd->rdev; 4040 struct bnxt_re_mw *mw; 4041 u32 active_mws; 4042 int rc; 4043 4044 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 4045 if (!mw) 4046 return ERR_PTR(-ENOMEM); 4047 mw->rdev = rdev; 4048 mw->qplib_mw.pd = &pd->qplib_pd; 4049 4050 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 4051 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 4052 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 4053 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 4054 if (rc) { 4055 ibdev_err(&rdev->ibdev, "Allocate MW failed!"); 4056 goto fail; 4057 } 4058 mw->ib_mw.rkey = mw->qplib_mw.rkey; 4059 4060 active_mws = atomic_inc_return(&rdev->stats.res.mw_count); 4061 if (active_mws > rdev->stats.res.mw_watermark) 4062 rdev->stats.res.mw_watermark = active_mws; 4063 return &mw->ib_mw; 4064 4065 fail: 4066 kfree(mw); 4067 return ERR_PTR(rc); 4068 } 4069 4070 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 4071 { 4072 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 4073 struct bnxt_re_dev *rdev = mw->rdev; 4074 int rc; 4075 4076 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 4077 if (rc) { 4078 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc); 4079 return rc; 4080 } 4081 4082 kfree(mw); 4083 atomic_dec(&rdev->stats.res.mw_count); 4084 return rc; 4085 } 4086 4087 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr, 4088 int mr_access_flags, struct ib_umem *umem) 4089 { 4090 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4091 struct bnxt_re_dev *rdev = pd->rdev; 4092 unsigned long page_size; 4093 struct bnxt_re_mr *mr; 4094 int umem_pgs, rc; 4095 u32 active_mrs; 4096 4097 if (length > BNXT_RE_MAX_MR_SIZE) { 4098 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n", 4099 length, BNXT_RE_MAX_MR_SIZE); 4100 return ERR_PTR(-ENOMEM); 4101 } 4102 4103 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr); 4104 if (!page_size) { 4105 ibdev_err(&rdev->ibdev, "umem page size unsupported!"); 4106 return ERR_PTR(-EINVAL); 4107 } 4108 4109 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 4110 if (!mr) 4111 return ERR_PTR(-ENOMEM); 4112 4113 mr->rdev = rdev; 4114 mr->qplib_mr.pd = &pd->qplib_pd; 4115 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 4116 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 4117 4118 if (!_is_alloc_mr_unified(rdev->dev_attr.dev_cap_flags)) { 4119 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4120 if (rc) { 4121 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc); 4122 rc = -EIO; 4123 goto free_mr; 4124 } 4125 /* The fixed portion of the rkey is the same as the lkey */ 4126 mr->ib_mr.rkey = mr->qplib_mr.rkey; 4127 } else { 4128 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR; 4129 } 4130 mr->ib_umem = umem; 4131 mr->qplib_mr.va = virt_addr; 4132 mr->qplib_mr.total_size = length; 4133 4134 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING) 4135 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr); 4136 4137 umem_pgs = ib_umem_num_dma_blocks(umem, page_size); 4138 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem, 4139 umem_pgs, page_size); 4140 if (rc) { 4141 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc); 4142 rc = -EIO; 4143 goto free_mrw; 4144 } 4145 4146 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4147 mr->ib_mr.rkey = mr->qplib_mr.lkey; 4148 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4149 if (active_mrs > rdev->stats.res.mr_watermark) 4150 rdev->stats.res.mr_watermark = active_mrs; 4151 4152 return &mr->ib_mr; 4153 4154 free_mrw: 4155 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4156 free_mr: 4157 kfree(mr); 4158 return ERR_PTR(rc); 4159 } 4160 4161 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 4162 u64 virt_addr, int mr_access_flags, 4163 struct ib_udata *udata) 4164 { 4165 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4166 struct bnxt_re_dev *rdev = pd->rdev; 4167 struct ib_umem *umem; 4168 struct ib_mr *ib_mr; 4169 4170 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags); 4171 if (IS_ERR(umem)) 4172 return ERR_CAST(umem); 4173 4174 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4175 if (IS_ERR(ib_mr)) 4176 ib_umem_release(umem); 4177 return ib_mr; 4178 } 4179 4180 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start, 4181 u64 length, u64 virt_addr, int fd, 4182 int mr_access_flags, 4183 struct uverbs_attr_bundle *attrs) 4184 { 4185 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4186 struct bnxt_re_dev *rdev = pd->rdev; 4187 struct ib_umem_dmabuf *umem_dmabuf; 4188 struct ib_umem *umem; 4189 struct ib_mr *ib_mr; 4190 4191 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length, 4192 fd, mr_access_flags); 4193 if (IS_ERR(umem_dmabuf)) 4194 return ERR_CAST(umem_dmabuf); 4195 4196 umem = &umem_dmabuf->umem; 4197 4198 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4199 if (IS_ERR(ib_mr)) 4200 ib_umem_release(umem); 4201 return ib_mr; 4202 } 4203 4204 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 4205 { 4206 struct ib_device *ibdev = ctx->device; 4207 struct bnxt_re_ucontext *uctx = 4208 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 4209 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4210 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 4211 struct bnxt_re_user_mmap_entry *entry; 4212 struct bnxt_re_uctx_resp resp = {}; 4213 struct bnxt_re_uctx_req ureq = {}; 4214 u32 chip_met_rev_num = 0; 4215 int rc; 4216 4217 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver); 4218 4219 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 4220 ibdev_dbg(ibdev, " is different from the device %d ", 4221 BNXT_RE_ABI_VERSION); 4222 return -EPERM; 4223 } 4224 4225 uctx->rdev = rdev; 4226 4227 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 4228 if (!uctx->shpg) { 4229 rc = -ENOMEM; 4230 goto fail; 4231 } 4232 spin_lock_init(&uctx->sh_lock); 4233 4234 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 4235 chip_met_rev_num = rdev->chip_ctx->chip_num; 4236 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) << 4237 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 4238 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) << 4239 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 4240 resp.chip_id0 = chip_met_rev_num; 4241 /*Temp, Use xa_alloc instead */ 4242 resp.dev_id = rdev->en_dev->pdev->devfn; 4243 resp.max_qp = rdev->qplib_ctx.qpc_count; 4244 resp.pg_size = PAGE_SIZE; 4245 resp.cqe_sz = sizeof(struct cq_base); 4246 resp.max_cqd = dev_attr->max_cq_wqes; 4247 4248 if (rdev->chip_ctx->modes.db_push) 4249 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED; 4250 4251 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL); 4252 if (!entry) { 4253 rc = -ENOMEM; 4254 goto cfail; 4255 } 4256 uctx->shpage_mmap = &entry->rdma_entry; 4257 if (rdev->pacing.dbr_pacing) 4258 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED; 4259 4260 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 4261 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED; 4262 4263 if (udata->inlen >= sizeof(ureq)) { 4264 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))); 4265 if (rc) 4266 goto cfail; 4267 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) { 4268 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4269 uctx->cmask |= BNXT_RE_UCNTX_CAP_POW2_DISABLED; 4270 } 4271 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT) { 4272 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE; 4273 resp.mode = rdev->chip_ctx->modes.wqe_mode; 4274 if (resp.mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 4275 uctx->cmask |= BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED; 4276 } 4277 } 4278 4279 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 4280 if (rc) { 4281 ibdev_err(ibdev, "Failed to copy user context"); 4282 rc = -EFAULT; 4283 goto cfail; 4284 } 4285 4286 return 0; 4287 cfail: 4288 free_page((unsigned long)uctx->shpg); 4289 uctx->shpg = NULL; 4290 fail: 4291 return rc; 4292 } 4293 4294 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 4295 { 4296 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4297 struct bnxt_re_ucontext, 4298 ib_uctx); 4299 4300 struct bnxt_re_dev *rdev = uctx->rdev; 4301 4302 rdma_user_mmap_entry_remove(uctx->shpage_mmap); 4303 uctx->shpage_mmap = NULL; 4304 if (uctx->shpg) 4305 free_page((unsigned long)uctx->shpg); 4306 4307 if (uctx->dpi.dbr) { 4308 /* Free DPI only if this is the first PD allocated by the 4309 * application and mark the context dpi as NULL 4310 */ 4311 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi); 4312 uctx->dpi.dbr = NULL; 4313 } 4314 } 4315 4316 static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id) 4317 { 4318 struct bnxt_re_cq *cq = NULL, *tmp_cq; 4319 4320 hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) { 4321 if (tmp_cq->qplib_cq.id == cq_id) { 4322 cq = tmp_cq; 4323 break; 4324 } 4325 } 4326 return cq; 4327 } 4328 4329 static struct bnxt_re_srq *bnxt_re_search_for_srq(struct bnxt_re_dev *rdev, u32 srq_id) 4330 { 4331 struct bnxt_re_srq *srq = NULL, *tmp_srq; 4332 4333 hash_for_each_possible(rdev->srq_hash, tmp_srq, hash_entry, srq_id) { 4334 if (tmp_srq->qplib_srq.id == srq_id) { 4335 srq = tmp_srq; 4336 break; 4337 } 4338 } 4339 return srq; 4340 } 4341 4342 /* Helper function to mmap the virtual memory from user app */ 4343 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 4344 { 4345 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4346 struct bnxt_re_ucontext, 4347 ib_uctx); 4348 struct bnxt_re_user_mmap_entry *bnxt_entry; 4349 struct rdma_user_mmap_entry *rdma_entry; 4350 int ret = 0; 4351 u64 pfn; 4352 4353 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma); 4354 if (!rdma_entry) 4355 return -EINVAL; 4356 4357 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4358 rdma_entry); 4359 4360 switch (bnxt_entry->mmap_flag) { 4361 case BNXT_RE_MMAP_WC_DB: 4362 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4363 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4364 pgprot_writecombine(vma->vm_page_prot), 4365 rdma_entry); 4366 break; 4367 case BNXT_RE_MMAP_UC_DB: 4368 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4369 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4370 pgprot_noncached(vma->vm_page_prot), 4371 rdma_entry); 4372 break; 4373 case BNXT_RE_MMAP_SH_PAGE: 4374 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg)); 4375 break; 4376 case BNXT_RE_MMAP_DBR_BAR: 4377 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4378 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4379 pgprot_noncached(vma->vm_page_prot), 4380 rdma_entry); 4381 break; 4382 case BNXT_RE_MMAP_DBR_PAGE: 4383 case BNXT_RE_MMAP_TOGGLE_PAGE: 4384 /* Driver doesn't expect write access for user space */ 4385 if (vma->vm_flags & VM_WRITE) 4386 return -EFAULT; 4387 ret = vm_insert_page(vma, vma->vm_start, 4388 virt_to_page((void *)bnxt_entry->mem_offset)); 4389 break; 4390 default: 4391 ret = -EINVAL; 4392 break; 4393 } 4394 4395 rdma_user_mmap_entry_put(rdma_entry); 4396 return ret; 4397 } 4398 4399 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 4400 { 4401 struct bnxt_re_user_mmap_entry *bnxt_entry; 4402 4403 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4404 rdma_entry); 4405 4406 kfree(bnxt_entry); 4407 } 4408 4409 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs) 4410 { 4411 struct bnxt_re_ucontext *uctx; 4412 4413 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4414 bnxt_re_pacing_alert(uctx->rdev); 4415 return 0; 4416 } 4417 4418 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs) 4419 { 4420 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4421 enum bnxt_re_alloc_page_type alloc_type; 4422 struct bnxt_re_user_mmap_entry *entry; 4423 enum bnxt_re_mmap_flag mmap_flag; 4424 struct bnxt_qplib_chip_ctx *cctx; 4425 struct bnxt_re_ucontext *uctx; 4426 struct bnxt_re_dev *rdev; 4427 u64 mmap_offset; 4428 u32 length; 4429 u32 dpi; 4430 u64 addr; 4431 int err; 4432 4433 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4434 if (IS_ERR(uctx)) 4435 return PTR_ERR(uctx); 4436 4437 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE); 4438 if (err) 4439 return err; 4440 4441 rdev = uctx->rdev; 4442 cctx = rdev->chip_ctx; 4443 4444 switch (alloc_type) { 4445 case BNXT_RE_ALLOC_WC_PAGE: 4446 if (cctx->modes.db_push) { 4447 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi, 4448 uctx, BNXT_QPLIB_DPI_TYPE_WC)) 4449 return -ENOMEM; 4450 length = PAGE_SIZE; 4451 dpi = uctx->wcdpi.dpi; 4452 addr = (u64)uctx->wcdpi.umdbr; 4453 mmap_flag = BNXT_RE_MMAP_WC_DB; 4454 } else { 4455 return -EINVAL; 4456 } 4457 4458 break; 4459 case BNXT_RE_ALLOC_DBR_BAR_PAGE: 4460 length = PAGE_SIZE; 4461 addr = (u64)rdev->pacing.dbr_bar_addr; 4462 mmap_flag = BNXT_RE_MMAP_DBR_BAR; 4463 break; 4464 4465 case BNXT_RE_ALLOC_DBR_PAGE: 4466 length = PAGE_SIZE; 4467 addr = (u64)rdev->pacing.dbr_page; 4468 mmap_flag = BNXT_RE_MMAP_DBR_PAGE; 4469 break; 4470 4471 default: 4472 return -EOPNOTSUPP; 4473 } 4474 4475 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset); 4476 if (!entry) 4477 return -ENOMEM; 4478 4479 uobj->object = entry; 4480 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4481 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4482 &mmap_offset, sizeof(mmap_offset)); 4483 if (err) 4484 return err; 4485 4486 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4487 &length, sizeof(length)); 4488 if (err) 4489 return err; 4490 4491 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI, 4492 &dpi, sizeof(length)); 4493 if (err) 4494 return err; 4495 4496 return 0; 4497 } 4498 4499 static int alloc_page_obj_cleanup(struct ib_uobject *uobject, 4500 enum rdma_remove_reason why, 4501 struct uverbs_attr_bundle *attrs) 4502 { 4503 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4504 struct bnxt_re_ucontext *uctx = entry->uctx; 4505 4506 switch (entry->mmap_flag) { 4507 case BNXT_RE_MMAP_WC_DB: 4508 if (uctx && uctx->wcdpi.dbr) { 4509 struct bnxt_re_dev *rdev = uctx->rdev; 4510 4511 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi); 4512 uctx->wcdpi.dbr = NULL; 4513 } 4514 break; 4515 case BNXT_RE_MMAP_DBR_BAR: 4516 case BNXT_RE_MMAP_DBR_PAGE: 4517 break; 4518 default: 4519 goto exit; 4520 } 4521 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4522 exit: 4523 return 0; 4524 } 4525 4526 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE, 4527 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE, 4528 BNXT_RE_OBJECT_ALLOC_PAGE, 4529 UVERBS_ACCESS_NEW, 4530 UA_MANDATORY), 4531 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE, 4532 enum bnxt_re_alloc_page_type, 4533 UA_MANDATORY), 4534 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4535 UVERBS_ATTR_TYPE(u64), 4536 UA_MANDATORY), 4537 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4538 UVERBS_ATTR_TYPE(u32), 4539 UA_MANDATORY), 4540 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI, 4541 UVERBS_ATTR_TYPE(u32), 4542 UA_MANDATORY)); 4543 4544 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE, 4545 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE, 4546 BNXT_RE_OBJECT_ALLOC_PAGE, 4547 UVERBS_ACCESS_DESTROY, 4548 UA_MANDATORY)); 4549 4550 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE, 4551 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup), 4552 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE), 4553 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE)); 4554 4555 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV); 4556 4557 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV, 4558 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV)); 4559 4560 /* Toggle MEM */ 4561 static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs) 4562 { 4563 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4564 enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE; 4565 enum bnxt_re_get_toggle_mem_type res_type; 4566 struct bnxt_re_user_mmap_entry *entry; 4567 struct bnxt_re_ucontext *uctx; 4568 struct ib_ucontext *ib_uctx; 4569 struct bnxt_re_dev *rdev; 4570 struct bnxt_re_srq *srq; 4571 u32 length = PAGE_SIZE; 4572 struct bnxt_re_cq *cq; 4573 u64 mem_offset; 4574 u32 offset = 0; 4575 u64 addr = 0; 4576 u32 res_id; 4577 int err; 4578 4579 ib_uctx = ib_uverbs_get_ucontext(attrs); 4580 if (IS_ERR(ib_uctx)) 4581 return PTR_ERR(ib_uctx); 4582 4583 err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE); 4584 if (err) 4585 return err; 4586 4587 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx); 4588 rdev = uctx->rdev; 4589 err = uverbs_copy_from(&res_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID); 4590 if (err) 4591 return err; 4592 4593 switch (res_type) { 4594 case BNXT_RE_CQ_TOGGLE_MEM: 4595 cq = bnxt_re_search_for_cq(rdev, res_id); 4596 if (!cq) 4597 return -EINVAL; 4598 4599 addr = (u64)cq->uctx_cq_page; 4600 break; 4601 case BNXT_RE_SRQ_TOGGLE_MEM: 4602 srq = bnxt_re_search_for_srq(rdev, res_id); 4603 if (!srq) 4604 return -EINVAL; 4605 4606 addr = (u64)srq->uctx_srq_page; 4607 break; 4608 4609 default: 4610 return -EOPNOTSUPP; 4611 } 4612 4613 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset); 4614 if (!entry) 4615 return -ENOMEM; 4616 4617 uobj->object = entry; 4618 uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4619 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4620 &mem_offset, sizeof(mem_offset)); 4621 if (err) 4622 return err; 4623 4624 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4625 &length, sizeof(length)); 4626 if (err) 4627 return err; 4628 4629 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4630 &offset, sizeof(length)); 4631 if (err) 4632 return err; 4633 4634 return 0; 4635 } 4636 4637 static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject, 4638 enum rdma_remove_reason why, 4639 struct uverbs_attr_bundle *attrs) 4640 { 4641 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4642 4643 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4644 return 0; 4645 } 4646 4647 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM, 4648 UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE, 4649 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4650 UVERBS_ACCESS_NEW, 4651 UA_MANDATORY), 4652 UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE, 4653 enum bnxt_re_get_toggle_mem_type, 4654 UA_MANDATORY), 4655 UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID, 4656 UVERBS_ATTR_TYPE(u32), 4657 UA_MANDATORY), 4658 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4659 UVERBS_ATTR_TYPE(u64), 4660 UA_MANDATORY), 4661 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4662 UVERBS_ATTR_TYPE(u32), 4663 UA_MANDATORY), 4664 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4665 UVERBS_ATTR_TYPE(u32), 4666 UA_MANDATORY)); 4667 4668 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM, 4669 UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE, 4670 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4671 UVERBS_ACCESS_DESTROY, 4672 UA_MANDATORY)); 4673 4674 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4675 UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup), 4676 &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM), 4677 &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM)); 4678 4679 const struct uapi_definition bnxt_re_uapi_defs[] = { 4680 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE), 4681 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV), 4682 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM), 4683 {} 4684 }; 4685