1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 #include <net/addrconf.h> 45 46 #include <rdma/ib_verbs.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_umem.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_mad.h> 51 #include <rdma/ib_cache.h> 52 #include <rdma/uverbs_ioctl.h> 53 #include <linux/hashtable.h> 54 55 #include "bnxt_ulp.h" 56 57 #include "roce_hsi.h" 58 #include "qplib_res.h" 59 #include "qplib_sp.h" 60 #include "qplib_fp.h" 61 #include "qplib_rcfw.h" 62 63 #include "bnxt_re.h" 64 #include "ib_verbs.h" 65 66 #include <rdma/uverbs_types.h> 67 #include <rdma/uverbs_std_types.h> 68 69 #include <rdma/ib_user_ioctl_cmds.h> 70 71 #define UVERBS_MODULE_NAME bnxt_re 72 #include <rdma/uverbs_named_ioctl.h> 73 74 #include <rdma/bnxt_re-abi.h> 75 76 static int __from_ib_access_flags(int iflags) 77 { 78 int qflags = 0; 79 80 if (iflags & IB_ACCESS_LOCAL_WRITE) 81 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 82 if (iflags & IB_ACCESS_REMOTE_READ) 83 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 84 if (iflags & IB_ACCESS_REMOTE_WRITE) 85 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 86 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 87 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 88 if (iflags & IB_ACCESS_MW_BIND) 89 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 90 if (iflags & IB_ZERO_BASED) 91 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 92 if (iflags & IB_ACCESS_ON_DEMAND) 93 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 94 return qflags; 95 }; 96 97 static enum ib_access_flags __to_ib_access_flags(int qflags) 98 { 99 enum ib_access_flags iflags = 0; 100 101 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 102 iflags |= IB_ACCESS_LOCAL_WRITE; 103 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 104 iflags |= IB_ACCESS_REMOTE_WRITE; 105 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 106 iflags |= IB_ACCESS_REMOTE_READ; 107 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 108 iflags |= IB_ACCESS_REMOTE_ATOMIC; 109 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 110 iflags |= IB_ACCESS_MW_BIND; 111 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 112 iflags |= IB_ZERO_BASED; 113 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 114 iflags |= IB_ACCESS_ON_DEMAND; 115 return iflags; 116 }; 117 118 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 119 struct bnxt_qplib_sge *sg_list, int num) 120 { 121 int i, total = 0; 122 123 for (i = 0; i < num; i++) { 124 sg_list[i].addr = ib_sg_list[i].addr; 125 sg_list[i].lkey = ib_sg_list[i].lkey; 126 sg_list[i].size = ib_sg_list[i].length; 127 total += sg_list[i].size; 128 } 129 return total; 130 } 131 132 /* Device */ 133 int bnxt_re_query_device(struct ib_device *ibdev, 134 struct ib_device_attr *ib_attr, 135 struct ib_udata *udata) 136 { 137 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 138 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 139 140 memset(ib_attr, 0, sizeof(*ib_attr)); 141 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 142 min(sizeof(dev_attr->fw_ver), 143 sizeof(ib_attr->fw_ver))); 144 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid, 145 rdev->netdev->dev_addr); 146 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 147 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED; 148 149 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 150 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 151 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 152 ib_attr->max_qp = dev_attr->max_qp; 153 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 154 ib_attr->device_cap_flags = 155 IB_DEVICE_CURR_QP_STATE_MOD 156 | IB_DEVICE_RC_RNR_NAK_GEN 157 | IB_DEVICE_SHUTDOWN_PORT 158 | IB_DEVICE_SYS_IMAGE_GUID 159 | IB_DEVICE_RESIZE_MAX_WR 160 | IB_DEVICE_PORT_ACTIVE_EVENT 161 | IB_DEVICE_N_NOTIFY_CQ 162 | IB_DEVICE_MEM_WINDOW 163 | IB_DEVICE_MEM_WINDOW_TYPE_2B 164 | IB_DEVICE_MEM_MGT_EXTENSIONS; 165 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY; 166 ib_attr->max_send_sge = dev_attr->max_qp_sges; 167 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 168 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 169 ib_attr->max_cq = dev_attr->max_cq; 170 ib_attr->max_cqe = dev_attr->max_cq_wqes; 171 ib_attr->max_mr = dev_attr->max_mr; 172 ib_attr->max_pd = dev_attr->max_pd; 173 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 174 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 175 ib_attr->atomic_cap = IB_ATOMIC_NONE; 176 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 177 if (dev_attr->is_atomic) { 178 ib_attr->atomic_cap = IB_ATOMIC_GLOB; 179 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; 180 } 181 182 ib_attr->max_ee_rd_atom = 0; 183 ib_attr->max_res_rd_atom = 0; 184 ib_attr->max_ee_init_rd_atom = 0; 185 ib_attr->max_ee = 0; 186 ib_attr->max_rdd = 0; 187 ib_attr->max_mw = dev_attr->max_mw; 188 ib_attr->max_raw_ipv6_qp = 0; 189 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 190 ib_attr->max_mcast_grp = 0; 191 ib_attr->max_mcast_qp_attach = 0; 192 ib_attr->max_total_mcast_qp_attach = 0; 193 ib_attr->max_ah = dev_attr->max_ah; 194 195 ib_attr->max_srq = dev_attr->max_srq; 196 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 197 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 198 199 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 200 201 ib_attr->max_pkeys = 1; 202 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 203 return 0; 204 } 205 206 /* Port */ 207 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num, 208 struct ib_port_attr *port_attr) 209 { 210 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 211 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 212 int rc; 213 214 memset(port_attr, 0, sizeof(*port_attr)); 215 216 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 217 port_attr->state = IB_PORT_ACTIVE; 218 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 219 } else { 220 port_attr->state = IB_PORT_DOWN; 221 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 222 } 223 port_attr->max_mtu = IB_MTU_4096; 224 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 225 port_attr->gid_tbl_len = dev_attr->max_sgid; 226 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 227 IB_PORT_DEVICE_MGMT_SUP | 228 IB_PORT_VENDOR_CLASS_SUP; 229 port_attr->ip_gids = true; 230 231 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 232 port_attr->bad_pkey_cntr = 0; 233 port_attr->qkey_viol_cntr = 0; 234 port_attr->pkey_tbl_len = dev_attr->max_pkey; 235 port_attr->lid = 0; 236 port_attr->sm_lid = 0; 237 port_attr->lmc = 0; 238 port_attr->max_vl_num = 4; 239 port_attr->sm_sl = 0; 240 port_attr->subnet_timeout = 0; 241 port_attr->init_type_reply = 0; 242 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed, 243 &port_attr->active_width); 244 245 return rc; 246 } 247 248 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num, 249 struct ib_port_immutable *immutable) 250 { 251 struct ib_port_attr port_attr; 252 253 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 254 return -EINVAL; 255 256 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 257 immutable->gid_tbl_len = port_attr.gid_tbl_len; 258 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 259 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 260 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 261 return 0; 262 } 263 264 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 265 { 266 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 267 268 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 269 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 270 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 271 } 272 273 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num, 274 u16 index, u16 *pkey) 275 { 276 if (index > 0) 277 return -EINVAL; 278 279 *pkey = IB_DEFAULT_PKEY_FULL; 280 281 return 0; 282 } 283 284 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num, 285 int index, union ib_gid *gid) 286 { 287 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 288 int rc; 289 290 /* Ignore port_num */ 291 memset(gid, 0, sizeof(*gid)); 292 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 293 &rdev->qplib_res.sgid_tbl, index, 294 (struct bnxt_qplib_gid *)gid); 295 return rc; 296 } 297 298 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 299 { 300 int rc = 0; 301 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 302 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 303 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 304 struct bnxt_qplib_gid *gid_to_del; 305 u16 vlan_id = 0xFFFF; 306 307 /* Delete the entry from the hardware */ 308 ctx = *context; 309 if (!ctx) 310 return -EINVAL; 311 312 if (sgid_tbl && sgid_tbl->active) { 313 if (ctx->idx >= sgid_tbl->max) 314 return -EINVAL; 315 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 316 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 317 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 318 * or via the ib_unregister_device path. In the former case QP1 319 * may not be destroyed yet, in which case just return as FW 320 * needs that entry to be present and will fail it's deletion. 321 * We could get invoked again after QP1 is destroyed OR get an 322 * ADD_GID call with a different GID value for the same index 323 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 324 */ 325 if (ctx->idx == 0 && 326 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 327 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) { 328 ibdev_dbg(&rdev->ibdev, 329 "Trying to delete GID0 while QP1 is alive\n"); 330 return -EFAULT; 331 } 332 ctx->refcnt--; 333 if (!ctx->refcnt) { 334 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 335 vlan_id, true); 336 if (rc) { 337 ibdev_err(&rdev->ibdev, 338 "Failed to remove GID: %#x", rc); 339 } else { 340 ctx_tbl = sgid_tbl->ctx; 341 ctx_tbl[ctx->idx] = NULL; 342 kfree(ctx); 343 } 344 } 345 } else { 346 return -EINVAL; 347 } 348 return rc; 349 } 350 351 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 352 { 353 int rc; 354 u32 tbl_idx = 0; 355 u16 vlan_id = 0xFFFF; 356 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 357 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 358 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 359 360 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 361 if (rc) 362 return rc; 363 364 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 365 rdev->qplib_res.netdev->dev_addr, 366 vlan_id, true, &tbl_idx); 367 if (rc == -EALREADY) { 368 ctx_tbl = sgid_tbl->ctx; 369 ctx_tbl[tbl_idx]->refcnt++; 370 *context = ctx_tbl[tbl_idx]; 371 return 0; 372 } 373 374 if (rc < 0) { 375 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc); 376 return rc; 377 } 378 379 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 380 if (!ctx) 381 return -ENOMEM; 382 ctx_tbl = sgid_tbl->ctx; 383 ctx->idx = tbl_idx; 384 ctx->refcnt = 1; 385 ctx_tbl[tbl_idx] = ctx; 386 *context = ctx; 387 388 return rc; 389 } 390 391 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 392 u32 port_num) 393 { 394 return IB_LINK_LAYER_ETHERNET; 395 } 396 397 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 398 399 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 400 { 401 struct bnxt_re_fence_data *fence = &pd->fence; 402 struct ib_mr *ib_mr = &fence->mr->ib_mr; 403 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 404 405 memset(wqe, 0, sizeof(*wqe)); 406 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 407 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 408 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 409 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 410 wqe->bind.zero_based = false; 411 wqe->bind.parent_l_key = ib_mr->lkey; 412 wqe->bind.va = (u64)(unsigned long)fence->va; 413 wqe->bind.length = fence->size; 414 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 415 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 416 417 /* Save the initial rkey in fence structure for now; 418 * wqe->bind.r_key will be set at (re)bind time. 419 */ 420 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 421 } 422 423 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 424 { 425 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 426 qplib_qp); 427 struct ib_pd *ib_pd = qp->ib_qp.pd; 428 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 429 struct bnxt_re_fence_data *fence = &pd->fence; 430 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 431 struct bnxt_qplib_swqe wqe; 432 int rc; 433 434 memcpy(&wqe, fence_wqe, sizeof(wqe)); 435 wqe.bind.r_key = fence->bind_rkey; 436 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 437 438 ibdev_dbg(&qp->rdev->ibdev, 439 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 440 wqe.bind.r_key, qp->qplib_qp.id, pd); 441 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 442 if (rc) { 443 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n"); 444 return rc; 445 } 446 bnxt_qplib_post_send_db(&qp->qplib_qp); 447 448 return rc; 449 } 450 451 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 452 { 453 struct bnxt_re_fence_data *fence = &pd->fence; 454 struct bnxt_re_dev *rdev = pd->rdev; 455 struct device *dev = &rdev->en_dev->pdev->dev; 456 struct bnxt_re_mr *mr = fence->mr; 457 458 if (fence->mw) { 459 bnxt_re_dealloc_mw(fence->mw); 460 fence->mw = NULL; 461 } 462 if (mr) { 463 if (mr->ib_mr.rkey) 464 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 465 true); 466 if (mr->ib_mr.lkey) 467 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 468 kfree(mr); 469 fence->mr = NULL; 470 } 471 if (fence->dma_addr) { 472 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 473 DMA_BIDIRECTIONAL); 474 fence->dma_addr = 0; 475 } 476 } 477 478 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 479 { 480 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 481 struct bnxt_re_fence_data *fence = &pd->fence; 482 struct bnxt_re_dev *rdev = pd->rdev; 483 struct device *dev = &rdev->en_dev->pdev->dev; 484 struct bnxt_re_mr *mr = NULL; 485 dma_addr_t dma_addr = 0; 486 struct ib_mw *mw; 487 int rc; 488 489 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 490 DMA_BIDIRECTIONAL); 491 rc = dma_mapping_error(dev, dma_addr); 492 if (rc) { 493 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n"); 494 rc = -EIO; 495 fence->dma_addr = 0; 496 goto fail; 497 } 498 fence->dma_addr = dma_addr; 499 500 /* Allocate a MR */ 501 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 502 if (!mr) { 503 rc = -ENOMEM; 504 goto fail; 505 } 506 fence->mr = mr; 507 mr->rdev = rdev; 508 mr->qplib_mr.pd = &pd->qplib_pd; 509 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 510 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 511 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 512 if (rc) { 513 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); 514 goto fail; 515 } 516 517 /* Register MR */ 518 mr->ib_mr.lkey = mr->qplib_mr.lkey; 519 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 520 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 521 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 522 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE); 523 if (rc) { 524 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n"); 525 goto fail; 526 } 527 mr->ib_mr.rkey = mr->qplib_mr.rkey; 528 529 /* Create a fence MW only for kernel consumers */ 530 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 531 if (IS_ERR(mw)) { 532 ibdev_err(&rdev->ibdev, 533 "Failed to create fence-MW for PD: %p\n", pd); 534 rc = PTR_ERR(mw); 535 goto fail; 536 } 537 fence->mw = mw; 538 539 bnxt_re_create_fence_wqe(pd); 540 return 0; 541 542 fail: 543 bnxt_re_destroy_fence_mr(pd); 544 return rc; 545 } 546 547 static struct bnxt_re_user_mmap_entry* 548 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset, 549 enum bnxt_re_mmap_flag mmap_flag, u64 *offset) 550 { 551 struct bnxt_re_user_mmap_entry *entry; 552 int ret; 553 554 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 555 if (!entry) 556 return NULL; 557 558 entry->mem_offset = mem_offset; 559 entry->mmap_flag = mmap_flag; 560 entry->uctx = uctx; 561 562 switch (mmap_flag) { 563 case BNXT_RE_MMAP_SH_PAGE: 564 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx, 565 &entry->rdma_entry, PAGE_SIZE, 0); 566 break; 567 case BNXT_RE_MMAP_UC_DB: 568 case BNXT_RE_MMAP_WC_DB: 569 case BNXT_RE_MMAP_DBR_BAR: 570 case BNXT_RE_MMAP_DBR_PAGE: 571 case BNXT_RE_MMAP_TOGGLE_PAGE: 572 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx, 573 &entry->rdma_entry, PAGE_SIZE); 574 break; 575 default: 576 ret = -EINVAL; 577 break; 578 } 579 580 if (ret) { 581 kfree(entry); 582 return NULL; 583 } 584 if (offset) 585 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 586 587 return entry; 588 } 589 590 /* Protection Domains */ 591 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 592 { 593 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 594 struct bnxt_re_dev *rdev = pd->rdev; 595 596 if (udata) { 597 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 598 pd->pd_db_mmap = NULL; 599 } 600 601 bnxt_re_destroy_fence_mr(pd); 602 603 if (pd->qplib_pd.id) { 604 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res, 605 &rdev->qplib_res.pd_tbl, 606 &pd->qplib_pd)) 607 atomic_dec(&rdev->stats.res.pd_count); 608 } 609 return 0; 610 } 611 612 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 613 { 614 struct ib_device *ibdev = ibpd->device; 615 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 616 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 617 udata, struct bnxt_re_ucontext, ib_uctx); 618 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 619 struct bnxt_re_user_mmap_entry *entry = NULL; 620 u32 active_pds; 621 int rc = 0; 622 623 pd->rdev = rdev; 624 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) { 625 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD"); 626 rc = -ENOMEM; 627 goto fail; 628 } 629 630 if (udata) { 631 struct bnxt_re_pd_resp resp = {}; 632 633 if (!ucntx->dpi.dbr) { 634 /* Allocate DPI in alloc_pd to avoid failing of 635 * ibv_devinfo and family of application when DPIs 636 * are depleted. 637 */ 638 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, 639 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) { 640 rc = -ENOMEM; 641 goto dbfail; 642 } 643 } 644 645 resp.pdid = pd->qplib_pd.id; 646 /* Still allow mapping this DBR to the new user PD. */ 647 resp.dpi = ucntx->dpi.dpi; 648 649 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr, 650 BNXT_RE_MMAP_UC_DB, &resp.dbr); 651 652 if (!entry) { 653 rc = -ENOMEM; 654 goto dbfail; 655 } 656 657 pd->pd_db_mmap = &entry->rdma_entry; 658 659 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 660 if (rc) { 661 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 662 rc = -EFAULT; 663 goto dbfail; 664 } 665 } 666 667 if (!udata) 668 if (bnxt_re_create_fence_mr(pd)) 669 ibdev_warn(&rdev->ibdev, 670 "Failed to create Fence-MR\n"); 671 active_pds = atomic_inc_return(&rdev->stats.res.pd_count); 672 if (active_pds > rdev->stats.res.pd_watermark) 673 rdev->stats.res.pd_watermark = active_pds; 674 675 return 0; 676 dbfail: 677 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 678 &pd->qplib_pd); 679 fail: 680 return rc; 681 } 682 683 /* Address Handles */ 684 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 685 { 686 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 687 struct bnxt_re_dev *rdev = ah->rdev; 688 bool block = true; 689 int rc; 690 691 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE); 692 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block); 693 if (BNXT_RE_CHECK_RC(rc)) { 694 if (rc == -ETIMEDOUT) 695 rc = 0; 696 else 697 goto fail; 698 } 699 atomic_dec(&rdev->stats.res.ah_count); 700 fail: 701 return rc; 702 } 703 704 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 705 { 706 u8 nw_type; 707 708 switch (ntype) { 709 case RDMA_NETWORK_IPV4: 710 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 711 break; 712 case RDMA_NETWORK_IPV6: 713 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 714 break; 715 default: 716 nw_type = CMDQ_CREATE_AH_TYPE_V1; 717 break; 718 } 719 return nw_type; 720 } 721 722 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr, 723 struct ib_udata *udata) 724 { 725 struct ib_pd *ib_pd = ib_ah->pd; 726 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 727 struct rdma_ah_attr *ah_attr = init_attr->ah_attr; 728 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 729 struct bnxt_re_dev *rdev = pd->rdev; 730 const struct ib_gid_attr *sgid_attr; 731 struct bnxt_re_gid_ctx *ctx; 732 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 733 u32 active_ahs; 734 u8 nw_type; 735 int rc; 736 737 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 738 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set"); 739 return -EINVAL; 740 } 741 742 ah->rdev = rdev; 743 ah->qplib_ah.pd = &pd->qplib_pd; 744 745 /* Supply the configuration for the HW */ 746 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 747 sizeof(union ib_gid)); 748 sgid_attr = grh->sgid_attr; 749 /* Get the HW context of the GID. The reference 750 * of GID table entry is already taken by the caller. 751 */ 752 ctx = rdma_read_gid_hw_context(sgid_attr); 753 ah->qplib_ah.sgid_index = ctx->idx; 754 ah->qplib_ah.host_sgid_index = grh->sgid_index; 755 ah->qplib_ah.traffic_class = grh->traffic_class; 756 ah->qplib_ah.flow_label = grh->flow_label; 757 ah->qplib_ah.hop_limit = grh->hop_limit; 758 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 759 760 /* Get network header type for this GID */ 761 nw_type = rdma_gid_attr_network_type(sgid_attr); 762 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 763 764 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 765 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 766 !(init_attr->flags & 767 RDMA_CREATE_AH_SLEEPABLE)); 768 if (rc) { 769 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH"); 770 return rc; 771 } 772 773 /* Write AVID to shared page. */ 774 if (udata) { 775 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 776 udata, struct bnxt_re_ucontext, ib_uctx); 777 unsigned long flag; 778 u32 *wrptr; 779 780 spin_lock_irqsave(&uctx->sh_lock, flag); 781 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 782 *wrptr = ah->qplib_ah.id; 783 wmb(); /* make sure cache is updated. */ 784 spin_unlock_irqrestore(&uctx->sh_lock, flag); 785 } 786 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count); 787 if (active_ahs > rdev->stats.res.ah_watermark) 788 rdev->stats.res.ah_watermark = active_ahs; 789 790 return 0; 791 } 792 793 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 794 { 795 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 796 797 ah_attr->type = ib_ah->type; 798 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 799 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 800 rdma_ah_set_grh(ah_attr, NULL, 0, 801 ah->qplib_ah.host_sgid_index, 802 0, ah->qplib_ah.traffic_class); 803 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 804 rdma_ah_set_port_num(ah_attr, 1); 805 rdma_ah_set_static_rate(ah_attr, 0); 806 return 0; 807 } 808 809 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 810 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 811 { 812 unsigned long flags; 813 814 spin_lock_irqsave(&qp->scq->cq_lock, flags); 815 if (qp->rcq != qp->scq) 816 spin_lock(&qp->rcq->cq_lock); 817 else 818 __acquire(&qp->rcq->cq_lock); 819 820 return flags; 821 } 822 823 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 824 unsigned long flags) 825 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 826 { 827 if (qp->rcq != qp->scq) 828 spin_unlock(&qp->rcq->cq_lock); 829 else 830 __release(&qp->rcq->cq_lock); 831 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 832 } 833 834 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp) 835 { 836 struct bnxt_re_qp *gsi_sqp; 837 struct bnxt_re_ah *gsi_sah; 838 struct bnxt_re_dev *rdev; 839 int rc; 840 841 rdev = qp->rdev; 842 gsi_sqp = rdev->gsi_ctx.gsi_sqp; 843 gsi_sah = rdev->gsi_ctx.gsi_sah; 844 845 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n"); 846 bnxt_qplib_destroy_ah(&rdev->qplib_res, 847 &gsi_sah->qplib_ah, 848 true); 849 atomic_dec(&rdev->stats.res.ah_count); 850 bnxt_qplib_clean_qp(&qp->qplib_qp); 851 852 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n"); 853 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp); 854 if (rc) { 855 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed"); 856 goto fail; 857 } 858 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp); 859 860 /* remove from active qp list */ 861 mutex_lock(&rdev->qp_lock); 862 list_del(&gsi_sqp->list); 863 mutex_unlock(&rdev->qp_lock); 864 atomic_dec(&rdev->stats.res.qp_count); 865 866 kfree(rdev->gsi_ctx.sqp_tbl); 867 kfree(gsi_sah); 868 kfree(gsi_sqp); 869 rdev->gsi_ctx.gsi_sqp = NULL; 870 rdev->gsi_ctx.gsi_sah = NULL; 871 rdev->gsi_ctx.sqp_tbl = NULL; 872 873 return 0; 874 fail: 875 return rc; 876 } 877 878 /* Queue Pairs */ 879 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 880 { 881 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 882 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 883 struct bnxt_re_dev *rdev = qp->rdev; 884 struct bnxt_qplib_nq *scq_nq = NULL; 885 struct bnxt_qplib_nq *rcq_nq = NULL; 886 unsigned int flags; 887 int rc; 888 889 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 890 891 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 892 if (rc) { 893 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP"); 894 return rc; 895 } 896 897 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 898 flags = bnxt_re_lock_cqs(qp); 899 bnxt_qplib_clean_qp(&qp->qplib_qp); 900 bnxt_re_unlock_cqs(qp, flags); 901 } 902 903 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 904 905 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) { 906 rc = bnxt_re_destroy_gsi_sqp(qp); 907 if (rc) 908 return rc; 909 } 910 911 mutex_lock(&rdev->qp_lock); 912 list_del(&qp->list); 913 mutex_unlock(&rdev->qp_lock); 914 atomic_dec(&rdev->stats.res.qp_count); 915 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC) 916 atomic_dec(&rdev->stats.res.rc_qp_count); 917 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD) 918 atomic_dec(&rdev->stats.res.ud_qp_count); 919 920 ib_umem_release(qp->rumem); 921 ib_umem_release(qp->sumem); 922 923 /* Flush all the entries of notification queue associated with 924 * given qp. 925 */ 926 scq_nq = qplib_qp->scq->nq; 927 rcq_nq = qplib_qp->rcq->nq; 928 bnxt_re_synchronize_nq(scq_nq); 929 if (scq_nq != rcq_nq) 930 bnxt_re_synchronize_nq(rcq_nq); 931 932 return 0; 933 } 934 935 static u8 __from_ib_qp_type(enum ib_qp_type type) 936 { 937 switch (type) { 938 case IB_QPT_GSI: 939 return CMDQ_CREATE_QP1_TYPE_GSI; 940 case IB_QPT_RC: 941 return CMDQ_CREATE_QP_TYPE_RC; 942 case IB_QPT_UD: 943 return CMDQ_CREATE_QP_TYPE_UD; 944 default: 945 return IB_QPT_MAX; 946 } 947 } 948 949 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp, 950 int rsge, int max) 951 { 952 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 953 rsge = max; 954 return bnxt_re_get_rwqe_size(rsge); 955 } 956 957 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge) 958 { 959 u16 wqe_size, calc_ils; 960 961 wqe_size = bnxt_re_get_swqe_size(nsge); 962 if (ilsize) { 963 calc_ils = sizeof(struct sq_send_hdr) + ilsize; 964 wqe_size = max_t(u16, calc_ils, wqe_size); 965 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr)); 966 } 967 return wqe_size; 968 } 969 970 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp, 971 struct ib_qp_init_attr *init_attr) 972 { 973 struct bnxt_qplib_dev_attr *dev_attr; 974 struct bnxt_qplib_qp *qplqp; 975 struct bnxt_re_dev *rdev; 976 struct bnxt_qplib_q *sq; 977 int align, ilsize; 978 979 rdev = qp->rdev; 980 qplqp = &qp->qplib_qp; 981 sq = &qplqp->sq; 982 dev_attr = &rdev->dev_attr; 983 984 align = sizeof(struct sq_send_hdr); 985 ilsize = ALIGN(init_attr->cap.max_inline_data, align); 986 987 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge); 988 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges)) 989 return -EINVAL; 990 /* For gen p4 and gen p5 backward compatibility mode 991 * wqe size is fixed to 128 bytes 992 */ 993 if (sq->wqe_size < bnxt_re_get_swqe_size(dev_attr->max_qp_sges) && 994 qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 995 sq->wqe_size = bnxt_re_get_swqe_size(dev_attr->max_qp_sges); 996 997 if (init_attr->cap.max_inline_data) { 998 qplqp->max_inline_data = sq->wqe_size - 999 sizeof(struct sq_send_hdr); 1000 init_attr->cap.max_inline_data = qplqp->max_inline_data; 1001 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 1002 sq->max_sge = qplqp->max_inline_data / 1003 sizeof(struct sq_sge); 1004 } 1005 1006 return 0; 1007 } 1008 1009 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 1010 struct bnxt_re_qp *qp, struct ib_udata *udata) 1011 { 1012 struct bnxt_qplib_qp *qplib_qp; 1013 struct bnxt_re_ucontext *cntx; 1014 struct bnxt_re_qp_req ureq; 1015 int bytes = 0, psn_sz; 1016 struct ib_umem *umem; 1017 int psn_nume; 1018 1019 qplib_qp = &qp->qplib_qp; 1020 cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, 1021 ib_uctx); 1022 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1023 return -EFAULT; 1024 1025 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size); 1026 /* Consider mapping PSN search memory only for RC QPs. */ 1027 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 1028 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 1029 sizeof(struct sq_psn_search_ext) : 1030 sizeof(struct sq_psn_search); 1031 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 1032 qplib_qp->sq.max_wqe : 1033 ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) / 1034 sizeof(struct bnxt_qplib_sge)); 1035 bytes += (psn_nume * psn_sz); 1036 } 1037 1038 bytes = PAGE_ALIGN(bytes); 1039 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes, 1040 IB_ACCESS_LOCAL_WRITE); 1041 if (IS_ERR(umem)) 1042 return PTR_ERR(umem); 1043 1044 qp->sumem = umem; 1045 qplib_qp->sq.sg_info.umem = umem; 1046 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE; 1047 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT; 1048 qplib_qp->qp_handle = ureq.qp_handle; 1049 1050 if (!qp->qplib_qp.srq) { 1051 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size); 1052 bytes = PAGE_ALIGN(bytes); 1053 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes, 1054 IB_ACCESS_LOCAL_WRITE); 1055 if (IS_ERR(umem)) 1056 goto rqfail; 1057 qp->rumem = umem; 1058 qplib_qp->rq.sg_info.umem = umem; 1059 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE; 1060 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT; 1061 } 1062 1063 qplib_qp->dpi = &cntx->dpi; 1064 return 0; 1065 rqfail: 1066 ib_umem_release(qp->sumem); 1067 qp->sumem = NULL; 1068 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 1069 1070 return PTR_ERR(umem); 1071 } 1072 1073 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 1074 (struct bnxt_re_pd *pd, 1075 struct bnxt_qplib_res *qp1_res, 1076 struct bnxt_qplib_qp *qp1_qp) 1077 { 1078 struct bnxt_re_dev *rdev = pd->rdev; 1079 struct bnxt_re_ah *ah; 1080 union ib_gid sgid; 1081 int rc; 1082 1083 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 1084 if (!ah) 1085 return NULL; 1086 1087 ah->rdev = rdev; 1088 ah->qplib_ah.pd = &pd->qplib_pd; 1089 1090 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 1091 if (rc) 1092 goto fail; 1093 1094 /* supply the dgid data same as sgid */ 1095 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 1096 sizeof(union ib_gid)); 1097 ah->qplib_ah.sgid_index = 0; 1098 1099 ah->qplib_ah.traffic_class = 0; 1100 ah->qplib_ah.flow_label = 0; 1101 ah->qplib_ah.hop_limit = 1; 1102 ah->qplib_ah.sl = 0; 1103 /* Have DMAC same as SMAC */ 1104 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 1105 1106 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 1107 if (rc) { 1108 ibdev_err(&rdev->ibdev, 1109 "Failed to allocate HW AH for Shadow QP"); 1110 goto fail; 1111 } 1112 atomic_inc(&rdev->stats.res.ah_count); 1113 1114 return ah; 1115 1116 fail: 1117 kfree(ah); 1118 return NULL; 1119 } 1120 1121 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 1122 (struct bnxt_re_pd *pd, 1123 struct bnxt_qplib_res *qp1_res, 1124 struct bnxt_qplib_qp *qp1_qp) 1125 { 1126 struct bnxt_re_dev *rdev = pd->rdev; 1127 struct bnxt_re_qp *qp; 1128 int rc; 1129 1130 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1131 if (!qp) 1132 return NULL; 1133 1134 qp->rdev = rdev; 1135 1136 /* Initialize the shadow QP structure from the QP1 values */ 1137 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1138 1139 qp->qplib_qp.pd = &pd->qplib_pd; 1140 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1141 qp->qplib_qp.type = IB_QPT_UD; 1142 1143 qp->qplib_qp.max_inline_data = 0; 1144 qp->qplib_qp.sig_type = true; 1145 1146 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 1147 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6); 1148 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1149 qp->qplib_qp.sq.max_sge = 2; 1150 /* Q full delta can be 1 since it is internal QP */ 1151 qp->qplib_qp.sq.q_full_delta = 1; 1152 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE; 1153 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT; 1154 1155 qp->qplib_qp.scq = qp1_qp->scq; 1156 qp->qplib_qp.rcq = qp1_qp->rcq; 1157 1158 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6); 1159 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1160 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1161 /* Q full delta can be 1 since it is internal QP */ 1162 qp->qplib_qp.rq.q_full_delta = 1; 1163 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE; 1164 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT; 1165 1166 qp->qplib_qp.mtu = qp1_qp->mtu; 1167 1168 qp->qplib_qp.sq_hdr_buf_size = 0; 1169 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1170 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1171 1172 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1173 if (rc) 1174 goto fail; 1175 1176 spin_lock_init(&qp->sq_lock); 1177 INIT_LIST_HEAD(&qp->list); 1178 mutex_lock(&rdev->qp_lock); 1179 list_add_tail(&qp->list, &rdev->qp_list); 1180 atomic_inc(&rdev->stats.res.qp_count); 1181 mutex_unlock(&rdev->qp_lock); 1182 return qp; 1183 fail: 1184 kfree(qp); 1185 return NULL; 1186 } 1187 1188 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 1189 struct ib_qp_init_attr *init_attr, 1190 struct bnxt_re_ucontext *uctx) 1191 { 1192 struct bnxt_qplib_dev_attr *dev_attr; 1193 struct bnxt_qplib_qp *qplqp; 1194 struct bnxt_re_dev *rdev; 1195 struct bnxt_qplib_q *rq; 1196 int entries; 1197 1198 rdev = qp->rdev; 1199 qplqp = &qp->qplib_qp; 1200 rq = &qplqp->rq; 1201 dev_attr = &rdev->dev_attr; 1202 1203 if (init_attr->srq) { 1204 struct bnxt_re_srq *srq; 1205 1206 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq); 1207 qplqp->srq = &srq->qplib_srq; 1208 rq->max_wqe = 0; 1209 } else { 1210 rq->max_sge = init_attr->cap.max_recv_sge; 1211 if (rq->max_sge > dev_attr->max_qp_sges) 1212 rq->max_sge = dev_attr->max_qp_sges; 1213 init_attr->cap.max_recv_sge = rq->max_sge; 1214 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge, 1215 dev_attr->max_qp_sges); 1216 /* Allocate 1 more than what's provided so posting max doesn't 1217 * mean empty. 1218 */ 1219 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx); 1220 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1221 rq->q_full_delta = 0; 1222 rq->sg_info.pgsize = PAGE_SIZE; 1223 rq->sg_info.pgshft = PAGE_SHIFT; 1224 } 1225 1226 return 0; 1227 } 1228 1229 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 1230 { 1231 struct bnxt_qplib_dev_attr *dev_attr; 1232 struct bnxt_qplib_qp *qplqp; 1233 struct bnxt_re_dev *rdev; 1234 1235 rdev = qp->rdev; 1236 qplqp = &qp->qplib_qp; 1237 dev_attr = &rdev->dev_attr; 1238 1239 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1240 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1241 if (qplqp->rq.max_sge > dev_attr->max_qp_sges) 1242 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1243 qplqp->rq.max_sge = 6; 1244 } 1245 } 1246 1247 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 1248 struct ib_qp_init_attr *init_attr, 1249 struct bnxt_re_ucontext *uctx) 1250 { 1251 struct bnxt_qplib_dev_attr *dev_attr; 1252 struct bnxt_qplib_qp *qplqp; 1253 struct bnxt_re_dev *rdev; 1254 struct bnxt_qplib_q *sq; 1255 int entries; 1256 int diff; 1257 int rc; 1258 1259 rdev = qp->rdev; 1260 qplqp = &qp->qplib_qp; 1261 sq = &qplqp->sq; 1262 dev_attr = &rdev->dev_attr; 1263 1264 sq->max_sge = init_attr->cap.max_send_sge; 1265 if (sq->max_sge > dev_attr->max_qp_sges) { 1266 sq->max_sge = dev_attr->max_qp_sges; 1267 init_attr->cap.max_send_sge = sq->max_sge; 1268 } 1269 1270 rc = bnxt_re_setup_swqe_size(qp, init_attr); 1271 if (rc) 1272 return rc; 1273 1274 entries = init_attr->cap.max_send_wr; 1275 /* Allocate 128 + 1 more than what's provided */ 1276 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ? 1277 0 : BNXT_QPLIB_RESERVED_QP_WRS; 1278 entries = bnxt_re_init_depth(entries + diff + 1, uctx); 1279 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1); 1280 sq->q_full_delta = diff + 1; 1281 /* 1282 * Reserving one slot for Phantom WQE. Application can 1283 * post one extra entry in this case. But allowing this to avoid 1284 * unexpected Queue full condition 1285 */ 1286 qplqp->sq.q_full_delta -= 1; 1287 qplqp->sq.sg_info.pgsize = PAGE_SIZE; 1288 qplqp->sq.sg_info.pgshft = PAGE_SHIFT; 1289 1290 return 0; 1291 } 1292 1293 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 1294 struct ib_qp_init_attr *init_attr, 1295 struct bnxt_re_ucontext *uctx) 1296 { 1297 struct bnxt_qplib_dev_attr *dev_attr; 1298 struct bnxt_qplib_qp *qplqp; 1299 struct bnxt_re_dev *rdev; 1300 int entries; 1301 1302 rdev = qp->rdev; 1303 qplqp = &qp->qplib_qp; 1304 dev_attr = &rdev->dev_attr; 1305 1306 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1307 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx); 1308 qplqp->sq.max_wqe = min_t(u32, entries, 1309 dev_attr->max_qp_wqes + 1); 1310 qplqp->sq.q_full_delta = qplqp->sq.max_wqe - 1311 init_attr->cap.max_send_wr; 1312 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ 1313 if (qplqp->sq.max_sge > dev_attr->max_qp_sges) 1314 qplqp->sq.max_sge = dev_attr->max_qp_sges; 1315 } 1316 } 1317 1318 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 1319 struct ib_qp_init_attr *init_attr) 1320 { 1321 struct bnxt_qplib_chip_ctx *chip_ctx; 1322 int qptype; 1323 1324 chip_ctx = rdev->chip_ctx; 1325 1326 qptype = __from_ib_qp_type(init_attr->qp_type); 1327 if (qptype == IB_QPT_MAX) { 1328 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype); 1329 qptype = -EOPNOTSUPP; 1330 goto out; 1331 } 1332 1333 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) && 1334 init_attr->qp_type == IB_QPT_GSI) 1335 qptype = CMDQ_CREATE_QP_TYPE_GSI; 1336 out: 1337 return qptype; 1338 } 1339 1340 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1341 struct ib_qp_init_attr *init_attr, 1342 struct ib_udata *udata) 1343 { 1344 struct bnxt_qplib_dev_attr *dev_attr; 1345 struct bnxt_re_ucontext *uctx; 1346 struct bnxt_qplib_qp *qplqp; 1347 struct bnxt_re_dev *rdev; 1348 struct bnxt_re_cq *cq; 1349 int rc = 0, qptype; 1350 1351 rdev = qp->rdev; 1352 qplqp = &qp->qplib_qp; 1353 dev_attr = &rdev->dev_attr; 1354 1355 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1356 /* Setup misc params */ 1357 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); 1358 qplqp->pd = &pd->qplib_pd; 1359 qplqp->qp_handle = (u64)qplqp; 1360 qplqp->max_inline_data = init_attr->cap.max_inline_data; 1361 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR; 1362 qptype = bnxt_re_init_qp_type(rdev, init_attr); 1363 if (qptype < 0) { 1364 rc = qptype; 1365 goto out; 1366 } 1367 qplqp->type = (u8)qptype; 1368 qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode; 1369 1370 if (init_attr->qp_type == IB_QPT_RC) { 1371 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom; 1372 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1373 } 1374 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1375 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */ 1376 if (init_attr->create_flags) { 1377 ibdev_dbg(&rdev->ibdev, 1378 "QP create flags 0x%x not supported", 1379 init_attr->create_flags); 1380 return -EOPNOTSUPP; 1381 } 1382 1383 /* Setup CQs */ 1384 if (init_attr->send_cq) { 1385 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq); 1386 qplqp->scq = &cq->qplib_cq; 1387 qp->scq = cq; 1388 } 1389 1390 if (init_attr->recv_cq) { 1391 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq); 1392 qplqp->rcq = &cq->qplib_cq; 1393 qp->rcq = cq; 1394 } 1395 1396 /* Setup RQ/SRQ */ 1397 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx); 1398 if (rc) 1399 goto out; 1400 if (init_attr->qp_type == IB_QPT_GSI) 1401 bnxt_re_adjust_gsi_rq_attr(qp); 1402 1403 /* Setup SQ */ 1404 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx); 1405 if (rc) 1406 goto out; 1407 if (init_attr->qp_type == IB_QPT_GSI) 1408 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx); 1409 1410 if (udata) /* This will update DPI and qp_handle */ 1411 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1412 out: 1413 return rc; 1414 } 1415 1416 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp, 1417 struct bnxt_re_pd *pd) 1418 { 1419 struct bnxt_re_sqp_entries *sqp_tbl; 1420 struct bnxt_re_dev *rdev; 1421 struct bnxt_re_qp *sqp; 1422 struct bnxt_re_ah *sah; 1423 int rc = 0; 1424 1425 rdev = qp->rdev; 1426 /* Create a shadow QP to handle the QP1 traffic */ 1427 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl), 1428 GFP_KERNEL); 1429 if (!sqp_tbl) 1430 return -ENOMEM; 1431 rdev->gsi_ctx.sqp_tbl = sqp_tbl; 1432 1433 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp); 1434 if (!sqp) { 1435 rc = -ENODEV; 1436 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1"); 1437 goto out; 1438 } 1439 rdev->gsi_ctx.gsi_sqp = sqp; 1440 1441 sqp->rcq = qp->rcq; 1442 sqp->scq = qp->scq; 1443 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1444 &qp->qplib_qp); 1445 if (!sah) { 1446 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1447 &sqp->qplib_qp); 1448 rc = -ENODEV; 1449 ibdev_err(&rdev->ibdev, 1450 "Failed to create AH entry for ShadowQP"); 1451 goto out; 1452 } 1453 rdev->gsi_ctx.gsi_sah = sah; 1454 1455 return 0; 1456 out: 1457 kfree(sqp_tbl); 1458 return rc; 1459 } 1460 1461 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1462 struct ib_qp_init_attr *init_attr) 1463 { 1464 struct bnxt_re_dev *rdev; 1465 struct bnxt_qplib_qp *qplqp; 1466 int rc; 1467 1468 rdev = qp->rdev; 1469 qplqp = &qp->qplib_qp; 1470 1471 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1472 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1473 1474 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp); 1475 if (rc) { 1476 ibdev_err(&rdev->ibdev, "create HW QP1 failed!"); 1477 goto out; 1478 } 1479 1480 rc = bnxt_re_create_shadow_gsi(qp, pd); 1481 out: 1482 return rc; 1483 } 1484 1485 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev, 1486 struct ib_qp_init_attr *init_attr, 1487 struct bnxt_qplib_dev_attr *dev_attr) 1488 { 1489 bool rc = true; 1490 1491 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes || 1492 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes || 1493 init_attr->cap.max_send_sge > dev_attr->max_qp_sges || 1494 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges || 1495 init_attr->cap.max_inline_data > dev_attr->max_inline_data) { 1496 ibdev_err(&rdev->ibdev, 1497 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x", 1498 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes, 1499 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes, 1500 init_attr->cap.max_send_sge, dev_attr->max_qp_sges, 1501 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges, 1502 init_attr->cap.max_inline_data, 1503 dev_attr->max_inline_data); 1504 rc = false; 1505 } 1506 return rc; 1507 } 1508 1509 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr, 1510 struct ib_udata *udata) 1511 { 1512 struct ib_pd *ib_pd = ib_qp->pd; 1513 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1514 struct bnxt_re_dev *rdev = pd->rdev; 1515 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1516 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1517 u32 active_qps; 1518 int rc; 1519 1520 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr); 1521 if (!rc) { 1522 rc = -EINVAL; 1523 goto fail; 1524 } 1525 1526 qp->rdev = rdev; 1527 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata); 1528 if (rc) 1529 goto fail; 1530 1531 if (qp_init_attr->qp_type == IB_QPT_GSI && 1532 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) { 1533 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr); 1534 if (rc == -ENODEV) 1535 goto qp_destroy; 1536 if (rc) 1537 goto fail; 1538 } else { 1539 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1540 if (rc) { 1541 ibdev_err(&rdev->ibdev, "Failed to create HW QP"); 1542 goto free_umem; 1543 } 1544 if (udata) { 1545 struct bnxt_re_qp_resp resp; 1546 1547 resp.qpid = qp->qplib_qp.id; 1548 resp.rsvd = 0; 1549 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1550 if (rc) { 1551 ibdev_err(&rdev->ibdev, "Failed to copy QP udata"); 1552 goto qp_destroy; 1553 } 1554 } 1555 } 1556 1557 qp->ib_qp.qp_num = qp->qplib_qp.id; 1558 if (qp_init_attr->qp_type == IB_QPT_GSI) 1559 rdev->gsi_ctx.gsi_qp = qp; 1560 spin_lock_init(&qp->sq_lock); 1561 spin_lock_init(&qp->rq_lock); 1562 INIT_LIST_HEAD(&qp->list); 1563 mutex_lock(&rdev->qp_lock); 1564 list_add_tail(&qp->list, &rdev->qp_list); 1565 mutex_unlock(&rdev->qp_lock); 1566 active_qps = atomic_inc_return(&rdev->stats.res.qp_count); 1567 if (active_qps > rdev->stats.res.qp_watermark) 1568 rdev->stats.res.qp_watermark = active_qps; 1569 if (qp_init_attr->qp_type == IB_QPT_RC) { 1570 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count); 1571 if (active_qps > rdev->stats.res.rc_qp_watermark) 1572 rdev->stats.res.rc_qp_watermark = active_qps; 1573 } else if (qp_init_attr->qp_type == IB_QPT_UD) { 1574 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count); 1575 if (active_qps > rdev->stats.res.ud_qp_watermark) 1576 rdev->stats.res.ud_qp_watermark = active_qps; 1577 } 1578 1579 return 0; 1580 qp_destroy: 1581 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1582 free_umem: 1583 ib_umem_release(qp->rumem); 1584 ib_umem_release(qp->sumem); 1585 fail: 1586 return rc; 1587 } 1588 1589 static u8 __from_ib_qp_state(enum ib_qp_state state) 1590 { 1591 switch (state) { 1592 case IB_QPS_RESET: 1593 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1594 case IB_QPS_INIT: 1595 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1596 case IB_QPS_RTR: 1597 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1598 case IB_QPS_RTS: 1599 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1600 case IB_QPS_SQD: 1601 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1602 case IB_QPS_SQE: 1603 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1604 case IB_QPS_ERR: 1605 default: 1606 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1607 } 1608 } 1609 1610 static enum ib_qp_state __to_ib_qp_state(u8 state) 1611 { 1612 switch (state) { 1613 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1614 return IB_QPS_RESET; 1615 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1616 return IB_QPS_INIT; 1617 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1618 return IB_QPS_RTR; 1619 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1620 return IB_QPS_RTS; 1621 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1622 return IB_QPS_SQD; 1623 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1624 return IB_QPS_SQE; 1625 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1626 default: 1627 return IB_QPS_ERR; 1628 } 1629 } 1630 1631 static u32 __from_ib_mtu(enum ib_mtu mtu) 1632 { 1633 switch (mtu) { 1634 case IB_MTU_256: 1635 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1636 case IB_MTU_512: 1637 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1638 case IB_MTU_1024: 1639 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1640 case IB_MTU_2048: 1641 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1642 case IB_MTU_4096: 1643 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1644 default: 1645 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1646 } 1647 } 1648 1649 static enum ib_mtu __to_ib_mtu(u32 mtu) 1650 { 1651 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1652 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1653 return IB_MTU_256; 1654 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1655 return IB_MTU_512; 1656 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1657 return IB_MTU_1024; 1658 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1659 return IB_MTU_2048; 1660 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1661 return IB_MTU_4096; 1662 default: 1663 return IB_MTU_2048; 1664 } 1665 } 1666 1667 /* Shared Receive Queues */ 1668 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1669 { 1670 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1671 ib_srq); 1672 struct bnxt_re_dev *rdev = srq->rdev; 1673 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1674 struct bnxt_qplib_nq *nq = NULL; 1675 1676 if (qplib_srq->cq) 1677 nq = qplib_srq->cq->nq; 1678 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1679 ib_umem_release(srq->umem); 1680 atomic_dec(&rdev->stats.res.srq_count); 1681 if (nq) 1682 nq->budget--; 1683 return 0; 1684 } 1685 1686 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1687 struct bnxt_re_pd *pd, 1688 struct bnxt_re_srq *srq, 1689 struct ib_udata *udata) 1690 { 1691 struct bnxt_re_srq_req ureq; 1692 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1693 struct ib_umem *umem; 1694 int bytes = 0; 1695 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1696 udata, struct bnxt_re_ucontext, ib_uctx); 1697 1698 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1699 return -EFAULT; 1700 1701 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size); 1702 bytes = PAGE_ALIGN(bytes); 1703 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes, 1704 IB_ACCESS_LOCAL_WRITE); 1705 if (IS_ERR(umem)) 1706 return PTR_ERR(umem); 1707 1708 srq->umem = umem; 1709 qplib_srq->sg_info.umem = umem; 1710 qplib_srq->sg_info.pgsize = PAGE_SIZE; 1711 qplib_srq->sg_info.pgshft = PAGE_SHIFT; 1712 qplib_srq->srq_handle = ureq.srq_handle; 1713 qplib_srq->dpi = &cntx->dpi; 1714 1715 return 0; 1716 } 1717 1718 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1719 struct ib_srq_init_attr *srq_init_attr, 1720 struct ib_udata *udata) 1721 { 1722 struct bnxt_qplib_dev_attr *dev_attr; 1723 struct bnxt_qplib_nq *nq = NULL; 1724 struct bnxt_re_ucontext *uctx; 1725 struct bnxt_re_dev *rdev; 1726 struct bnxt_re_srq *srq; 1727 struct bnxt_re_pd *pd; 1728 struct ib_pd *ib_pd; 1729 u32 active_srqs; 1730 int rc, entries; 1731 1732 ib_pd = ib_srq->pd; 1733 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1734 rdev = pd->rdev; 1735 dev_attr = &rdev->dev_attr; 1736 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1737 1738 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1739 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded"); 1740 rc = -EINVAL; 1741 goto exit; 1742 } 1743 1744 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1745 rc = -EOPNOTSUPP; 1746 goto exit; 1747 } 1748 1749 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1750 srq->rdev = rdev; 1751 srq->qplib_srq.pd = &pd->qplib_pd; 1752 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1753 /* Allocate 1 more than what's provided so posting max doesn't 1754 * mean empty 1755 */ 1756 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx); 1757 if (entries > dev_attr->max_srq_wqes + 1) 1758 entries = dev_attr->max_srq_wqes + 1; 1759 srq->qplib_srq.max_wqe = entries; 1760 1761 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1762 /* 128 byte wqe size for SRQ . So use max sges */ 1763 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges); 1764 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1765 srq->srq_limit = srq_init_attr->attr.srq_limit; 1766 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1767 nq = &rdev->nq[0]; 1768 1769 if (udata) { 1770 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1771 if (rc) 1772 goto fail; 1773 } 1774 1775 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1776 if (rc) { 1777 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!"); 1778 goto fail; 1779 } 1780 1781 if (udata) { 1782 struct bnxt_re_srq_resp resp; 1783 1784 resp.srqid = srq->qplib_srq.id; 1785 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1786 if (rc) { 1787 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!"); 1788 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1789 &srq->qplib_srq); 1790 goto fail; 1791 } 1792 } 1793 if (nq) 1794 nq->budget++; 1795 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count); 1796 if (active_srqs > rdev->stats.res.srq_watermark) 1797 rdev->stats.res.srq_watermark = active_srqs; 1798 spin_lock_init(&srq->lock); 1799 1800 return 0; 1801 1802 fail: 1803 ib_umem_release(srq->umem); 1804 exit: 1805 return rc; 1806 } 1807 1808 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1809 enum ib_srq_attr_mask srq_attr_mask, 1810 struct ib_udata *udata) 1811 { 1812 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1813 ib_srq); 1814 struct bnxt_re_dev *rdev = srq->rdev; 1815 int rc; 1816 1817 switch (srq_attr_mask) { 1818 case IB_SRQ_MAX_WR: 1819 /* SRQ resize is not supported */ 1820 break; 1821 case IB_SRQ_LIMIT: 1822 /* Change the SRQ threshold */ 1823 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1824 return -EINVAL; 1825 1826 srq->qplib_srq.threshold = srq_attr->srq_limit; 1827 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1828 if (rc) { 1829 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!"); 1830 return rc; 1831 } 1832 /* On success, update the shadow */ 1833 srq->srq_limit = srq_attr->srq_limit; 1834 /* No need to Build and send response back to udata */ 1835 break; 1836 default: 1837 ibdev_err(&rdev->ibdev, 1838 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1839 return -EINVAL; 1840 } 1841 return 0; 1842 } 1843 1844 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1845 { 1846 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1847 ib_srq); 1848 struct bnxt_re_srq tsrq; 1849 struct bnxt_re_dev *rdev = srq->rdev; 1850 int rc; 1851 1852 /* Get live SRQ attr */ 1853 tsrq.qplib_srq.id = srq->qplib_srq.id; 1854 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1855 if (rc) { 1856 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!"); 1857 return rc; 1858 } 1859 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1860 srq_attr->max_sge = srq->qplib_srq.max_sge; 1861 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1862 1863 return 0; 1864 } 1865 1866 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1867 const struct ib_recv_wr **bad_wr) 1868 { 1869 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1870 ib_srq); 1871 struct bnxt_qplib_swqe wqe; 1872 unsigned long flags; 1873 int rc = 0; 1874 1875 spin_lock_irqsave(&srq->lock, flags); 1876 while (wr) { 1877 /* Transcribe each ib_recv_wr to qplib_swqe */ 1878 wqe.num_sge = wr->num_sge; 1879 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1880 wqe.wr_id = wr->wr_id; 1881 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1882 1883 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1884 if (rc) { 1885 *bad_wr = wr; 1886 break; 1887 } 1888 wr = wr->next; 1889 } 1890 spin_unlock_irqrestore(&srq->lock, flags); 1891 1892 return rc; 1893 } 1894 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1895 struct bnxt_re_qp *qp1_qp, 1896 int qp_attr_mask) 1897 { 1898 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp; 1899 int rc; 1900 1901 if (qp_attr_mask & IB_QP_STATE) { 1902 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1903 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1904 } 1905 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1906 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1907 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1908 } 1909 1910 if (qp_attr_mask & IB_QP_QKEY) { 1911 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1912 /* Using a Random QKEY */ 1913 qp->qplib_qp.qkey = 0x81818181; 1914 } 1915 if (qp_attr_mask & IB_QP_SQ_PSN) { 1916 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1917 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1918 } 1919 1920 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1921 if (rc) 1922 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1"); 1923 return rc; 1924 } 1925 1926 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1927 int qp_attr_mask, struct ib_udata *udata) 1928 { 1929 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1930 struct bnxt_re_dev *rdev = qp->rdev; 1931 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1932 enum ib_qp_state curr_qp_state, new_qp_state; 1933 int rc, entries; 1934 unsigned int flags; 1935 u8 nw_type; 1936 1937 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 1938 return -EOPNOTSUPP; 1939 1940 qp->qplib_qp.modify_flags = 0; 1941 if (qp_attr_mask & IB_QP_STATE) { 1942 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1943 new_qp_state = qp_attr->qp_state; 1944 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1945 ib_qp->qp_type, qp_attr_mask)) { 1946 ibdev_err(&rdev->ibdev, 1947 "Invalid attribute mask: %#x specified ", 1948 qp_attr_mask); 1949 ibdev_err(&rdev->ibdev, 1950 "for qpn: %#x type: %#x", 1951 ib_qp->qp_num, ib_qp->qp_type); 1952 ibdev_err(&rdev->ibdev, 1953 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1954 curr_qp_state, new_qp_state); 1955 return -EINVAL; 1956 } 1957 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1958 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1959 1960 if (!qp->sumem && 1961 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1962 ibdev_dbg(&rdev->ibdev, 1963 "Move QP = %p to flush list\n", qp); 1964 flags = bnxt_re_lock_cqs(qp); 1965 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1966 bnxt_re_unlock_cqs(qp, flags); 1967 } 1968 if (!qp->sumem && 1969 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1970 ibdev_dbg(&rdev->ibdev, 1971 "Move QP = %p out of flush list\n", qp); 1972 flags = bnxt_re_lock_cqs(qp); 1973 bnxt_qplib_clean_qp(&qp->qplib_qp); 1974 bnxt_re_unlock_cqs(qp, flags); 1975 } 1976 } 1977 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1978 qp->qplib_qp.modify_flags |= 1979 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1980 qp->qplib_qp.en_sqd_async_notify = true; 1981 } 1982 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1983 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1984 qp->qplib_qp.access = 1985 __from_ib_access_flags(qp_attr->qp_access_flags); 1986 /* LOCAL_WRITE access must be set to allow RC receive */ 1987 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1988 /* Temp: Set all params on QP as of now */ 1989 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 1990 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 1991 } 1992 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1993 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1994 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 1995 } 1996 if (qp_attr_mask & IB_QP_QKEY) { 1997 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1998 qp->qplib_qp.qkey = qp_attr->qkey; 1999 } 2000 if (qp_attr_mask & IB_QP_AV) { 2001 const struct ib_global_route *grh = 2002 rdma_ah_read_grh(&qp_attr->ah_attr); 2003 const struct ib_gid_attr *sgid_attr; 2004 struct bnxt_re_gid_ctx *ctx; 2005 2006 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 2007 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 2008 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 2009 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 2010 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 2011 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 2012 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 2013 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 2014 sizeof(qp->qplib_qp.ah.dgid.data)); 2015 qp->qplib_qp.ah.flow_label = grh->flow_label; 2016 sgid_attr = grh->sgid_attr; 2017 /* Get the HW context of the GID. The reference 2018 * of GID table entry is already taken by the caller. 2019 */ 2020 ctx = rdma_read_gid_hw_context(sgid_attr); 2021 qp->qplib_qp.ah.sgid_index = ctx->idx; 2022 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 2023 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 2024 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 2025 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 2026 ether_addr_copy(qp->qplib_qp.ah.dmac, 2027 qp_attr->ah_attr.roce.dmac); 2028 2029 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 2030 &qp->qplib_qp.smac[0]); 2031 if (rc) 2032 return rc; 2033 2034 nw_type = rdma_gid_attr_network_type(sgid_attr); 2035 switch (nw_type) { 2036 case RDMA_NETWORK_IPV4: 2037 qp->qplib_qp.nw_type = 2038 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 2039 break; 2040 case RDMA_NETWORK_IPV6: 2041 qp->qplib_qp.nw_type = 2042 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 2043 break; 2044 default: 2045 qp->qplib_qp.nw_type = 2046 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 2047 break; 2048 } 2049 } 2050 2051 if (qp_attr_mask & IB_QP_PATH_MTU) { 2052 qp->qplib_qp.modify_flags |= 2053 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2054 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 2055 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 2056 } else if (qp_attr->qp_state == IB_QPS_RTR) { 2057 qp->qplib_qp.modify_flags |= 2058 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2059 qp->qplib_qp.path_mtu = 2060 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 2061 qp->qplib_qp.mtu = 2062 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 2063 } 2064 2065 if (qp_attr_mask & IB_QP_TIMEOUT) { 2066 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 2067 qp->qplib_qp.timeout = qp_attr->timeout; 2068 } 2069 if (qp_attr_mask & IB_QP_RETRY_CNT) { 2070 qp->qplib_qp.modify_flags |= 2071 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 2072 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 2073 } 2074 if (qp_attr_mask & IB_QP_RNR_RETRY) { 2075 qp->qplib_qp.modify_flags |= 2076 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 2077 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 2078 } 2079 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 2080 qp->qplib_qp.modify_flags |= 2081 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 2082 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 2083 } 2084 if (qp_attr_mask & IB_QP_RQ_PSN) { 2085 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 2086 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 2087 } 2088 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2089 qp->qplib_qp.modify_flags |= 2090 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 2091 /* Cap the max_rd_atomic to device max */ 2092 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 2093 dev_attr->max_qp_rd_atom); 2094 } 2095 if (qp_attr_mask & IB_QP_SQ_PSN) { 2096 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2097 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 2098 } 2099 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2100 if (qp_attr->max_dest_rd_atomic > 2101 dev_attr->max_qp_init_rd_atom) { 2102 ibdev_err(&rdev->ibdev, 2103 "max_dest_rd_atomic requested%d is > dev_max%d", 2104 qp_attr->max_dest_rd_atomic, 2105 dev_attr->max_qp_init_rd_atom); 2106 return -EINVAL; 2107 } 2108 2109 qp->qplib_qp.modify_flags |= 2110 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 2111 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 2112 } 2113 if (qp_attr_mask & IB_QP_CAP) { 2114 struct bnxt_re_ucontext *uctx = 2115 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2116 2117 qp->qplib_qp.modify_flags |= 2118 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 2119 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 2120 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 2121 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 2122 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 2123 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 2124 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 2125 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 2126 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 2127 (qp_attr->cap.max_inline_data >= 2128 dev_attr->max_inline_data)) { 2129 ibdev_err(&rdev->ibdev, 2130 "Create QP failed - max exceeded"); 2131 return -EINVAL; 2132 } 2133 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx); 2134 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 2135 dev_attr->max_qp_wqes + 1); 2136 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 2137 qp_attr->cap.max_send_wr; 2138 /* 2139 * Reserving one slot for Phantom WQE. Some application can 2140 * post one extra entry in this case. Allowing this to avoid 2141 * unexpected Queue full condition 2142 */ 2143 qp->qplib_qp.sq.q_full_delta -= 1; 2144 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 2145 if (qp->qplib_qp.rq.max_wqe) { 2146 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx); 2147 qp->qplib_qp.rq.max_wqe = 2148 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 2149 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 2150 qp_attr->cap.max_recv_wr; 2151 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 2152 } else { 2153 /* SRQ was used prior, just ignore the RQ caps */ 2154 } 2155 } 2156 if (qp_attr_mask & IB_QP_DEST_QPN) { 2157 qp->qplib_qp.modify_flags |= 2158 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 2159 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 2160 } 2161 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2162 if (rc) { 2163 ibdev_err(&rdev->ibdev, "Failed to modify HW QP"); 2164 return rc; 2165 } 2166 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 2167 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 2168 return rc; 2169 } 2170 2171 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2172 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 2173 { 2174 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2175 struct bnxt_re_dev *rdev = qp->rdev; 2176 struct bnxt_qplib_qp *qplib_qp; 2177 int rc; 2178 2179 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 2180 if (!qplib_qp) 2181 return -ENOMEM; 2182 2183 qplib_qp->id = qp->qplib_qp.id; 2184 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 2185 2186 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 2187 if (rc) { 2188 ibdev_err(&rdev->ibdev, "Failed to query HW QP"); 2189 goto out; 2190 } 2191 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 2192 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state); 2193 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 2194 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 2195 qp_attr->pkey_index = qplib_qp->pkey_index; 2196 qp_attr->qkey = qplib_qp->qkey; 2197 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2198 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 2199 qplib_qp->ah.host_sgid_index, 2200 qplib_qp->ah.hop_limit, 2201 qplib_qp->ah.traffic_class); 2202 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 2203 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 2204 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 2205 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 2206 qp_attr->timeout = qplib_qp->timeout; 2207 qp_attr->retry_cnt = qplib_qp->retry_cnt; 2208 qp_attr->rnr_retry = qplib_qp->rnr_retry; 2209 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 2210 qp_attr->rq_psn = qplib_qp->rq.psn; 2211 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 2212 qp_attr->sq_psn = qplib_qp->sq.psn; 2213 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 2214 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 2215 IB_SIGNAL_REQ_WR; 2216 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 2217 2218 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 2219 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 2220 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 2221 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 2222 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 2223 qp_init_attr->cap = qp_attr->cap; 2224 2225 out: 2226 kfree(qplib_qp); 2227 return rc; 2228 } 2229 2230 /* Routine for sending QP1 packets for RoCE V1 an V2 2231 */ 2232 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 2233 const struct ib_send_wr *wr, 2234 struct bnxt_qplib_swqe *wqe, 2235 int payload_size) 2236 { 2237 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 2238 ib_ah); 2239 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 2240 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 2241 struct bnxt_qplib_sge sge; 2242 u8 nw_type; 2243 u16 ether_type; 2244 union ib_gid dgid; 2245 bool is_eth = false; 2246 bool is_vlan = false; 2247 bool is_grh = false; 2248 bool is_udp = false; 2249 u8 ip_version = 0; 2250 u16 vlan_id = 0xFFFF; 2251 void *buf; 2252 int i, rc; 2253 2254 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 2255 2256 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 2257 if (rc) 2258 return rc; 2259 2260 /* Get network header type for this GID */ 2261 nw_type = rdma_gid_attr_network_type(sgid_attr); 2262 switch (nw_type) { 2263 case RDMA_NETWORK_IPV4: 2264 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 2265 break; 2266 case RDMA_NETWORK_IPV6: 2267 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 2268 break; 2269 default: 2270 nw_type = BNXT_RE_ROCE_V1_PACKET; 2271 break; 2272 } 2273 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 2274 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2275 if (is_udp) { 2276 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 2277 ip_version = 4; 2278 ether_type = ETH_P_IP; 2279 } else { 2280 ip_version = 6; 2281 ether_type = ETH_P_IPV6; 2282 } 2283 is_grh = false; 2284 } else { 2285 ether_type = ETH_P_IBOE; 2286 is_grh = true; 2287 } 2288 2289 is_eth = true; 2290 is_vlan = vlan_id && (vlan_id < 0x1000); 2291 2292 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 2293 ip_version, is_udp, 0, &qp->qp1_hdr); 2294 2295 /* ETH */ 2296 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 2297 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 2298 2299 /* For vlan, check the sgid for vlan existence */ 2300 2301 if (!is_vlan) { 2302 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 2303 } else { 2304 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 2305 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 2306 } 2307 2308 if (is_grh || (ip_version == 6)) { 2309 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 2310 sizeof(sgid_attr->gid)); 2311 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 2312 sizeof(sgid_attr->gid)); 2313 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 2314 } 2315 2316 if (ip_version == 4) { 2317 qp->qp1_hdr.ip4.tos = 0; 2318 qp->qp1_hdr.ip4.id = 0; 2319 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 2320 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 2321 2322 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 2323 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 2324 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 2325 } 2326 2327 if (is_udp) { 2328 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 2329 qp->qp1_hdr.udp.sport = htons(0x8CD1); 2330 qp->qp1_hdr.udp.csum = 0; 2331 } 2332 2333 /* BTH */ 2334 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 2335 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2336 qp->qp1_hdr.immediate_present = 1; 2337 } else { 2338 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2339 } 2340 if (wr->send_flags & IB_SEND_SOLICITED) 2341 qp->qp1_hdr.bth.solicited_event = 1; 2342 /* pad_count */ 2343 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 2344 2345 /* P_key for QP1 is for all members */ 2346 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 2347 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 2348 qp->qp1_hdr.bth.ack_req = 0; 2349 qp->send_psn++; 2350 qp->send_psn &= BTH_PSN_MASK; 2351 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 2352 /* DETH */ 2353 /* Use the priviledged Q_Key for QP1 */ 2354 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 2355 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2356 2357 /* Pack the QP1 to the transmit buffer */ 2358 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2359 if (buf) { 2360 ib_ud_header_pack(&qp->qp1_hdr, buf); 2361 for (i = wqe->num_sge; i; i--) { 2362 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2363 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2364 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2365 } 2366 2367 /* 2368 * Max Header buf size for IPV6 RoCE V2 is 86, 2369 * which is same as the QP1 SQ header buffer. 2370 * Header buf size for IPV4 RoCE V2 can be 66. 2371 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2372 * Subtract 20 bytes from QP1 SQ header buf size 2373 */ 2374 if (is_udp && ip_version == 4) 2375 sge.size -= 20; 2376 /* 2377 * Max Header buf size for RoCE V1 is 78. 2378 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2379 * Subtract 8 bytes from QP1 SQ header buf size 2380 */ 2381 if (!is_udp) 2382 sge.size -= 8; 2383 2384 /* Subtract 4 bytes for non vlan packets */ 2385 if (!is_vlan) 2386 sge.size -= 4; 2387 2388 wqe->sg_list[0].addr = sge.addr; 2389 wqe->sg_list[0].lkey = sge.lkey; 2390 wqe->sg_list[0].size = sge.size; 2391 wqe->num_sge++; 2392 2393 } else { 2394 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!"); 2395 rc = -ENOMEM; 2396 } 2397 return rc; 2398 } 2399 2400 /* For the MAD layer, it only provides the recv SGE the size of 2401 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2402 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2403 * receive packet (334 bytes) with no VLAN and then copy the GRH 2404 * and the MAD datagram out to the provided SGE. 2405 */ 2406 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2407 const struct ib_recv_wr *wr, 2408 struct bnxt_qplib_swqe *wqe, 2409 int payload_size) 2410 { 2411 struct bnxt_re_sqp_entries *sqp_entry; 2412 struct bnxt_qplib_sge ref, sge; 2413 struct bnxt_re_dev *rdev; 2414 u32 rq_prod_index; 2415 2416 rdev = qp->rdev; 2417 2418 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2419 2420 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2421 return -ENOMEM; 2422 2423 /* Create 1 SGE to receive the entire 2424 * ethernet packet 2425 */ 2426 /* Save the reference from ULP */ 2427 ref.addr = wqe->sg_list[0].addr; 2428 ref.lkey = wqe->sg_list[0].lkey; 2429 ref.size = wqe->sg_list[0].size; 2430 2431 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index]; 2432 2433 /* SGE 1 */ 2434 wqe->sg_list[0].addr = sge.addr; 2435 wqe->sg_list[0].lkey = sge.lkey; 2436 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2437 sge.size -= wqe->sg_list[0].size; 2438 2439 sqp_entry->sge.addr = ref.addr; 2440 sqp_entry->sge.lkey = ref.lkey; 2441 sqp_entry->sge.size = ref.size; 2442 /* Store the wrid for reporting completion */ 2443 sqp_entry->wrid = wqe->wr_id; 2444 /* change the wqe->wrid to table index */ 2445 wqe->wr_id = rq_prod_index; 2446 return 0; 2447 } 2448 2449 static int is_ud_qp(struct bnxt_re_qp *qp) 2450 { 2451 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2452 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2453 } 2454 2455 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2456 const struct ib_send_wr *wr, 2457 struct bnxt_qplib_swqe *wqe) 2458 { 2459 struct bnxt_re_ah *ah = NULL; 2460 2461 if (is_ud_qp(qp)) { 2462 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2463 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2464 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2465 wqe->send.avid = ah->qplib_ah.id; 2466 } 2467 switch (wr->opcode) { 2468 case IB_WR_SEND: 2469 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2470 break; 2471 case IB_WR_SEND_WITH_IMM: 2472 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2473 wqe->send.imm_data = wr->ex.imm_data; 2474 break; 2475 case IB_WR_SEND_WITH_INV: 2476 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2477 wqe->send.inv_key = wr->ex.invalidate_rkey; 2478 break; 2479 default: 2480 return -EINVAL; 2481 } 2482 if (wr->send_flags & IB_SEND_SIGNALED) 2483 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2484 if (wr->send_flags & IB_SEND_FENCE) 2485 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2486 if (wr->send_flags & IB_SEND_SOLICITED) 2487 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2488 if (wr->send_flags & IB_SEND_INLINE) 2489 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2490 2491 return 0; 2492 } 2493 2494 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2495 struct bnxt_qplib_swqe *wqe) 2496 { 2497 switch (wr->opcode) { 2498 case IB_WR_RDMA_WRITE: 2499 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2500 break; 2501 case IB_WR_RDMA_WRITE_WITH_IMM: 2502 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2503 wqe->rdma.imm_data = wr->ex.imm_data; 2504 break; 2505 case IB_WR_RDMA_READ: 2506 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2507 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2508 break; 2509 default: 2510 return -EINVAL; 2511 } 2512 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2513 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2514 if (wr->send_flags & IB_SEND_SIGNALED) 2515 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2516 if (wr->send_flags & IB_SEND_FENCE) 2517 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2518 if (wr->send_flags & IB_SEND_SOLICITED) 2519 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2520 if (wr->send_flags & IB_SEND_INLINE) 2521 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2522 2523 return 0; 2524 } 2525 2526 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2527 struct bnxt_qplib_swqe *wqe) 2528 { 2529 switch (wr->opcode) { 2530 case IB_WR_ATOMIC_CMP_AND_SWP: 2531 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2532 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2533 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2534 break; 2535 case IB_WR_ATOMIC_FETCH_AND_ADD: 2536 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2537 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2538 break; 2539 default: 2540 return -EINVAL; 2541 } 2542 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2543 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2544 if (wr->send_flags & IB_SEND_SIGNALED) 2545 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2546 if (wr->send_flags & IB_SEND_FENCE) 2547 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2548 if (wr->send_flags & IB_SEND_SOLICITED) 2549 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2550 return 0; 2551 } 2552 2553 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2554 struct bnxt_qplib_swqe *wqe) 2555 { 2556 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2557 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2558 2559 /* Need unconditional fence for local invalidate 2560 * opcode to work as expected. 2561 */ 2562 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2563 2564 if (wr->send_flags & IB_SEND_SIGNALED) 2565 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2566 if (wr->send_flags & IB_SEND_SOLICITED) 2567 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2568 2569 return 0; 2570 } 2571 2572 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2573 struct bnxt_qplib_swqe *wqe) 2574 { 2575 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2576 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2577 int access = wr->access; 2578 2579 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2580 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2581 wqe->frmr.page_list = mr->pages; 2582 wqe->frmr.page_list_len = mr->npages; 2583 wqe->frmr.levels = qplib_frpl->hwq.level; 2584 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2585 2586 /* Need unconditional fence for reg_mr 2587 * opcode to function as expected. 2588 */ 2589 2590 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2591 2592 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2593 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2594 2595 if (access & IB_ACCESS_LOCAL_WRITE) 2596 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2597 if (access & IB_ACCESS_REMOTE_READ) 2598 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2599 if (access & IB_ACCESS_REMOTE_WRITE) 2600 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2601 if (access & IB_ACCESS_REMOTE_ATOMIC) 2602 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2603 if (access & IB_ACCESS_MW_BIND) 2604 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2605 2606 wqe->frmr.l_key = wr->key; 2607 wqe->frmr.length = wr->mr->length; 2608 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K); 2609 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K); 2610 wqe->frmr.va = wr->mr->iova; 2611 return 0; 2612 } 2613 2614 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2615 const struct ib_send_wr *wr, 2616 struct bnxt_qplib_swqe *wqe) 2617 { 2618 /* Copy the inline data to the data field */ 2619 u8 *in_data; 2620 u32 i, sge_len; 2621 void *sge_addr; 2622 2623 in_data = wqe->inline_data; 2624 for (i = 0; i < wr->num_sge; i++) { 2625 sge_addr = (void *)(unsigned long) 2626 wr->sg_list[i].addr; 2627 sge_len = wr->sg_list[i].length; 2628 2629 if ((sge_len + wqe->inline_len) > 2630 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2631 ibdev_err(&rdev->ibdev, 2632 "Inline data size requested > supported value"); 2633 return -EINVAL; 2634 } 2635 sge_len = wr->sg_list[i].length; 2636 2637 memcpy(in_data, sge_addr, sge_len); 2638 in_data += wr->sg_list[i].length; 2639 wqe->inline_len += wr->sg_list[i].length; 2640 } 2641 return wqe->inline_len; 2642 } 2643 2644 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2645 const struct ib_send_wr *wr, 2646 struct bnxt_qplib_swqe *wqe) 2647 { 2648 int payload_sz = 0; 2649 2650 if (wr->send_flags & IB_SEND_INLINE) 2651 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2652 else 2653 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2654 wqe->num_sge); 2655 2656 return payload_sz; 2657 } 2658 2659 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2660 { 2661 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2662 qp->ib_qp.qp_type == IB_QPT_GSI || 2663 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2664 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2665 int qp_attr_mask; 2666 struct ib_qp_attr qp_attr; 2667 2668 qp_attr_mask = IB_QP_STATE; 2669 qp_attr.qp_state = IB_QPS_RTS; 2670 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2671 qp->qplib_qp.wqe_cnt = 0; 2672 } 2673 } 2674 2675 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2676 struct bnxt_re_qp *qp, 2677 const struct ib_send_wr *wr) 2678 { 2679 int rc = 0, payload_sz = 0; 2680 unsigned long flags; 2681 2682 spin_lock_irqsave(&qp->sq_lock, flags); 2683 while (wr) { 2684 struct bnxt_qplib_swqe wqe = {}; 2685 2686 /* Common */ 2687 wqe.num_sge = wr->num_sge; 2688 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2689 ibdev_err(&rdev->ibdev, 2690 "Limit exceeded for Send SGEs"); 2691 rc = -EINVAL; 2692 goto bad; 2693 } 2694 2695 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2696 if (payload_sz < 0) { 2697 rc = -EINVAL; 2698 goto bad; 2699 } 2700 wqe.wr_id = wr->wr_id; 2701 2702 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2703 2704 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2705 if (!rc) 2706 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2707 bad: 2708 if (rc) { 2709 ibdev_err(&rdev->ibdev, 2710 "Post send failed opcode = %#x rc = %d", 2711 wr->opcode, rc); 2712 break; 2713 } 2714 wr = wr->next; 2715 } 2716 bnxt_qplib_post_send_db(&qp->qplib_qp); 2717 bnxt_ud_qp_hw_stall_workaround(qp); 2718 spin_unlock_irqrestore(&qp->sq_lock, flags); 2719 return rc; 2720 } 2721 2722 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2723 const struct ib_send_wr **bad_wr) 2724 { 2725 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2726 struct bnxt_qplib_swqe wqe; 2727 int rc = 0, payload_sz = 0; 2728 unsigned long flags; 2729 2730 spin_lock_irqsave(&qp->sq_lock, flags); 2731 while (wr) { 2732 /* House keeping */ 2733 memset(&wqe, 0, sizeof(wqe)); 2734 2735 /* Common */ 2736 wqe.num_sge = wr->num_sge; 2737 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2738 ibdev_err(&qp->rdev->ibdev, 2739 "Limit exceeded for Send SGEs"); 2740 rc = -EINVAL; 2741 goto bad; 2742 } 2743 2744 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2745 if (payload_sz < 0) { 2746 rc = -EINVAL; 2747 goto bad; 2748 } 2749 wqe.wr_id = wr->wr_id; 2750 2751 switch (wr->opcode) { 2752 case IB_WR_SEND: 2753 case IB_WR_SEND_WITH_IMM: 2754 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2755 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2756 payload_sz); 2757 if (rc) 2758 goto bad; 2759 wqe.rawqp1.lflags |= 2760 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2761 } 2762 switch (wr->send_flags) { 2763 case IB_SEND_IP_CSUM: 2764 wqe.rawqp1.lflags |= 2765 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2766 break; 2767 default: 2768 break; 2769 } 2770 fallthrough; 2771 case IB_WR_SEND_WITH_INV: 2772 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2773 break; 2774 case IB_WR_RDMA_WRITE: 2775 case IB_WR_RDMA_WRITE_WITH_IMM: 2776 case IB_WR_RDMA_READ: 2777 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2778 break; 2779 case IB_WR_ATOMIC_CMP_AND_SWP: 2780 case IB_WR_ATOMIC_FETCH_AND_ADD: 2781 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2782 break; 2783 case IB_WR_RDMA_READ_WITH_INV: 2784 ibdev_err(&qp->rdev->ibdev, 2785 "RDMA Read with Invalidate is not supported"); 2786 rc = -EINVAL; 2787 goto bad; 2788 case IB_WR_LOCAL_INV: 2789 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2790 break; 2791 case IB_WR_REG_MR: 2792 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2793 break; 2794 default: 2795 /* Unsupported WRs */ 2796 ibdev_err(&qp->rdev->ibdev, 2797 "WR (%#x) is not supported", wr->opcode); 2798 rc = -EINVAL; 2799 goto bad; 2800 } 2801 if (!rc) 2802 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2803 bad: 2804 if (rc) { 2805 ibdev_err(&qp->rdev->ibdev, 2806 "post_send failed op:%#x qps = %#x rc = %d\n", 2807 wr->opcode, qp->qplib_qp.state, rc); 2808 *bad_wr = wr; 2809 break; 2810 } 2811 wr = wr->next; 2812 } 2813 bnxt_qplib_post_send_db(&qp->qplib_qp); 2814 bnxt_ud_qp_hw_stall_workaround(qp); 2815 spin_unlock_irqrestore(&qp->sq_lock, flags); 2816 2817 return rc; 2818 } 2819 2820 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2821 struct bnxt_re_qp *qp, 2822 const struct ib_recv_wr *wr) 2823 { 2824 struct bnxt_qplib_swqe wqe; 2825 int rc = 0; 2826 2827 while (wr) { 2828 /* House keeping */ 2829 memset(&wqe, 0, sizeof(wqe)); 2830 2831 /* Common */ 2832 wqe.num_sge = wr->num_sge; 2833 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2834 ibdev_err(&rdev->ibdev, 2835 "Limit exceeded for Receive SGEs"); 2836 rc = -EINVAL; 2837 break; 2838 } 2839 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2840 wqe.wr_id = wr->wr_id; 2841 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2842 2843 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2844 if (rc) 2845 break; 2846 2847 wr = wr->next; 2848 } 2849 if (!rc) 2850 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2851 return rc; 2852 } 2853 2854 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2855 const struct ib_recv_wr **bad_wr) 2856 { 2857 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2858 struct bnxt_qplib_swqe wqe; 2859 int rc = 0, payload_sz = 0; 2860 unsigned long flags; 2861 u32 count = 0; 2862 2863 spin_lock_irqsave(&qp->rq_lock, flags); 2864 while (wr) { 2865 /* House keeping */ 2866 memset(&wqe, 0, sizeof(wqe)); 2867 2868 /* Common */ 2869 wqe.num_sge = wr->num_sge; 2870 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2871 ibdev_err(&qp->rdev->ibdev, 2872 "Limit exceeded for Receive SGEs"); 2873 rc = -EINVAL; 2874 *bad_wr = wr; 2875 break; 2876 } 2877 2878 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2879 wr->num_sge); 2880 wqe.wr_id = wr->wr_id; 2881 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2882 2883 if (ib_qp->qp_type == IB_QPT_GSI && 2884 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 2885 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2886 payload_sz); 2887 if (!rc) 2888 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2889 if (rc) { 2890 *bad_wr = wr; 2891 break; 2892 } 2893 2894 /* Ring DB if the RQEs posted reaches a threshold value */ 2895 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2896 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2897 count = 0; 2898 } 2899 2900 wr = wr->next; 2901 } 2902 2903 if (count) 2904 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2905 2906 spin_unlock_irqrestore(&qp->rq_lock, flags); 2907 2908 return rc; 2909 } 2910 2911 /* Completion Queues */ 2912 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 2913 { 2914 struct bnxt_qplib_chip_ctx *cctx; 2915 struct bnxt_qplib_nq *nq; 2916 struct bnxt_re_dev *rdev; 2917 struct bnxt_re_cq *cq; 2918 2919 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2920 rdev = cq->rdev; 2921 nq = cq->qplib_cq.nq; 2922 cctx = rdev->chip_ctx; 2923 2924 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 2925 free_page((unsigned long)cq->uctx_cq_page); 2926 hash_del(&cq->hash_entry); 2927 } 2928 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2929 ib_umem_release(cq->umem); 2930 2931 atomic_dec(&rdev->stats.res.cq_count); 2932 nq->budget--; 2933 kfree(cq->cql); 2934 return 0; 2935 } 2936 2937 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 2938 struct ib_udata *udata) 2939 { 2940 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 2941 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 2942 struct bnxt_re_ucontext *uctx = 2943 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2944 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2945 struct bnxt_qplib_chip_ctx *cctx; 2946 struct bnxt_qplib_nq *nq = NULL; 2947 unsigned int nq_alloc_cnt; 2948 int cqe = attr->cqe; 2949 int rc, entries; 2950 u32 active_cqs; 2951 2952 if (attr->flags) 2953 return -EOPNOTSUPP; 2954 2955 /* Validate CQ fields */ 2956 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2957 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded"); 2958 return -EINVAL; 2959 } 2960 2961 cq->rdev = rdev; 2962 cctx = rdev->chip_ctx; 2963 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2964 2965 entries = bnxt_re_init_depth(cqe + 1, uctx); 2966 if (entries > dev_attr->max_cq_wqes + 1) 2967 entries = dev_attr->max_cq_wqes + 1; 2968 2969 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 2970 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 2971 if (udata) { 2972 struct bnxt_re_cq_req req; 2973 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2974 rc = -EFAULT; 2975 goto fail; 2976 } 2977 2978 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va, 2979 entries * sizeof(struct cq_base), 2980 IB_ACCESS_LOCAL_WRITE); 2981 if (IS_ERR(cq->umem)) { 2982 rc = PTR_ERR(cq->umem); 2983 goto fail; 2984 } 2985 cq->qplib_cq.sg_info.umem = cq->umem; 2986 cq->qplib_cq.dpi = &uctx->dpi; 2987 } else { 2988 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 2989 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 2990 GFP_KERNEL); 2991 if (!cq->cql) { 2992 rc = -ENOMEM; 2993 goto fail; 2994 } 2995 2996 cq->qplib_cq.dpi = &rdev->dpi_privileged; 2997 } 2998 /* 2999 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 3000 * used for getting the NQ index. 3001 */ 3002 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 3003 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 3004 cq->qplib_cq.max_wqe = entries; 3005 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 3006 cq->qplib_cq.nq = nq; 3007 3008 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 3009 if (rc) { 3010 ibdev_err(&rdev->ibdev, "Failed to create HW CQ"); 3011 goto fail; 3012 } 3013 3014 cq->ib_cq.cqe = entries; 3015 cq->cq_period = cq->qplib_cq.period; 3016 nq->budget++; 3017 3018 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count); 3019 if (active_cqs > rdev->stats.res.cq_watermark) 3020 rdev->stats.res.cq_watermark = active_cqs; 3021 spin_lock_init(&cq->cq_lock); 3022 3023 if (udata) { 3024 struct bnxt_re_cq_resp resp = {}; 3025 3026 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 3027 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id); 3028 /* Allocate a page */ 3029 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL); 3030 if (!cq->uctx_cq_page) { 3031 rc = -ENOMEM; 3032 goto c2fail; 3033 } 3034 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT; 3035 } 3036 resp.cqid = cq->qplib_cq.id; 3037 resp.tail = cq->qplib_cq.hwq.cons; 3038 resp.phase = cq->qplib_cq.period; 3039 resp.rsvd = 0; 3040 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 3041 if (rc) { 3042 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata"); 3043 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3044 goto free_mem; 3045 } 3046 } 3047 3048 return 0; 3049 3050 free_mem: 3051 free_page((unsigned long)cq->uctx_cq_page); 3052 c2fail: 3053 ib_umem_release(cq->umem); 3054 fail: 3055 kfree(cq->cql); 3056 return rc; 3057 } 3058 3059 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq) 3060 { 3061 struct bnxt_re_dev *rdev = cq->rdev; 3062 3063 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq); 3064 3065 cq->qplib_cq.max_wqe = cq->resize_cqe; 3066 if (cq->resize_umem) { 3067 ib_umem_release(cq->umem); 3068 cq->umem = cq->resize_umem; 3069 cq->resize_umem = NULL; 3070 cq->resize_cqe = 0; 3071 } 3072 } 3073 3074 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata) 3075 { 3076 struct bnxt_qplib_sg_info sg_info = {}; 3077 struct bnxt_qplib_dpi *orig_dpi = NULL; 3078 struct bnxt_qplib_dev_attr *dev_attr; 3079 struct bnxt_re_ucontext *uctx = NULL; 3080 struct bnxt_re_resize_cq_req req; 3081 struct bnxt_re_dev *rdev; 3082 struct bnxt_re_cq *cq; 3083 int rc, entries; 3084 3085 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3086 rdev = cq->rdev; 3087 dev_attr = &rdev->dev_attr; 3088 if (!ibcq->uobject) { 3089 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported"); 3090 return -EOPNOTSUPP; 3091 } 3092 3093 if (cq->resize_umem) { 3094 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy", 3095 cq->qplib_cq.id); 3096 return -EBUSY; 3097 } 3098 3099 /* Check the requested cq depth out of supported depth */ 3100 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3101 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d", 3102 cq->qplib_cq.id, cqe); 3103 return -EINVAL; 3104 } 3105 3106 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3107 entries = bnxt_re_init_depth(cqe + 1, uctx); 3108 if (entries > dev_attr->max_cq_wqes + 1) 3109 entries = dev_attr->max_cq_wqes + 1; 3110 3111 /* uverbs consumer */ 3112 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3113 rc = -EFAULT; 3114 goto fail; 3115 } 3116 3117 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3118 entries * sizeof(struct cq_base), 3119 IB_ACCESS_LOCAL_WRITE); 3120 if (IS_ERR(cq->resize_umem)) { 3121 rc = PTR_ERR(cq->resize_umem); 3122 cq->resize_umem = NULL; 3123 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n", 3124 __func__, rc); 3125 goto fail; 3126 } 3127 cq->resize_cqe = entries; 3128 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info)); 3129 orig_dpi = cq->qplib_cq.dpi; 3130 3131 cq->qplib_cq.sg_info.umem = cq->resize_umem; 3132 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3133 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3134 cq->qplib_cq.dpi = &uctx->dpi; 3135 3136 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries); 3137 if (rc) { 3138 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!", 3139 cq->qplib_cq.id); 3140 goto fail; 3141 } 3142 3143 cq->ib_cq.cqe = cq->resize_cqe; 3144 atomic_inc(&rdev->stats.res.resize_count); 3145 3146 return 0; 3147 3148 fail: 3149 if (cq->resize_umem) { 3150 ib_umem_release(cq->resize_umem); 3151 cq->resize_umem = NULL; 3152 cq->resize_cqe = 0; 3153 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info)); 3154 cq->qplib_cq.dpi = orig_dpi; 3155 } 3156 return rc; 3157 } 3158 3159 static u8 __req_to_ib_wc_status(u8 qstatus) 3160 { 3161 switch (qstatus) { 3162 case CQ_REQ_STATUS_OK: 3163 return IB_WC_SUCCESS; 3164 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 3165 return IB_WC_BAD_RESP_ERR; 3166 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 3167 return IB_WC_LOC_LEN_ERR; 3168 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 3169 return IB_WC_LOC_QP_OP_ERR; 3170 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 3171 return IB_WC_LOC_PROT_ERR; 3172 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 3173 return IB_WC_GENERAL_ERR; 3174 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 3175 return IB_WC_REM_INV_REQ_ERR; 3176 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 3177 return IB_WC_REM_ACCESS_ERR; 3178 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 3179 return IB_WC_REM_OP_ERR; 3180 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 3181 return IB_WC_RNR_RETRY_EXC_ERR; 3182 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 3183 return IB_WC_RETRY_EXC_ERR; 3184 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 3185 return IB_WC_WR_FLUSH_ERR; 3186 default: 3187 return IB_WC_GENERAL_ERR; 3188 } 3189 return 0; 3190 } 3191 3192 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 3193 { 3194 switch (qstatus) { 3195 case CQ_RES_RAWETH_QP1_STATUS_OK: 3196 return IB_WC_SUCCESS; 3197 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 3198 return IB_WC_LOC_ACCESS_ERR; 3199 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 3200 return IB_WC_LOC_LEN_ERR; 3201 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 3202 return IB_WC_LOC_PROT_ERR; 3203 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 3204 return IB_WC_LOC_QP_OP_ERR; 3205 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 3206 return IB_WC_GENERAL_ERR; 3207 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 3208 return IB_WC_WR_FLUSH_ERR; 3209 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 3210 return IB_WC_WR_FLUSH_ERR; 3211 default: 3212 return IB_WC_GENERAL_ERR; 3213 } 3214 } 3215 3216 static u8 __rc_to_ib_wc_status(u8 qstatus) 3217 { 3218 switch (qstatus) { 3219 case CQ_RES_RC_STATUS_OK: 3220 return IB_WC_SUCCESS; 3221 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 3222 return IB_WC_LOC_ACCESS_ERR; 3223 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 3224 return IB_WC_LOC_LEN_ERR; 3225 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 3226 return IB_WC_LOC_PROT_ERR; 3227 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 3228 return IB_WC_LOC_QP_OP_ERR; 3229 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 3230 return IB_WC_GENERAL_ERR; 3231 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 3232 return IB_WC_REM_INV_REQ_ERR; 3233 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 3234 return IB_WC_WR_FLUSH_ERR; 3235 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 3236 return IB_WC_WR_FLUSH_ERR; 3237 default: 3238 return IB_WC_GENERAL_ERR; 3239 } 3240 } 3241 3242 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 3243 { 3244 switch (cqe->type) { 3245 case BNXT_QPLIB_SWQE_TYPE_SEND: 3246 wc->opcode = IB_WC_SEND; 3247 break; 3248 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 3249 wc->opcode = IB_WC_SEND; 3250 wc->wc_flags |= IB_WC_WITH_IMM; 3251 break; 3252 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 3253 wc->opcode = IB_WC_SEND; 3254 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3255 break; 3256 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 3257 wc->opcode = IB_WC_RDMA_WRITE; 3258 break; 3259 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 3260 wc->opcode = IB_WC_RDMA_WRITE; 3261 wc->wc_flags |= IB_WC_WITH_IMM; 3262 break; 3263 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 3264 wc->opcode = IB_WC_RDMA_READ; 3265 break; 3266 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 3267 wc->opcode = IB_WC_COMP_SWAP; 3268 break; 3269 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 3270 wc->opcode = IB_WC_FETCH_ADD; 3271 break; 3272 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 3273 wc->opcode = IB_WC_LOCAL_INV; 3274 break; 3275 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 3276 wc->opcode = IB_WC_REG_MR; 3277 break; 3278 default: 3279 wc->opcode = IB_WC_SEND; 3280 break; 3281 } 3282 3283 wc->status = __req_to_ib_wc_status(cqe->status); 3284 } 3285 3286 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 3287 u16 raweth_qp1_flags2) 3288 { 3289 bool is_ipv6 = false, is_ipv4 = false; 3290 3291 /* raweth_qp1_flags Bit 9-6 indicates itype */ 3292 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3293 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3294 return -1; 3295 3296 if (raweth_qp1_flags2 & 3297 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 3298 raweth_qp1_flags2 & 3299 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 3300 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 3301 (raweth_qp1_flags2 & 3302 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 3303 (is_ipv6 = true) : (is_ipv4 = true); 3304 return ((is_ipv6) ? 3305 BNXT_RE_ROCEV2_IPV6_PACKET : 3306 BNXT_RE_ROCEV2_IPV4_PACKET); 3307 } else { 3308 return BNXT_RE_ROCE_V1_PACKET; 3309 } 3310 } 3311 3312 static int bnxt_re_to_ib_nw_type(int nw_type) 3313 { 3314 u8 nw_hdr_type = 0xFF; 3315 3316 switch (nw_type) { 3317 case BNXT_RE_ROCE_V1_PACKET: 3318 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 3319 break; 3320 case BNXT_RE_ROCEV2_IPV4_PACKET: 3321 nw_hdr_type = RDMA_NETWORK_IPV4; 3322 break; 3323 case BNXT_RE_ROCEV2_IPV6_PACKET: 3324 nw_hdr_type = RDMA_NETWORK_IPV6; 3325 break; 3326 } 3327 return nw_hdr_type; 3328 } 3329 3330 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 3331 void *rq_hdr_buf) 3332 { 3333 u8 *tmp_buf = NULL; 3334 struct ethhdr *eth_hdr; 3335 u16 eth_type; 3336 bool rc = false; 3337 3338 tmp_buf = (u8 *)rq_hdr_buf; 3339 /* 3340 * If dest mac is not same as I/F mac, this could be a 3341 * loopback address or multicast address, check whether 3342 * it is a loopback packet 3343 */ 3344 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 3345 tmp_buf += 4; 3346 /* Check the ether type */ 3347 eth_hdr = (struct ethhdr *)tmp_buf; 3348 eth_type = ntohs(eth_hdr->h_proto); 3349 switch (eth_type) { 3350 case ETH_P_IBOE: 3351 rc = true; 3352 break; 3353 case ETH_P_IP: 3354 case ETH_P_IPV6: { 3355 u32 len; 3356 struct udphdr *udp_hdr; 3357 3358 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 3359 sizeof(struct ipv6hdr)); 3360 tmp_buf += sizeof(struct ethhdr) + len; 3361 udp_hdr = (struct udphdr *)tmp_buf; 3362 if (ntohs(udp_hdr->dest) == 3363 ROCE_V2_UDP_DPORT) 3364 rc = true; 3365 break; 3366 } 3367 default: 3368 break; 3369 } 3370 } 3371 3372 return rc; 3373 } 3374 3375 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp, 3376 struct bnxt_qplib_cqe *cqe) 3377 { 3378 struct bnxt_re_dev *rdev = gsi_qp->rdev; 3379 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3380 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp; 3381 dma_addr_t shrq_hdr_buf_map; 3382 struct ib_sge s_sge[2] = {}; 3383 struct ib_sge r_sge[2] = {}; 3384 struct bnxt_re_ah *gsi_sah; 3385 struct ib_recv_wr rwr = {}; 3386 dma_addr_t rq_hdr_buf_map; 3387 struct ib_ud_wr udwr = {}; 3388 struct ib_send_wr *swr; 3389 u32 skip_bytes = 0; 3390 int pkt_type = 0; 3391 void *rq_hdr_buf; 3392 u32 offset = 0; 3393 u32 tbl_idx; 3394 int rc; 3395 3396 swr = &udwr.wr; 3397 tbl_idx = cqe->wr_id; 3398 3399 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf + 3400 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size); 3401 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3402 tbl_idx); 3403 3404 /* Shadow QP header buffer */ 3405 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3406 tbl_idx); 3407 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3408 3409 /* Store this cqe */ 3410 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 3411 sqp_entry->qp1_qp = gsi_qp; 3412 3413 /* Find packet type from the cqe */ 3414 3415 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 3416 cqe->raweth_qp1_flags2); 3417 if (pkt_type < 0) { 3418 ibdev_err(&rdev->ibdev, "Invalid packet\n"); 3419 return -EINVAL; 3420 } 3421 3422 /* Adjust the offset for the user buffer and post in the rq */ 3423 3424 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 3425 offset = 20; 3426 3427 /* 3428 * QP1 loopback packet has 4 bytes of internal header before 3429 * ether header. Skip these four bytes. 3430 */ 3431 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 3432 skip_bytes = 4; 3433 3434 /* First send SGE . Skip the ether header*/ 3435 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 3436 + skip_bytes; 3437 s_sge[0].lkey = 0xFFFFFFFF; 3438 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 3439 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 3440 3441 /* Second Send SGE */ 3442 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 3443 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 3444 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 3445 s_sge[1].addr += 8; 3446 s_sge[1].lkey = 0xFFFFFFFF; 3447 s_sge[1].length = 256; 3448 3449 /* First recv SGE */ 3450 3451 r_sge[0].addr = shrq_hdr_buf_map; 3452 r_sge[0].lkey = 0xFFFFFFFF; 3453 r_sge[0].length = 40; 3454 3455 r_sge[1].addr = sqp_entry->sge.addr + offset; 3456 r_sge[1].lkey = sqp_entry->sge.lkey; 3457 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 3458 3459 /* Create receive work request */ 3460 rwr.num_sge = 2; 3461 rwr.sg_list = r_sge; 3462 rwr.wr_id = tbl_idx; 3463 rwr.next = NULL; 3464 3465 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr); 3466 if (rc) { 3467 ibdev_err(&rdev->ibdev, 3468 "Failed to post Rx buffers to shadow QP"); 3469 return -ENOMEM; 3470 } 3471 3472 swr->num_sge = 2; 3473 swr->sg_list = s_sge; 3474 swr->wr_id = tbl_idx; 3475 swr->opcode = IB_WR_SEND; 3476 swr->next = NULL; 3477 gsi_sah = rdev->gsi_ctx.gsi_sah; 3478 udwr.ah = &gsi_sah->ib_ah; 3479 udwr.remote_qpn = gsi_sqp->qplib_qp.id; 3480 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey; 3481 3482 /* post data received in the send queue */ 3483 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr); 3484 } 3485 3486 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 3487 struct bnxt_qplib_cqe *cqe) 3488 { 3489 wc->opcode = IB_WC_RECV; 3490 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 3491 wc->wc_flags |= IB_WC_GRH; 3492 } 3493 3494 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev, 3495 u16 vlan_id) 3496 { 3497 /* 3498 * Check if the vlan is configured in the host. If not configured, it 3499 * can be a transparent VLAN. So dont report the vlan id. 3500 */ 3501 if (!__vlan_find_dev_deep_rcu(rdev->netdev, 3502 htons(ETH_P_8021Q), vlan_id)) 3503 return false; 3504 return true; 3505 } 3506 3507 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 3508 u16 *vid, u8 *sl) 3509 { 3510 bool ret = false; 3511 u32 metadata; 3512 u16 tpid; 3513 3514 metadata = orig_cqe->raweth_qp1_metadata; 3515 if (orig_cqe->raweth_qp1_flags2 & 3516 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3517 tpid = ((metadata & 3518 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3519 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3520 if (tpid == ETH_P_8021Q) { 3521 *vid = metadata & 3522 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3523 *sl = (metadata & 3524 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3525 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3526 ret = true; 3527 } 3528 } 3529 3530 return ret; 3531 } 3532 3533 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3534 struct bnxt_qplib_cqe *cqe) 3535 { 3536 wc->opcode = IB_WC_RECV; 3537 wc->status = __rc_to_ib_wc_status(cqe->status); 3538 3539 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3540 wc->wc_flags |= IB_WC_WITH_IMM; 3541 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3542 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3543 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3544 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3545 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3546 } 3547 3548 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp, 3549 struct ib_wc *wc, 3550 struct bnxt_qplib_cqe *cqe) 3551 { 3552 struct bnxt_re_dev *rdev = gsi_sqp->rdev; 3553 struct bnxt_re_qp *gsi_qp = NULL; 3554 struct bnxt_qplib_cqe *orig_cqe = NULL; 3555 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3556 int nw_type; 3557 u32 tbl_idx; 3558 u16 vlan_id; 3559 u8 sl; 3560 3561 tbl_idx = cqe->wr_id; 3562 3563 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3564 gsi_qp = sqp_entry->qp1_qp; 3565 orig_cqe = &sqp_entry->cqe; 3566 3567 wc->wr_id = sqp_entry->wrid; 3568 wc->byte_len = orig_cqe->length; 3569 wc->qp = &gsi_qp->ib_qp; 3570 3571 wc->ex.imm_data = orig_cqe->immdata; 3572 wc->src_qp = orig_cqe->src_qp; 3573 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3574 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3575 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3576 wc->vlan_id = vlan_id; 3577 wc->sl = sl; 3578 wc->wc_flags |= IB_WC_WITH_VLAN; 3579 } 3580 } 3581 wc->port_num = 1; 3582 wc->vendor_err = orig_cqe->status; 3583 3584 wc->opcode = IB_WC_RECV; 3585 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3586 wc->wc_flags |= IB_WC_GRH; 3587 3588 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3589 orig_cqe->raweth_qp1_flags2); 3590 if (nw_type >= 0) { 3591 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3592 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3593 } 3594 } 3595 3596 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3597 struct ib_wc *wc, 3598 struct bnxt_qplib_cqe *cqe) 3599 { 3600 struct bnxt_re_dev *rdev; 3601 u16 vlan_id = 0; 3602 u8 nw_type; 3603 3604 rdev = qp->rdev; 3605 wc->opcode = IB_WC_RECV; 3606 wc->status = __rc_to_ib_wc_status(cqe->status); 3607 3608 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3609 wc->wc_flags |= IB_WC_WITH_IMM; 3610 /* report only on GSI QP for Thor */ 3611 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3612 wc->wc_flags |= IB_WC_GRH; 3613 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3614 wc->wc_flags |= IB_WC_WITH_SMAC; 3615 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3616 vlan_id = (cqe->cfa_meta & 0xFFF); 3617 } 3618 /* Mark only if vlan_id is non zero */ 3619 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3620 wc->vlan_id = vlan_id; 3621 wc->wc_flags |= IB_WC_WITH_VLAN; 3622 } 3623 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3624 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3625 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3626 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3627 } 3628 3629 } 3630 3631 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3632 { 3633 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3634 unsigned long flags; 3635 int rc; 3636 3637 spin_lock_irqsave(&qp->sq_lock, flags); 3638 3639 rc = bnxt_re_bind_fence_mw(lib_qp); 3640 if (!rc) { 3641 lib_qp->sq.phantom_wqe_cnt++; 3642 ibdev_dbg(&qp->rdev->ibdev, 3643 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3644 lib_qp->id, lib_qp->sq.hwq.prod, 3645 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3646 lib_qp->sq.phantom_wqe_cnt); 3647 } 3648 3649 spin_unlock_irqrestore(&qp->sq_lock, flags); 3650 return rc; 3651 } 3652 3653 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3654 { 3655 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3656 struct bnxt_re_qp *qp, *sh_qp; 3657 struct bnxt_qplib_cqe *cqe; 3658 int i, ncqe, budget; 3659 struct bnxt_qplib_q *sq; 3660 struct bnxt_qplib_qp *lib_qp; 3661 u32 tbl_idx; 3662 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3663 unsigned long flags; 3664 3665 /* User CQ; the only processing we do is to 3666 * complete any pending CQ resize operation. 3667 */ 3668 if (cq->umem) { 3669 if (cq->resize_umem) 3670 bnxt_re_resize_cq_complete(cq); 3671 return 0; 3672 } 3673 3674 spin_lock_irqsave(&cq->cq_lock, flags); 3675 budget = min_t(u32, num_entries, cq->max_cql); 3676 num_entries = budget; 3677 if (!cq->cql) { 3678 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use"); 3679 goto exit; 3680 } 3681 cqe = &cq->cql[0]; 3682 while (budget) { 3683 lib_qp = NULL; 3684 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3685 if (lib_qp) { 3686 sq = &lib_qp->sq; 3687 if (sq->send_phantom) { 3688 qp = container_of(lib_qp, 3689 struct bnxt_re_qp, qplib_qp); 3690 if (send_phantom_wqe(qp) == -ENOMEM) 3691 ibdev_err(&cq->rdev->ibdev, 3692 "Phantom failed! Scheduled to send again\n"); 3693 else 3694 sq->send_phantom = false; 3695 } 3696 } 3697 if (ncqe < budget) 3698 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3699 cqe + ncqe, 3700 budget - ncqe); 3701 3702 if (!ncqe) 3703 break; 3704 3705 for (i = 0; i < ncqe; i++, cqe++) { 3706 /* Transcribe each qplib_wqe back to ib_wc */ 3707 memset(wc, 0, sizeof(*wc)); 3708 3709 wc->wr_id = cqe->wr_id; 3710 wc->byte_len = cqe->length; 3711 qp = container_of 3712 ((struct bnxt_qplib_qp *) 3713 (unsigned long)(cqe->qp_handle), 3714 struct bnxt_re_qp, qplib_qp); 3715 wc->qp = &qp->ib_qp; 3716 wc->ex.imm_data = cqe->immdata; 3717 wc->src_qp = cqe->src_qp; 3718 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3719 wc->port_num = 1; 3720 wc->vendor_err = cqe->status; 3721 3722 switch (cqe->opcode) { 3723 case CQ_BASE_CQE_TYPE_REQ: 3724 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3725 if (sh_qp && 3726 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3727 /* Handle this completion with 3728 * the stored completion 3729 */ 3730 memset(wc, 0, sizeof(*wc)); 3731 continue; 3732 } 3733 bnxt_re_process_req_wc(wc, cqe); 3734 break; 3735 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3736 if (!cqe->status) { 3737 int rc = 0; 3738 3739 rc = bnxt_re_process_raw_qp_pkt_rx 3740 (qp, cqe); 3741 if (!rc) { 3742 memset(wc, 0, sizeof(*wc)); 3743 continue; 3744 } 3745 cqe->status = -1; 3746 } 3747 /* Errors need not be looped back. 3748 * But change the wr_id to the one 3749 * stored in the table 3750 */ 3751 tbl_idx = cqe->wr_id; 3752 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3753 wc->wr_id = sqp_entry->wrid; 3754 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3755 break; 3756 case CQ_BASE_CQE_TYPE_RES_RC: 3757 bnxt_re_process_res_rc_wc(wc, cqe); 3758 break; 3759 case CQ_BASE_CQE_TYPE_RES_UD: 3760 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3761 if (sh_qp && 3762 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3763 /* Handle this completion with 3764 * the stored completion 3765 */ 3766 if (cqe->status) { 3767 continue; 3768 } else { 3769 bnxt_re_process_res_shadow_qp_wc 3770 (qp, wc, cqe); 3771 break; 3772 } 3773 } 3774 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3775 break; 3776 default: 3777 ibdev_err(&cq->rdev->ibdev, 3778 "POLL CQ : type 0x%x not handled", 3779 cqe->opcode); 3780 continue; 3781 } 3782 wc++; 3783 budget--; 3784 } 3785 } 3786 exit: 3787 spin_unlock_irqrestore(&cq->cq_lock, flags); 3788 return num_entries - budget; 3789 } 3790 3791 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3792 enum ib_cq_notify_flags ib_cqn_flags) 3793 { 3794 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3795 int type = 0, rc = 0; 3796 unsigned long flags; 3797 3798 spin_lock_irqsave(&cq->cq_lock, flags); 3799 /* Trigger on the very next completion */ 3800 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3801 type = DBC_DBC_TYPE_CQ_ARMALL; 3802 /* Trigger on the next solicited completion */ 3803 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3804 type = DBC_DBC_TYPE_CQ_ARMSE; 3805 3806 /* Poll to see if there are missed events */ 3807 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3808 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3809 rc = 1; 3810 goto exit; 3811 } 3812 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3813 3814 exit: 3815 spin_unlock_irqrestore(&cq->cq_lock, flags); 3816 return rc; 3817 } 3818 3819 /* Memory Regions */ 3820 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3821 { 3822 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3823 struct bnxt_re_dev *rdev = pd->rdev; 3824 struct bnxt_re_mr *mr; 3825 u32 active_mrs; 3826 int rc; 3827 3828 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3829 if (!mr) 3830 return ERR_PTR(-ENOMEM); 3831 3832 mr->rdev = rdev; 3833 mr->qplib_mr.pd = &pd->qplib_pd; 3834 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3835 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3836 3837 /* Allocate and register 0 as the address */ 3838 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3839 if (rc) 3840 goto fail; 3841 3842 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3843 mr->qplib_mr.total_size = -1; /* Infinte length */ 3844 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0, 3845 PAGE_SIZE); 3846 if (rc) 3847 goto fail_mr; 3848 3849 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3850 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3851 IB_ACCESS_REMOTE_ATOMIC)) 3852 mr->ib_mr.rkey = mr->ib_mr.lkey; 3853 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 3854 if (active_mrs > rdev->stats.res.mr_watermark) 3855 rdev->stats.res.mr_watermark = active_mrs; 3856 3857 return &mr->ib_mr; 3858 3859 fail_mr: 3860 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3861 fail: 3862 kfree(mr); 3863 return ERR_PTR(rc); 3864 } 3865 3866 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3867 { 3868 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3869 struct bnxt_re_dev *rdev = mr->rdev; 3870 int rc; 3871 3872 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3873 if (rc) { 3874 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc); 3875 return rc; 3876 } 3877 3878 if (mr->pages) { 3879 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3880 &mr->qplib_frpl); 3881 kfree(mr->pages); 3882 mr->npages = 0; 3883 mr->pages = NULL; 3884 } 3885 ib_umem_release(mr->ib_umem); 3886 3887 kfree(mr); 3888 atomic_dec(&rdev->stats.res.mr_count); 3889 return rc; 3890 } 3891 3892 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3893 { 3894 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3895 3896 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3897 return -ENOMEM; 3898 3899 mr->pages[mr->npages++] = addr; 3900 return 0; 3901 } 3902 3903 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3904 unsigned int *sg_offset) 3905 { 3906 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3907 3908 mr->npages = 0; 3909 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3910 } 3911 3912 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3913 u32 max_num_sg) 3914 { 3915 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3916 struct bnxt_re_dev *rdev = pd->rdev; 3917 struct bnxt_re_mr *mr = NULL; 3918 u32 active_mrs; 3919 int rc; 3920 3921 if (type != IB_MR_TYPE_MEM_REG) { 3922 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type); 3923 return ERR_PTR(-EINVAL); 3924 } 3925 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3926 return ERR_PTR(-EINVAL); 3927 3928 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3929 if (!mr) 3930 return ERR_PTR(-ENOMEM); 3931 3932 mr->rdev = rdev; 3933 mr->qplib_mr.pd = &pd->qplib_pd; 3934 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3935 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3936 3937 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3938 if (rc) 3939 goto bail; 3940 3941 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3942 mr->ib_mr.rkey = mr->ib_mr.lkey; 3943 3944 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3945 if (!mr->pages) { 3946 rc = -ENOMEM; 3947 goto fail; 3948 } 3949 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3950 &mr->qplib_frpl, max_num_sg); 3951 if (rc) { 3952 ibdev_err(&rdev->ibdev, 3953 "Failed to allocate HW FR page list"); 3954 goto fail_mr; 3955 } 3956 3957 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 3958 if (active_mrs > rdev->stats.res.mr_watermark) 3959 rdev->stats.res.mr_watermark = active_mrs; 3960 return &mr->ib_mr; 3961 3962 fail_mr: 3963 kfree(mr->pages); 3964 fail: 3965 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3966 bail: 3967 kfree(mr); 3968 return ERR_PTR(rc); 3969 } 3970 3971 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3972 struct ib_udata *udata) 3973 { 3974 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3975 struct bnxt_re_dev *rdev = pd->rdev; 3976 struct bnxt_re_mw *mw; 3977 u32 active_mws; 3978 int rc; 3979 3980 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3981 if (!mw) 3982 return ERR_PTR(-ENOMEM); 3983 mw->rdev = rdev; 3984 mw->qplib_mw.pd = &pd->qplib_pd; 3985 3986 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3987 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3988 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3989 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3990 if (rc) { 3991 ibdev_err(&rdev->ibdev, "Allocate MW failed!"); 3992 goto fail; 3993 } 3994 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3995 3996 active_mws = atomic_inc_return(&rdev->stats.res.mw_count); 3997 if (active_mws > rdev->stats.res.mw_watermark) 3998 rdev->stats.res.mw_watermark = active_mws; 3999 return &mw->ib_mw; 4000 4001 fail: 4002 kfree(mw); 4003 return ERR_PTR(rc); 4004 } 4005 4006 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 4007 { 4008 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 4009 struct bnxt_re_dev *rdev = mw->rdev; 4010 int rc; 4011 4012 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 4013 if (rc) { 4014 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc); 4015 return rc; 4016 } 4017 4018 kfree(mw); 4019 atomic_dec(&rdev->stats.res.mw_count); 4020 return rc; 4021 } 4022 4023 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr, 4024 int mr_access_flags, struct ib_umem *umem) 4025 { 4026 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4027 struct bnxt_re_dev *rdev = pd->rdev; 4028 unsigned long page_size; 4029 struct bnxt_re_mr *mr; 4030 int umem_pgs, rc; 4031 u32 active_mrs; 4032 4033 if (length > BNXT_RE_MAX_MR_SIZE) { 4034 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n", 4035 length, BNXT_RE_MAX_MR_SIZE); 4036 return ERR_PTR(-ENOMEM); 4037 } 4038 4039 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr); 4040 if (!page_size) { 4041 ibdev_err(&rdev->ibdev, "umem page size unsupported!"); 4042 return ERR_PTR(-EINVAL); 4043 } 4044 4045 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 4046 if (!mr) 4047 return ERR_PTR(-ENOMEM); 4048 4049 mr->rdev = rdev; 4050 mr->qplib_mr.pd = &pd->qplib_pd; 4051 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 4052 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 4053 4054 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4055 if (rc) { 4056 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc); 4057 rc = -EIO; 4058 goto free_mr; 4059 } 4060 /* The fixed portion of the rkey is the same as the lkey */ 4061 mr->ib_mr.rkey = mr->qplib_mr.rkey; 4062 mr->ib_umem = umem; 4063 mr->qplib_mr.va = virt_addr; 4064 mr->qplib_mr.total_size = length; 4065 4066 umem_pgs = ib_umem_num_dma_blocks(umem, page_size); 4067 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem, 4068 umem_pgs, page_size); 4069 if (rc) { 4070 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc); 4071 rc = -EIO; 4072 goto free_mrw; 4073 } 4074 4075 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4076 mr->ib_mr.rkey = mr->qplib_mr.lkey; 4077 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4078 if (active_mrs > rdev->stats.res.mr_watermark) 4079 rdev->stats.res.mr_watermark = active_mrs; 4080 4081 return &mr->ib_mr; 4082 4083 free_mrw: 4084 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4085 free_mr: 4086 kfree(mr); 4087 return ERR_PTR(rc); 4088 } 4089 4090 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 4091 u64 virt_addr, int mr_access_flags, 4092 struct ib_udata *udata) 4093 { 4094 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4095 struct bnxt_re_dev *rdev = pd->rdev; 4096 struct ib_umem *umem; 4097 struct ib_mr *ib_mr; 4098 4099 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags); 4100 if (IS_ERR(umem)) 4101 return ERR_CAST(umem); 4102 4103 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4104 if (IS_ERR(ib_mr)) 4105 ib_umem_release(umem); 4106 return ib_mr; 4107 } 4108 4109 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start, 4110 u64 length, u64 virt_addr, int fd, 4111 int mr_access_flags, struct ib_udata *udata) 4112 { 4113 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4114 struct bnxt_re_dev *rdev = pd->rdev; 4115 struct ib_umem_dmabuf *umem_dmabuf; 4116 struct ib_umem *umem; 4117 struct ib_mr *ib_mr; 4118 4119 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length, 4120 fd, mr_access_flags); 4121 if (IS_ERR(umem_dmabuf)) 4122 return ERR_CAST(umem_dmabuf); 4123 4124 umem = &umem_dmabuf->umem; 4125 4126 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4127 if (IS_ERR(ib_mr)) 4128 ib_umem_release(umem); 4129 return ib_mr; 4130 } 4131 4132 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 4133 { 4134 struct ib_device *ibdev = ctx->device; 4135 struct bnxt_re_ucontext *uctx = 4136 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 4137 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4138 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 4139 struct bnxt_re_user_mmap_entry *entry; 4140 struct bnxt_re_uctx_resp resp = {}; 4141 struct bnxt_re_uctx_req ureq = {}; 4142 u32 chip_met_rev_num = 0; 4143 int rc; 4144 4145 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver); 4146 4147 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 4148 ibdev_dbg(ibdev, " is different from the device %d ", 4149 BNXT_RE_ABI_VERSION); 4150 return -EPERM; 4151 } 4152 4153 uctx->rdev = rdev; 4154 4155 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 4156 if (!uctx->shpg) { 4157 rc = -ENOMEM; 4158 goto fail; 4159 } 4160 spin_lock_init(&uctx->sh_lock); 4161 4162 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 4163 chip_met_rev_num = rdev->chip_ctx->chip_num; 4164 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) << 4165 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 4166 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) << 4167 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 4168 resp.chip_id0 = chip_met_rev_num; 4169 /*Temp, Use xa_alloc instead */ 4170 resp.dev_id = rdev->en_dev->pdev->devfn; 4171 resp.max_qp = rdev->qplib_ctx.qpc_count; 4172 resp.pg_size = PAGE_SIZE; 4173 resp.cqe_sz = sizeof(struct cq_base); 4174 resp.max_cqd = dev_attr->max_cq_wqes; 4175 4176 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE; 4177 resp.mode = rdev->chip_ctx->modes.wqe_mode; 4178 4179 if (rdev->chip_ctx->modes.db_push) 4180 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED; 4181 4182 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL); 4183 if (!entry) { 4184 rc = -ENOMEM; 4185 goto cfail; 4186 } 4187 uctx->shpage_mmap = &entry->rdma_entry; 4188 if (rdev->pacing.dbr_pacing) 4189 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED; 4190 4191 if (udata->inlen >= sizeof(ureq)) { 4192 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))); 4193 if (rc) 4194 goto cfail; 4195 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) { 4196 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4197 uctx->cmask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4198 } 4199 } 4200 4201 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 4202 if (rc) { 4203 ibdev_err(ibdev, "Failed to copy user context"); 4204 rc = -EFAULT; 4205 goto cfail; 4206 } 4207 4208 return 0; 4209 cfail: 4210 free_page((unsigned long)uctx->shpg); 4211 uctx->shpg = NULL; 4212 fail: 4213 return rc; 4214 } 4215 4216 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 4217 { 4218 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4219 struct bnxt_re_ucontext, 4220 ib_uctx); 4221 4222 struct bnxt_re_dev *rdev = uctx->rdev; 4223 4224 rdma_user_mmap_entry_remove(uctx->shpage_mmap); 4225 uctx->shpage_mmap = NULL; 4226 if (uctx->shpg) 4227 free_page((unsigned long)uctx->shpg); 4228 4229 if (uctx->dpi.dbr) { 4230 /* Free DPI only if this is the first PD allocated by the 4231 * application and mark the context dpi as NULL 4232 */ 4233 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi); 4234 uctx->dpi.dbr = NULL; 4235 } 4236 } 4237 4238 static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id) 4239 { 4240 struct bnxt_re_cq *cq = NULL, *tmp_cq; 4241 4242 hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) { 4243 if (tmp_cq->qplib_cq.id == cq_id) { 4244 cq = tmp_cq; 4245 break; 4246 } 4247 } 4248 return cq; 4249 } 4250 4251 /* Helper function to mmap the virtual memory from user app */ 4252 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 4253 { 4254 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4255 struct bnxt_re_ucontext, 4256 ib_uctx); 4257 struct bnxt_re_user_mmap_entry *bnxt_entry; 4258 struct rdma_user_mmap_entry *rdma_entry; 4259 int ret = 0; 4260 u64 pfn; 4261 4262 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma); 4263 if (!rdma_entry) 4264 return -EINVAL; 4265 4266 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4267 rdma_entry); 4268 4269 switch (bnxt_entry->mmap_flag) { 4270 case BNXT_RE_MMAP_WC_DB: 4271 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4272 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4273 pgprot_writecombine(vma->vm_page_prot), 4274 rdma_entry); 4275 break; 4276 case BNXT_RE_MMAP_UC_DB: 4277 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4278 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4279 pgprot_noncached(vma->vm_page_prot), 4280 rdma_entry); 4281 break; 4282 case BNXT_RE_MMAP_SH_PAGE: 4283 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg)); 4284 break; 4285 case BNXT_RE_MMAP_DBR_BAR: 4286 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4287 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4288 pgprot_noncached(vma->vm_page_prot), 4289 rdma_entry); 4290 break; 4291 case BNXT_RE_MMAP_DBR_PAGE: 4292 case BNXT_RE_MMAP_TOGGLE_PAGE: 4293 /* Driver doesn't expect write access for user space */ 4294 if (vma->vm_flags & VM_WRITE) 4295 return -EFAULT; 4296 ret = vm_insert_page(vma, vma->vm_start, 4297 virt_to_page((void *)bnxt_entry->mem_offset)); 4298 break; 4299 default: 4300 ret = -EINVAL; 4301 break; 4302 } 4303 4304 rdma_user_mmap_entry_put(rdma_entry); 4305 return ret; 4306 } 4307 4308 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 4309 { 4310 struct bnxt_re_user_mmap_entry *bnxt_entry; 4311 4312 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4313 rdma_entry); 4314 4315 kfree(bnxt_entry); 4316 } 4317 4318 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs) 4319 { 4320 struct bnxt_re_ucontext *uctx; 4321 4322 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4323 bnxt_re_pacing_alert(uctx->rdev); 4324 return 0; 4325 } 4326 4327 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs) 4328 { 4329 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4330 enum bnxt_re_alloc_page_type alloc_type; 4331 struct bnxt_re_user_mmap_entry *entry; 4332 enum bnxt_re_mmap_flag mmap_flag; 4333 struct bnxt_qplib_chip_ctx *cctx; 4334 struct bnxt_re_ucontext *uctx; 4335 struct bnxt_re_dev *rdev; 4336 u64 mmap_offset; 4337 u32 length; 4338 u32 dpi; 4339 u64 addr; 4340 int err; 4341 4342 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4343 if (IS_ERR(uctx)) 4344 return PTR_ERR(uctx); 4345 4346 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE); 4347 if (err) 4348 return err; 4349 4350 rdev = uctx->rdev; 4351 cctx = rdev->chip_ctx; 4352 4353 switch (alloc_type) { 4354 case BNXT_RE_ALLOC_WC_PAGE: 4355 if (cctx->modes.db_push) { 4356 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi, 4357 uctx, BNXT_QPLIB_DPI_TYPE_WC)) 4358 return -ENOMEM; 4359 length = PAGE_SIZE; 4360 dpi = uctx->wcdpi.dpi; 4361 addr = (u64)uctx->wcdpi.umdbr; 4362 mmap_flag = BNXT_RE_MMAP_WC_DB; 4363 } else { 4364 return -EINVAL; 4365 } 4366 4367 break; 4368 case BNXT_RE_ALLOC_DBR_BAR_PAGE: 4369 length = PAGE_SIZE; 4370 addr = (u64)rdev->pacing.dbr_bar_addr; 4371 mmap_flag = BNXT_RE_MMAP_DBR_BAR; 4372 break; 4373 4374 case BNXT_RE_ALLOC_DBR_PAGE: 4375 length = PAGE_SIZE; 4376 addr = (u64)rdev->pacing.dbr_page; 4377 mmap_flag = BNXT_RE_MMAP_DBR_PAGE; 4378 break; 4379 4380 default: 4381 return -EOPNOTSUPP; 4382 } 4383 4384 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset); 4385 if (!entry) 4386 return -ENOMEM; 4387 4388 uobj->object = entry; 4389 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4390 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4391 &mmap_offset, sizeof(mmap_offset)); 4392 if (err) 4393 return err; 4394 4395 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4396 &length, sizeof(length)); 4397 if (err) 4398 return err; 4399 4400 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI, 4401 &dpi, sizeof(length)); 4402 if (err) 4403 return err; 4404 4405 return 0; 4406 } 4407 4408 static int alloc_page_obj_cleanup(struct ib_uobject *uobject, 4409 enum rdma_remove_reason why, 4410 struct uverbs_attr_bundle *attrs) 4411 { 4412 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4413 struct bnxt_re_ucontext *uctx = entry->uctx; 4414 4415 switch (entry->mmap_flag) { 4416 case BNXT_RE_MMAP_WC_DB: 4417 if (uctx && uctx->wcdpi.dbr) { 4418 struct bnxt_re_dev *rdev = uctx->rdev; 4419 4420 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi); 4421 uctx->wcdpi.dbr = NULL; 4422 } 4423 break; 4424 case BNXT_RE_MMAP_DBR_BAR: 4425 case BNXT_RE_MMAP_DBR_PAGE: 4426 break; 4427 default: 4428 goto exit; 4429 } 4430 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4431 exit: 4432 return 0; 4433 } 4434 4435 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE, 4436 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE, 4437 BNXT_RE_OBJECT_ALLOC_PAGE, 4438 UVERBS_ACCESS_NEW, 4439 UA_MANDATORY), 4440 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE, 4441 enum bnxt_re_alloc_page_type, 4442 UA_MANDATORY), 4443 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4444 UVERBS_ATTR_TYPE(u64), 4445 UA_MANDATORY), 4446 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4447 UVERBS_ATTR_TYPE(u32), 4448 UA_MANDATORY), 4449 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI, 4450 UVERBS_ATTR_TYPE(u32), 4451 UA_MANDATORY)); 4452 4453 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE, 4454 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE, 4455 BNXT_RE_OBJECT_ALLOC_PAGE, 4456 UVERBS_ACCESS_DESTROY, 4457 UA_MANDATORY)); 4458 4459 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE, 4460 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup), 4461 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE), 4462 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE)); 4463 4464 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV); 4465 4466 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV, 4467 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV)); 4468 4469 /* Toggle MEM */ 4470 static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs) 4471 { 4472 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4473 enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE; 4474 enum bnxt_re_get_toggle_mem_type res_type; 4475 struct bnxt_re_user_mmap_entry *entry; 4476 struct bnxt_re_ucontext *uctx; 4477 struct ib_ucontext *ib_uctx; 4478 struct bnxt_re_dev *rdev; 4479 struct bnxt_re_cq *cq; 4480 u64 mem_offset; 4481 u64 addr = 0; 4482 u32 length; 4483 u32 offset; 4484 u32 cq_id; 4485 int err; 4486 4487 ib_uctx = ib_uverbs_get_ucontext(attrs); 4488 if (IS_ERR(ib_uctx)) 4489 return PTR_ERR(ib_uctx); 4490 4491 err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE); 4492 if (err) 4493 return err; 4494 4495 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx); 4496 rdev = uctx->rdev; 4497 4498 switch (res_type) { 4499 case BNXT_RE_CQ_TOGGLE_MEM: 4500 err = uverbs_copy_from(&cq_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID); 4501 if (err) 4502 return err; 4503 4504 cq = bnxt_re_search_for_cq(rdev, cq_id); 4505 if (!cq) 4506 return -EINVAL; 4507 4508 length = PAGE_SIZE; 4509 addr = (u64)cq->uctx_cq_page; 4510 mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE; 4511 offset = 0; 4512 break; 4513 case BNXT_RE_SRQ_TOGGLE_MEM: 4514 break; 4515 4516 default: 4517 return -EOPNOTSUPP; 4518 } 4519 4520 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset); 4521 if (!entry) 4522 return -ENOMEM; 4523 4524 uobj->object = entry; 4525 uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE); 4526 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4527 &mem_offset, sizeof(mem_offset)); 4528 if (err) 4529 return err; 4530 4531 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4532 &length, sizeof(length)); 4533 if (err) 4534 return err; 4535 4536 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4537 &offset, sizeof(length)); 4538 if (err) 4539 return err; 4540 4541 return 0; 4542 } 4543 4544 static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject, 4545 enum rdma_remove_reason why, 4546 struct uverbs_attr_bundle *attrs) 4547 { 4548 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4549 4550 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4551 return 0; 4552 } 4553 4554 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM, 4555 UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE, 4556 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4557 UVERBS_ACCESS_NEW, 4558 UA_MANDATORY), 4559 UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE, 4560 enum bnxt_re_get_toggle_mem_type, 4561 UA_MANDATORY), 4562 UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID, 4563 UVERBS_ATTR_TYPE(u32), 4564 UA_MANDATORY), 4565 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 4566 UVERBS_ATTR_TYPE(u64), 4567 UA_MANDATORY), 4568 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 4569 UVERBS_ATTR_TYPE(u32), 4570 UA_MANDATORY), 4571 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 4572 UVERBS_ATTR_TYPE(u32), 4573 UA_MANDATORY)); 4574 4575 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM, 4576 UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE, 4577 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4578 UVERBS_ACCESS_DESTROY, 4579 UA_MANDATORY)); 4580 4581 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM, 4582 UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup), 4583 &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM), 4584 &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM)); 4585 4586 const struct uapi_definition bnxt_re_uapi_defs[] = { 4587 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE), 4588 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV), 4589 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM), 4590 {} 4591 }; 4592