1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (c) 2025 Broadcom. 3 4 #ifndef __BNG_RES_H__ 5 #define __BNG_RES_H__ 6 7 #define BNG_ROCE_FW_MAX_TIMEOUT 60 8 9 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *)) 10 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1) 11 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG) 12 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG) 13 14 #define MAX_PBL_LVL_0_PGS 1 15 #define MAX_PBL_LVL_1_PGS 512 16 #define MAX_PBL_LVL_1_PGS_SHIFT 9 17 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256 18 #define MAX_PBL_LVL_2_PGS (256 * 512) 19 #define MAX_PDL_LVL_SHIFT 9 20 21 struct bng_re_chip_ctx { 22 u16 chip_num; 23 u16 hw_stats_size; 24 u64 hwrm_intf_ver; 25 u16 hwrm_cmd_max_timeout; 26 }; 27 28 struct bng_re_pbl { 29 u32 pg_count; 30 u32 pg_size; 31 void **pg_arr; 32 dma_addr_t *pg_map_arr; 33 }; 34 35 enum bng_re_pbl_lvl { 36 BNG_PBL_LVL_0, 37 BNG_PBL_LVL_1, 38 BNG_PBL_LVL_2, 39 BNG_PBL_LVL_MAX 40 }; 41 42 enum bng_re_hwq_type { 43 BNG_HWQ_TYPE_CTX, 44 BNG_HWQ_TYPE_QUEUE 45 }; 46 47 struct bng_re_sg_info { 48 u32 npages; 49 u32 pgshft; 50 u32 pgsize; 51 bool nopte; 52 }; 53 54 struct bng_re_hwq_attr { 55 struct bng_re_res *res; 56 struct bng_re_sg_info *sginfo; 57 enum bng_re_hwq_type type; 58 u32 depth; 59 u32 stride; 60 u32 aux_stride; 61 u32 aux_depth; 62 }; 63 64 struct bng_re_hwq { 65 struct pci_dev *pdev; 66 /* lock to protect hwq */ 67 spinlock_t lock; 68 struct bng_re_pbl pbl[BNG_PBL_LVL_MAX + 1]; 69 /* Valid values: 0, 1, 2 */ 70 enum bng_re_pbl_lvl level; 71 /* PBL entries */ 72 void **pbl_ptr; 73 /* PBL dma_addr */ 74 dma_addr_t *pbl_dma_ptr; 75 u32 max_elements; 76 u32 depth; 77 u16 element_size; 78 u32 prod; 79 u32 cons; 80 }; 81 82 struct bng_re_res { 83 struct pci_dev *pdev; 84 struct bng_re_chip_ctx *cctx; 85 }; 86 87 void bng_re_free_hwq(struct bng_re_res *res, 88 struct bng_re_hwq *hwq); 89 90 int bng_re_alloc_init_hwq(struct bng_re_hwq *hwq, 91 struct bng_re_hwq_attr *hwq_attr); 92 #endif 93