1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2016 4 * 5 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 6 * 7 */ 8 9 #include <linux/iio/iio.h> 10 #include <linux/iio/sysfs.h> 11 #include <linux/iio/timer/stm32-timer-trigger.h> 12 #include <linux/iio/trigger.h> 13 #include <linux/mfd/stm32-timers.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/of_device.h> 17 18 #define MAX_TRIGGERS 7 19 #define MAX_VALIDS 5 20 21 /* List the triggers created by each timer */ 22 static const void *triggers_table[][MAX_TRIGGERS] = { 23 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, 24 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,}, 25 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,}, 26 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,}, 27 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,}, 28 { TIM6_TRGO,}, 29 { TIM7_TRGO,}, 30 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, 31 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,}, 32 { TIM10_OC1,}, 33 { TIM11_OC1,}, 34 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,}, 35 { TIM13_OC1,}, 36 { TIM14_OC1,}, 37 { TIM15_TRGO,}, 38 { TIM16_OC1,}, 39 { TIM17_OC1,}, 40 }; 41 42 /* List the triggers accepted by each timer */ 43 static const void *valids_table[][MAX_VALIDS] = { 44 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 45 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 46 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,}, 47 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 48 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,}, 49 { }, /* timer 6 */ 50 { }, /* timer 7 */ 51 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 52 { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,}, 53 { }, /* timer 10 */ 54 { }, /* timer 11 */ 55 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,}, 56 }; 57 58 static const void *stm32h7_valids_table[][MAX_VALIDS] = { 59 { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 60 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 61 { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,}, 62 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 63 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 64 { }, /* timer 6 */ 65 { }, /* timer 7 */ 66 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 67 { }, /* timer 9 */ 68 { }, /* timer 10 */ 69 { }, /* timer 11 */ 70 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,}, 71 { }, /* timer 13 */ 72 { }, /* timer 14 */ 73 { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,}, 74 { }, /* timer 16 */ 75 { }, /* timer 17 */ 76 }; 77 78 struct stm32_timer_trigger_regs { 79 u32 cr1; 80 u32 cr2; 81 u32 psc; 82 u32 arr; 83 u32 cnt; 84 u32 smcr; 85 }; 86 87 struct stm32_timer_trigger { 88 struct device *dev; 89 struct regmap *regmap; 90 struct clk *clk; 91 bool enabled; 92 u32 max_arr; 93 const void *triggers; 94 const void *valids; 95 bool has_trgo2; 96 struct mutex lock; /* concurrent sysfs configuration */ 97 struct list_head tr_list; 98 struct stm32_timer_trigger_regs bak; 99 }; 100 101 struct stm32_timer_trigger_cfg { 102 const void *(*valids_table)[MAX_VALIDS]; 103 const unsigned int num_valids_table; 104 }; 105 106 static bool stm32_timer_is_trgo2_name(const char *name) 107 { 108 return !!strstr(name, "trgo2"); 109 } 110 111 static bool stm32_timer_is_trgo_name(const char *name) 112 { 113 return (!!strstr(name, "trgo") && !strstr(name, "trgo2")); 114 } 115 116 static int stm32_timer_start(struct stm32_timer_trigger *priv, 117 struct iio_trigger *trig, 118 unsigned int frequency) 119 { 120 unsigned long long prd, div; 121 int prescaler = 0; 122 u32 ccer; 123 124 /* Period and prescaler values depends of clock rate */ 125 div = (unsigned long long)clk_get_rate(priv->clk); 126 127 do_div(div, frequency); 128 129 prd = div; 130 131 /* 132 * Increase prescaler value until we get a result that fit 133 * with auto reload register maximum value. 134 */ 135 while (div > priv->max_arr) { 136 prescaler++; 137 div = prd; 138 do_div(div, (prescaler + 1)); 139 } 140 prd = div; 141 142 if (prescaler > MAX_TIM_PSC) { 143 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); 144 return -EINVAL; 145 } 146 147 /* Check if nobody else use the timer */ 148 regmap_read(priv->regmap, TIM_CCER, &ccer); 149 if (ccer & TIM_CCER_CCXE) 150 return -EBUSY; 151 152 mutex_lock(&priv->lock); 153 if (!priv->enabled) { 154 priv->enabled = true; 155 clk_enable(priv->clk); 156 } 157 158 regmap_write(priv->regmap, TIM_PSC, prescaler); 159 regmap_write(priv->regmap, TIM_ARR, prd - 1); 160 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 161 162 /* Force master mode to update mode */ 163 if (stm32_timer_is_trgo2_name(trig->name)) 164 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 165 0x2 << TIM_CR2_MMS2_SHIFT); 166 else 167 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 168 0x2 << TIM_CR2_MMS_SHIFT); 169 170 /* Make sure that registers are updated */ 171 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 172 173 /* Enable controller */ 174 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); 175 mutex_unlock(&priv->lock); 176 177 return 0; 178 } 179 180 static void stm32_timer_stop(struct stm32_timer_trigger *priv) 181 { 182 u32 ccer; 183 184 regmap_read(priv->regmap, TIM_CCER, &ccer); 185 if (ccer & TIM_CCER_CCXE) 186 return; 187 188 mutex_lock(&priv->lock); 189 /* Stop timer */ 190 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); 191 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 192 regmap_write(priv->regmap, TIM_PSC, 0); 193 regmap_write(priv->regmap, TIM_ARR, 0); 194 195 /* Make sure that registers are updated */ 196 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 197 198 if (priv->enabled) { 199 priv->enabled = false; 200 clk_disable(priv->clk); 201 } 202 mutex_unlock(&priv->lock); 203 } 204 205 static ssize_t stm32_tt_store_frequency(struct device *dev, 206 struct device_attribute *attr, 207 const char *buf, size_t len) 208 { 209 struct iio_trigger *trig = to_iio_trigger(dev); 210 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 211 unsigned int freq; 212 int ret; 213 214 ret = kstrtouint(buf, 10, &freq); 215 if (ret) 216 return ret; 217 218 if (freq == 0) { 219 stm32_timer_stop(priv); 220 } else { 221 ret = stm32_timer_start(priv, trig, freq); 222 if (ret) 223 return ret; 224 } 225 226 return len; 227 } 228 229 static ssize_t stm32_tt_read_frequency(struct device *dev, 230 struct device_attribute *attr, char *buf) 231 { 232 struct iio_trigger *trig = to_iio_trigger(dev); 233 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 234 u32 psc, arr, cr1; 235 unsigned long long freq = 0; 236 237 regmap_read(priv->regmap, TIM_CR1, &cr1); 238 regmap_read(priv->regmap, TIM_PSC, &psc); 239 regmap_read(priv->regmap, TIM_ARR, &arr); 240 241 if (cr1 & TIM_CR1_CEN) { 242 freq = (unsigned long long)clk_get_rate(priv->clk); 243 do_div(freq, psc + 1); 244 do_div(freq, arr + 1); 245 } 246 247 return sprintf(buf, "%d\n", (unsigned int)freq); 248 } 249 250 static IIO_DEV_ATTR_SAMP_FREQ(0660, 251 stm32_tt_read_frequency, 252 stm32_tt_store_frequency); 253 254 #define MASTER_MODE_MAX 7 255 #define MASTER_MODE2_MAX 15 256 257 static char *master_mode_table[] = { 258 "reset", 259 "enable", 260 "update", 261 "compare_pulse", 262 "OC1REF", 263 "OC2REF", 264 "OC3REF", 265 "OC4REF", 266 /* Master mode selection 2 only */ 267 "OC5REF", 268 "OC6REF", 269 "compare_pulse_OC4REF", 270 "compare_pulse_OC6REF", 271 "compare_pulse_OC4REF_r_or_OC6REF_r", 272 "compare_pulse_OC4REF_r_or_OC6REF_f", 273 "compare_pulse_OC5REF_r_or_OC6REF_r", 274 "compare_pulse_OC5REF_r_or_OC6REF_f", 275 }; 276 277 static ssize_t stm32_tt_show_master_mode(struct device *dev, 278 struct device_attribute *attr, 279 char *buf) 280 { 281 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 282 struct iio_trigger *trig = to_iio_trigger(dev); 283 u32 cr2; 284 285 regmap_read(priv->regmap, TIM_CR2, &cr2); 286 287 if (stm32_timer_is_trgo2_name(trig->name)) 288 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT; 289 else 290 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; 291 292 return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]); 293 } 294 295 static ssize_t stm32_tt_store_master_mode(struct device *dev, 296 struct device_attribute *attr, 297 const char *buf, size_t len) 298 { 299 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 300 struct iio_trigger *trig = to_iio_trigger(dev); 301 u32 mask, shift, master_mode_max; 302 int i; 303 304 if (stm32_timer_is_trgo2_name(trig->name)) { 305 mask = TIM_CR2_MMS2; 306 shift = TIM_CR2_MMS2_SHIFT; 307 master_mode_max = MASTER_MODE2_MAX; 308 } else { 309 mask = TIM_CR2_MMS; 310 shift = TIM_CR2_MMS_SHIFT; 311 master_mode_max = MASTER_MODE_MAX; 312 } 313 314 for (i = 0; i <= master_mode_max; i++) { 315 if (!strncmp(master_mode_table[i], buf, 316 strlen(master_mode_table[i]))) { 317 mutex_lock(&priv->lock); 318 if (!priv->enabled) { 319 /* Clock should be enabled first */ 320 priv->enabled = true; 321 clk_enable(priv->clk); 322 } 323 regmap_update_bits(priv->regmap, TIM_CR2, mask, 324 i << shift); 325 mutex_unlock(&priv->lock); 326 return len; 327 } 328 } 329 330 return -EINVAL; 331 } 332 333 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev, 334 struct device_attribute *attr, 335 char *buf) 336 { 337 struct iio_trigger *trig = to_iio_trigger(dev); 338 unsigned int i, master_mode_max; 339 size_t len = 0; 340 341 if (stm32_timer_is_trgo2_name(trig->name)) 342 master_mode_max = MASTER_MODE2_MAX; 343 else 344 master_mode_max = MASTER_MODE_MAX; 345 346 for (i = 0; i <= master_mode_max; i++) 347 len += scnprintf(buf + len, PAGE_SIZE - len, 348 "%s ", master_mode_table[i]); 349 350 /* replace trailing space by newline */ 351 buf[len - 1] = '\n'; 352 353 return len; 354 } 355 356 static IIO_DEVICE_ATTR(master_mode_available, 0444, 357 stm32_tt_show_master_mode_avail, NULL, 0); 358 359 static IIO_DEVICE_ATTR(master_mode, 0660, 360 stm32_tt_show_master_mode, 361 stm32_tt_store_master_mode, 362 0); 363 364 static struct attribute *stm32_trigger_attrs[] = { 365 &iio_dev_attr_sampling_frequency.dev_attr.attr, 366 &iio_dev_attr_master_mode.dev_attr.attr, 367 &iio_dev_attr_master_mode_available.dev_attr.attr, 368 NULL, 369 }; 370 371 static const struct attribute_group stm32_trigger_attr_group = { 372 .attrs = stm32_trigger_attrs, 373 }; 374 375 static const struct attribute_group *stm32_trigger_attr_groups[] = { 376 &stm32_trigger_attr_group, 377 NULL, 378 }; 379 380 static const struct iio_trigger_ops timer_trigger_ops = { 381 }; 382 383 static void stm32_unregister_iio_triggers(struct stm32_timer_trigger *priv) 384 { 385 struct iio_trigger *tr; 386 387 list_for_each_entry(tr, &priv->tr_list, alloc_list) 388 iio_trigger_unregister(tr); 389 } 390 391 static int stm32_register_iio_triggers(struct stm32_timer_trigger *priv) 392 { 393 int ret; 394 const char * const *cur = priv->triggers; 395 396 INIT_LIST_HEAD(&priv->tr_list); 397 398 while (cur && *cur) { 399 struct iio_trigger *trig; 400 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur); 401 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur); 402 403 if (cur_is_trgo2 && !priv->has_trgo2) { 404 cur++; 405 continue; 406 } 407 408 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); 409 if (!trig) 410 return -ENOMEM; 411 412 trig->dev.parent = priv->dev->parent; 413 trig->ops = &timer_trigger_ops; 414 415 /* 416 * sampling frequency and master mode attributes 417 * should only be available on trgo/trgo2 triggers 418 */ 419 if (cur_is_trgo || cur_is_trgo2) 420 trig->dev.groups = stm32_trigger_attr_groups; 421 422 iio_trigger_set_drvdata(trig, priv); 423 424 ret = iio_trigger_register(trig); 425 if (ret) { 426 stm32_unregister_iio_triggers(priv); 427 return ret; 428 } 429 430 list_add_tail(&trig->alloc_list, &priv->tr_list); 431 cur++; 432 } 433 434 return 0; 435 } 436 437 static int stm32_counter_read_raw(struct iio_dev *indio_dev, 438 struct iio_chan_spec const *chan, 439 int *val, int *val2, long mask) 440 { 441 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 442 u32 dat; 443 444 switch (mask) { 445 case IIO_CHAN_INFO_RAW: 446 regmap_read(priv->regmap, TIM_CNT, &dat); 447 *val = dat; 448 return IIO_VAL_INT; 449 450 case IIO_CHAN_INFO_ENABLE: 451 regmap_read(priv->regmap, TIM_CR1, &dat); 452 *val = (dat & TIM_CR1_CEN) ? 1 : 0; 453 return IIO_VAL_INT; 454 455 case IIO_CHAN_INFO_SCALE: 456 regmap_read(priv->regmap, TIM_SMCR, &dat); 457 dat &= TIM_SMCR_SMS; 458 459 *val = 1; 460 *val2 = 0; 461 462 /* in quadrature case scale = 0.25 */ 463 if (dat == 3) 464 *val2 = 2; 465 466 return IIO_VAL_FRACTIONAL_LOG2; 467 } 468 469 return -EINVAL; 470 } 471 472 static int stm32_counter_write_raw(struct iio_dev *indio_dev, 473 struct iio_chan_spec const *chan, 474 int val, int val2, long mask) 475 { 476 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 477 478 switch (mask) { 479 case IIO_CHAN_INFO_RAW: 480 return regmap_write(priv->regmap, TIM_CNT, val); 481 482 case IIO_CHAN_INFO_SCALE: 483 /* fixed scale */ 484 return -EINVAL; 485 486 case IIO_CHAN_INFO_ENABLE: 487 mutex_lock(&priv->lock); 488 if (val) { 489 if (!priv->enabled) { 490 priv->enabled = true; 491 clk_enable(priv->clk); 492 } 493 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 494 TIM_CR1_CEN); 495 } else { 496 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 497 0); 498 if (priv->enabled) { 499 priv->enabled = false; 500 clk_disable(priv->clk); 501 } 502 } 503 mutex_unlock(&priv->lock); 504 return 0; 505 } 506 507 return -EINVAL; 508 } 509 510 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev, 511 struct iio_trigger *trig) 512 { 513 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 514 const char * const *cur = priv->valids; 515 unsigned int i = 0; 516 517 if (!is_stm32_timer_trigger(trig)) 518 return -EINVAL; 519 520 while (cur && *cur) { 521 if (!strncmp(trig->name, *cur, strlen(trig->name))) { 522 regmap_update_bits(priv->regmap, 523 TIM_SMCR, TIM_SMCR_TS, 524 i << TIM_SMCR_TS_SHIFT); 525 return 0; 526 } 527 cur++; 528 i++; 529 } 530 531 return -EINVAL; 532 } 533 534 static const struct iio_info stm32_trigger_info = { 535 .validate_trigger = stm32_counter_validate_trigger, 536 .read_raw = stm32_counter_read_raw, 537 .write_raw = stm32_counter_write_raw 538 }; 539 540 static const char *const stm32_trigger_modes[] = { 541 "trigger", 542 }; 543 544 static int stm32_set_trigger_mode(struct iio_dev *indio_dev, 545 const struct iio_chan_spec *chan, 546 unsigned int mode) 547 { 548 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 549 550 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS); 551 552 return 0; 553 } 554 555 static int stm32_get_trigger_mode(struct iio_dev *indio_dev, 556 const struct iio_chan_spec *chan) 557 { 558 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 559 u32 smcr; 560 561 regmap_read(priv->regmap, TIM_SMCR, &smcr); 562 563 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL; 564 } 565 566 static const struct iio_enum stm32_trigger_mode_enum = { 567 .items = stm32_trigger_modes, 568 .num_items = ARRAY_SIZE(stm32_trigger_modes), 569 .set = stm32_set_trigger_mode, 570 .get = stm32_get_trigger_mode 571 }; 572 573 static const char *const stm32_enable_modes[] = { 574 "always", 575 "gated", 576 "triggered", 577 }; 578 579 static int stm32_enable_mode2sms(int mode) 580 { 581 switch (mode) { 582 case 0: 583 return 0; 584 case 1: 585 return 5; 586 case 2: 587 return 6; 588 } 589 590 return -EINVAL; 591 } 592 593 static int stm32_set_enable_mode(struct iio_dev *indio_dev, 594 const struct iio_chan_spec *chan, 595 unsigned int mode) 596 { 597 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 598 int sms = stm32_enable_mode2sms(mode); 599 600 if (sms < 0) 601 return sms; 602 /* 603 * Triggered mode sets CEN bit automatically by hardware. So, first 604 * enable counter clock, so it can use it. Keeps it in sync with CEN. 605 */ 606 mutex_lock(&priv->lock); 607 if (sms == 6 && !priv->enabled) { 608 clk_enable(priv->clk); 609 priv->enabled = true; 610 } 611 mutex_unlock(&priv->lock); 612 613 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 614 615 return 0; 616 } 617 618 static int stm32_sms2enable_mode(int mode) 619 { 620 switch (mode) { 621 case 0: 622 return 0; 623 case 5: 624 return 1; 625 case 6: 626 return 2; 627 } 628 629 return -EINVAL; 630 } 631 632 static int stm32_get_enable_mode(struct iio_dev *indio_dev, 633 const struct iio_chan_spec *chan) 634 { 635 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 636 u32 smcr; 637 638 regmap_read(priv->regmap, TIM_SMCR, &smcr); 639 smcr &= TIM_SMCR_SMS; 640 641 return stm32_sms2enable_mode(smcr); 642 } 643 644 static const struct iio_enum stm32_enable_mode_enum = { 645 .items = stm32_enable_modes, 646 .num_items = ARRAY_SIZE(stm32_enable_modes), 647 .set = stm32_set_enable_mode, 648 .get = stm32_get_enable_mode 649 }; 650 651 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev, 652 uintptr_t private, 653 const struct iio_chan_spec *chan, 654 char *buf) 655 { 656 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 657 u32 arr; 658 659 regmap_read(priv->regmap, TIM_ARR, &arr); 660 661 return snprintf(buf, PAGE_SIZE, "%u\n", arr); 662 } 663 664 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, 665 uintptr_t private, 666 const struct iio_chan_spec *chan, 667 const char *buf, size_t len) 668 { 669 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 670 unsigned int preset; 671 int ret; 672 673 ret = kstrtouint(buf, 0, &preset); 674 if (ret) 675 return ret; 676 677 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ 678 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); 679 regmap_write(priv->regmap, TIM_ARR, preset); 680 681 return len; 682 } 683 684 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = { 685 { 686 .name = "preset", 687 .shared = IIO_SEPARATE, 688 .read = stm32_count_get_preset, 689 .write = stm32_count_set_preset 690 }, 691 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum), 692 IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum), 693 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum), 694 IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum), 695 {} 696 }; 697 698 static const struct iio_chan_spec stm32_trigger_channel = { 699 .type = IIO_COUNT, 700 .channel = 0, 701 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 702 BIT(IIO_CHAN_INFO_ENABLE) | 703 BIT(IIO_CHAN_INFO_SCALE), 704 .ext_info = stm32_trigger_count_info, 705 .indexed = 1 706 }; 707 708 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev) 709 { 710 struct iio_dev *indio_dev; 711 int ret; 712 713 indio_dev = devm_iio_device_alloc(dev, 714 sizeof(struct stm32_timer_trigger)); 715 if (!indio_dev) 716 return NULL; 717 718 indio_dev->name = dev_name(dev); 719 indio_dev->dev.parent = dev; 720 indio_dev->info = &stm32_trigger_info; 721 indio_dev->modes = INDIO_HARDWARE_TRIGGERED; 722 indio_dev->num_channels = 1; 723 indio_dev->channels = &stm32_trigger_channel; 724 indio_dev->dev.of_node = dev->of_node; 725 726 ret = devm_iio_device_register(dev, indio_dev); 727 if (ret) 728 return NULL; 729 730 return iio_priv(indio_dev); 731 } 732 733 /** 734 * is_stm32_timer_trigger 735 * @trig: trigger to be checked 736 * 737 * return true if the trigger is a valid stm32 iio timer trigger 738 * either return false 739 */ 740 bool is_stm32_timer_trigger(struct iio_trigger *trig) 741 { 742 return (trig->ops == &timer_trigger_ops); 743 } 744 EXPORT_SYMBOL(is_stm32_timer_trigger); 745 746 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv) 747 { 748 u32 val; 749 750 /* 751 * Master mode selection 2 bits can only be written and read back when 752 * timer supports it. 753 */ 754 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2); 755 regmap_read(priv->regmap, TIM_CR2, &val); 756 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0); 757 priv->has_trgo2 = !!val; 758 } 759 760 static int stm32_timer_trigger_probe(struct platform_device *pdev) 761 { 762 struct device *dev = &pdev->dev; 763 struct stm32_timer_trigger *priv; 764 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 765 const struct stm32_timer_trigger_cfg *cfg; 766 unsigned int index; 767 int ret; 768 769 if (of_property_read_u32(dev->of_node, "reg", &index)) 770 return -EINVAL; 771 772 cfg = (const struct stm32_timer_trigger_cfg *) 773 of_match_device(dev->driver->of_match_table, dev)->data; 774 775 if (index >= ARRAY_SIZE(triggers_table) || 776 index >= cfg->num_valids_table) 777 return -EINVAL; 778 779 /* Create an IIO device only if we have triggers to be validated */ 780 if (*cfg->valids_table[index]) 781 priv = stm32_setup_counter_device(dev); 782 else 783 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 784 785 if (!priv) 786 return -ENOMEM; 787 788 priv->dev = dev; 789 priv->regmap = ddata->regmap; 790 priv->clk = ddata->clk; 791 priv->max_arr = ddata->max_arr; 792 priv->triggers = triggers_table[index]; 793 priv->valids = cfg->valids_table[index]; 794 stm32_timer_detect_trgo2(priv); 795 mutex_init(&priv->lock); 796 797 ret = stm32_register_iio_triggers(priv); 798 if (ret) 799 return ret; 800 801 platform_set_drvdata(pdev, priv); 802 803 return 0; 804 } 805 806 static int stm32_timer_trigger_remove(struct platform_device *pdev) 807 { 808 struct stm32_timer_trigger *priv = platform_get_drvdata(pdev); 809 u32 val; 810 811 /* Unregister triggers before everything can be safely turned off */ 812 stm32_unregister_iio_triggers(priv); 813 814 /* Check if nobody else use the timer, then disable it */ 815 regmap_read(priv->regmap, TIM_CCER, &val); 816 if (!(val & TIM_CCER_CCXE)) 817 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 818 819 if (priv->enabled) 820 clk_disable(priv->clk); 821 822 return 0; 823 } 824 825 static int __maybe_unused stm32_timer_trigger_suspend(struct device *dev) 826 { 827 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 828 829 /* Only take care of enabled timer: don't disturb other MFD child */ 830 if (priv->enabled) { 831 /* Backup registers that may get lost in low power mode */ 832 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1); 833 regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2); 834 regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc); 835 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr); 836 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt); 837 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr); 838 839 /* Disable the timer */ 840 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 841 clk_disable(priv->clk); 842 } 843 844 return 0; 845 } 846 847 static int __maybe_unused stm32_timer_trigger_resume(struct device *dev) 848 { 849 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 850 int ret; 851 852 if (priv->enabled) { 853 ret = clk_enable(priv->clk); 854 if (ret) 855 return ret; 856 857 /* restore master/slave modes */ 858 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr); 859 regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2); 860 861 /* restore sampling_frequency (trgo / trgo2 triggers) */ 862 regmap_write(priv->regmap, TIM_PSC, priv->bak.psc); 863 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr); 864 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt); 865 866 /* Also re-enables the timer */ 867 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1); 868 } 869 870 return 0; 871 } 872 873 static SIMPLE_DEV_PM_OPS(stm32_timer_trigger_pm_ops, 874 stm32_timer_trigger_suspend, 875 stm32_timer_trigger_resume); 876 877 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = { 878 .valids_table = valids_table, 879 .num_valids_table = ARRAY_SIZE(valids_table), 880 }; 881 882 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = { 883 .valids_table = stm32h7_valids_table, 884 .num_valids_table = ARRAY_SIZE(stm32h7_valids_table), 885 }; 886 887 static const struct of_device_id stm32_trig_of_match[] = { 888 { 889 .compatible = "st,stm32-timer-trigger", 890 .data = (void *)&stm32_timer_trg_cfg, 891 }, { 892 .compatible = "st,stm32h7-timer-trigger", 893 .data = (void *)&stm32h7_timer_trg_cfg, 894 }, 895 { /* end node */ }, 896 }; 897 MODULE_DEVICE_TABLE(of, stm32_trig_of_match); 898 899 static struct platform_driver stm32_timer_trigger_driver = { 900 .probe = stm32_timer_trigger_probe, 901 .remove = stm32_timer_trigger_remove, 902 .driver = { 903 .name = "stm32-timer-trigger", 904 .of_match_table = stm32_trig_of_match, 905 .pm = &stm32_timer_trigger_pm_ops, 906 }, 907 }; 908 module_platform_driver(stm32_timer_trigger_driver); 909 910 MODULE_ALIAS("platform: stm32-timer-trigger"); 911 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver"); 912 MODULE_LICENSE("GPL v2"); 913