1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2016 4 * 5 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 6 * 7 */ 8 9 #include <linux/iio/iio.h> 10 #include <linux/iio/sysfs.h> 11 #include <linux/iio/timer/stm32-timer-trigger.h> 12 #include <linux/iio/trigger.h> 13 #include <linux/mfd/stm32-timers.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 19 #define MAX_TRIGGERS 7 20 #define MAX_VALIDS 5 21 22 /* List the triggers created by each timer */ 23 static const void *triggers_table[][MAX_TRIGGERS] = { 24 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, 25 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,}, 26 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,}, 27 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,}, 28 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,}, 29 { TIM6_TRGO,}, 30 { TIM7_TRGO,}, 31 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, 32 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,}, 33 { TIM10_OC1,}, 34 { TIM11_OC1,}, 35 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,}, 36 { TIM13_OC1,}, 37 { TIM14_OC1,}, 38 { TIM15_TRGO,}, 39 { TIM16_OC1,}, 40 { TIM17_OC1,}, 41 { }, /* timer 18 */ 42 { }, /* timer 19 */ 43 { TIM20_TRGO, TIM20_TRGO2, TIM20_OC1, TIM20_OC2, TIM20_OC3, }, 44 }; 45 46 /* List the triggers accepted by each timer */ 47 static const void *valids_table[][MAX_VALIDS] = { 48 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 49 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 50 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,}, 51 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 52 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,}, 53 { }, /* timer 6 */ 54 { }, /* timer 7 */ 55 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 56 { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,}, 57 { }, /* timer 10 */ 58 { }, /* timer 11 */ 59 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,}, 60 }; 61 62 static const void *stm32h7_valids_table[][MAX_VALIDS] = { 63 { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 64 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 65 { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,}, 66 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 67 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 68 { }, /* timer 6 */ 69 { }, /* timer 7 */ 70 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 71 { }, /* timer 9 */ 72 { }, /* timer 10 */ 73 { }, /* timer 11 */ 74 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,}, 75 { }, /* timer 13 */ 76 { }, /* timer 14 */ 77 { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,}, 78 { }, /* timer 16 */ 79 { }, /* timer 17 */ 80 }; 81 82 struct stm32_timer_trigger_regs { 83 u32 cr1; 84 u32 cr2; 85 u32 psc; 86 u32 arr; 87 u32 cnt; 88 u32 smcr; 89 }; 90 91 struct stm32_timer_trigger { 92 struct device *dev; 93 struct regmap *regmap; 94 struct clk *clk; 95 bool enabled; 96 u32 max_arr; 97 const void *triggers; 98 const void *valids; 99 bool has_trgo2; 100 struct mutex lock; /* concurrent sysfs configuration */ 101 struct list_head tr_list; 102 struct stm32_timer_trigger_regs bak; 103 }; 104 105 struct stm32_timer_trigger_cfg { 106 const void *(*valids_table)[MAX_VALIDS]; 107 const unsigned int num_valids_table; 108 }; 109 110 static bool stm32_timer_is_trgo2_name(const char *name) 111 { 112 return !!strstr(name, "trgo2"); 113 } 114 115 static bool stm32_timer_is_trgo_name(const char *name) 116 { 117 return (!!strstr(name, "trgo") && !strstr(name, "trgo2")); 118 } 119 120 static int stm32_timer_start(struct stm32_timer_trigger *priv, 121 struct iio_trigger *trig, 122 unsigned int frequency) 123 { 124 unsigned long long prd, div; 125 int prescaler = 0, ret; 126 u32 ccer; 127 128 /* Period and prescaler values depends of clock rate */ 129 div = (unsigned long long)clk_get_rate(priv->clk); 130 131 do_div(div, frequency); 132 133 prd = div; 134 135 /* 136 * Increase prescaler value until we get a result that fit 137 * with auto reload register maximum value. 138 */ 139 while (div > priv->max_arr) { 140 prescaler++; 141 div = prd; 142 do_div(div, (prescaler + 1)); 143 } 144 prd = div; 145 146 if (prescaler > MAX_TIM_PSC) { 147 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); 148 return -EINVAL; 149 } 150 151 /* Check if nobody else use the timer */ 152 regmap_read(priv->regmap, TIM_CCER, &ccer); 153 if (ccer & TIM_CCER_CCXE) 154 return -EBUSY; 155 156 guard(mutex)(&priv->lock); 157 if (!priv->enabled) { 158 priv->enabled = true; 159 ret = clk_enable(priv->clk); 160 if (ret) 161 return ret; 162 } 163 164 regmap_write(priv->regmap, TIM_PSC, prescaler); 165 regmap_write(priv->regmap, TIM_ARR, prd - 1); 166 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 167 168 /* Force master mode to update mode */ 169 if (stm32_timer_is_trgo2_name(trig->name)) 170 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 171 0x2 << TIM_CR2_MMS2_SHIFT); 172 else 173 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 174 0x2 << TIM_CR2_MMS_SHIFT); 175 176 /* Make sure that registers are updated */ 177 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 178 179 /* Enable controller */ 180 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 181 182 return 0; 183 } 184 185 static void stm32_timer_stop(struct stm32_timer_trigger *priv, 186 struct iio_trigger *trig) 187 { 188 u32 ccer; 189 190 regmap_read(priv->regmap, TIM_CCER, &ccer); 191 if (ccer & TIM_CCER_CCXE) 192 return; 193 194 mutex_lock(&priv->lock); 195 /* Stop timer */ 196 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 197 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 198 regmap_write(priv->regmap, TIM_PSC, 0); 199 regmap_write(priv->regmap, TIM_ARR, 0); 200 201 /* Force disable master mode */ 202 if (stm32_timer_is_trgo2_name(trig->name)) 203 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); 204 else 205 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS); 206 207 /* Make sure that registers are updated */ 208 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 209 210 if (priv->enabled) { 211 priv->enabled = false; 212 clk_disable(priv->clk); 213 } 214 mutex_unlock(&priv->lock); 215 } 216 217 static ssize_t stm32_tt_store_frequency(struct device *dev, 218 struct device_attribute *attr, 219 const char *buf, size_t len) 220 { 221 struct iio_trigger *trig = to_iio_trigger(dev); 222 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 223 unsigned int freq; 224 int ret; 225 226 ret = kstrtouint(buf, 10, &freq); 227 if (ret) 228 return ret; 229 230 if (freq == 0) { 231 stm32_timer_stop(priv, trig); 232 } else { 233 ret = stm32_timer_start(priv, trig, freq); 234 if (ret) 235 return ret; 236 } 237 238 return len; 239 } 240 241 static ssize_t stm32_tt_read_frequency(struct device *dev, 242 struct device_attribute *attr, char *buf) 243 { 244 struct iio_trigger *trig = to_iio_trigger(dev); 245 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 246 u32 psc, arr, cr1; 247 unsigned long long freq = 0; 248 249 regmap_read(priv->regmap, TIM_CR1, &cr1); 250 regmap_read(priv->regmap, TIM_PSC, &psc); 251 regmap_read(priv->regmap, TIM_ARR, &arr); 252 253 if (cr1 & TIM_CR1_CEN) { 254 freq = (unsigned long long)clk_get_rate(priv->clk); 255 do_div(freq, psc + 1); 256 do_div(freq, arr + 1); 257 } 258 259 return sprintf(buf, "%d\n", (unsigned int)freq); 260 } 261 262 static IIO_DEV_ATTR_SAMP_FREQ(0660, 263 stm32_tt_read_frequency, 264 stm32_tt_store_frequency); 265 266 #define MASTER_MODE_MAX 7 267 #define MASTER_MODE2_MAX 15 268 269 static char *master_mode_table[] = { 270 "reset", 271 "enable", 272 "update", 273 "compare_pulse", 274 "OC1REF", 275 "OC2REF", 276 "OC3REF", 277 "OC4REF", 278 /* Master mode selection 2 only */ 279 "OC5REF", 280 "OC6REF", 281 "compare_pulse_OC4REF", 282 "compare_pulse_OC6REF", 283 "compare_pulse_OC4REF_r_or_OC6REF_r", 284 "compare_pulse_OC4REF_r_or_OC6REF_f", 285 "compare_pulse_OC5REF_r_or_OC6REF_r", 286 "compare_pulse_OC5REF_r_or_OC6REF_f", 287 }; 288 289 static ssize_t stm32_tt_show_master_mode(struct device *dev, 290 struct device_attribute *attr, 291 char *buf) 292 { 293 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 294 struct iio_trigger *trig = to_iio_trigger(dev); 295 u32 cr2; 296 297 regmap_read(priv->regmap, TIM_CR2, &cr2); 298 299 if (stm32_timer_is_trgo2_name(trig->name)) 300 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT; 301 else 302 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; 303 304 return sysfs_emit(buf, "%s\n", master_mode_table[cr2]); 305 } 306 307 static ssize_t stm32_tt_store_master_mode(struct device *dev, 308 struct device_attribute *attr, 309 const char *buf, size_t len) 310 { 311 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 312 struct iio_trigger *trig = to_iio_trigger(dev); 313 u32 mask, shift, master_mode_max; 314 int i, ret; 315 316 if (stm32_timer_is_trgo2_name(trig->name)) { 317 mask = TIM_CR2_MMS2; 318 shift = TIM_CR2_MMS2_SHIFT; 319 master_mode_max = MASTER_MODE2_MAX; 320 } else { 321 mask = TIM_CR2_MMS; 322 shift = TIM_CR2_MMS_SHIFT; 323 master_mode_max = MASTER_MODE_MAX; 324 } 325 326 for (i = 0; i <= master_mode_max; i++) { 327 if (!strncmp(master_mode_table[i], buf, 328 strlen(master_mode_table[i]))) { 329 guard(mutex)(&priv->lock); 330 if (!priv->enabled) { 331 /* Clock should be enabled first */ 332 priv->enabled = true; 333 ret = clk_enable(priv->clk); 334 if (ret) 335 return ret; 336 } 337 regmap_update_bits(priv->regmap, TIM_CR2, mask, 338 i << shift); 339 return len; 340 } 341 } 342 343 return -EINVAL; 344 } 345 346 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev, 347 struct device_attribute *attr, 348 char *buf) 349 { 350 struct iio_trigger *trig = to_iio_trigger(dev); 351 unsigned int i, master_mode_max; 352 size_t len = 0; 353 354 if (stm32_timer_is_trgo2_name(trig->name)) 355 master_mode_max = MASTER_MODE2_MAX; 356 else 357 master_mode_max = MASTER_MODE_MAX; 358 359 for (i = 0; i <= master_mode_max; i++) 360 len += scnprintf(buf + len, PAGE_SIZE - len, 361 "%s ", master_mode_table[i]); 362 363 /* replace trailing space by newline */ 364 buf[len - 1] = '\n'; 365 366 return len; 367 } 368 369 static IIO_DEVICE_ATTR(master_mode_available, 0444, 370 stm32_tt_show_master_mode_avail, NULL, 0); 371 372 static IIO_DEVICE_ATTR(master_mode, 0660, 373 stm32_tt_show_master_mode, 374 stm32_tt_store_master_mode, 375 0); 376 377 static struct attribute *stm32_trigger_attrs[] = { 378 &iio_dev_attr_sampling_frequency.dev_attr.attr, 379 &iio_dev_attr_master_mode.dev_attr.attr, 380 &iio_dev_attr_master_mode_available.dev_attr.attr, 381 NULL, 382 }; 383 384 static const struct attribute_group stm32_trigger_attr_group = { 385 .attrs = stm32_trigger_attrs, 386 }; 387 388 static const struct attribute_group *stm32_trigger_attr_groups[] = { 389 &stm32_trigger_attr_group, 390 NULL, 391 }; 392 393 static const struct iio_trigger_ops timer_trigger_ops = { 394 }; 395 396 static void stm32_unregister_iio_triggers(struct stm32_timer_trigger *priv) 397 { 398 struct iio_trigger *tr; 399 400 list_for_each_entry(tr, &priv->tr_list, alloc_list) 401 iio_trigger_unregister(tr); 402 } 403 404 static int stm32_register_iio_triggers(struct stm32_timer_trigger *priv) 405 { 406 int ret; 407 const char * const *cur = priv->triggers; 408 409 INIT_LIST_HEAD(&priv->tr_list); 410 411 while (cur && *cur) { 412 struct iio_trigger *trig; 413 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur); 414 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur); 415 416 if (cur_is_trgo2 && !priv->has_trgo2) { 417 cur++; 418 continue; 419 } 420 421 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); 422 if (!trig) 423 return -ENOMEM; 424 425 trig->dev.parent = priv->dev->parent; 426 trig->ops = &timer_trigger_ops; 427 428 /* 429 * sampling frequency and master mode attributes 430 * should only be available on trgo/trgo2 triggers 431 */ 432 if (cur_is_trgo || cur_is_trgo2) 433 trig->dev.groups = stm32_trigger_attr_groups; 434 435 iio_trigger_set_drvdata(trig, priv); 436 437 ret = iio_trigger_register(trig); 438 if (ret) { 439 stm32_unregister_iio_triggers(priv); 440 return ret; 441 } 442 443 list_add_tail(&trig->alloc_list, &priv->tr_list); 444 cur++; 445 } 446 447 return 0; 448 } 449 450 static int stm32_counter_read_raw(struct iio_dev *indio_dev, 451 struct iio_chan_spec const *chan, 452 int *val, int *val2, long mask) 453 { 454 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 455 u32 dat; 456 457 switch (mask) { 458 case IIO_CHAN_INFO_RAW: 459 regmap_read(priv->regmap, TIM_CNT, &dat); 460 *val = dat; 461 return IIO_VAL_INT; 462 463 case IIO_CHAN_INFO_ENABLE: 464 regmap_read(priv->regmap, TIM_CR1, &dat); 465 *val = (dat & TIM_CR1_CEN) ? 1 : 0; 466 return IIO_VAL_INT; 467 468 case IIO_CHAN_INFO_SCALE: 469 regmap_read(priv->regmap, TIM_SMCR, &dat); 470 dat &= TIM_SMCR_SMS; 471 472 *val = 1; 473 *val2 = 0; 474 475 /* in quadrature case scale = 0.25 */ 476 if (dat == 3) 477 *val2 = 2; 478 479 return IIO_VAL_FRACTIONAL_LOG2; 480 } 481 482 return -EINVAL; 483 } 484 485 static int stm32_counter_write_raw(struct iio_dev *indio_dev, 486 struct iio_chan_spec const *chan, 487 int val, int val2, long mask) 488 { 489 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 490 int ret; 491 492 switch (mask) { 493 case IIO_CHAN_INFO_RAW: 494 return regmap_write(priv->regmap, TIM_CNT, val); 495 496 case IIO_CHAN_INFO_SCALE: 497 /* fixed scale */ 498 return -EINVAL; 499 500 case IIO_CHAN_INFO_ENABLE: { 501 guard(mutex)(&priv->lock); 502 if (val) { 503 if (!priv->enabled) { 504 priv->enabled = true; 505 ret = clk_enable(priv->clk); 506 if (ret) 507 return ret; 508 } 509 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 510 } else { 511 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 512 if (priv->enabled) { 513 priv->enabled = false; 514 clk_disable(priv->clk); 515 } 516 } 517 518 return 0; 519 } 520 default: 521 return -EINVAL; 522 } 523 } 524 525 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev, 526 struct iio_trigger *trig) 527 { 528 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 529 const char * const *cur = priv->valids; 530 unsigned int i = 0; 531 532 if (!is_stm32_timer_trigger(trig)) 533 return -EINVAL; 534 535 while (cur && *cur) { 536 if (!strncmp(trig->name, *cur, strlen(trig->name))) { 537 regmap_update_bits(priv->regmap, 538 TIM_SMCR, TIM_SMCR_TS, 539 i << TIM_SMCR_TS_SHIFT); 540 return 0; 541 } 542 cur++; 543 i++; 544 } 545 546 return -EINVAL; 547 } 548 549 static const struct iio_info stm32_trigger_info = { 550 .validate_trigger = stm32_counter_validate_trigger, 551 .read_raw = stm32_counter_read_raw, 552 .write_raw = stm32_counter_write_raw 553 }; 554 555 static const char *const stm32_trigger_modes[] = { 556 "trigger", 557 }; 558 559 static int stm32_set_trigger_mode(struct iio_dev *indio_dev, 560 const struct iio_chan_spec *chan, 561 unsigned int mode) 562 { 563 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 564 565 regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS); 566 567 return 0; 568 } 569 570 static int stm32_get_trigger_mode(struct iio_dev *indio_dev, 571 const struct iio_chan_spec *chan) 572 { 573 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 574 u32 smcr; 575 576 regmap_read(priv->regmap, TIM_SMCR, &smcr); 577 578 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL; 579 } 580 581 static const struct iio_enum stm32_trigger_mode_enum = { 582 .items = stm32_trigger_modes, 583 .num_items = ARRAY_SIZE(stm32_trigger_modes), 584 .set = stm32_set_trigger_mode, 585 .get = stm32_get_trigger_mode 586 }; 587 588 static const char *const stm32_enable_modes[] = { 589 "always", 590 "gated", 591 "triggered", 592 }; 593 594 static int stm32_enable_mode2sms(int mode) 595 { 596 switch (mode) { 597 case 0: 598 return 0; 599 case 1: 600 return 5; 601 case 2: 602 return 6; 603 } 604 605 return -EINVAL; 606 } 607 608 static int stm32_set_enable_mode(struct iio_dev *indio_dev, 609 const struct iio_chan_spec *chan, 610 unsigned int mode) 611 { 612 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 613 int sms = stm32_enable_mode2sms(mode); 614 int ret; 615 616 if (sms < 0) 617 return sms; 618 /* 619 * Triggered mode sets CEN bit automatically by hardware. So, first 620 * enable counter clock, so it can use it. Keeps it in sync with CEN. 621 */ 622 scoped_guard(mutex, &priv->lock) { 623 if (sms == 6 && !priv->enabled) { 624 ret = clk_enable(priv->clk); 625 if (ret) 626 return ret; 627 628 priv->enabled = true; 629 } 630 } 631 632 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 633 634 return 0; 635 } 636 637 static int stm32_sms2enable_mode(int mode) 638 { 639 switch (mode) { 640 case 0: 641 return 0; 642 case 5: 643 return 1; 644 case 6: 645 return 2; 646 } 647 648 return -EINVAL; 649 } 650 651 static int stm32_get_enable_mode(struct iio_dev *indio_dev, 652 const struct iio_chan_spec *chan) 653 { 654 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 655 u32 smcr; 656 657 regmap_read(priv->regmap, TIM_SMCR, &smcr); 658 smcr &= TIM_SMCR_SMS; 659 660 return stm32_sms2enable_mode(smcr); 661 } 662 663 static const struct iio_enum stm32_enable_mode_enum = { 664 .items = stm32_enable_modes, 665 .num_items = ARRAY_SIZE(stm32_enable_modes), 666 .set = stm32_set_enable_mode, 667 .get = stm32_get_enable_mode 668 }; 669 670 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev, 671 uintptr_t private, 672 const struct iio_chan_spec *chan, 673 char *buf) 674 { 675 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 676 u32 arr; 677 678 regmap_read(priv->regmap, TIM_ARR, &arr); 679 680 return snprintf(buf, PAGE_SIZE, "%u\n", arr); 681 } 682 683 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, 684 uintptr_t private, 685 const struct iio_chan_spec *chan, 686 const char *buf, size_t len) 687 { 688 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 689 unsigned int preset; 690 int ret; 691 692 ret = kstrtouint(buf, 0, &preset); 693 if (ret) 694 return ret; 695 696 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ 697 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 698 regmap_write(priv->regmap, TIM_ARR, preset); 699 700 return len; 701 } 702 703 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = { 704 { 705 .name = "preset", 706 .shared = IIO_SEPARATE, 707 .read = stm32_count_get_preset, 708 .write = stm32_count_set_preset 709 }, 710 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum), 711 IIO_ENUM_AVAILABLE("enable_mode", IIO_SHARED_BY_TYPE, &stm32_enable_mode_enum), 712 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum), 713 IIO_ENUM_AVAILABLE("trigger_mode", IIO_SHARED_BY_TYPE, &stm32_trigger_mode_enum), 714 {} 715 }; 716 717 static const struct iio_chan_spec stm32_trigger_channel = { 718 .type = IIO_COUNT, 719 .channel = 0, 720 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 721 BIT(IIO_CHAN_INFO_ENABLE) | 722 BIT(IIO_CHAN_INFO_SCALE), 723 .ext_info = stm32_trigger_count_info, 724 .indexed = 1 725 }; 726 727 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev) 728 { 729 struct iio_dev *indio_dev; 730 int ret; 731 732 indio_dev = devm_iio_device_alloc(dev, 733 sizeof(struct stm32_timer_trigger)); 734 if (!indio_dev) 735 return NULL; 736 737 indio_dev->name = dev_name(dev); 738 indio_dev->info = &stm32_trigger_info; 739 indio_dev->modes = INDIO_HARDWARE_TRIGGERED; 740 indio_dev->num_channels = 1; 741 indio_dev->channels = &stm32_trigger_channel; 742 743 ret = devm_iio_device_register(dev, indio_dev); 744 if (ret) 745 return NULL; 746 747 return iio_priv(indio_dev); 748 } 749 750 /** 751 * is_stm32_timer_trigger 752 * @trig: trigger to be checked 753 * 754 * return true if the trigger is a valid stm32 iio timer trigger 755 * either return false 756 */ 757 bool is_stm32_timer_trigger(struct iio_trigger *trig) 758 { 759 return (trig->ops == &timer_trigger_ops); 760 } 761 EXPORT_SYMBOL(is_stm32_timer_trigger); 762 763 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv) 764 { 765 u32 val; 766 767 /* 768 * Master mode selection 2 bits can only be written and read back when 769 * timer supports it. 770 */ 771 regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); 772 regmap_read(priv->regmap, TIM_CR2, &val); 773 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); 774 priv->has_trgo2 = !!val; 775 } 776 777 static int stm32_timer_trigger_probe(struct platform_device *pdev) 778 { 779 struct device *dev = &pdev->dev; 780 struct stm32_timer_trigger *priv; 781 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 782 const struct stm32_timer_trigger_cfg *cfg; 783 unsigned int index; 784 int ret; 785 786 ret = device_property_read_u32(dev, "reg", &index); 787 if (ret) 788 return ret; 789 790 cfg = device_get_match_data(dev); 791 792 if (index >= ARRAY_SIZE(triggers_table) || 793 index >= cfg->num_valids_table) 794 return -EINVAL; 795 796 /* Create an IIO device only if we have triggers to be validated */ 797 if (cfg->valids_table && *cfg->valids_table[index]) 798 priv = stm32_setup_counter_device(dev); 799 else 800 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 801 802 if (!priv) 803 return -ENOMEM; 804 805 priv->dev = dev; 806 priv->regmap = ddata->regmap; 807 priv->clk = ddata->clk; 808 priv->max_arr = ddata->max_arr; 809 priv->triggers = triggers_table[index]; 810 if (cfg->valids_table && *cfg->valids_table[index]) 811 priv->valids = cfg->valids_table[index]; 812 stm32_timer_detect_trgo2(priv); 813 mutex_init(&priv->lock); 814 815 ret = stm32_register_iio_triggers(priv); 816 if (ret) 817 return ret; 818 819 platform_set_drvdata(pdev, priv); 820 821 return 0; 822 } 823 824 static void stm32_timer_trigger_remove(struct platform_device *pdev) 825 { 826 struct stm32_timer_trigger *priv = platform_get_drvdata(pdev); 827 u32 val; 828 829 /* Unregister triggers before everything can be safely turned off */ 830 stm32_unregister_iio_triggers(priv); 831 832 /* Check if nobody else use the timer, then disable it */ 833 regmap_read(priv->regmap, TIM_CCER, &val); 834 if (!(val & TIM_CCER_CCXE)) 835 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 836 837 if (priv->enabled) 838 clk_disable(priv->clk); 839 } 840 841 static int stm32_timer_trigger_suspend(struct device *dev) 842 { 843 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 844 845 /* Only take care of enabled timer: don't disturb other MFD child */ 846 if (priv->enabled) { 847 /* Backup registers that may get lost in low power mode */ 848 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1); 849 regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2); 850 regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc); 851 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr); 852 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt); 853 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr); 854 855 /* Disable the timer */ 856 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 857 clk_disable(priv->clk); 858 } 859 860 return 0; 861 } 862 863 static int stm32_timer_trigger_resume(struct device *dev) 864 { 865 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 866 int ret; 867 868 if (priv->enabled) { 869 ret = clk_enable(priv->clk); 870 if (ret) 871 return ret; 872 873 /* restore master/slave modes */ 874 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr); 875 regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2); 876 877 /* restore sampling_frequency (trgo / trgo2 triggers) */ 878 regmap_write(priv->regmap, TIM_PSC, priv->bak.psc); 879 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr); 880 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt); 881 882 /* Also re-enables the timer */ 883 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1); 884 } 885 886 return 0; 887 } 888 889 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_timer_trigger_pm_ops, 890 stm32_timer_trigger_suspend, 891 stm32_timer_trigger_resume); 892 893 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = { 894 .valids_table = valids_table, 895 .num_valids_table = ARRAY_SIZE(valids_table), 896 }; 897 898 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = { 899 .valids_table = stm32h7_valids_table, 900 .num_valids_table = ARRAY_SIZE(stm32h7_valids_table), 901 }; 902 903 static const struct stm32_timer_trigger_cfg stm32mp25_timer_trg_cfg = { 904 /* 905 * valids_table not used: counter framework is now superseding the deprecated IIO 906 * counter interface (IIO_COUNT), so don't support it. num_valids_table is only 907 * kept here to register the IIO HW triggers. valids_table should be moved at some 908 * point to the stm32-timer-cnt driver instead. 909 */ 910 .num_valids_table = ARRAY_SIZE(triggers_table), 911 }; 912 913 static const struct of_device_id stm32_trig_of_match[] = { 914 { 915 .compatible = "st,stm32-timer-trigger", 916 .data = (void *)&stm32_timer_trg_cfg, 917 }, { 918 .compatible = "st,stm32h7-timer-trigger", 919 .data = (void *)&stm32h7_timer_trg_cfg, 920 }, { 921 .compatible = "st,stm32mp25-timer-trigger", 922 .data = (void *)&stm32mp25_timer_trg_cfg, 923 }, 924 { /* end node */ }, 925 }; 926 MODULE_DEVICE_TABLE(of, stm32_trig_of_match); 927 928 static struct platform_driver stm32_timer_trigger_driver = { 929 .probe = stm32_timer_trigger_probe, 930 .remove = stm32_timer_trigger_remove, 931 .driver = { 932 .name = "stm32-timer-trigger", 933 .of_match_table = stm32_trig_of_match, 934 .pm = pm_sleep_ptr(&stm32_timer_trigger_pm_ops), 935 }, 936 }; 937 module_platform_driver(stm32_timer_trigger_driver); 938 939 MODULE_ALIAS("platform:stm32-timer-trigger"); 940 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver"); 941 MODULE_LICENSE("GPL v2"); 942