1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics 2016
4 *
5 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
6 *
7 */
8
9 #include <linux/iio/iio.h>
10 #include <linux/iio/sysfs.h>
11 #include <linux/iio/timer/stm32-timer-trigger.h>
12 #include <linux/iio/trigger.h>
13 #include <linux/mfd/stm32-timers.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18
19 #define MAX_TRIGGERS 7
20 #define MAX_VALIDS 5
21
22 /* List the triggers created by each timer */
23 static const void *triggers_table[][MAX_TRIGGERS] = {
24 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
25 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
26 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
27 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
28 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
29 { TIM6_TRGO,},
30 { TIM7_TRGO,},
31 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
32 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
33 { TIM10_OC1,},
34 { TIM11_OC1,},
35 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
36 { TIM13_OC1,},
37 { TIM14_OC1,},
38 { TIM15_TRGO,},
39 { TIM16_OC1,},
40 { TIM17_OC1,},
41 };
42
43 /* List the triggers accepted by each timer */
44 static const void *valids_table[][MAX_VALIDS] = {
45 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
46 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
47 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
48 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
49 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
50 { }, /* timer 6 */
51 { }, /* timer 7 */
52 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
53 { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
54 { }, /* timer 10 */
55 { }, /* timer 11 */
56 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
57 };
58
59 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
60 { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
61 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
62 { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
63 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
64 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
65 { }, /* timer 6 */
66 { }, /* timer 7 */
67 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
68 { }, /* timer 9 */
69 { }, /* timer 10 */
70 { }, /* timer 11 */
71 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
72 { }, /* timer 13 */
73 { }, /* timer 14 */
74 { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
75 { }, /* timer 16 */
76 { }, /* timer 17 */
77 };
78
79 struct stm32_timer_trigger_regs {
80 u32 cr1;
81 u32 cr2;
82 u32 psc;
83 u32 arr;
84 u32 cnt;
85 u32 smcr;
86 };
87
88 struct stm32_timer_trigger {
89 struct device *dev;
90 struct regmap *regmap;
91 struct clk *clk;
92 bool enabled;
93 u32 max_arr;
94 const void *triggers;
95 const void *valids;
96 bool has_trgo2;
97 struct mutex lock; /* concurrent sysfs configuration */
98 struct list_head tr_list;
99 struct stm32_timer_trigger_regs bak;
100 };
101
102 struct stm32_timer_trigger_cfg {
103 const void *(*valids_table)[MAX_VALIDS];
104 const unsigned int num_valids_table;
105 };
106
stm32_timer_is_trgo2_name(const char * name)107 static bool stm32_timer_is_trgo2_name(const char *name)
108 {
109 return !!strstr(name, "trgo2");
110 }
111
stm32_timer_is_trgo_name(const char * name)112 static bool stm32_timer_is_trgo_name(const char *name)
113 {
114 return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
115 }
116
stm32_timer_start(struct stm32_timer_trigger * priv,struct iio_trigger * trig,unsigned int frequency)117 static int stm32_timer_start(struct stm32_timer_trigger *priv,
118 struct iio_trigger *trig,
119 unsigned int frequency)
120 {
121 unsigned long long prd, div;
122 int prescaler = 0;
123 u32 ccer;
124
125 /* Period and prescaler values depends of clock rate */
126 div = (unsigned long long)clk_get_rate(priv->clk);
127
128 do_div(div, frequency);
129
130 prd = div;
131
132 /*
133 * Increase prescaler value until we get a result that fit
134 * with auto reload register maximum value.
135 */
136 while (div > priv->max_arr) {
137 prescaler++;
138 div = prd;
139 do_div(div, (prescaler + 1));
140 }
141 prd = div;
142
143 if (prescaler > MAX_TIM_PSC) {
144 dev_err(priv->dev, "prescaler exceeds the maximum value\n");
145 return -EINVAL;
146 }
147
148 /* Check if nobody else use the timer */
149 regmap_read(priv->regmap, TIM_CCER, &ccer);
150 if (ccer & TIM_CCER_CCXE)
151 return -EBUSY;
152
153 mutex_lock(&priv->lock);
154 if (!priv->enabled) {
155 priv->enabled = true;
156 clk_enable(priv->clk);
157 }
158
159 regmap_write(priv->regmap, TIM_PSC, prescaler);
160 regmap_write(priv->regmap, TIM_ARR, prd - 1);
161 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
162
163 /* Force master mode to update mode */
164 if (stm32_timer_is_trgo2_name(trig->name))
165 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
166 0x2 << TIM_CR2_MMS2_SHIFT);
167 else
168 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
169 0x2 << TIM_CR2_MMS_SHIFT);
170
171 /* Make sure that registers are updated */
172 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
173
174 /* Enable controller */
175 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
176 mutex_unlock(&priv->lock);
177
178 return 0;
179 }
180
stm32_timer_stop(struct stm32_timer_trigger * priv,struct iio_trigger * trig)181 static void stm32_timer_stop(struct stm32_timer_trigger *priv,
182 struct iio_trigger *trig)
183 {
184 u32 ccer;
185
186 regmap_read(priv->regmap, TIM_CCER, &ccer);
187 if (ccer & TIM_CCER_CCXE)
188 return;
189
190 mutex_lock(&priv->lock);
191 /* Stop timer */
192 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
193 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
194 regmap_write(priv->regmap, TIM_PSC, 0);
195 regmap_write(priv->regmap, TIM_ARR, 0);
196
197 /* Force disable master mode */
198 if (stm32_timer_is_trgo2_name(trig->name))
199 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
200 else
201 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS);
202
203 /* Make sure that registers are updated */
204 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
205
206 if (priv->enabled) {
207 priv->enabled = false;
208 clk_disable(priv->clk);
209 }
210 mutex_unlock(&priv->lock);
211 }
212
stm32_tt_store_frequency(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)213 static ssize_t stm32_tt_store_frequency(struct device *dev,
214 struct device_attribute *attr,
215 const char *buf, size_t len)
216 {
217 struct iio_trigger *trig = to_iio_trigger(dev);
218 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
219 unsigned int freq;
220 int ret;
221
222 ret = kstrtouint(buf, 10, &freq);
223 if (ret)
224 return ret;
225
226 if (freq == 0) {
227 stm32_timer_stop(priv, trig);
228 } else {
229 ret = stm32_timer_start(priv, trig, freq);
230 if (ret)
231 return ret;
232 }
233
234 return len;
235 }
236
stm32_tt_read_frequency(struct device * dev,struct device_attribute * attr,char * buf)237 static ssize_t stm32_tt_read_frequency(struct device *dev,
238 struct device_attribute *attr, char *buf)
239 {
240 struct iio_trigger *trig = to_iio_trigger(dev);
241 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
242 u32 psc, arr, cr1;
243 unsigned long long freq = 0;
244
245 regmap_read(priv->regmap, TIM_CR1, &cr1);
246 regmap_read(priv->regmap, TIM_PSC, &psc);
247 regmap_read(priv->regmap, TIM_ARR, &arr);
248
249 if (cr1 & TIM_CR1_CEN) {
250 freq = (unsigned long long)clk_get_rate(priv->clk);
251 do_div(freq, psc + 1);
252 do_div(freq, arr + 1);
253 }
254
255 return sprintf(buf, "%d\n", (unsigned int)freq);
256 }
257
258 static IIO_DEV_ATTR_SAMP_FREQ(0660,
259 stm32_tt_read_frequency,
260 stm32_tt_store_frequency);
261
262 #define MASTER_MODE_MAX 7
263 #define MASTER_MODE2_MAX 15
264
265 static char *master_mode_table[] = {
266 "reset",
267 "enable",
268 "update",
269 "compare_pulse",
270 "OC1REF",
271 "OC2REF",
272 "OC3REF",
273 "OC4REF",
274 /* Master mode selection 2 only */
275 "OC5REF",
276 "OC6REF",
277 "compare_pulse_OC4REF",
278 "compare_pulse_OC6REF",
279 "compare_pulse_OC4REF_r_or_OC6REF_r",
280 "compare_pulse_OC4REF_r_or_OC6REF_f",
281 "compare_pulse_OC5REF_r_or_OC6REF_r",
282 "compare_pulse_OC5REF_r_or_OC6REF_f",
283 };
284
stm32_tt_show_master_mode(struct device * dev,struct device_attribute * attr,char * buf)285 static ssize_t stm32_tt_show_master_mode(struct device *dev,
286 struct device_attribute *attr,
287 char *buf)
288 {
289 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
290 struct iio_trigger *trig = to_iio_trigger(dev);
291 u32 cr2;
292
293 regmap_read(priv->regmap, TIM_CR2, &cr2);
294
295 if (stm32_timer_is_trgo2_name(trig->name))
296 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
297 else
298 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
299
300 return sysfs_emit(buf, "%s\n", master_mode_table[cr2]);
301 }
302
stm32_tt_store_master_mode(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)303 static ssize_t stm32_tt_store_master_mode(struct device *dev,
304 struct device_attribute *attr,
305 const char *buf, size_t len)
306 {
307 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
308 struct iio_trigger *trig = to_iio_trigger(dev);
309 u32 mask, shift, master_mode_max;
310 int i;
311
312 if (stm32_timer_is_trgo2_name(trig->name)) {
313 mask = TIM_CR2_MMS2;
314 shift = TIM_CR2_MMS2_SHIFT;
315 master_mode_max = MASTER_MODE2_MAX;
316 } else {
317 mask = TIM_CR2_MMS;
318 shift = TIM_CR2_MMS_SHIFT;
319 master_mode_max = MASTER_MODE_MAX;
320 }
321
322 for (i = 0; i <= master_mode_max; i++) {
323 if (!strncmp(master_mode_table[i], buf,
324 strlen(master_mode_table[i]))) {
325 mutex_lock(&priv->lock);
326 if (!priv->enabled) {
327 /* Clock should be enabled first */
328 priv->enabled = true;
329 clk_enable(priv->clk);
330 }
331 regmap_update_bits(priv->regmap, TIM_CR2, mask,
332 i << shift);
333 mutex_unlock(&priv->lock);
334 return len;
335 }
336 }
337
338 return -EINVAL;
339 }
340
stm32_tt_show_master_mode_avail(struct device * dev,struct device_attribute * attr,char * buf)341 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
342 struct device_attribute *attr,
343 char *buf)
344 {
345 struct iio_trigger *trig = to_iio_trigger(dev);
346 unsigned int i, master_mode_max;
347 size_t len = 0;
348
349 if (stm32_timer_is_trgo2_name(trig->name))
350 master_mode_max = MASTER_MODE2_MAX;
351 else
352 master_mode_max = MASTER_MODE_MAX;
353
354 for (i = 0; i <= master_mode_max; i++)
355 len += scnprintf(buf + len, PAGE_SIZE - len,
356 "%s ", master_mode_table[i]);
357
358 /* replace trailing space by newline */
359 buf[len - 1] = '\n';
360
361 return len;
362 }
363
364 static IIO_DEVICE_ATTR(master_mode_available, 0444,
365 stm32_tt_show_master_mode_avail, NULL, 0);
366
367 static IIO_DEVICE_ATTR(master_mode, 0660,
368 stm32_tt_show_master_mode,
369 stm32_tt_store_master_mode,
370 0);
371
372 static struct attribute *stm32_trigger_attrs[] = {
373 &iio_dev_attr_sampling_frequency.dev_attr.attr,
374 &iio_dev_attr_master_mode.dev_attr.attr,
375 &iio_dev_attr_master_mode_available.dev_attr.attr,
376 NULL,
377 };
378
379 static const struct attribute_group stm32_trigger_attr_group = {
380 .attrs = stm32_trigger_attrs,
381 };
382
383 static const struct attribute_group *stm32_trigger_attr_groups[] = {
384 &stm32_trigger_attr_group,
385 NULL,
386 };
387
388 static const struct iio_trigger_ops timer_trigger_ops = {
389 };
390
stm32_unregister_iio_triggers(struct stm32_timer_trigger * priv)391 static void stm32_unregister_iio_triggers(struct stm32_timer_trigger *priv)
392 {
393 struct iio_trigger *tr;
394
395 list_for_each_entry(tr, &priv->tr_list, alloc_list)
396 iio_trigger_unregister(tr);
397 }
398
stm32_register_iio_triggers(struct stm32_timer_trigger * priv)399 static int stm32_register_iio_triggers(struct stm32_timer_trigger *priv)
400 {
401 int ret;
402 const char * const *cur = priv->triggers;
403
404 INIT_LIST_HEAD(&priv->tr_list);
405
406 while (cur && *cur) {
407 struct iio_trigger *trig;
408 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
409 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
410
411 if (cur_is_trgo2 && !priv->has_trgo2) {
412 cur++;
413 continue;
414 }
415
416 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
417 if (!trig)
418 return -ENOMEM;
419
420 trig->dev.parent = priv->dev->parent;
421 trig->ops = &timer_trigger_ops;
422
423 /*
424 * sampling frequency and master mode attributes
425 * should only be available on trgo/trgo2 triggers
426 */
427 if (cur_is_trgo || cur_is_trgo2)
428 trig->dev.groups = stm32_trigger_attr_groups;
429
430 iio_trigger_set_drvdata(trig, priv);
431
432 ret = iio_trigger_register(trig);
433 if (ret) {
434 stm32_unregister_iio_triggers(priv);
435 return ret;
436 }
437
438 list_add_tail(&trig->alloc_list, &priv->tr_list);
439 cur++;
440 }
441
442 return 0;
443 }
444
stm32_counter_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)445 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
446 struct iio_chan_spec const *chan,
447 int *val, int *val2, long mask)
448 {
449 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
450 u32 dat;
451
452 switch (mask) {
453 case IIO_CHAN_INFO_RAW:
454 regmap_read(priv->regmap, TIM_CNT, &dat);
455 *val = dat;
456 return IIO_VAL_INT;
457
458 case IIO_CHAN_INFO_ENABLE:
459 regmap_read(priv->regmap, TIM_CR1, &dat);
460 *val = (dat & TIM_CR1_CEN) ? 1 : 0;
461 return IIO_VAL_INT;
462
463 case IIO_CHAN_INFO_SCALE:
464 regmap_read(priv->regmap, TIM_SMCR, &dat);
465 dat &= TIM_SMCR_SMS;
466
467 *val = 1;
468 *val2 = 0;
469
470 /* in quadrature case scale = 0.25 */
471 if (dat == 3)
472 *val2 = 2;
473
474 return IIO_VAL_FRACTIONAL_LOG2;
475 }
476
477 return -EINVAL;
478 }
479
stm32_counter_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)480 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
481 struct iio_chan_spec const *chan,
482 int val, int val2, long mask)
483 {
484 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
485
486 switch (mask) {
487 case IIO_CHAN_INFO_RAW:
488 return regmap_write(priv->regmap, TIM_CNT, val);
489
490 case IIO_CHAN_INFO_SCALE:
491 /* fixed scale */
492 return -EINVAL;
493
494 case IIO_CHAN_INFO_ENABLE:
495 mutex_lock(&priv->lock);
496 if (val) {
497 if (!priv->enabled) {
498 priv->enabled = true;
499 clk_enable(priv->clk);
500 }
501 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
502 } else {
503 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
504 if (priv->enabled) {
505 priv->enabled = false;
506 clk_disable(priv->clk);
507 }
508 }
509 mutex_unlock(&priv->lock);
510 return 0;
511 }
512
513 return -EINVAL;
514 }
515
stm32_counter_validate_trigger(struct iio_dev * indio_dev,struct iio_trigger * trig)516 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
517 struct iio_trigger *trig)
518 {
519 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
520 const char * const *cur = priv->valids;
521 unsigned int i = 0;
522
523 if (!is_stm32_timer_trigger(trig))
524 return -EINVAL;
525
526 while (cur && *cur) {
527 if (!strncmp(trig->name, *cur, strlen(trig->name))) {
528 regmap_update_bits(priv->regmap,
529 TIM_SMCR, TIM_SMCR_TS,
530 i << TIM_SMCR_TS_SHIFT);
531 return 0;
532 }
533 cur++;
534 i++;
535 }
536
537 return -EINVAL;
538 }
539
540 static const struct iio_info stm32_trigger_info = {
541 .validate_trigger = stm32_counter_validate_trigger,
542 .read_raw = stm32_counter_read_raw,
543 .write_raw = stm32_counter_write_raw
544 };
545
546 static const char *const stm32_trigger_modes[] = {
547 "trigger",
548 };
549
stm32_set_trigger_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)550 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
551 const struct iio_chan_spec *chan,
552 unsigned int mode)
553 {
554 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
555
556 regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS);
557
558 return 0;
559 }
560
stm32_get_trigger_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)561 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
562 const struct iio_chan_spec *chan)
563 {
564 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
565 u32 smcr;
566
567 regmap_read(priv->regmap, TIM_SMCR, &smcr);
568
569 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
570 }
571
572 static const struct iio_enum stm32_trigger_mode_enum = {
573 .items = stm32_trigger_modes,
574 .num_items = ARRAY_SIZE(stm32_trigger_modes),
575 .set = stm32_set_trigger_mode,
576 .get = stm32_get_trigger_mode
577 };
578
579 static const char *const stm32_enable_modes[] = {
580 "always",
581 "gated",
582 "triggered",
583 };
584
stm32_enable_mode2sms(int mode)585 static int stm32_enable_mode2sms(int mode)
586 {
587 switch (mode) {
588 case 0:
589 return 0;
590 case 1:
591 return 5;
592 case 2:
593 return 6;
594 }
595
596 return -EINVAL;
597 }
598
stm32_set_enable_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)599 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
600 const struct iio_chan_spec *chan,
601 unsigned int mode)
602 {
603 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
604 int sms = stm32_enable_mode2sms(mode);
605
606 if (sms < 0)
607 return sms;
608 /*
609 * Triggered mode sets CEN bit automatically by hardware. So, first
610 * enable counter clock, so it can use it. Keeps it in sync with CEN.
611 */
612 mutex_lock(&priv->lock);
613 if (sms == 6 && !priv->enabled) {
614 clk_enable(priv->clk);
615 priv->enabled = true;
616 }
617 mutex_unlock(&priv->lock);
618
619 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
620
621 return 0;
622 }
623
stm32_sms2enable_mode(int mode)624 static int stm32_sms2enable_mode(int mode)
625 {
626 switch (mode) {
627 case 0:
628 return 0;
629 case 5:
630 return 1;
631 case 6:
632 return 2;
633 }
634
635 return -EINVAL;
636 }
637
stm32_get_enable_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)638 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
639 const struct iio_chan_spec *chan)
640 {
641 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
642 u32 smcr;
643
644 regmap_read(priv->regmap, TIM_SMCR, &smcr);
645 smcr &= TIM_SMCR_SMS;
646
647 return stm32_sms2enable_mode(smcr);
648 }
649
650 static const struct iio_enum stm32_enable_mode_enum = {
651 .items = stm32_enable_modes,
652 .num_items = ARRAY_SIZE(stm32_enable_modes),
653 .set = stm32_set_enable_mode,
654 .get = stm32_get_enable_mode
655 };
656
stm32_count_get_preset(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)657 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
658 uintptr_t private,
659 const struct iio_chan_spec *chan,
660 char *buf)
661 {
662 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
663 u32 arr;
664
665 regmap_read(priv->regmap, TIM_ARR, &arr);
666
667 return snprintf(buf, PAGE_SIZE, "%u\n", arr);
668 }
669
stm32_count_set_preset(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)670 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
671 uintptr_t private,
672 const struct iio_chan_spec *chan,
673 const char *buf, size_t len)
674 {
675 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
676 unsigned int preset;
677 int ret;
678
679 ret = kstrtouint(buf, 0, &preset);
680 if (ret)
681 return ret;
682
683 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
684 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
685 regmap_write(priv->regmap, TIM_ARR, preset);
686
687 return len;
688 }
689
690 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
691 {
692 .name = "preset",
693 .shared = IIO_SEPARATE,
694 .read = stm32_count_get_preset,
695 .write = stm32_count_set_preset
696 },
697 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
698 IIO_ENUM_AVAILABLE("enable_mode", IIO_SHARED_BY_TYPE, &stm32_enable_mode_enum),
699 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
700 IIO_ENUM_AVAILABLE("trigger_mode", IIO_SHARED_BY_TYPE, &stm32_trigger_mode_enum),
701 {}
702 };
703
704 static const struct iio_chan_spec stm32_trigger_channel = {
705 .type = IIO_COUNT,
706 .channel = 0,
707 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
708 BIT(IIO_CHAN_INFO_ENABLE) |
709 BIT(IIO_CHAN_INFO_SCALE),
710 .ext_info = stm32_trigger_count_info,
711 .indexed = 1
712 };
713
stm32_setup_counter_device(struct device * dev)714 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
715 {
716 struct iio_dev *indio_dev;
717 int ret;
718
719 indio_dev = devm_iio_device_alloc(dev,
720 sizeof(struct stm32_timer_trigger));
721 if (!indio_dev)
722 return NULL;
723
724 indio_dev->name = dev_name(dev);
725 indio_dev->info = &stm32_trigger_info;
726 indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
727 indio_dev->num_channels = 1;
728 indio_dev->channels = &stm32_trigger_channel;
729
730 ret = devm_iio_device_register(dev, indio_dev);
731 if (ret)
732 return NULL;
733
734 return iio_priv(indio_dev);
735 }
736
737 /**
738 * is_stm32_timer_trigger
739 * @trig: trigger to be checked
740 *
741 * return true if the trigger is a valid stm32 iio timer trigger
742 * either return false
743 */
is_stm32_timer_trigger(struct iio_trigger * trig)744 bool is_stm32_timer_trigger(struct iio_trigger *trig)
745 {
746 return (trig->ops == &timer_trigger_ops);
747 }
748 EXPORT_SYMBOL(is_stm32_timer_trigger);
749
stm32_timer_detect_trgo2(struct stm32_timer_trigger * priv)750 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
751 {
752 u32 val;
753
754 /*
755 * Master mode selection 2 bits can only be written and read back when
756 * timer supports it.
757 */
758 regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
759 regmap_read(priv->regmap, TIM_CR2, &val);
760 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
761 priv->has_trgo2 = !!val;
762 }
763
stm32_timer_trigger_probe(struct platform_device * pdev)764 static int stm32_timer_trigger_probe(struct platform_device *pdev)
765 {
766 struct device *dev = &pdev->dev;
767 struct stm32_timer_trigger *priv;
768 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
769 const struct stm32_timer_trigger_cfg *cfg;
770 unsigned int index;
771 int ret;
772
773 ret = device_property_read_u32(dev, "reg", &index);
774 if (ret)
775 return ret;
776
777 cfg = device_get_match_data(dev);
778
779 if (index >= ARRAY_SIZE(triggers_table) ||
780 index >= cfg->num_valids_table)
781 return -EINVAL;
782
783 /* Create an IIO device only if we have triggers to be validated */
784 if (*cfg->valids_table[index])
785 priv = stm32_setup_counter_device(dev);
786 else
787 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
788
789 if (!priv)
790 return -ENOMEM;
791
792 priv->dev = dev;
793 priv->regmap = ddata->regmap;
794 priv->clk = ddata->clk;
795 priv->max_arr = ddata->max_arr;
796 priv->triggers = triggers_table[index];
797 priv->valids = cfg->valids_table[index];
798 stm32_timer_detect_trgo2(priv);
799 mutex_init(&priv->lock);
800
801 ret = stm32_register_iio_triggers(priv);
802 if (ret)
803 return ret;
804
805 platform_set_drvdata(pdev, priv);
806
807 return 0;
808 }
809
stm32_timer_trigger_remove(struct platform_device * pdev)810 static void stm32_timer_trigger_remove(struct platform_device *pdev)
811 {
812 struct stm32_timer_trigger *priv = platform_get_drvdata(pdev);
813 u32 val;
814
815 /* Unregister triggers before everything can be safely turned off */
816 stm32_unregister_iio_triggers(priv);
817
818 /* Check if nobody else use the timer, then disable it */
819 regmap_read(priv->regmap, TIM_CCER, &val);
820 if (!(val & TIM_CCER_CCXE))
821 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
822
823 if (priv->enabled)
824 clk_disable(priv->clk);
825 }
826
stm32_timer_trigger_suspend(struct device * dev)827 static int stm32_timer_trigger_suspend(struct device *dev)
828 {
829 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
830
831 /* Only take care of enabled timer: don't disturb other MFD child */
832 if (priv->enabled) {
833 /* Backup registers that may get lost in low power mode */
834 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
835 regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2);
836 regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc);
837 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
838 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
839 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
840
841 /* Disable the timer */
842 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
843 clk_disable(priv->clk);
844 }
845
846 return 0;
847 }
848
stm32_timer_trigger_resume(struct device * dev)849 static int stm32_timer_trigger_resume(struct device *dev)
850 {
851 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
852 int ret;
853
854 if (priv->enabled) {
855 ret = clk_enable(priv->clk);
856 if (ret)
857 return ret;
858
859 /* restore master/slave modes */
860 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
861 regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2);
862
863 /* restore sampling_frequency (trgo / trgo2 triggers) */
864 regmap_write(priv->regmap, TIM_PSC, priv->bak.psc);
865 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
866 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
867
868 /* Also re-enables the timer */
869 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
870 }
871
872 return 0;
873 }
874
875 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_timer_trigger_pm_ops,
876 stm32_timer_trigger_suspend,
877 stm32_timer_trigger_resume);
878
879 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
880 .valids_table = valids_table,
881 .num_valids_table = ARRAY_SIZE(valids_table),
882 };
883
884 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
885 .valids_table = stm32h7_valids_table,
886 .num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
887 };
888
889 static const struct of_device_id stm32_trig_of_match[] = {
890 {
891 .compatible = "st,stm32-timer-trigger",
892 .data = (void *)&stm32_timer_trg_cfg,
893 }, {
894 .compatible = "st,stm32h7-timer-trigger",
895 .data = (void *)&stm32h7_timer_trg_cfg,
896 },
897 { /* end node */ },
898 };
899 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
900
901 static struct platform_driver stm32_timer_trigger_driver = {
902 .probe = stm32_timer_trigger_probe,
903 .remove_new = stm32_timer_trigger_remove,
904 .driver = {
905 .name = "stm32-timer-trigger",
906 .of_match_table = stm32_trig_of_match,
907 .pm = pm_sleep_ptr(&stm32_timer_trigger_pm_ops),
908 },
909 };
910 module_platform_driver(stm32_timer_trigger_driver);
911
912 MODULE_ALIAS("platform:stm32-timer-trigger");
913 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
914 MODULE_LICENSE("GPL v2");
915