1caa8ce7fSGwendal Grignou // SPDX-License-Identifier: GPL-2.0
2caa8ce7fSGwendal Grignou /*
3caa8ce7fSGwendal Grignou * Copyright 2021 Google LLC.
4caa8ce7fSGwendal Grignou *
5caa8ce7fSGwendal Grignou * Common part of most Semtech SAR sensor.
6caa8ce7fSGwendal Grignou */
7caa8ce7fSGwendal Grignou
8caa8ce7fSGwendal Grignou #include <linux/bitops.h>
9caa8ce7fSGwendal Grignou #include <linux/byteorder/generic.h>
10caa8ce7fSGwendal Grignou #include <linux/delay.h>
11caa8ce7fSGwendal Grignou #include <linux/device.h>
12caa8ce7fSGwendal Grignou #include <linux/err.h>
13caa8ce7fSGwendal Grignou #include <linux/export.h>
14caa8ce7fSGwendal Grignou #include <linux/interrupt.h>
15caa8ce7fSGwendal Grignou #include <linux/irqreturn.h>
16caa8ce7fSGwendal Grignou #include <linux/i2c.h>
17caa8ce7fSGwendal Grignou #include <linux/kernel.h>
18caa8ce7fSGwendal Grignou #include <linux/module.h>
19caa8ce7fSGwendal Grignou #include <linux/regmap.h>
20caa8ce7fSGwendal Grignou #include <linux/regulator/consumer.h>
21caa8ce7fSGwendal Grignou #include <vdso/bits.h>
22caa8ce7fSGwendal Grignou
23caa8ce7fSGwendal Grignou #include <linux/iio/buffer.h>
24caa8ce7fSGwendal Grignou #include <linux/iio/events.h>
25caa8ce7fSGwendal Grignou #include <linux/iio/iio.h>
26caa8ce7fSGwendal Grignou #include <linux/iio/trigger.h>
27caa8ce7fSGwendal Grignou #include <linux/iio/triggered_buffer.h>
28caa8ce7fSGwendal Grignou #include <linux/iio/trigger_consumer.h>
29caa8ce7fSGwendal Grignou
30caa8ce7fSGwendal Grignou #include "sx_common.h"
31caa8ce7fSGwendal Grignou
32caa8ce7fSGwendal Grignou /* All Semtech SAR sensors have IRQ bit in the same order. */
33caa8ce7fSGwendal Grignou #define SX_COMMON_CONVDONE_IRQ BIT(0)
34caa8ce7fSGwendal Grignou #define SX_COMMON_FAR_IRQ BIT(2)
35caa8ce7fSGwendal Grignou #define SX_COMMON_CLOSE_IRQ BIT(3)
36caa8ce7fSGwendal Grignou
37caa8ce7fSGwendal Grignou const struct iio_event_spec sx_common_events[3] = {
38caa8ce7fSGwendal Grignou {
39caa8ce7fSGwendal Grignou .type = IIO_EV_TYPE_THRESH,
40caa8ce7fSGwendal Grignou .dir = IIO_EV_DIR_RISING,
41caa8ce7fSGwendal Grignou .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD),
42caa8ce7fSGwendal Grignou },
43caa8ce7fSGwendal Grignou {
44caa8ce7fSGwendal Grignou .type = IIO_EV_TYPE_THRESH,
45caa8ce7fSGwendal Grignou .dir = IIO_EV_DIR_FALLING,
46caa8ce7fSGwendal Grignou .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD),
47caa8ce7fSGwendal Grignou },
48caa8ce7fSGwendal Grignou {
49caa8ce7fSGwendal Grignou .type = IIO_EV_TYPE_THRESH,
50caa8ce7fSGwendal Grignou .dir = IIO_EV_DIR_EITHER,
51caa8ce7fSGwendal Grignou .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
52caa8ce7fSGwendal Grignou BIT(IIO_EV_INFO_HYSTERESIS) |
53caa8ce7fSGwendal Grignou BIT(IIO_EV_INFO_VALUE),
54caa8ce7fSGwendal Grignou },
55caa8ce7fSGwendal Grignou };
56caa8ce7fSGwendal Grignou EXPORT_SYMBOL_NS_GPL(sx_common_events, SEMTECH_PROX);
57caa8ce7fSGwendal Grignou
sx_common_irq_handler(int irq,void * private)58caa8ce7fSGwendal Grignou static irqreturn_t sx_common_irq_handler(int irq, void *private)
59caa8ce7fSGwendal Grignou {
60caa8ce7fSGwendal Grignou struct iio_dev *indio_dev = private;
61caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
62caa8ce7fSGwendal Grignou
63caa8ce7fSGwendal Grignou if (data->trigger_enabled)
64caa8ce7fSGwendal Grignou iio_trigger_poll(data->trig);
65caa8ce7fSGwendal Grignou
66caa8ce7fSGwendal Grignou /*
67caa8ce7fSGwendal Grignou * Even if no event is enabled, we need to wake the thread to clear the
68caa8ce7fSGwendal Grignou * interrupt state by reading SX_COMMON_REG_IRQ_SRC.
69caa8ce7fSGwendal Grignou * It is not possible to do that here because regmap_read takes a mutex.
70caa8ce7fSGwendal Grignou */
71caa8ce7fSGwendal Grignou return IRQ_WAKE_THREAD;
72caa8ce7fSGwendal Grignou }
73caa8ce7fSGwendal Grignou
sx_common_push_events(struct iio_dev * indio_dev)74caa8ce7fSGwendal Grignou static void sx_common_push_events(struct iio_dev *indio_dev)
75caa8ce7fSGwendal Grignou {
76caa8ce7fSGwendal Grignou int ret;
77caa8ce7fSGwendal Grignou unsigned int val, chan;
78caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
79caa8ce7fSGwendal Grignou s64 timestamp = iio_get_time_ns(indio_dev);
80caa8ce7fSGwendal Grignou unsigned long prox_changed;
81caa8ce7fSGwendal Grignou
82caa8ce7fSGwendal Grignou /* Read proximity state on all channels */
83caa8ce7fSGwendal Grignou ret = regmap_read(data->regmap, data->chip_info->reg_stat, &val);
84caa8ce7fSGwendal Grignou if (ret) {
85caa8ce7fSGwendal Grignou dev_err(&data->client->dev, "i2c transfer error in irq\n");
86caa8ce7fSGwendal Grignou return;
87caa8ce7fSGwendal Grignou }
88caa8ce7fSGwendal Grignou
8919d32860SJongpil Jung val >>= data->chip_info->stat_offset;
90caa8ce7fSGwendal Grignou
91caa8ce7fSGwendal Grignou /*
92caa8ce7fSGwendal Grignou * Only iterate over channels with changes on proximity status that have
93caa8ce7fSGwendal Grignou * events enabled.
94caa8ce7fSGwendal Grignou */
95caa8ce7fSGwendal Grignou prox_changed = (data->chan_prox_stat ^ val) & data->chan_event;
96caa8ce7fSGwendal Grignou
97caa8ce7fSGwendal Grignou for_each_set_bit(chan, &prox_changed, data->chip_info->num_channels) {
98caa8ce7fSGwendal Grignou int dir;
99caa8ce7fSGwendal Grignou u64 ev;
100caa8ce7fSGwendal Grignou
101caa8ce7fSGwendal Grignou dir = (val & BIT(chan)) ? IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING;
102caa8ce7fSGwendal Grignou ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, chan,
103caa8ce7fSGwendal Grignou IIO_EV_TYPE_THRESH, dir);
104caa8ce7fSGwendal Grignou
105caa8ce7fSGwendal Grignou iio_push_event(indio_dev, ev, timestamp);
106caa8ce7fSGwendal Grignou }
107caa8ce7fSGwendal Grignou data->chan_prox_stat = val;
108caa8ce7fSGwendal Grignou }
109caa8ce7fSGwendal Grignou
sx_common_enable_irq(struct sx_common_data * data,unsigned int irq)110caa8ce7fSGwendal Grignou static int sx_common_enable_irq(struct sx_common_data *data, unsigned int irq)
111caa8ce7fSGwendal Grignou {
112caa8ce7fSGwendal Grignou if (!data->client->irq)
113caa8ce7fSGwendal Grignou return 0;
1149ba22652STrevor Gamblin return regmap_set_bits(data->regmap, data->chip_info->reg_irq_msk,
115caa8ce7fSGwendal Grignou irq << data->chip_info->irq_msk_offset);
116caa8ce7fSGwendal Grignou }
117caa8ce7fSGwendal Grignou
sx_common_disable_irq(struct sx_common_data * data,unsigned int irq)118caa8ce7fSGwendal Grignou static int sx_common_disable_irq(struct sx_common_data *data, unsigned int irq)
119caa8ce7fSGwendal Grignou {
120caa8ce7fSGwendal Grignou if (!data->client->irq)
121caa8ce7fSGwendal Grignou return 0;
1229ba22652STrevor Gamblin return regmap_clear_bits(data->regmap, data->chip_info->reg_irq_msk,
1239ba22652STrevor Gamblin irq << data->chip_info->irq_msk_offset);
124caa8ce7fSGwendal Grignou }
125caa8ce7fSGwendal Grignou
sx_common_update_chan_en(struct sx_common_data * data,unsigned long chan_read,unsigned long chan_event)126caa8ce7fSGwendal Grignou static int sx_common_update_chan_en(struct sx_common_data *data,
127caa8ce7fSGwendal Grignou unsigned long chan_read,
128caa8ce7fSGwendal Grignou unsigned long chan_event)
129caa8ce7fSGwendal Grignou {
130caa8ce7fSGwendal Grignou int ret;
131caa8ce7fSGwendal Grignou unsigned long channels = chan_read | chan_event;
132caa8ce7fSGwendal Grignou
133caa8ce7fSGwendal Grignou if ((data->chan_read | data->chan_event) != channels) {
134caa8ce7fSGwendal Grignou ret = regmap_update_bits(data->regmap,
135caa8ce7fSGwendal Grignou data->chip_info->reg_enable_chan,
136caa8ce7fSGwendal Grignou data->chip_info->mask_enable_chan,
137caa8ce7fSGwendal Grignou channels);
138caa8ce7fSGwendal Grignou if (ret)
139caa8ce7fSGwendal Grignou return ret;
140caa8ce7fSGwendal Grignou }
141caa8ce7fSGwendal Grignou data->chan_read = chan_read;
142caa8ce7fSGwendal Grignou data->chan_event = chan_event;
143caa8ce7fSGwendal Grignou return 0;
144caa8ce7fSGwendal Grignou }
145caa8ce7fSGwendal Grignou
sx_common_get_read_channel(struct sx_common_data * data,int channel)146caa8ce7fSGwendal Grignou static int sx_common_get_read_channel(struct sx_common_data *data, int channel)
147caa8ce7fSGwendal Grignou {
148caa8ce7fSGwendal Grignou return sx_common_update_chan_en(data, data->chan_read | BIT(channel),
149caa8ce7fSGwendal Grignou data->chan_event);
150caa8ce7fSGwendal Grignou }
151caa8ce7fSGwendal Grignou
sx_common_put_read_channel(struct sx_common_data * data,int channel)152caa8ce7fSGwendal Grignou static int sx_common_put_read_channel(struct sx_common_data *data, int channel)
153caa8ce7fSGwendal Grignou {
154caa8ce7fSGwendal Grignou return sx_common_update_chan_en(data, data->chan_read & ~BIT(channel),
155caa8ce7fSGwendal Grignou data->chan_event);
156caa8ce7fSGwendal Grignou }
157caa8ce7fSGwendal Grignou
sx_common_get_event_channel(struct sx_common_data * data,int channel)158caa8ce7fSGwendal Grignou static int sx_common_get_event_channel(struct sx_common_data *data, int channel)
159caa8ce7fSGwendal Grignou {
160caa8ce7fSGwendal Grignou return sx_common_update_chan_en(data, data->chan_read,
161caa8ce7fSGwendal Grignou data->chan_event | BIT(channel));
162caa8ce7fSGwendal Grignou }
163caa8ce7fSGwendal Grignou
sx_common_put_event_channel(struct sx_common_data * data,int channel)164caa8ce7fSGwendal Grignou static int sx_common_put_event_channel(struct sx_common_data *data, int channel)
165caa8ce7fSGwendal Grignou {
166caa8ce7fSGwendal Grignou return sx_common_update_chan_en(data, data->chan_read,
167caa8ce7fSGwendal Grignou data->chan_event & ~BIT(channel));
168caa8ce7fSGwendal Grignou }
169caa8ce7fSGwendal Grignou
170caa8ce7fSGwendal Grignou /**
171caa8ce7fSGwendal Grignou * sx_common_read_proximity() - Read raw proximity value.
172caa8ce7fSGwendal Grignou * @data: Internal data
173caa8ce7fSGwendal Grignou * @chan: Channel to read
174caa8ce7fSGwendal Grignou * @val: pointer to return read value.
175caa8ce7fSGwendal Grignou *
176caa8ce7fSGwendal Grignou * Request a conversion, wait for the sensor to be ready and
177caa8ce7fSGwendal Grignou * return the raw proximity value.
178caa8ce7fSGwendal Grignou */
sx_common_read_proximity(struct sx_common_data * data,const struct iio_chan_spec * chan,int * val)179caa8ce7fSGwendal Grignou int sx_common_read_proximity(struct sx_common_data *data,
180caa8ce7fSGwendal Grignou const struct iio_chan_spec *chan, int *val)
181caa8ce7fSGwendal Grignou {
182caa8ce7fSGwendal Grignou int ret;
183caa8ce7fSGwendal Grignou __be16 rawval;
184caa8ce7fSGwendal Grignou
185caa8ce7fSGwendal Grignou mutex_lock(&data->mutex);
186caa8ce7fSGwendal Grignou
187caa8ce7fSGwendal Grignou ret = sx_common_get_read_channel(data, chan->channel);
188caa8ce7fSGwendal Grignou if (ret)
189caa8ce7fSGwendal Grignou goto out;
190caa8ce7fSGwendal Grignou
191caa8ce7fSGwendal Grignou ret = sx_common_enable_irq(data, SX_COMMON_CONVDONE_IRQ);
192caa8ce7fSGwendal Grignou if (ret)
193caa8ce7fSGwendal Grignou goto out_put_channel;
194caa8ce7fSGwendal Grignou
195caa8ce7fSGwendal Grignou mutex_unlock(&data->mutex);
196caa8ce7fSGwendal Grignou
197caa8ce7fSGwendal Grignou if (data->client->irq) {
198caa8ce7fSGwendal Grignou ret = wait_for_completion_interruptible(&data->completion);
199caa8ce7fSGwendal Grignou reinit_completion(&data->completion);
200caa8ce7fSGwendal Grignou } else {
201caa8ce7fSGwendal Grignou ret = data->chip_info->ops.wait_for_sample(data);
202caa8ce7fSGwendal Grignou }
203caa8ce7fSGwendal Grignou
204caa8ce7fSGwendal Grignou mutex_lock(&data->mutex);
205caa8ce7fSGwendal Grignou
206caa8ce7fSGwendal Grignou if (ret)
207caa8ce7fSGwendal Grignou goto out_disable_irq;
208caa8ce7fSGwendal Grignou
209caa8ce7fSGwendal Grignou ret = data->chip_info->ops.read_prox_data(data, chan, &rawval);
210caa8ce7fSGwendal Grignou if (ret)
211caa8ce7fSGwendal Grignou goto out_disable_irq;
212caa8ce7fSGwendal Grignou
213caa8ce7fSGwendal Grignou *val = sign_extend32(be16_to_cpu(rawval), chan->scan_type.realbits - 1);
214caa8ce7fSGwendal Grignou
215caa8ce7fSGwendal Grignou ret = sx_common_disable_irq(data, SX_COMMON_CONVDONE_IRQ);
216caa8ce7fSGwendal Grignou if (ret)
217caa8ce7fSGwendal Grignou goto out_put_channel;
218caa8ce7fSGwendal Grignou
219caa8ce7fSGwendal Grignou ret = sx_common_put_read_channel(data, chan->channel);
220caa8ce7fSGwendal Grignou if (ret)
221caa8ce7fSGwendal Grignou goto out;
222caa8ce7fSGwendal Grignou
223caa8ce7fSGwendal Grignou mutex_unlock(&data->mutex);
224caa8ce7fSGwendal Grignou
225caa8ce7fSGwendal Grignou return IIO_VAL_INT;
226caa8ce7fSGwendal Grignou
227caa8ce7fSGwendal Grignou out_disable_irq:
228caa8ce7fSGwendal Grignou sx_common_disable_irq(data, SX_COMMON_CONVDONE_IRQ);
229caa8ce7fSGwendal Grignou out_put_channel:
230caa8ce7fSGwendal Grignou sx_common_put_read_channel(data, chan->channel);
231caa8ce7fSGwendal Grignou out:
232caa8ce7fSGwendal Grignou mutex_unlock(&data->mutex);
233caa8ce7fSGwendal Grignou
234caa8ce7fSGwendal Grignou return ret;
235caa8ce7fSGwendal Grignou }
236caa8ce7fSGwendal Grignou EXPORT_SYMBOL_NS_GPL(sx_common_read_proximity, SEMTECH_PROX);
237caa8ce7fSGwendal Grignou
238caa8ce7fSGwendal Grignou /**
239caa8ce7fSGwendal Grignou * sx_common_read_event_config() - Configure event setting.
240caa8ce7fSGwendal Grignou * @indio_dev: iio device object
241caa8ce7fSGwendal Grignou * @chan: Channel to read
242caa8ce7fSGwendal Grignou * @type: Type of event (unused)
243caa8ce7fSGwendal Grignou * @dir: Direction of event (unused)
244caa8ce7fSGwendal Grignou *
245caa8ce7fSGwendal Grignou * return if the given channel is used for event gathering.
246caa8ce7fSGwendal Grignou */
sx_common_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)247caa8ce7fSGwendal Grignou int sx_common_read_event_config(struct iio_dev *indio_dev,
248caa8ce7fSGwendal Grignou const struct iio_chan_spec *chan,
249caa8ce7fSGwendal Grignou enum iio_event_type type,
250caa8ce7fSGwendal Grignou enum iio_event_direction dir)
251caa8ce7fSGwendal Grignou {
252caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
253caa8ce7fSGwendal Grignou
254caa8ce7fSGwendal Grignou return !!(data->chan_event & BIT(chan->channel));
255caa8ce7fSGwendal Grignou }
256caa8ce7fSGwendal Grignou EXPORT_SYMBOL_NS_GPL(sx_common_read_event_config, SEMTECH_PROX);
257caa8ce7fSGwendal Grignou
258caa8ce7fSGwendal Grignou /**
259caa8ce7fSGwendal Grignou * sx_common_write_event_config() - Configure event setting.
260caa8ce7fSGwendal Grignou * @indio_dev: iio device object
261caa8ce7fSGwendal Grignou * @chan: Channel to enable
262caa8ce7fSGwendal Grignou * @type: Type of event (unused)
263caa8ce7fSGwendal Grignou * @dir: Direction of event (unused)
264caa8ce7fSGwendal Grignou * @state: State of the event.
265caa8ce7fSGwendal Grignou *
266caa8ce7fSGwendal Grignou * Enable/Disable event on a given channel.
267caa8ce7fSGwendal Grignou */
sx_common_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)268caa8ce7fSGwendal Grignou int sx_common_write_event_config(struct iio_dev *indio_dev,
269caa8ce7fSGwendal Grignou const struct iio_chan_spec *chan,
270caa8ce7fSGwendal Grignou enum iio_event_type type,
271caa8ce7fSGwendal Grignou enum iio_event_direction dir, int state)
272caa8ce7fSGwendal Grignou {
273caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
274caa8ce7fSGwendal Grignou unsigned int eventirq = SX_COMMON_FAR_IRQ | SX_COMMON_CLOSE_IRQ;
275caa8ce7fSGwendal Grignou int ret;
276caa8ce7fSGwendal Grignou
277caa8ce7fSGwendal Grignou /* If the state hasn't changed, there's nothing to do. */
278caa8ce7fSGwendal Grignou if (!!(data->chan_event & BIT(chan->channel)) == state)
279caa8ce7fSGwendal Grignou return 0;
280caa8ce7fSGwendal Grignou
281caa8ce7fSGwendal Grignou mutex_lock(&data->mutex);
282caa8ce7fSGwendal Grignou if (state) {
283caa8ce7fSGwendal Grignou ret = sx_common_get_event_channel(data, chan->channel);
284caa8ce7fSGwendal Grignou if (ret)
285caa8ce7fSGwendal Grignou goto out_unlock;
286caa8ce7fSGwendal Grignou if (!(data->chan_event & ~BIT(chan->channel))) {
287caa8ce7fSGwendal Grignou ret = sx_common_enable_irq(data, eventirq);
288caa8ce7fSGwendal Grignou if (ret)
289caa8ce7fSGwendal Grignou sx_common_put_event_channel(data, chan->channel);
290caa8ce7fSGwendal Grignou }
291caa8ce7fSGwendal Grignou } else {
292caa8ce7fSGwendal Grignou ret = sx_common_put_event_channel(data, chan->channel);
293caa8ce7fSGwendal Grignou if (ret)
294caa8ce7fSGwendal Grignou goto out_unlock;
295caa8ce7fSGwendal Grignou if (!data->chan_event) {
296caa8ce7fSGwendal Grignou ret = sx_common_disable_irq(data, eventirq);
297caa8ce7fSGwendal Grignou if (ret)
298caa8ce7fSGwendal Grignou sx_common_get_event_channel(data, chan->channel);
299caa8ce7fSGwendal Grignou }
300caa8ce7fSGwendal Grignou }
301caa8ce7fSGwendal Grignou
302caa8ce7fSGwendal Grignou out_unlock:
303caa8ce7fSGwendal Grignou mutex_unlock(&data->mutex);
304caa8ce7fSGwendal Grignou return ret;
305caa8ce7fSGwendal Grignou }
306caa8ce7fSGwendal Grignou EXPORT_SYMBOL_NS_GPL(sx_common_write_event_config, SEMTECH_PROX);
307caa8ce7fSGwendal Grignou
sx_common_set_trigger_state(struct iio_trigger * trig,bool state)308caa8ce7fSGwendal Grignou static int sx_common_set_trigger_state(struct iio_trigger *trig, bool state)
309caa8ce7fSGwendal Grignou {
310caa8ce7fSGwendal Grignou struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
311caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
312caa8ce7fSGwendal Grignou int ret = 0;
313caa8ce7fSGwendal Grignou
314caa8ce7fSGwendal Grignou mutex_lock(&data->mutex);
315caa8ce7fSGwendal Grignou
316caa8ce7fSGwendal Grignou if (state)
317caa8ce7fSGwendal Grignou ret = sx_common_enable_irq(data, SX_COMMON_CONVDONE_IRQ);
318caa8ce7fSGwendal Grignou else if (!data->chan_read)
319caa8ce7fSGwendal Grignou ret = sx_common_disable_irq(data, SX_COMMON_CONVDONE_IRQ);
320caa8ce7fSGwendal Grignou if (ret)
321caa8ce7fSGwendal Grignou goto out;
322caa8ce7fSGwendal Grignou
323caa8ce7fSGwendal Grignou data->trigger_enabled = state;
324caa8ce7fSGwendal Grignou
325caa8ce7fSGwendal Grignou out:
326caa8ce7fSGwendal Grignou mutex_unlock(&data->mutex);
327caa8ce7fSGwendal Grignou
328caa8ce7fSGwendal Grignou return ret;
329caa8ce7fSGwendal Grignou }
330caa8ce7fSGwendal Grignou
331caa8ce7fSGwendal Grignou static const struct iio_trigger_ops sx_common_trigger_ops = {
332caa8ce7fSGwendal Grignou .set_trigger_state = sx_common_set_trigger_state,
333caa8ce7fSGwendal Grignou };
334caa8ce7fSGwendal Grignou
sx_common_irq_thread_handler(int irq,void * private)335caa8ce7fSGwendal Grignou static irqreturn_t sx_common_irq_thread_handler(int irq, void *private)
336caa8ce7fSGwendal Grignou {
337caa8ce7fSGwendal Grignou struct iio_dev *indio_dev = private;
338caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
339caa8ce7fSGwendal Grignou int ret;
340caa8ce7fSGwendal Grignou unsigned int val;
341caa8ce7fSGwendal Grignou
342caa8ce7fSGwendal Grignou mutex_lock(&data->mutex);
343caa8ce7fSGwendal Grignou
344caa8ce7fSGwendal Grignou ret = regmap_read(data->regmap, SX_COMMON_REG_IRQ_SRC, &val);
345caa8ce7fSGwendal Grignou if (ret) {
346caa8ce7fSGwendal Grignou dev_err(&data->client->dev, "i2c transfer error in irq\n");
347caa8ce7fSGwendal Grignou goto out;
348caa8ce7fSGwendal Grignou }
349caa8ce7fSGwendal Grignou
350caa8ce7fSGwendal Grignou if (val & ((SX_COMMON_FAR_IRQ | SX_COMMON_CLOSE_IRQ) << data->chip_info->irq_msk_offset))
351caa8ce7fSGwendal Grignou sx_common_push_events(indio_dev);
352caa8ce7fSGwendal Grignou
353caa8ce7fSGwendal Grignou if (val & (SX_COMMON_CONVDONE_IRQ << data->chip_info->irq_msk_offset))
354caa8ce7fSGwendal Grignou complete(&data->completion);
355caa8ce7fSGwendal Grignou
356caa8ce7fSGwendal Grignou out:
357caa8ce7fSGwendal Grignou mutex_unlock(&data->mutex);
358caa8ce7fSGwendal Grignou
359caa8ce7fSGwendal Grignou return IRQ_HANDLED;
360caa8ce7fSGwendal Grignou }
361caa8ce7fSGwendal Grignou
sx_common_trigger_handler(int irq,void * private)362caa8ce7fSGwendal Grignou static irqreturn_t sx_common_trigger_handler(int irq, void *private)
363caa8ce7fSGwendal Grignou {
364caa8ce7fSGwendal Grignou struct iio_poll_func *pf = private;
365caa8ce7fSGwendal Grignou struct iio_dev *indio_dev = pf->indio_dev;
366caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
367caa8ce7fSGwendal Grignou __be16 val;
368caa8ce7fSGwendal Grignou int bit, ret, i = 0;
369caa8ce7fSGwendal Grignou
370caa8ce7fSGwendal Grignou mutex_lock(&data->mutex);
371caa8ce7fSGwendal Grignou
372*6dd42bb7SNuno Sa iio_for_each_active_channel(indio_dev, bit) {
373caa8ce7fSGwendal Grignou ret = data->chip_info->ops.read_prox_data(data,
374caa8ce7fSGwendal Grignou &indio_dev->channels[bit],
375caa8ce7fSGwendal Grignou &val);
376caa8ce7fSGwendal Grignou if (ret)
377caa8ce7fSGwendal Grignou goto out;
378caa8ce7fSGwendal Grignou
379caa8ce7fSGwendal Grignou data->buffer.channels[i++] = val;
380caa8ce7fSGwendal Grignou }
381caa8ce7fSGwendal Grignou
382caa8ce7fSGwendal Grignou iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
383caa8ce7fSGwendal Grignou pf->timestamp);
384caa8ce7fSGwendal Grignou
385caa8ce7fSGwendal Grignou out:
386caa8ce7fSGwendal Grignou mutex_unlock(&data->mutex);
387caa8ce7fSGwendal Grignou
388caa8ce7fSGwendal Grignou iio_trigger_notify_done(indio_dev->trig);
389caa8ce7fSGwendal Grignou
390caa8ce7fSGwendal Grignou return IRQ_HANDLED;
391caa8ce7fSGwendal Grignou }
392caa8ce7fSGwendal Grignou
sx_common_buffer_preenable(struct iio_dev * indio_dev)393caa8ce7fSGwendal Grignou static int sx_common_buffer_preenable(struct iio_dev *indio_dev)
394caa8ce7fSGwendal Grignou {
395caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
396caa8ce7fSGwendal Grignou unsigned long channels = 0;
397caa8ce7fSGwendal Grignou int bit, ret;
398caa8ce7fSGwendal Grignou
399caa8ce7fSGwendal Grignou mutex_lock(&data->mutex);
400*6dd42bb7SNuno Sa iio_for_each_active_channel(indio_dev, bit)
401caa8ce7fSGwendal Grignou __set_bit(indio_dev->channels[bit].channel, &channels);
402caa8ce7fSGwendal Grignou
403caa8ce7fSGwendal Grignou ret = sx_common_update_chan_en(data, channels, data->chan_event);
404caa8ce7fSGwendal Grignou mutex_unlock(&data->mutex);
405caa8ce7fSGwendal Grignou return ret;
406caa8ce7fSGwendal Grignou }
407caa8ce7fSGwendal Grignou
sx_common_buffer_postdisable(struct iio_dev * indio_dev)408caa8ce7fSGwendal Grignou static int sx_common_buffer_postdisable(struct iio_dev *indio_dev)
409caa8ce7fSGwendal Grignou {
410caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
411caa8ce7fSGwendal Grignou int ret;
412caa8ce7fSGwendal Grignou
413caa8ce7fSGwendal Grignou mutex_lock(&data->mutex);
414caa8ce7fSGwendal Grignou ret = sx_common_update_chan_en(data, 0, data->chan_event);
415caa8ce7fSGwendal Grignou mutex_unlock(&data->mutex);
416caa8ce7fSGwendal Grignou return ret;
417caa8ce7fSGwendal Grignou }
418caa8ce7fSGwendal Grignou
419caa8ce7fSGwendal Grignou static const struct iio_buffer_setup_ops sx_common_buffer_setup_ops = {
420caa8ce7fSGwendal Grignou .preenable = sx_common_buffer_preenable,
421caa8ce7fSGwendal Grignou .postdisable = sx_common_buffer_postdisable,
422caa8ce7fSGwendal Grignou };
423caa8ce7fSGwendal Grignou
sx_common_get_raw_register_config(struct device * dev,struct sx_common_reg_default * reg_def)424e522a6f7SGwendal Grignou void sx_common_get_raw_register_config(struct device *dev,
425e522a6f7SGwendal Grignou struct sx_common_reg_default *reg_def)
426e522a6f7SGwendal Grignou {
427e522a6f7SGwendal Grignou #ifdef CONFIG_ACPI
428e522a6f7SGwendal Grignou struct acpi_device *adev = ACPI_COMPANION(dev);
429e522a6f7SGwendal Grignou u32 raw = 0, ret;
430e522a6f7SGwendal Grignou char prop[80];
431e522a6f7SGwendal Grignou
432e522a6f7SGwendal Grignou if (!reg_def->property || !adev)
433e522a6f7SGwendal Grignou return;
434e522a6f7SGwendal Grignou
435e522a6f7SGwendal Grignou snprintf(prop, ARRAY_SIZE(prop), "%s,reg_%s", acpi_device_hid(adev), reg_def->property);
436e522a6f7SGwendal Grignou ret = device_property_read_u32(dev, prop, &raw);
437e522a6f7SGwendal Grignou if (ret)
438e522a6f7SGwendal Grignou return;
439e522a6f7SGwendal Grignou
440e522a6f7SGwendal Grignou reg_def->def = raw;
441e522a6f7SGwendal Grignou #endif
442e522a6f7SGwendal Grignou }
443e522a6f7SGwendal Grignou EXPORT_SYMBOL_NS_GPL(sx_common_get_raw_register_config, SEMTECH_PROX);
444e522a6f7SGwendal Grignou
445caa8ce7fSGwendal Grignou #define SX_COMMON_SOFT_RESET 0xde
446caa8ce7fSGwendal Grignou
sx_common_init_device(struct device * dev,struct iio_dev * indio_dev)4477008f35cSAndy Shevchenko static int sx_common_init_device(struct device *dev, struct iio_dev *indio_dev)
448caa8ce7fSGwendal Grignou {
449caa8ce7fSGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev);
450caa8ce7fSGwendal Grignou struct sx_common_reg_default tmp;
451caa8ce7fSGwendal Grignou const struct sx_common_reg_default *initval;
452caa8ce7fSGwendal Grignou int ret;
453caa8ce7fSGwendal Grignou unsigned int i, val;
454caa8ce7fSGwendal Grignou
455caa8ce7fSGwendal Grignou ret = regmap_write(data->regmap, data->chip_info->reg_reset,
456caa8ce7fSGwendal Grignou SX_COMMON_SOFT_RESET);
457caa8ce7fSGwendal Grignou if (ret)
458caa8ce7fSGwendal Grignou return ret;
459caa8ce7fSGwendal Grignou
460caa8ce7fSGwendal Grignou usleep_range(1000, 2000); /* power-up time is ~1ms. */
461caa8ce7fSGwendal Grignou
462caa8ce7fSGwendal Grignou /* Clear reset interrupt state by reading SX_COMMON_REG_IRQ_SRC. */
463caa8ce7fSGwendal Grignou ret = regmap_read(data->regmap, SX_COMMON_REG_IRQ_SRC, &val);
464caa8ce7fSGwendal Grignou if (ret)
465caa8ce7fSGwendal Grignou return ret;
466caa8ce7fSGwendal Grignou
467caa8ce7fSGwendal Grignou /* Program defaults from constant or BIOS. */
468caa8ce7fSGwendal Grignou for (i = 0; i < data->chip_info->num_default_regs; i++) {
4697008f35cSAndy Shevchenko initval = data->chip_info->ops.get_default_reg(dev, i, &tmp);
470caa8ce7fSGwendal Grignou ret = regmap_write(data->regmap, initval->reg, initval->def);
471caa8ce7fSGwendal Grignou if (ret)
472caa8ce7fSGwendal Grignou return ret;
473caa8ce7fSGwendal Grignou }
474caa8ce7fSGwendal Grignou
475caa8ce7fSGwendal Grignou return data->chip_info->ops.init_compensation(indio_dev);
476caa8ce7fSGwendal Grignou }
477caa8ce7fSGwendal Grignou
478caa8ce7fSGwendal Grignou /**
479caa8ce7fSGwendal Grignou * sx_common_probe() - Common setup for Semtech SAR sensor
480caa8ce7fSGwendal Grignou * @client: I2C client object
481caa8ce7fSGwendal Grignou * @chip_info: Semtech sensor chip information.
482caa8ce7fSGwendal Grignou * @regmap_config: Sensor registers map configuration.
483caa8ce7fSGwendal Grignou */
sx_common_probe(struct i2c_client * client,const struct sx_common_chip_info * chip_info,const struct regmap_config * regmap_config)484caa8ce7fSGwendal Grignou int sx_common_probe(struct i2c_client *client,
485caa8ce7fSGwendal Grignou const struct sx_common_chip_info *chip_info,
486caa8ce7fSGwendal Grignou const struct regmap_config *regmap_config)
487caa8ce7fSGwendal Grignou {
4881db96143SJonathan Cameron static const char * const regulator_names[] = { "vdd", "svdd" };
489caa8ce7fSGwendal Grignou struct device *dev = &client->dev;
490caa8ce7fSGwendal Grignou struct iio_dev *indio_dev;
491caa8ce7fSGwendal Grignou struct sx_common_data *data;
492caa8ce7fSGwendal Grignou int ret;
493caa8ce7fSGwendal Grignou
494caa8ce7fSGwendal Grignou indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
495caa8ce7fSGwendal Grignou if (!indio_dev)
496caa8ce7fSGwendal Grignou return -ENOMEM;
497caa8ce7fSGwendal Grignou
498caa8ce7fSGwendal Grignou data = iio_priv(indio_dev);
499caa8ce7fSGwendal Grignou
500caa8ce7fSGwendal Grignou data->chip_info = chip_info;
501caa8ce7fSGwendal Grignou data->client = client;
502caa8ce7fSGwendal Grignou mutex_init(&data->mutex);
503caa8ce7fSGwendal Grignou init_completion(&data->completion);
504caa8ce7fSGwendal Grignou
505caa8ce7fSGwendal Grignou data->regmap = devm_regmap_init_i2c(client, regmap_config);
506caa8ce7fSGwendal Grignou if (IS_ERR(data->regmap))
507caa8ce7fSGwendal Grignou return dev_err_probe(dev, PTR_ERR(data->regmap),
508caa8ce7fSGwendal Grignou "Could init register map\n");
509caa8ce7fSGwendal Grignou
5101db96143SJonathan Cameron ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),
5111db96143SJonathan Cameron regulator_names);
512caa8ce7fSGwendal Grignou if (ret)
513caa8ce7fSGwendal Grignou return dev_err_probe(dev, ret, "Unable to get regulators\n");
514caa8ce7fSGwendal Grignou
515caa8ce7fSGwendal Grignou /* Must wait for Tpor time after initial power up */
516caa8ce7fSGwendal Grignou usleep_range(1000, 1100);
517caa8ce7fSGwendal Grignou
518caa8ce7fSGwendal Grignou ret = data->chip_info->ops.check_whoami(dev, indio_dev);
519caa8ce7fSGwendal Grignou if (ret)
520caa8ce7fSGwendal Grignou return dev_err_probe(dev, ret, "error reading WHOAMI\n");
521caa8ce7fSGwendal Grignou
522caa8ce7fSGwendal Grignou indio_dev->modes = INDIO_DIRECT_MODE;
523caa8ce7fSGwendal Grignou
524caa8ce7fSGwendal Grignou indio_dev->channels = data->chip_info->iio_channels;
525caa8ce7fSGwendal Grignou indio_dev->num_channels = data->chip_info->num_iio_channels;
526caa8ce7fSGwendal Grignou indio_dev->info = &data->chip_info->iio_info;
527caa8ce7fSGwendal Grignou
528caa8ce7fSGwendal Grignou i2c_set_clientdata(client, indio_dev);
529caa8ce7fSGwendal Grignou
5307008f35cSAndy Shevchenko ret = sx_common_init_device(dev, indio_dev);
531caa8ce7fSGwendal Grignou if (ret)
532caa8ce7fSGwendal Grignou return dev_err_probe(dev, ret, "Unable to initialize sensor\n");
533caa8ce7fSGwendal Grignou
534caa8ce7fSGwendal Grignou if (client->irq) {
535caa8ce7fSGwendal Grignou ret = devm_request_threaded_irq(dev, client->irq,
536caa8ce7fSGwendal Grignou sx_common_irq_handler,
537caa8ce7fSGwendal Grignou sx_common_irq_thread_handler,
538caa8ce7fSGwendal Grignou IRQF_ONESHOT,
539caa8ce7fSGwendal Grignou "sx_event", indio_dev);
540caa8ce7fSGwendal Grignou if (ret)
541caa8ce7fSGwendal Grignou return dev_err_probe(dev, ret, "No IRQ\n");
542caa8ce7fSGwendal Grignou
543caa8ce7fSGwendal Grignou data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
544caa8ce7fSGwendal Grignou indio_dev->name,
545caa8ce7fSGwendal Grignou iio_device_id(indio_dev));
546caa8ce7fSGwendal Grignou if (!data->trig)
547caa8ce7fSGwendal Grignou return -ENOMEM;
548caa8ce7fSGwendal Grignou
549caa8ce7fSGwendal Grignou data->trig->ops = &sx_common_trigger_ops;
550caa8ce7fSGwendal Grignou iio_trigger_set_drvdata(data->trig, indio_dev);
551caa8ce7fSGwendal Grignou
552caa8ce7fSGwendal Grignou ret = devm_iio_trigger_register(dev, data->trig);
553caa8ce7fSGwendal Grignou if (ret)
554caa8ce7fSGwendal Grignou return ret;
555caa8ce7fSGwendal Grignou }
556caa8ce7fSGwendal Grignou
557caa8ce7fSGwendal Grignou ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
558caa8ce7fSGwendal Grignou iio_pollfunc_store_time,
559caa8ce7fSGwendal Grignou sx_common_trigger_handler,
560caa8ce7fSGwendal Grignou &sx_common_buffer_setup_ops);
561caa8ce7fSGwendal Grignou if (ret)
562caa8ce7fSGwendal Grignou return ret;
563caa8ce7fSGwendal Grignou
564caa8ce7fSGwendal Grignou return devm_iio_device_register(dev, indio_dev);
565caa8ce7fSGwendal Grignou }
566caa8ce7fSGwendal Grignou EXPORT_SYMBOL_NS_GPL(sx_common_probe, SEMTECH_PROX);
567caa8ce7fSGwendal Grignou
568caa8ce7fSGwendal Grignou MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>");
569caa8ce7fSGwendal Grignou MODULE_DESCRIPTION("Common functions and structures for Semtech sensor");
570caa8ce7fSGwendal Grignou MODULE_LICENSE("GPL v2");
571