1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2021 Google LLC. 4 * 5 * Driver for Semtech's SX9360 capacitive proximity/button solution. 6 * Based on SX9360 driver and copy of datasheet at: 7 * https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf 8 */ 9 10 #include <linux/bits.h> 11 #include <linux/bitfield.h> 12 #include <linux/delay.h> 13 #include <linux/i2c.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/log2.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/pm.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 23 #include <linux/iio/iio.h> 24 25 #include "sx_common.h" 26 27 /* Nominal Oscillator Frequency. */ 28 #define SX9360_FOSC_MHZ 4 29 #define SX9360_FOSC_HZ (SX9360_FOSC_MHZ * 1000000) 30 31 /* Register definitions. */ 32 #define SX9360_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC 33 #define SX9360_REG_STAT 0x01 34 #define SX9360_REG_STAT_COMPSTAT_MASK GENMASK(2, 1) 35 #define SX9360_REG_IRQ_MSK 0x02 36 #define SX9360_CONVDONE_IRQ BIT(0) 37 #define SX9360_FAR_IRQ BIT(2) 38 #define SX9360_CLOSE_IRQ BIT(3) 39 #define SX9360_REG_IRQ_CFG 0x03 40 41 #define SX9360_REG_GNRL_CTRL0 0x10 42 #define SX9360_REG_GNRL_CTRL0_PHEN_MASK GENMASK(1, 0) 43 #define SX9360_REG_GNRL_CTRL1 0x11 44 #define SX9360_REG_GNRL_CTRL1_SCANPERIOD_MASK GENMASK(2, 0) 45 #define SX9360_REG_GNRL_CTRL2 0x12 46 #define SX9360_REG_GNRL_CTRL2_PERIOD_102MS 0x32 47 #define SX9360_REG_GNRL_REG_2_PERIOD_MS(_r) \ 48 (((_r) * 8192) / (SX9360_FOSC_HZ / 1000)) 49 #define SX9360_REG_GNRL_FREQ_2_REG(_f) (((_f) * 8192) / SX9360_FOSC_HZ) 50 #define SX9360_REG_GNRL_REG_2_FREQ(_r) (SX9360_FOSC_HZ / ((_r) * 8192)) 51 52 #define SX9360_REG_AFE_CTRL1 0x21 53 #define SX9360_REG_AFE_CTRL1_RESFILTIN_MASK GENMASK(3, 0) 54 #define SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS 0 55 #define SX9360_REG_AFE_PARAM0_PHR 0x22 56 #define SX9360_REG_AFE_PARAM1_PHR 0x23 57 #define SX9360_REG_AFE_PARAM0_PHM 0x24 58 #define SX9360_REG_AFE_PARAM0_RSVD 0x08 59 #define SX9360_REG_AFE_PARAM0_RESOLUTION_MASK GENMASK(2, 0) 60 #define SX9360_REG_AFE_PARAM0_RESOLUTION_128 0x02 61 #define SX9360_REG_AFE_PARAM1_PHM 0x25 62 #define SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF 0x40 63 #define SX9360_REG_AFE_PARAM1_FREQ_83_33HZ 0x06 64 65 #define SX9360_REG_PROX_CTRL0_PHR 0x40 66 #define SX9360_REG_PROX_CTRL0_PHM 0x41 67 #define SX9360_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3) 68 #define SX9360_REG_PROX_CTRL0_GAIN_1 0x80 69 #define SX9360_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0) 70 #define SX9360_REG_PROX_CTRL0_RAWFILT_1P50 0x01 71 #define SX9360_REG_PROX_CTRL1 0x42 72 #define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_MASK GENMASK(5, 3) 73 #define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K 0x20 74 #define SX9360_REG_PROX_CTRL2 0x43 75 #define SX9360_REG_PROX_CTRL2_AVGDEB_MASK GENMASK(7, 6) 76 #define SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES 0x40 77 #define SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K 0x20 78 #define SX9360_REG_PROX_CTRL3 0x44 79 #define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_MASK GENMASK(5, 3) 80 #define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 0x08 81 #define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK GENMASK(2, 0) 82 #define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256 0x04 83 #define SX9360_REG_PROX_CTRL4 0x45 84 #define SX9360_REG_PROX_CTRL4_HYST_MASK GENMASK(5, 4) 85 #define SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK GENMASK(3, 2) 86 #define SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK GENMASK(1, 0) 87 #define SX9360_REG_PROX_CTRL5 0x46 88 #define SX9360_REG_PROX_CTRL5_PROXTHRESH_32 0x08 89 90 #define SX9360_REG_REF_CORR0 0x60 91 #define SX9360_REG_REF_CORR1 0x61 92 93 #define SX9360_REG_USEFUL_PHR_MSB 0x90 94 #define SX9360_REG_USEFUL_PHR_LSB 0x91 95 96 #define SX9360_REG_OFFSET_PMR_MSB 0x92 97 #define SX9360_REG_OFFSET_PMR_LSB 0x93 98 99 #define SX9360_REG_USEFUL_PHM_MSB 0x94 100 #define SX9360_REG_USEFUL_PHM_LSB 0x95 101 102 #define SX9360_REG_AVG_PHM_MSB 0x96 103 #define SX9360_REG_AVG_PHM_LSB 0x97 104 105 #define SX9360_REG_DIFF_PHM_MSB 0x98 106 #define SX9360_REG_DIFF_PHM_LSB 0x99 107 108 #define SX9360_REG_OFFSET_PHM_MSB 0x9a 109 #define SX9360_REG_OFFSET_PHM_LSB 0x9b 110 111 #define SX9360_REG_USE_FILTER_MSB 0x9a 112 #define SX9360_REG_USE_FILTER_LSB 0x9b 113 114 #define SX9360_REG_RESET 0xcf 115 /* Write this to REG_RESET to do a soft reset. */ 116 #define SX9360_SOFT_RESET 0xde 117 118 #define SX9360_REG_WHOAMI 0xfa 119 #define SX9360_WHOAMI_VALUE 0x60 120 121 #define SX9360_REG_REVISION 0xfe 122 123 /* 2 channels, Phase Reference and Measurement. */ 124 #define SX9360_NUM_CHANNELS 2 125 126 static const struct iio_chan_spec sx9360_channels[] = { 127 { 128 .type = IIO_PROXIMITY, 129 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 130 BIT(IIO_CHAN_INFO_HARDWAREGAIN), 131 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 132 .info_mask_separate_available = 133 BIT(IIO_CHAN_INFO_HARDWAREGAIN), 134 .info_mask_shared_by_all_available = 135 BIT(IIO_CHAN_INFO_SAMP_FREQ), 136 .indexed = 1, 137 .address = SX9360_REG_USEFUL_PHR_MSB, 138 .channel = 0, 139 .scan_index = 0, 140 .scan_type = { 141 .sign = 's', 142 .realbits = 12, 143 .storagebits = 16, 144 .endianness = IIO_BE, 145 }, 146 }, 147 { 148 .type = IIO_PROXIMITY, 149 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 150 BIT(IIO_CHAN_INFO_HARDWAREGAIN), 151 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 152 .info_mask_separate_available = 153 BIT(IIO_CHAN_INFO_HARDWAREGAIN), 154 .info_mask_shared_by_all_available = 155 BIT(IIO_CHAN_INFO_SAMP_FREQ), 156 .indexed = 1, 157 .address = SX9360_REG_USEFUL_PHM_MSB, 158 .event_spec = sx_common_events, 159 .num_event_specs = ARRAY_SIZE(sx_common_events), 160 .channel = 1, 161 .scan_index = 1, 162 .scan_type = { 163 .sign = 's', 164 .realbits = 12, 165 .storagebits = 16, 166 .endianness = IIO_BE, 167 }, 168 }, 169 IIO_CHAN_SOFT_TIMESTAMP(2), 170 }; 171 172 /* 173 * Each entry contains the integer part (val) and the fractional part, in micro 174 * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO. 175 * 176 * The frequency control register holds the period, with a ~2ms increment. 177 * Therefore the smallest frequency is 4MHz / (2047 * 8192), 178 * The fastest is 4MHz / 8192. 179 * The interval is not linear, but given there is 2047 possible value, 180 * Returns the fake increment of (Max-Min)/2047 181 */ 182 static const struct { 183 int val; 184 int val2; 185 } sx9360_samp_freq_interval[] = { 186 { 0, 281250 }, /* 4MHz / (8192 * 2047) */ 187 { 0, 281250 }, 188 { 448, 281250 }, /* 4MHz / 8192 */ 189 }; 190 191 static const struct regmap_range sx9360_writable_reg_ranges[] = { 192 /* 193 * To set COMPSTAT for compensation, even if datasheet says register is 194 * RO. 195 */ 196 regmap_reg_range(SX9360_REG_STAT, SX9360_REG_IRQ_CFG), 197 regmap_reg_range(SX9360_REG_GNRL_CTRL0, SX9360_REG_GNRL_CTRL2), 198 regmap_reg_range(SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_PARAM1_PHM), 199 regmap_reg_range(SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL5), 200 regmap_reg_range(SX9360_REG_REF_CORR0, SX9360_REG_REF_CORR1), 201 regmap_reg_range(SX9360_REG_OFFSET_PMR_MSB, SX9360_REG_OFFSET_PMR_LSB), 202 regmap_reg_range(SX9360_REG_RESET, SX9360_REG_RESET), 203 }; 204 205 static const struct regmap_access_table sx9360_writeable_regs = { 206 .yes_ranges = sx9360_writable_reg_ranges, 207 .n_yes_ranges = ARRAY_SIZE(sx9360_writable_reg_ranges), 208 }; 209 210 /* 211 * All allocated registers are readable, so we just list unallocated 212 * ones. 213 */ 214 static const struct regmap_range sx9360_non_readable_reg_ranges[] = { 215 regmap_reg_range(SX9360_REG_IRQ_CFG + 1, SX9360_REG_GNRL_CTRL0 - 1), 216 regmap_reg_range(SX9360_REG_GNRL_CTRL2 + 1, SX9360_REG_AFE_CTRL1 - 1), 217 regmap_reg_range(SX9360_REG_AFE_PARAM1_PHM + 1, 218 SX9360_REG_PROX_CTRL0_PHR - 1), 219 regmap_reg_range(SX9360_REG_PROX_CTRL5 + 1, SX9360_REG_REF_CORR0 - 1), 220 regmap_reg_range(SX9360_REG_REF_CORR1 + 1, 221 SX9360_REG_USEFUL_PHR_MSB - 1), 222 regmap_reg_range(SX9360_REG_USE_FILTER_LSB + 1, SX9360_REG_RESET - 1), 223 regmap_reg_range(SX9360_REG_RESET + 1, SX9360_REG_WHOAMI - 1), 224 regmap_reg_range(SX9360_REG_WHOAMI + 1, SX9360_REG_REVISION - 1), 225 }; 226 227 static const struct regmap_access_table sx9360_readable_regs = { 228 .no_ranges = sx9360_non_readable_reg_ranges, 229 .n_no_ranges = ARRAY_SIZE(sx9360_non_readable_reg_ranges), 230 }; 231 232 static const struct regmap_range sx9360_volatile_reg_ranges[] = { 233 regmap_reg_range(SX9360_REG_IRQ_SRC, SX9360_REG_STAT), 234 regmap_reg_range(SX9360_REG_USEFUL_PHR_MSB, SX9360_REG_USE_FILTER_LSB), 235 regmap_reg_range(SX9360_REG_WHOAMI, SX9360_REG_WHOAMI), 236 regmap_reg_range(SX9360_REG_REVISION, SX9360_REG_REVISION), 237 }; 238 239 static const struct regmap_access_table sx9360_volatile_regs = { 240 .yes_ranges = sx9360_volatile_reg_ranges, 241 .n_yes_ranges = ARRAY_SIZE(sx9360_volatile_reg_ranges), 242 }; 243 244 static const struct regmap_config sx9360_regmap_config = { 245 .reg_bits = 8, 246 .val_bits = 8, 247 248 .max_register = SX9360_REG_REVISION, 249 .cache_type = REGCACHE_RBTREE, 250 251 .wr_table = &sx9360_writeable_regs, 252 .rd_table = &sx9360_readable_regs, 253 .volatile_table = &sx9360_volatile_regs, 254 }; 255 256 static int sx9360_read_prox_data(struct sx_common_data *data, 257 const struct iio_chan_spec *chan, 258 __be16 *val) 259 { 260 return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val)); 261 } 262 263 /* 264 * If we have no interrupt support, we have to wait for a scan period 265 * after enabling a channel to get a result. 266 */ 267 static int sx9360_wait_for_sample(struct sx_common_data *data) 268 { 269 int ret; 270 __be16 buf; 271 272 ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1, 273 &buf, sizeof(buf)); 274 if (ret < 0) 275 return ret; 276 msleep(SX9360_REG_GNRL_REG_2_PERIOD_MS(be16_to_cpu(buf))); 277 278 return 0; 279 } 280 281 static int sx9360_read_gain(struct sx_common_data *data, 282 const struct iio_chan_spec *chan, int *val) 283 { 284 unsigned int reg, regval; 285 int ret; 286 287 reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel; 288 ret = regmap_read(data->regmap, reg, ®val); 289 if (ret) 290 return ret; 291 292 *val = 1 << FIELD_GET(SX9360_REG_PROX_CTRL0_GAIN_MASK, regval); 293 294 return IIO_VAL_INT; 295 } 296 297 static int sx9360_read_samp_freq(struct sx_common_data *data, 298 int *val, int *val2) 299 { 300 int ret, divisor; 301 __be16 buf; 302 303 ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1, 304 &buf, sizeof(buf)); 305 if (ret < 0) 306 return ret; 307 divisor = be16_to_cpu(buf); 308 if (divisor == 0) { 309 *val = 0; 310 return IIO_VAL_INT; 311 } 312 313 *val = SX9360_FOSC_HZ; 314 *val2 = divisor * 8192; 315 316 return IIO_VAL_FRACTIONAL; 317 } 318 319 static int sx9360_read_raw(struct iio_dev *indio_dev, 320 const struct iio_chan_spec *chan, 321 int *val, int *val2, long mask) 322 { 323 struct sx_common_data *data = iio_priv(indio_dev); 324 325 switch (mask) { 326 case IIO_CHAN_INFO_RAW: 327 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) 328 return sx_common_read_proximity(data, chan, val); 329 unreachable(); 330 case IIO_CHAN_INFO_HARDWAREGAIN: 331 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) 332 return sx9360_read_gain(data, chan, val); 333 unreachable(); 334 case IIO_CHAN_INFO_SAMP_FREQ: 335 return sx9360_read_samp_freq(data, val, val2); 336 default: 337 return -EINVAL; 338 } 339 } 340 341 static const char *sx9360_channel_labels[SX9360_NUM_CHANNELS] = { 342 "reference", "main", 343 }; 344 345 static int sx9360_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, 346 char *label) 347 { 348 return sysfs_emit(label, "%s\n", sx9360_channel_labels[chan->channel]); 349 } 350 351 static const int sx9360_gain_vals[] = { 1, 2, 4, 8 }; 352 353 static int sx9360_read_avail(struct iio_dev *indio_dev, 354 struct iio_chan_spec const *chan, 355 const int **vals, int *type, int *length, 356 long mask) 357 { 358 if (chan->type != IIO_PROXIMITY) 359 return -EINVAL; 360 361 switch (mask) { 362 case IIO_CHAN_INFO_HARDWAREGAIN: 363 *type = IIO_VAL_INT; 364 *length = ARRAY_SIZE(sx9360_gain_vals); 365 *vals = sx9360_gain_vals; 366 return IIO_AVAIL_LIST; 367 case IIO_CHAN_INFO_SAMP_FREQ: 368 *type = IIO_VAL_INT_PLUS_MICRO; 369 *length = ARRAY_SIZE(sx9360_samp_freq_interval) * 2; 370 *vals = (int *)sx9360_samp_freq_interval; 371 return IIO_AVAIL_RANGE; 372 default: 373 return -EINVAL; 374 } 375 } 376 377 static int sx9360_set_samp_freq(struct sx_common_data *data, 378 int val, int val2) 379 { 380 int reg; 381 __be16 buf; 382 383 reg = val * 8192 / SX9360_FOSC_HZ + val2 * 8192 / (SX9360_FOSC_MHZ); 384 buf = cpu_to_be16(reg); 385 guard(mutex)(&data->mutex); 386 387 return regmap_bulk_write(data->regmap, SX9360_REG_GNRL_CTRL1, &buf, 388 sizeof(buf)); 389 } 390 391 static int sx9360_read_thresh(struct sx_common_data *data, int *val) 392 { 393 unsigned int regval; 394 int ret; 395 396 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL5, ®val); 397 if (ret) 398 return ret; 399 400 if (regval <= 1) 401 *val = regval; 402 else 403 *val = (regval * regval) / 2; 404 405 return IIO_VAL_INT; 406 } 407 408 static int sx9360_read_hysteresis(struct sx_common_data *data, int *val) 409 { 410 unsigned int regval, pthresh; 411 int ret; 412 413 ret = sx9360_read_thresh(data, &pthresh); 414 if (ret < 0) 415 return ret; 416 417 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 418 if (ret) 419 return ret; 420 421 regval = FIELD_GET(SX9360_REG_PROX_CTRL4_HYST_MASK, regval); 422 if (!regval) 423 *val = 0; 424 else 425 *val = pthresh >> (5 - regval); 426 427 return IIO_VAL_INT; 428 } 429 430 static int sx9360_read_far_debounce(struct sx_common_data *data, int *val) 431 { 432 unsigned int regval; 433 int ret; 434 435 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 436 if (ret) 437 return ret; 438 439 regval = FIELD_GET(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, regval); 440 if (regval) 441 *val = 1 << regval; 442 else 443 *val = 0; 444 445 return IIO_VAL_INT; 446 } 447 448 static int sx9360_read_close_debounce(struct sx_common_data *data, int *val) 449 { 450 unsigned int regval; 451 int ret; 452 453 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 454 if (ret) 455 return ret; 456 457 regval = FIELD_GET(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, regval); 458 if (regval) 459 *val = 1 << regval; 460 else 461 *val = 0; 462 463 return IIO_VAL_INT; 464 } 465 466 static int sx9360_read_event_val(struct iio_dev *indio_dev, 467 const struct iio_chan_spec *chan, 468 enum iio_event_type type, 469 enum iio_event_direction dir, 470 enum iio_event_info info, int *val, int *val2) 471 { 472 struct sx_common_data *data = iio_priv(indio_dev); 473 474 if (chan->type != IIO_PROXIMITY) 475 return -EINVAL; 476 477 switch (info) { 478 case IIO_EV_INFO_VALUE: 479 return sx9360_read_thresh(data, val); 480 case IIO_EV_INFO_PERIOD: 481 switch (dir) { 482 case IIO_EV_DIR_RISING: 483 return sx9360_read_far_debounce(data, val); 484 case IIO_EV_DIR_FALLING: 485 return sx9360_read_close_debounce(data, val); 486 default: 487 return -EINVAL; 488 } 489 case IIO_EV_INFO_HYSTERESIS: 490 return sx9360_read_hysteresis(data, val); 491 default: 492 return -EINVAL; 493 } 494 } 495 496 static int sx9360_write_thresh(struct sx_common_data *data, int _val) 497 { 498 unsigned int val = _val; 499 500 if (val >= 1) 501 val = int_sqrt(2 * val); 502 503 if (val > 0xff) 504 return -EINVAL; 505 506 guard(mutex)(&data->mutex); 507 return regmap_write(data->regmap, SX9360_REG_PROX_CTRL5, val); 508 } 509 510 static int sx9360_write_hysteresis(struct sx_common_data *data, int _val) 511 { 512 unsigned int hyst, val = _val; 513 int ret, pthresh; 514 515 ret = sx9360_read_thresh(data, &pthresh); 516 if (ret < 0) 517 return ret; 518 519 if (val == 0) 520 hyst = 0; 521 else if (val >= pthresh >> 2) 522 hyst = 3; 523 else if (val >= pthresh >> 3) 524 hyst = 2; 525 else if (val >= pthresh >> 4) 526 hyst = 1; 527 else 528 return -EINVAL; 529 530 hyst = FIELD_PREP(SX9360_REG_PROX_CTRL4_HYST_MASK, hyst); 531 guard(mutex)(&data->mutex); 532 return regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 533 SX9360_REG_PROX_CTRL4_HYST_MASK, hyst); 534 } 535 536 static int sx9360_write_far_debounce(struct sx_common_data *data, int _val) 537 { 538 unsigned int regval, val = _val; 539 540 if (val > 0) 541 val = ilog2(val); 542 if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val)) 543 return -EINVAL; 544 545 regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val); 546 547 guard(mutex)(&data->mutex); 548 return regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 549 SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, 550 regval); 551 } 552 553 static int sx9360_write_close_debounce(struct sx_common_data *data, int _val) 554 { 555 unsigned int regval, val = _val; 556 557 if (val > 0) 558 val = ilog2(val); 559 if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val)) 560 return -EINVAL; 561 562 regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val); 563 564 guard(mutex)(&data->mutex); 565 return regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 566 SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, 567 regval); 568 } 569 570 static int sx9360_write_event_val(struct iio_dev *indio_dev, 571 const struct iio_chan_spec *chan, 572 enum iio_event_type type, 573 enum iio_event_direction dir, 574 enum iio_event_info info, int val, int val2) 575 { 576 struct sx_common_data *data = iio_priv(indio_dev); 577 578 if (chan->type != IIO_PROXIMITY) 579 return -EINVAL; 580 581 switch (info) { 582 case IIO_EV_INFO_VALUE: 583 return sx9360_write_thresh(data, val); 584 case IIO_EV_INFO_PERIOD: 585 switch (dir) { 586 case IIO_EV_DIR_RISING: 587 return sx9360_write_far_debounce(data, val); 588 case IIO_EV_DIR_FALLING: 589 return sx9360_write_close_debounce(data, val); 590 default: 591 return -EINVAL; 592 } 593 case IIO_EV_INFO_HYSTERESIS: 594 return sx9360_write_hysteresis(data, val); 595 default: 596 return -EINVAL; 597 } 598 } 599 600 static int sx9360_write_gain(struct sx_common_data *data, 601 const struct iio_chan_spec *chan, int val) 602 { 603 unsigned int gain, reg; 604 605 gain = ilog2(val); 606 reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel; 607 gain = FIELD_PREP(SX9360_REG_PROX_CTRL0_GAIN_MASK, gain); 608 609 guard(mutex)(&data->mutex); 610 return regmap_update_bits(data->regmap, reg, 611 SX9360_REG_PROX_CTRL0_GAIN_MASK, 612 gain); 613 } 614 615 static int sx9360_write_raw(struct iio_dev *indio_dev, 616 const struct iio_chan_spec *chan, int val, int val2, 617 long mask) 618 { 619 struct sx_common_data *data = iio_priv(indio_dev); 620 621 switch (mask) { 622 case IIO_CHAN_INFO_SAMP_FREQ: 623 return sx9360_set_samp_freq(data, val, val2); 624 case IIO_CHAN_INFO_HARDWAREGAIN: 625 return sx9360_write_gain(data, chan, val); 626 default: 627 return -EINVAL; 628 } 629 } 630 631 static const struct sx_common_reg_default sx9360_default_regs[] = { 632 { SX9360_REG_IRQ_MSK, 0x00 }, 633 { SX9360_REG_IRQ_CFG, 0x00, "irq_cfg" }, 634 /* 635 * The lower 2 bits should not be set as it enable sensors measurements. 636 * Turning the detection on before the configuration values are set to 637 * good values can cause the device to return erroneous readings. 638 */ 639 { SX9360_REG_GNRL_CTRL0, 0x00, "gnrl_ctrl0" }, 640 { SX9360_REG_GNRL_CTRL1, 0x00, "gnrl_ctrl1" }, 641 { SX9360_REG_GNRL_CTRL2, SX9360_REG_GNRL_CTRL2_PERIOD_102MS, "gnrl_ctrl2" }, 642 643 { SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS, "afe_ctrl0" }, 644 { SX9360_REG_AFE_PARAM0_PHR, SX9360_REG_AFE_PARAM0_RSVD | 645 SX9360_REG_AFE_PARAM0_RESOLUTION_128, "afe_param0_phr" }, 646 { SX9360_REG_AFE_PARAM1_PHR, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | 647 SX9360_REG_AFE_PARAM1_FREQ_83_33HZ, "afe_param1_phr" }, 648 { SX9360_REG_AFE_PARAM0_PHM, SX9360_REG_AFE_PARAM0_RSVD | 649 SX9360_REG_AFE_PARAM0_RESOLUTION_128, "afe_param0_phm" }, 650 { SX9360_REG_AFE_PARAM1_PHM, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | 651 SX9360_REG_AFE_PARAM1_FREQ_83_33HZ, "afe_param1_phm" }, 652 653 { SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL0_GAIN_1 | 654 SX9360_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl0_phr" }, 655 { SX9360_REG_PROX_CTRL0_PHM, SX9360_REG_PROX_CTRL0_GAIN_1 | 656 SX9360_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl0_phm" }, 657 { SX9360_REG_PROX_CTRL1, SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K, "prox_ctrl1" }, 658 { SX9360_REG_PROX_CTRL2, SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES | 659 SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K, "prox_ctrl2" }, 660 { SX9360_REG_PROX_CTRL3, SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 | 661 SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256, "prox_ctrl3" }, 662 { SX9360_REG_PROX_CTRL4, 0x00, "prox_ctrl4" }, 663 { SX9360_REG_PROX_CTRL5, SX9360_REG_PROX_CTRL5_PROXTHRESH_32, "prox_ctrl5" }, 664 }; 665 666 /* Activate all channels and perform an initial compensation. */ 667 static int sx9360_init_compensation(struct iio_dev *indio_dev) 668 { 669 struct sx_common_data *data = iio_priv(indio_dev); 670 unsigned int val; 671 int ret; 672 673 /* run the compensation phase on all channels */ 674 ret = regmap_set_bits(data->regmap, SX9360_REG_STAT, 675 SX9360_REG_STAT_COMPSTAT_MASK); 676 if (ret) 677 return ret; 678 679 return regmap_read_poll_timeout(data->regmap, SX9360_REG_STAT, val, 680 !(val & SX9360_REG_STAT_COMPSTAT_MASK), 681 20000, 2000000); 682 } 683 684 static const struct sx_common_reg_default * 685 sx9360_get_default_reg(struct device *dev, int idx, 686 struct sx_common_reg_default *reg_def) 687 { 688 u32 raw = 0, pos = 0; 689 int ret; 690 691 memcpy(reg_def, &sx9360_default_regs[idx], sizeof(*reg_def)); 692 switch (reg_def->reg) { 693 case SX9360_REG_AFE_CTRL1: 694 ret = device_property_read_u32(dev, 695 "semtech,input-precharge-resistor-ohms", 696 &raw); 697 if (ret) 698 break; 699 700 reg_def->def &= ~SX9360_REG_AFE_CTRL1_RESFILTIN_MASK; 701 reg_def->def |= FIELD_PREP(SX9360_REG_AFE_CTRL1_RESFILTIN_MASK, 702 raw / 2000); 703 break; 704 case SX9360_REG_AFE_PARAM0_PHR: 705 case SX9360_REG_AFE_PARAM0_PHM: 706 ret = device_property_read_u32(dev, "semtech,resolution", &raw); 707 if (ret) 708 break; 709 710 raw = ilog2(raw) - 3; 711 712 reg_def->def &= ~SX9360_REG_AFE_PARAM0_RESOLUTION_MASK; 713 reg_def->def |= FIELD_PREP(SX9360_REG_AFE_PARAM0_RESOLUTION_MASK, raw); 714 break; 715 case SX9360_REG_PROX_CTRL0_PHR: 716 case SX9360_REG_PROX_CTRL0_PHM: 717 ret = device_property_read_u32(dev, "semtech,proxraw-strength", &raw); 718 if (ret) 719 break; 720 721 reg_def->def &= ~SX9360_REG_PROX_CTRL0_RAWFILT_MASK; 722 reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL0_RAWFILT_MASK, raw); 723 break; 724 case SX9360_REG_PROX_CTRL3: 725 ret = device_property_read_u32(dev, "semtech,avg-pos-strength", 726 &pos); 727 if (ret) 728 break; 729 730 /* Powers of 2, except for a gap between 16 and 64 */ 731 raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3); 732 reg_def->def &= ~SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK; 733 reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK, raw); 734 break; 735 } 736 737 return reg_def; 738 } 739 740 static int sx9360_check_whoami(struct device *dev, struct iio_dev *indio_dev) 741 { 742 /* 743 * Only one sensor for this driver. Assuming the device tree 744 * is correct, just set the sensor name. 745 */ 746 indio_dev->name = "sx9360"; 747 return 0; 748 } 749 750 static const struct sx_common_chip_info sx9360_chip_info = { 751 .reg_stat = SX9360_REG_STAT, 752 .reg_irq_msk = SX9360_REG_IRQ_MSK, 753 .reg_enable_chan = SX9360_REG_GNRL_CTRL0, 754 .reg_reset = SX9360_REG_RESET, 755 756 .mask_enable_chan = SX9360_REG_GNRL_CTRL0_PHEN_MASK, 757 .stat_offset = 2, 758 .num_channels = SX9360_NUM_CHANNELS, 759 .num_default_regs = ARRAY_SIZE(sx9360_default_regs), 760 761 .ops = { 762 .read_prox_data = sx9360_read_prox_data, 763 .check_whoami = sx9360_check_whoami, 764 .init_compensation = sx9360_init_compensation, 765 .wait_for_sample = sx9360_wait_for_sample, 766 .get_default_reg = sx9360_get_default_reg, 767 }, 768 769 .iio_channels = sx9360_channels, 770 .num_iio_channels = ARRAY_SIZE(sx9360_channels), 771 .iio_info = { 772 .read_raw = sx9360_read_raw, 773 .read_avail = sx9360_read_avail, 774 .read_label = sx9360_read_label, 775 .read_event_value = sx9360_read_event_val, 776 .write_event_value = sx9360_write_event_val, 777 .write_raw = sx9360_write_raw, 778 .read_event_config = sx_common_read_event_config, 779 .write_event_config = sx_common_write_event_config, 780 }, 781 }; 782 783 static int sx9360_probe(struct i2c_client *client) 784 { 785 return sx_common_probe(client, &sx9360_chip_info, &sx9360_regmap_config); 786 } 787 788 static int sx9360_suspend(struct device *dev) 789 { 790 struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 791 unsigned int regval; 792 int ret; 793 794 disable_irq_nosync(data->client->irq); 795 796 guard(mutex)(&data->mutex); 797 ret = regmap_read(data->regmap, SX9360_REG_GNRL_CTRL0, ®val); 798 if (ret < 0) 799 return ret; 800 801 data->suspend_ctrl = 802 FIELD_GET(SX9360_REG_GNRL_CTRL0_PHEN_MASK, regval); 803 804 805 /* Disable all phases, send the device to sleep. */ 806 return regmap_write(data->regmap, SX9360_REG_GNRL_CTRL0, 0); 807 } 808 809 static int sx9360_resume(struct device *dev) 810 { 811 struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 812 813 scoped_guard(mutex, &data->mutex) { 814 int ret = regmap_update_bits(data->regmap, 815 SX9360_REG_GNRL_CTRL0, 816 SX9360_REG_GNRL_CTRL0_PHEN_MASK, 817 data->suspend_ctrl); 818 if (ret) 819 return ret; 820 } 821 enable_irq(data->client->irq); 822 return 0; 823 } 824 825 static DEFINE_SIMPLE_DEV_PM_OPS(sx9360_pm_ops, sx9360_suspend, sx9360_resume); 826 827 static const struct acpi_device_id sx9360_acpi_match[] = { 828 { "STH9360", SX9360_WHOAMI_VALUE }, 829 { "SAMM0208", SX9360_WHOAMI_VALUE }, 830 { } 831 }; 832 MODULE_DEVICE_TABLE(acpi, sx9360_acpi_match); 833 834 static const struct of_device_id sx9360_of_match[] = { 835 { .compatible = "semtech,sx9360", (void *)SX9360_WHOAMI_VALUE }, 836 { } 837 }; 838 MODULE_DEVICE_TABLE(of, sx9360_of_match); 839 840 static const struct i2c_device_id sx9360_id[] = { 841 {"sx9360", SX9360_WHOAMI_VALUE }, 842 { } 843 }; 844 MODULE_DEVICE_TABLE(i2c, sx9360_id); 845 846 static struct i2c_driver sx9360_driver = { 847 .driver = { 848 .name = "sx9360", 849 .acpi_match_table = sx9360_acpi_match, 850 .of_match_table = sx9360_of_match, 851 .pm = pm_sleep_ptr(&sx9360_pm_ops), 852 853 /* 854 * Lots of i2c transfers in probe + over 200 ms waiting in 855 * sx9360_init_compensation() mean a slow probe; prefer async 856 * so we don't delay boot if we're builtin to the kernel. 857 */ 858 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 859 }, 860 .probe = sx9360_probe, 861 .id_table = sx9360_id, 862 }; 863 module_i2c_driver(sx9360_driver); 864 865 MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>"); 866 MODULE_DESCRIPTION("Driver for Semtech SX9360 proximity sensor"); 867 MODULE_LICENSE("GPL v2"); 868 MODULE_IMPORT_NS("SEMTECH_PROX"); 869