1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2021 Google LLC. 4 * 5 * Driver for Semtech's SX9360 capacitive proximity/button solution. 6 * Based on SX9360 driver and copy of datasheet at: 7 * https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bits.h> 12 #include <linux/bitfield.h> 13 #include <linux/delay.h> 14 #include <linux/i2c.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/log2.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/pm.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 24 #include <linux/iio/iio.h> 25 26 #include "sx_common.h" 27 28 /* Nominal Oscillator Frequency. */ 29 #define SX9360_FOSC_MHZ 4 30 #define SX9360_FOSC_HZ (SX9360_FOSC_MHZ * 1000000) 31 32 /* Register definitions. */ 33 #define SX9360_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC 34 #define SX9360_REG_STAT 0x01 35 #define SX9360_REG_STAT_COMPSTAT_MASK GENMASK(2, 1) 36 #define SX9360_REG_IRQ_MSK 0x02 37 #define SX9360_CONVDONE_IRQ BIT(0) 38 #define SX9360_FAR_IRQ BIT(2) 39 #define SX9360_CLOSE_IRQ BIT(3) 40 #define SX9360_REG_IRQ_CFG 0x03 41 42 #define SX9360_REG_GNRL_CTRL0 0x10 43 #define SX9360_REG_GNRL_CTRL0_PHEN_MASK GENMASK(1, 0) 44 #define SX9360_REG_GNRL_CTRL1 0x11 45 #define SX9360_REG_GNRL_CTRL1_SCANPERIOD_MASK GENMASK(2, 0) 46 #define SX9360_REG_GNRL_CTRL2 0x12 47 #define SX9360_REG_GNRL_CTRL2_PERIOD_102MS 0x32 48 #define SX9360_REG_GNRL_REG_2_PERIOD_MS(_r) \ 49 (((_r) * 8192) / (SX9360_FOSC_HZ / 1000)) 50 #define SX9360_REG_GNRL_FREQ_2_REG(_f) (((_f) * 8192) / SX9360_FOSC_HZ) 51 #define SX9360_REG_GNRL_REG_2_FREQ(_r) (SX9360_FOSC_HZ / ((_r) * 8192)) 52 53 #define SX9360_REG_AFE_CTRL1 0x21 54 #define SX9360_REG_AFE_CTRL1_RESFILTIN_MASK GENMASK(3, 0) 55 #define SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS 0 56 #define SX9360_REG_AFE_PARAM0_PHR 0x22 57 #define SX9360_REG_AFE_PARAM1_PHR 0x23 58 #define SX9360_REG_AFE_PARAM0_PHM 0x24 59 #define SX9360_REG_AFE_PARAM0_RSVD 0x08 60 #define SX9360_REG_AFE_PARAM0_RESOLUTION_MASK GENMASK(2, 0) 61 #define SX9360_REG_AFE_PARAM0_RESOLUTION_128 0x02 62 #define SX9360_REG_AFE_PARAM1_PHM 0x25 63 #define SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF 0x40 64 #define SX9360_REG_AFE_PARAM1_FREQ_83_33HZ 0x06 65 66 #define SX9360_REG_PROX_CTRL0_PHR 0x40 67 #define SX9360_REG_PROX_CTRL0_PHM 0x41 68 #define SX9360_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3) 69 #define SX9360_REG_PROX_CTRL0_GAIN_1 0x80 70 #define SX9360_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0) 71 #define SX9360_REG_PROX_CTRL0_RAWFILT_1P50 0x01 72 #define SX9360_REG_PROX_CTRL1 0x42 73 #define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_MASK GENMASK(5, 3) 74 #define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K 0x20 75 #define SX9360_REG_PROX_CTRL2 0x43 76 #define SX9360_REG_PROX_CTRL2_AVGDEB_MASK GENMASK(7, 6) 77 #define SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES 0x40 78 #define SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K 0x20 79 #define SX9360_REG_PROX_CTRL3 0x44 80 #define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_MASK GENMASK(5, 3) 81 #define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 0x08 82 #define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK GENMASK(2, 0) 83 #define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256 0x04 84 #define SX9360_REG_PROX_CTRL4 0x45 85 #define SX9360_REG_PROX_CTRL4_HYST_MASK GENMASK(5, 4) 86 #define SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK GENMASK(3, 2) 87 #define SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK GENMASK(1, 0) 88 #define SX9360_REG_PROX_CTRL5 0x46 89 #define SX9360_REG_PROX_CTRL5_PROXTHRESH_32 0x08 90 91 #define SX9360_REG_REF_CORR0 0x60 92 #define SX9360_REG_REF_CORR1 0x61 93 94 #define SX9360_REG_USEFUL_PHR_MSB 0x90 95 #define SX9360_REG_USEFUL_PHR_LSB 0x91 96 97 #define SX9360_REG_OFFSET_PMR_MSB 0x92 98 #define SX9360_REG_OFFSET_PMR_LSB 0x93 99 100 #define SX9360_REG_USEFUL_PHM_MSB 0x94 101 #define SX9360_REG_USEFUL_PHM_LSB 0x95 102 103 #define SX9360_REG_AVG_PHM_MSB 0x96 104 #define SX9360_REG_AVG_PHM_LSB 0x97 105 106 #define SX9360_REG_DIFF_PHM_MSB 0x98 107 #define SX9360_REG_DIFF_PHM_LSB 0x99 108 109 #define SX9360_REG_OFFSET_PHM_MSB 0x9a 110 #define SX9360_REG_OFFSET_PHM_LSB 0x9b 111 112 #define SX9360_REG_USE_FILTER_MSB 0x9a 113 #define SX9360_REG_USE_FILTER_LSB 0x9b 114 115 #define SX9360_REG_RESET 0xcf 116 /* Write this to REG_RESET to do a soft reset. */ 117 #define SX9360_SOFT_RESET 0xde 118 119 #define SX9360_REG_WHOAMI 0xfa 120 #define SX9360_WHOAMI_VALUE 0x60 121 122 #define SX9360_REG_REVISION 0xfe 123 124 /* 2 channels, Phase Reference and Measurement. */ 125 #define SX9360_NUM_CHANNELS 2 126 127 static const struct iio_chan_spec sx9360_channels[] = { 128 { 129 .type = IIO_PROXIMITY, 130 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 131 BIT(IIO_CHAN_INFO_HARDWAREGAIN), 132 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 133 .info_mask_separate_available = 134 BIT(IIO_CHAN_INFO_HARDWAREGAIN), 135 .info_mask_shared_by_all_available = 136 BIT(IIO_CHAN_INFO_SAMP_FREQ), 137 .indexed = 1, 138 .address = SX9360_REG_USEFUL_PHR_MSB, 139 .channel = 0, 140 .scan_index = 0, 141 .scan_type = { 142 .sign = 's', 143 .realbits = 12, 144 .storagebits = 16, 145 .endianness = IIO_BE, 146 }, 147 }, 148 { 149 .type = IIO_PROXIMITY, 150 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 151 BIT(IIO_CHAN_INFO_HARDWAREGAIN), 152 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 153 .info_mask_separate_available = 154 BIT(IIO_CHAN_INFO_HARDWAREGAIN), 155 .info_mask_shared_by_all_available = 156 BIT(IIO_CHAN_INFO_SAMP_FREQ), 157 .indexed = 1, 158 .address = SX9360_REG_USEFUL_PHM_MSB, 159 .event_spec = sx_common_events, 160 .num_event_specs = ARRAY_SIZE(sx_common_events), 161 .channel = 1, 162 .scan_index = 1, 163 .scan_type = { 164 .sign = 's', 165 .realbits = 12, 166 .storagebits = 16, 167 .endianness = IIO_BE, 168 }, 169 }, 170 IIO_CHAN_SOFT_TIMESTAMP(2), 171 }; 172 173 /* 174 * Each entry contains the integer part (val) and the fractional part, in micro 175 * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO. 176 * 177 * The frequency control register holds the period, with a ~2ms increment. 178 * Therefore the smallest frequency is 4MHz / (2047 * 8192), 179 * The fastest is 4MHz / 8192. 180 * The interval is not linear, but given there is 2047 possible value, 181 * Returns the fake increment of (Max-Min)/2047 182 */ 183 static const struct { 184 int val; 185 int val2; 186 } sx9360_samp_freq_interval[] = { 187 { 0, 281250 }, /* 4MHz / (8192 * 2047) */ 188 { 0, 281250 }, 189 { 448, 281250 }, /* 4MHz / 8192 */ 190 }; 191 192 static const struct regmap_range sx9360_writable_reg_ranges[] = { 193 /* 194 * To set COMPSTAT for compensation, even if datasheet says register is 195 * RO. 196 */ 197 regmap_reg_range(SX9360_REG_STAT, SX9360_REG_IRQ_CFG), 198 regmap_reg_range(SX9360_REG_GNRL_CTRL0, SX9360_REG_GNRL_CTRL2), 199 regmap_reg_range(SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_PARAM1_PHM), 200 regmap_reg_range(SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL5), 201 regmap_reg_range(SX9360_REG_REF_CORR0, SX9360_REG_REF_CORR1), 202 regmap_reg_range(SX9360_REG_OFFSET_PMR_MSB, SX9360_REG_OFFSET_PMR_LSB), 203 regmap_reg_range(SX9360_REG_RESET, SX9360_REG_RESET), 204 }; 205 206 static const struct regmap_access_table sx9360_writeable_regs = { 207 .yes_ranges = sx9360_writable_reg_ranges, 208 .n_yes_ranges = ARRAY_SIZE(sx9360_writable_reg_ranges), 209 }; 210 211 /* 212 * All allocated registers are readable, so we just list unallocated 213 * ones. 214 */ 215 static const struct regmap_range sx9360_non_readable_reg_ranges[] = { 216 regmap_reg_range(SX9360_REG_IRQ_CFG + 1, SX9360_REG_GNRL_CTRL0 - 1), 217 regmap_reg_range(SX9360_REG_GNRL_CTRL2 + 1, SX9360_REG_AFE_CTRL1 - 1), 218 regmap_reg_range(SX9360_REG_AFE_PARAM1_PHM + 1, 219 SX9360_REG_PROX_CTRL0_PHR - 1), 220 regmap_reg_range(SX9360_REG_PROX_CTRL5 + 1, SX9360_REG_REF_CORR0 - 1), 221 regmap_reg_range(SX9360_REG_REF_CORR1 + 1, 222 SX9360_REG_USEFUL_PHR_MSB - 1), 223 regmap_reg_range(SX9360_REG_USE_FILTER_LSB + 1, SX9360_REG_RESET - 1), 224 regmap_reg_range(SX9360_REG_RESET + 1, SX9360_REG_WHOAMI - 1), 225 regmap_reg_range(SX9360_REG_WHOAMI + 1, SX9360_REG_REVISION - 1), 226 }; 227 228 static const struct regmap_access_table sx9360_readable_regs = { 229 .no_ranges = sx9360_non_readable_reg_ranges, 230 .n_no_ranges = ARRAY_SIZE(sx9360_non_readable_reg_ranges), 231 }; 232 233 static const struct regmap_range sx9360_volatile_reg_ranges[] = { 234 regmap_reg_range(SX9360_REG_IRQ_SRC, SX9360_REG_STAT), 235 regmap_reg_range(SX9360_REG_USEFUL_PHR_MSB, SX9360_REG_USE_FILTER_LSB), 236 regmap_reg_range(SX9360_REG_WHOAMI, SX9360_REG_WHOAMI), 237 regmap_reg_range(SX9360_REG_REVISION, SX9360_REG_REVISION), 238 }; 239 240 static const struct regmap_access_table sx9360_volatile_regs = { 241 .yes_ranges = sx9360_volatile_reg_ranges, 242 .n_yes_ranges = ARRAY_SIZE(sx9360_volatile_reg_ranges), 243 }; 244 245 static const struct regmap_config sx9360_regmap_config = { 246 .reg_bits = 8, 247 .val_bits = 8, 248 249 .max_register = SX9360_REG_REVISION, 250 .cache_type = REGCACHE_RBTREE, 251 252 .wr_table = &sx9360_writeable_regs, 253 .rd_table = &sx9360_readable_regs, 254 .volatile_table = &sx9360_volatile_regs, 255 }; 256 257 static int sx9360_read_prox_data(struct sx_common_data *data, 258 const struct iio_chan_spec *chan, 259 __be16 *val) 260 { 261 return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val)); 262 } 263 264 /* 265 * If we have no interrupt support, we have to wait for a scan period 266 * after enabling a channel to get a result. 267 */ 268 static int sx9360_wait_for_sample(struct sx_common_data *data) 269 { 270 int ret; 271 __be16 buf; 272 273 ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1, 274 &buf, sizeof(buf)); 275 if (ret < 0) 276 return ret; 277 msleep(SX9360_REG_GNRL_REG_2_PERIOD_MS(be16_to_cpu(buf))); 278 279 return 0; 280 } 281 282 static int sx9360_read_gain(struct sx_common_data *data, 283 const struct iio_chan_spec *chan, int *val) 284 { 285 unsigned int reg, regval; 286 int ret; 287 288 reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel; 289 ret = regmap_read(data->regmap, reg, ®val); 290 if (ret) 291 return ret; 292 293 *val = 1 << FIELD_GET(SX9360_REG_PROX_CTRL0_GAIN_MASK, regval); 294 295 return IIO_VAL_INT; 296 } 297 298 static int sx9360_read_samp_freq(struct sx_common_data *data, 299 int *val, int *val2) 300 { 301 int ret, divisor; 302 __be16 buf; 303 304 ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1, 305 &buf, sizeof(buf)); 306 if (ret < 0) 307 return ret; 308 divisor = be16_to_cpu(buf); 309 if (divisor == 0) { 310 *val = 0; 311 return IIO_VAL_INT; 312 } 313 314 *val = SX9360_FOSC_HZ; 315 *val2 = divisor * 8192; 316 317 return IIO_VAL_FRACTIONAL; 318 } 319 320 static int sx9360_read_raw(struct iio_dev *indio_dev, 321 const struct iio_chan_spec *chan, 322 int *val, int *val2, long mask) 323 { 324 struct sx_common_data *data = iio_priv(indio_dev); 325 int ret; 326 327 switch (mask) { 328 case IIO_CHAN_INFO_RAW: 329 ret = iio_device_claim_direct_mode(indio_dev); 330 if (ret) 331 return ret; 332 333 ret = sx_common_read_proximity(data, chan, val); 334 iio_device_release_direct_mode(indio_dev); 335 return ret; 336 case IIO_CHAN_INFO_HARDWAREGAIN: 337 ret = iio_device_claim_direct_mode(indio_dev); 338 if (ret) 339 return ret; 340 341 ret = sx9360_read_gain(data, chan, val); 342 iio_device_release_direct_mode(indio_dev); 343 return ret; 344 case IIO_CHAN_INFO_SAMP_FREQ: 345 return sx9360_read_samp_freq(data, val, val2); 346 default: 347 return -EINVAL; 348 } 349 } 350 351 static const char *sx9360_channel_labels[SX9360_NUM_CHANNELS] = { 352 "reference", "main", 353 }; 354 355 static int sx9360_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, 356 char *label) 357 { 358 return sysfs_emit(label, "%s\n", sx9360_channel_labels[chan->channel]); 359 } 360 361 static const int sx9360_gain_vals[] = { 1, 2, 4, 8 }; 362 363 static int sx9360_read_avail(struct iio_dev *indio_dev, 364 struct iio_chan_spec const *chan, 365 const int **vals, int *type, int *length, 366 long mask) 367 { 368 if (chan->type != IIO_PROXIMITY) 369 return -EINVAL; 370 371 switch (mask) { 372 case IIO_CHAN_INFO_HARDWAREGAIN: 373 *type = IIO_VAL_INT; 374 *length = ARRAY_SIZE(sx9360_gain_vals); 375 *vals = sx9360_gain_vals; 376 return IIO_AVAIL_LIST; 377 case IIO_CHAN_INFO_SAMP_FREQ: 378 *type = IIO_VAL_INT_PLUS_MICRO; 379 *length = ARRAY_SIZE(sx9360_samp_freq_interval) * 2; 380 *vals = (int *)sx9360_samp_freq_interval; 381 return IIO_AVAIL_RANGE; 382 default: 383 return -EINVAL; 384 } 385 } 386 387 static int sx9360_set_samp_freq(struct sx_common_data *data, 388 int val, int val2) 389 { 390 int ret, reg; 391 __be16 buf; 392 393 reg = val * 8192 / SX9360_FOSC_HZ + val2 * 8192 / (SX9360_FOSC_MHZ); 394 buf = cpu_to_be16(reg); 395 mutex_lock(&data->mutex); 396 397 ret = regmap_bulk_write(data->regmap, SX9360_REG_GNRL_CTRL1, &buf, 398 sizeof(buf)); 399 400 mutex_unlock(&data->mutex); 401 402 return ret; 403 } 404 405 static int sx9360_read_thresh(struct sx_common_data *data, int *val) 406 { 407 unsigned int regval; 408 int ret; 409 410 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL5, ®val); 411 if (ret) 412 return ret; 413 414 if (regval <= 1) 415 *val = regval; 416 else 417 *val = (regval * regval) / 2; 418 419 return IIO_VAL_INT; 420 } 421 422 static int sx9360_read_hysteresis(struct sx_common_data *data, int *val) 423 { 424 unsigned int regval, pthresh; 425 int ret; 426 427 ret = sx9360_read_thresh(data, &pthresh); 428 if (ret < 0) 429 return ret; 430 431 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 432 if (ret) 433 return ret; 434 435 regval = FIELD_GET(SX9360_REG_PROX_CTRL4_HYST_MASK, regval); 436 if (!regval) 437 *val = 0; 438 else 439 *val = pthresh >> (5 - regval); 440 441 return IIO_VAL_INT; 442 } 443 444 static int sx9360_read_far_debounce(struct sx_common_data *data, int *val) 445 { 446 unsigned int regval; 447 int ret; 448 449 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 450 if (ret) 451 return ret; 452 453 regval = FIELD_GET(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, regval); 454 if (regval) 455 *val = 1 << regval; 456 else 457 *val = 0; 458 459 return IIO_VAL_INT; 460 } 461 462 static int sx9360_read_close_debounce(struct sx_common_data *data, int *val) 463 { 464 unsigned int regval; 465 int ret; 466 467 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 468 if (ret) 469 return ret; 470 471 regval = FIELD_GET(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, regval); 472 if (regval) 473 *val = 1 << regval; 474 else 475 *val = 0; 476 477 return IIO_VAL_INT; 478 } 479 480 static int sx9360_read_event_val(struct iio_dev *indio_dev, 481 const struct iio_chan_spec *chan, 482 enum iio_event_type type, 483 enum iio_event_direction dir, 484 enum iio_event_info info, int *val, int *val2) 485 { 486 struct sx_common_data *data = iio_priv(indio_dev); 487 488 if (chan->type != IIO_PROXIMITY) 489 return -EINVAL; 490 491 switch (info) { 492 case IIO_EV_INFO_VALUE: 493 return sx9360_read_thresh(data, val); 494 case IIO_EV_INFO_PERIOD: 495 switch (dir) { 496 case IIO_EV_DIR_RISING: 497 return sx9360_read_far_debounce(data, val); 498 case IIO_EV_DIR_FALLING: 499 return sx9360_read_close_debounce(data, val); 500 default: 501 return -EINVAL; 502 } 503 case IIO_EV_INFO_HYSTERESIS: 504 return sx9360_read_hysteresis(data, val); 505 default: 506 return -EINVAL; 507 } 508 } 509 510 static int sx9360_write_thresh(struct sx_common_data *data, int _val) 511 { 512 unsigned int val = _val; 513 int ret; 514 515 if (val >= 1) 516 val = int_sqrt(2 * val); 517 518 if (val > 0xff) 519 return -EINVAL; 520 521 mutex_lock(&data->mutex); 522 ret = regmap_write(data->regmap, SX9360_REG_PROX_CTRL5, val); 523 mutex_unlock(&data->mutex); 524 525 return ret; 526 } 527 528 static int sx9360_write_hysteresis(struct sx_common_data *data, int _val) 529 { 530 unsigned int hyst, val = _val; 531 int ret, pthresh; 532 533 ret = sx9360_read_thresh(data, &pthresh); 534 if (ret < 0) 535 return ret; 536 537 if (val == 0) 538 hyst = 0; 539 else if (val >= pthresh >> 2) 540 hyst = 3; 541 else if (val >= pthresh >> 3) 542 hyst = 2; 543 else if (val >= pthresh >> 4) 544 hyst = 1; 545 else 546 return -EINVAL; 547 548 hyst = FIELD_PREP(SX9360_REG_PROX_CTRL4_HYST_MASK, hyst); 549 mutex_lock(&data->mutex); 550 ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 551 SX9360_REG_PROX_CTRL4_HYST_MASK, hyst); 552 mutex_unlock(&data->mutex); 553 554 return ret; 555 } 556 557 static int sx9360_write_far_debounce(struct sx_common_data *data, int _val) 558 { 559 unsigned int regval, val = _val; 560 int ret; 561 562 if (val > 0) 563 val = ilog2(val); 564 if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val)) 565 return -EINVAL; 566 567 regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val); 568 569 mutex_lock(&data->mutex); 570 ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 571 SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, 572 regval); 573 mutex_unlock(&data->mutex); 574 575 return ret; 576 } 577 578 static int sx9360_write_close_debounce(struct sx_common_data *data, int _val) 579 { 580 unsigned int regval, val = _val; 581 int ret; 582 583 if (val > 0) 584 val = ilog2(val); 585 if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val)) 586 return -EINVAL; 587 588 regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val); 589 590 mutex_lock(&data->mutex); 591 ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 592 SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, 593 regval); 594 mutex_unlock(&data->mutex); 595 596 return ret; 597 } 598 599 static int sx9360_write_event_val(struct iio_dev *indio_dev, 600 const struct iio_chan_spec *chan, 601 enum iio_event_type type, 602 enum iio_event_direction dir, 603 enum iio_event_info info, int val, int val2) 604 { 605 struct sx_common_data *data = iio_priv(indio_dev); 606 607 if (chan->type != IIO_PROXIMITY) 608 return -EINVAL; 609 610 switch (info) { 611 case IIO_EV_INFO_VALUE: 612 return sx9360_write_thresh(data, val); 613 case IIO_EV_INFO_PERIOD: 614 switch (dir) { 615 case IIO_EV_DIR_RISING: 616 return sx9360_write_far_debounce(data, val); 617 case IIO_EV_DIR_FALLING: 618 return sx9360_write_close_debounce(data, val); 619 default: 620 return -EINVAL; 621 } 622 case IIO_EV_INFO_HYSTERESIS: 623 return sx9360_write_hysteresis(data, val); 624 default: 625 return -EINVAL; 626 } 627 } 628 629 static int sx9360_write_gain(struct sx_common_data *data, 630 const struct iio_chan_spec *chan, int val) 631 { 632 unsigned int gain, reg; 633 int ret; 634 635 gain = ilog2(val); 636 reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel; 637 gain = FIELD_PREP(SX9360_REG_PROX_CTRL0_GAIN_MASK, gain); 638 639 mutex_lock(&data->mutex); 640 ret = regmap_update_bits(data->regmap, reg, 641 SX9360_REG_PROX_CTRL0_GAIN_MASK, 642 gain); 643 mutex_unlock(&data->mutex); 644 645 return ret; 646 } 647 648 static int sx9360_write_raw(struct iio_dev *indio_dev, 649 const struct iio_chan_spec *chan, int val, int val2, 650 long mask) 651 { 652 struct sx_common_data *data = iio_priv(indio_dev); 653 654 switch (mask) { 655 case IIO_CHAN_INFO_SAMP_FREQ: 656 return sx9360_set_samp_freq(data, val, val2); 657 case IIO_CHAN_INFO_HARDWAREGAIN: 658 return sx9360_write_gain(data, chan, val); 659 default: 660 return -EINVAL; 661 } 662 } 663 664 static const struct sx_common_reg_default sx9360_default_regs[] = { 665 { SX9360_REG_IRQ_MSK, 0x00 }, 666 { SX9360_REG_IRQ_CFG, 0x00 }, 667 /* 668 * The lower 2 bits should not be set as it enable sensors measurements. 669 * Turning the detection on before the configuration values are set to 670 * good values can cause the device to return erroneous readings. 671 */ 672 { SX9360_REG_GNRL_CTRL0, 0x00 }, 673 { SX9360_REG_GNRL_CTRL1, 0x00 }, 674 { SX9360_REG_GNRL_CTRL2, SX9360_REG_GNRL_CTRL2_PERIOD_102MS }, 675 676 { SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS }, 677 { SX9360_REG_AFE_PARAM0_PHR, SX9360_REG_AFE_PARAM0_RSVD | 678 SX9360_REG_AFE_PARAM0_RESOLUTION_128 }, 679 { SX9360_REG_AFE_PARAM1_PHR, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | 680 SX9360_REG_AFE_PARAM1_FREQ_83_33HZ }, 681 { SX9360_REG_AFE_PARAM0_PHM, SX9360_REG_AFE_PARAM0_RSVD | 682 SX9360_REG_AFE_PARAM0_RESOLUTION_128 }, 683 { SX9360_REG_AFE_PARAM1_PHM, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | 684 SX9360_REG_AFE_PARAM1_FREQ_83_33HZ }, 685 686 { SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL0_GAIN_1 | 687 SX9360_REG_PROX_CTRL0_RAWFILT_1P50 }, 688 { SX9360_REG_PROX_CTRL0_PHM, SX9360_REG_PROX_CTRL0_GAIN_1 | 689 SX9360_REG_PROX_CTRL0_RAWFILT_1P50 }, 690 { SX9360_REG_PROX_CTRL1, SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K }, 691 { SX9360_REG_PROX_CTRL2, SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES | 692 SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K }, 693 { SX9360_REG_PROX_CTRL3, SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 | 694 SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256 }, 695 { SX9360_REG_PROX_CTRL4, 0x00 }, 696 { SX9360_REG_PROX_CTRL5, SX9360_REG_PROX_CTRL5_PROXTHRESH_32 }, 697 }; 698 699 /* Activate all channels and perform an initial compensation. */ 700 static int sx9360_init_compensation(struct iio_dev *indio_dev) 701 { 702 struct sx_common_data *data = iio_priv(indio_dev); 703 unsigned int val; 704 int ret; 705 706 /* run the compensation phase on all channels */ 707 ret = regmap_update_bits(data->regmap, SX9360_REG_STAT, 708 SX9360_REG_STAT_COMPSTAT_MASK, 709 SX9360_REG_STAT_COMPSTAT_MASK); 710 if (ret) 711 return ret; 712 713 return regmap_read_poll_timeout(data->regmap, SX9360_REG_STAT, val, 714 !(val & SX9360_REG_STAT_COMPSTAT_MASK), 715 20000, 2000000); 716 } 717 718 static const struct sx_common_reg_default * 719 sx9360_get_default_reg(struct device *dev, int idx, 720 struct sx_common_reg_default *reg_def) 721 { 722 u32 raw = 0, pos = 0; 723 int ret; 724 725 memcpy(reg_def, &sx9360_default_regs[idx], sizeof(*reg_def)); 726 switch (reg_def->reg) { 727 case SX9360_REG_AFE_CTRL1: 728 ret = device_property_read_u32(dev, 729 "semtech,input-precharge-resistor-ohms", 730 &raw); 731 if (ret) 732 break; 733 734 reg_def->def &= ~SX9360_REG_AFE_CTRL1_RESFILTIN_MASK; 735 reg_def->def |= FIELD_PREP(SX9360_REG_AFE_CTRL1_RESFILTIN_MASK, 736 raw / 2000); 737 break; 738 case SX9360_REG_AFE_PARAM0_PHR: 739 case SX9360_REG_AFE_PARAM0_PHM: 740 ret = device_property_read_u32(dev, "semtech,resolution", &raw); 741 if (ret) 742 break; 743 744 raw = ilog2(raw) - 3; 745 746 reg_def->def &= ~SX9360_REG_AFE_PARAM0_RESOLUTION_MASK; 747 reg_def->def |= FIELD_PREP(SX9360_REG_AFE_PARAM0_RESOLUTION_MASK, raw); 748 break; 749 case SX9360_REG_PROX_CTRL0_PHR: 750 case SX9360_REG_PROX_CTRL0_PHM: 751 ret = device_property_read_u32(dev, "semtech,proxraw-strength", &raw); 752 if (ret) 753 break; 754 755 reg_def->def &= ~SX9360_REG_PROX_CTRL0_RAWFILT_MASK; 756 reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL0_RAWFILT_MASK, raw); 757 break; 758 case SX9360_REG_PROX_CTRL3: 759 ret = device_property_read_u32(dev, "semtech,avg-pos-strength", 760 &pos); 761 if (ret) 762 break; 763 764 /* Powers of 2, except for a gap between 16 and 64 */ 765 raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3); 766 reg_def->def &= ~SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK; 767 reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK, raw); 768 break; 769 } 770 771 return reg_def; 772 } 773 774 static int sx9360_check_whoami(struct device *dev, struct iio_dev *indio_dev) 775 { 776 /* 777 * Only one sensor for this driver. Assuming the device tree 778 * is correct, just set the sensor name. 779 */ 780 indio_dev->name = "sx9360"; 781 return 0; 782 } 783 784 static const struct sx_common_chip_info sx9360_chip_info = { 785 .reg_stat = SX9360_REG_STAT, 786 .reg_irq_msk = SX9360_REG_IRQ_MSK, 787 .reg_enable_chan = SX9360_REG_GNRL_CTRL0, 788 .reg_reset = SX9360_REG_RESET, 789 790 .mask_enable_chan = SX9360_REG_GNRL_CTRL0_PHEN_MASK, 791 .stat_offset = 2, 792 .num_channels = SX9360_NUM_CHANNELS, 793 .num_default_regs = ARRAY_SIZE(sx9360_default_regs), 794 795 .ops = { 796 .read_prox_data = sx9360_read_prox_data, 797 .check_whoami = sx9360_check_whoami, 798 .init_compensation = sx9360_init_compensation, 799 .wait_for_sample = sx9360_wait_for_sample, 800 .get_default_reg = sx9360_get_default_reg, 801 }, 802 803 .iio_channels = sx9360_channels, 804 .num_iio_channels = ARRAY_SIZE(sx9360_channels), 805 .iio_info = { 806 .read_raw = sx9360_read_raw, 807 .read_avail = sx9360_read_avail, 808 .read_label = sx9360_read_label, 809 .read_event_value = sx9360_read_event_val, 810 .write_event_value = sx9360_write_event_val, 811 .write_raw = sx9360_write_raw, 812 .read_event_config = sx_common_read_event_config, 813 .write_event_config = sx_common_write_event_config, 814 }, 815 }; 816 817 static int sx9360_probe(struct i2c_client *client) 818 { 819 return sx_common_probe(client, &sx9360_chip_info, &sx9360_regmap_config); 820 } 821 822 static int sx9360_suspend(struct device *dev) 823 { 824 struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 825 unsigned int regval; 826 int ret; 827 828 disable_irq_nosync(data->client->irq); 829 830 mutex_lock(&data->mutex); 831 ret = regmap_read(data->regmap, SX9360_REG_GNRL_CTRL0, ®val); 832 833 data->suspend_ctrl = 834 FIELD_GET(SX9360_REG_GNRL_CTRL0_PHEN_MASK, regval); 835 836 if (ret < 0) 837 goto out; 838 839 /* Disable all phases, send the device to sleep. */ 840 ret = regmap_write(data->regmap, SX9360_REG_GNRL_CTRL0, 0); 841 842 out: 843 mutex_unlock(&data->mutex); 844 return ret; 845 } 846 847 static int sx9360_resume(struct device *dev) 848 { 849 struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 850 int ret; 851 852 mutex_lock(&data->mutex); 853 ret = regmap_update_bits(data->regmap, SX9360_REG_GNRL_CTRL0, 854 SX9360_REG_GNRL_CTRL0_PHEN_MASK, 855 data->suspend_ctrl); 856 mutex_unlock(&data->mutex); 857 if (ret) 858 return ret; 859 860 enable_irq(data->client->irq); 861 return 0; 862 } 863 864 static DEFINE_SIMPLE_DEV_PM_OPS(sx9360_pm_ops, sx9360_suspend, sx9360_resume); 865 866 static const struct acpi_device_id sx9360_acpi_match[] = { 867 { "STH9360", SX9360_WHOAMI_VALUE }, 868 { "SAMM0208", SX9360_WHOAMI_VALUE }, 869 { } 870 }; 871 MODULE_DEVICE_TABLE(acpi, sx9360_acpi_match); 872 873 static const struct of_device_id sx9360_of_match[] = { 874 { .compatible = "semtech,sx9360", (void *)SX9360_WHOAMI_VALUE }, 875 { } 876 }; 877 MODULE_DEVICE_TABLE(of, sx9360_of_match); 878 879 static const struct i2c_device_id sx9360_id[] = { 880 {"sx9360", SX9360_WHOAMI_VALUE }, 881 { } 882 }; 883 MODULE_DEVICE_TABLE(i2c, sx9360_id); 884 885 static struct i2c_driver sx9360_driver = { 886 .driver = { 887 .name = "sx9360", 888 .acpi_match_table = sx9360_acpi_match, 889 .of_match_table = sx9360_of_match, 890 .pm = pm_sleep_ptr(&sx9360_pm_ops), 891 892 /* 893 * Lots of i2c transfers in probe + over 200 ms waiting in 894 * sx9360_init_compensation() mean a slow probe; prefer async 895 * so we don't delay boot if we're builtin to the kernel. 896 */ 897 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 898 }, 899 .probe_new = sx9360_probe, 900 .id_table = sx9360_id, 901 }; 902 module_i2c_driver(sx9360_driver); 903 904 MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>"); 905 MODULE_DESCRIPTION("Driver for Semtech SX9360 proximity sensor"); 906 MODULE_LICENSE("GPL v2"); 907 MODULE_IMPORT_NS(SEMTECH_PROX); 908