1*1cdb4c47SGwendal Grignou // SPDX-License-Identifier: GPL-2.0 2*1cdb4c47SGwendal Grignou /* 3*1cdb4c47SGwendal Grignou * Copyright 2021 Google LLC. 4*1cdb4c47SGwendal Grignou * 5*1cdb4c47SGwendal Grignou * Driver for Semtech's SX9360 capacitive proximity/button solution. 6*1cdb4c47SGwendal Grignou * Based on SX9360 driver and copy of datasheet at: 7*1cdb4c47SGwendal Grignou * https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf 8*1cdb4c47SGwendal Grignou */ 9*1cdb4c47SGwendal Grignou 10*1cdb4c47SGwendal Grignou #include <linux/acpi.h> 11*1cdb4c47SGwendal Grignou #include <linux/bits.h> 12*1cdb4c47SGwendal Grignou #include <linux/bitfield.h> 13*1cdb4c47SGwendal Grignou #include <linux/delay.h> 14*1cdb4c47SGwendal Grignou #include <linux/i2c.h> 15*1cdb4c47SGwendal Grignou #include <linux/interrupt.h> 16*1cdb4c47SGwendal Grignou #include <linux/kernel.h> 17*1cdb4c47SGwendal Grignou #include <linux/log2.h> 18*1cdb4c47SGwendal Grignou #include <linux/mod_devicetable.h> 19*1cdb4c47SGwendal Grignou #include <linux/module.h> 20*1cdb4c47SGwendal Grignou #include <linux/pm.h> 21*1cdb4c47SGwendal Grignou #include <linux/regmap.h> 22*1cdb4c47SGwendal Grignou 23*1cdb4c47SGwendal Grignou #include <linux/iio/iio.h> 24*1cdb4c47SGwendal Grignou 25*1cdb4c47SGwendal Grignou #include "sx_common.h" 26*1cdb4c47SGwendal Grignou 27*1cdb4c47SGwendal Grignou /* Nominal Oscillator Frequency. */ 28*1cdb4c47SGwendal Grignou #define SX9360_FOSC_MHZ 4 29*1cdb4c47SGwendal Grignou #define SX9360_FOSC_HZ (SX9360_FOSC_MHZ * 1000000) 30*1cdb4c47SGwendal Grignou 31*1cdb4c47SGwendal Grignou /* Register definitions. */ 32*1cdb4c47SGwendal Grignou #define SX9360_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC 33*1cdb4c47SGwendal Grignou #define SX9360_REG_STAT 0x01 34*1cdb4c47SGwendal Grignou #define SX9360_REG_STAT_COMPSTAT_MASK GENMASK(2, 1) 35*1cdb4c47SGwendal Grignou #define SX9360_REG_IRQ_MSK 0x02 36*1cdb4c47SGwendal Grignou #define SX9360_CONVDONE_IRQ BIT(0) 37*1cdb4c47SGwendal Grignou #define SX9360_FAR_IRQ BIT(2) 38*1cdb4c47SGwendal Grignou #define SX9360_CLOSE_IRQ BIT(3) 39*1cdb4c47SGwendal Grignou #define SX9360_REG_IRQ_CFG 0x03 40*1cdb4c47SGwendal Grignou 41*1cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL0 0x10 42*1cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL0_PHEN_MASK GENMASK(1, 0) 43*1cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL1 0x11 44*1cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL1_SCANPERIOD_MASK GENMASK(2, 0) 45*1cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL2 0x12 46*1cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL2_PERIOD_102MS 0x32 47*1cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_REG_2_PERIOD_MS(_r) \ 48*1cdb4c47SGwendal Grignou (((_r) * 8192) / (SX9360_FOSC_HZ / 1000)) 49*1cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_FREQ_2_REG(_f) (((_f) * 8192) / SX9360_FOSC_HZ) 50*1cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_REG_2_FREQ(_r) (SX9360_FOSC_HZ / ((_r) * 8192)) 51*1cdb4c47SGwendal Grignou 52*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_CTRL1 0x21 53*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_PHR 0x22 54*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM1_PHR 0x23 55*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_PHM 0x24 56*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_RSVD 0x08 57*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_RESOLUTION_MASK GENMASK(2, 0) 58*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_RESOLUTION_128 0x02 59*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM1_PHM 0x25 60*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF 0x40 61*1cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM1_FREQ_83_33HZ 0x06 62*1cdb4c47SGwendal Grignou 63*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_PHR 0x40 64*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_PHM 0x41 65*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3) 66*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_GAIN_1 0x80 67*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_RAWFILT_1P50 0x01 68*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL1 0x42 69*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_MASK GENMASK(5, 3) 70*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K 0x20 71*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL2 0x43 72*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL2_AVGDEB_MASK GENMASK(7, 6) 73*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES 0x40 74*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K 0x20 75*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3 0x44 76*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_MASK GENMASK(5, 3) 77*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 0x08 78*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK GENMASK(2, 0) 79*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256 0x04 80*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL4 0x45 81*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL4_HYST_MASK GENMASK(5, 4) 82*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK GENMASK(3, 2) 83*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK GENMASK(1, 0) 84*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL5 0x46 85*1cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL5_PROXTHRESH_32 0x08 86*1cdb4c47SGwendal Grignou 87*1cdb4c47SGwendal Grignou #define SX9360_REG_REF_CORR0 0x60 88*1cdb4c47SGwendal Grignou #define SX9360_REG_REF_CORR1 0x61 89*1cdb4c47SGwendal Grignou 90*1cdb4c47SGwendal Grignou #define SX9360_REG_USEFUL_PHR_MSB 0x90 91*1cdb4c47SGwendal Grignou #define SX9360_REG_USEFUL_PHR_LSB 0x91 92*1cdb4c47SGwendal Grignou 93*1cdb4c47SGwendal Grignou #define SX9360_REG_OFFSET_PMR_MSB 0x92 94*1cdb4c47SGwendal Grignou #define SX9360_REG_OFFSET_PMR_LSB 0x93 95*1cdb4c47SGwendal Grignou 96*1cdb4c47SGwendal Grignou #define SX9360_REG_USEFUL_PHM_MSB 0x94 97*1cdb4c47SGwendal Grignou #define SX9360_REG_USEFUL_PHM_LSB 0x95 98*1cdb4c47SGwendal Grignou 99*1cdb4c47SGwendal Grignou #define SX9360_REG_AVG_PHM_MSB 0x96 100*1cdb4c47SGwendal Grignou #define SX9360_REG_AVG_PHM_LSB 0x97 101*1cdb4c47SGwendal Grignou 102*1cdb4c47SGwendal Grignou #define SX9360_REG_DIFF_PHM_MSB 0x98 103*1cdb4c47SGwendal Grignou #define SX9360_REG_DIFF_PHM_LSB 0x99 104*1cdb4c47SGwendal Grignou 105*1cdb4c47SGwendal Grignou #define SX9360_REG_OFFSET_PHM_MSB 0x9a 106*1cdb4c47SGwendal Grignou #define SX9360_REG_OFFSET_PHM_LSB 0x9b 107*1cdb4c47SGwendal Grignou 108*1cdb4c47SGwendal Grignou #define SX9360_REG_USE_FILTER_MSB 0x9a 109*1cdb4c47SGwendal Grignou #define SX9360_REG_USE_FILTER_LSB 0x9b 110*1cdb4c47SGwendal Grignou 111*1cdb4c47SGwendal Grignou #define SX9360_REG_RESET 0xcf 112*1cdb4c47SGwendal Grignou /* Write this to REG_RESET to do a soft reset. */ 113*1cdb4c47SGwendal Grignou #define SX9360_SOFT_RESET 0xde 114*1cdb4c47SGwendal Grignou 115*1cdb4c47SGwendal Grignou #define SX9360_REG_WHOAMI 0xfa 116*1cdb4c47SGwendal Grignou #define SX9360_WHOAMI_VALUE 0x60 117*1cdb4c47SGwendal Grignou 118*1cdb4c47SGwendal Grignou #define SX9360_REG_REVISION 0xfe 119*1cdb4c47SGwendal Grignou 120*1cdb4c47SGwendal Grignou /* 2 channels, Phase Reference and Measurement. */ 121*1cdb4c47SGwendal Grignou #define SX9360_NUM_CHANNELS 2 122*1cdb4c47SGwendal Grignou 123*1cdb4c47SGwendal Grignou static const struct iio_chan_spec sx9360_channels[] = { 124*1cdb4c47SGwendal Grignou { 125*1cdb4c47SGwendal Grignou .type = IIO_PROXIMITY, 126*1cdb4c47SGwendal Grignou .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 127*1cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_HARDWAREGAIN), 128*1cdb4c47SGwendal Grignou .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 129*1cdb4c47SGwendal Grignou .info_mask_separate_available = 130*1cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_HARDWAREGAIN), 131*1cdb4c47SGwendal Grignou .info_mask_shared_by_all_available = 132*1cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_SAMP_FREQ), 133*1cdb4c47SGwendal Grignou .indexed = 1, 134*1cdb4c47SGwendal Grignou .address = SX9360_REG_USEFUL_PHR_MSB, 135*1cdb4c47SGwendal Grignou .channel = 0, 136*1cdb4c47SGwendal Grignou .scan_index = 0, 137*1cdb4c47SGwendal Grignou .scan_type = { 138*1cdb4c47SGwendal Grignou .sign = 's', 139*1cdb4c47SGwendal Grignou .realbits = 12, 140*1cdb4c47SGwendal Grignou .storagebits = 16, 141*1cdb4c47SGwendal Grignou .endianness = IIO_BE, 142*1cdb4c47SGwendal Grignou }, 143*1cdb4c47SGwendal Grignou }, 144*1cdb4c47SGwendal Grignou { 145*1cdb4c47SGwendal Grignou .type = IIO_PROXIMITY, 146*1cdb4c47SGwendal Grignou .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 147*1cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_HARDWAREGAIN), 148*1cdb4c47SGwendal Grignou .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 149*1cdb4c47SGwendal Grignou .info_mask_separate_available = 150*1cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_HARDWAREGAIN), 151*1cdb4c47SGwendal Grignou .info_mask_shared_by_all_available = 152*1cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_SAMP_FREQ), 153*1cdb4c47SGwendal Grignou .indexed = 1, 154*1cdb4c47SGwendal Grignou .address = SX9360_REG_USEFUL_PHM_MSB, 155*1cdb4c47SGwendal Grignou .event_spec = sx_common_events, 156*1cdb4c47SGwendal Grignou .num_event_specs = ARRAY_SIZE(sx_common_events), 157*1cdb4c47SGwendal Grignou .channel = 1, 158*1cdb4c47SGwendal Grignou .scan_index = 1, 159*1cdb4c47SGwendal Grignou .scan_type = { 160*1cdb4c47SGwendal Grignou .sign = 's', 161*1cdb4c47SGwendal Grignou .realbits = 12, 162*1cdb4c47SGwendal Grignou .storagebits = 16, 163*1cdb4c47SGwendal Grignou .endianness = IIO_BE, 164*1cdb4c47SGwendal Grignou }, 165*1cdb4c47SGwendal Grignou }, 166*1cdb4c47SGwendal Grignou IIO_CHAN_SOFT_TIMESTAMP(2), 167*1cdb4c47SGwendal Grignou }; 168*1cdb4c47SGwendal Grignou 169*1cdb4c47SGwendal Grignou /* 170*1cdb4c47SGwendal Grignou * Each entry contains the integer part (val) and the fractional part, in micro 171*1cdb4c47SGwendal Grignou * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO. 172*1cdb4c47SGwendal Grignou * 173*1cdb4c47SGwendal Grignou * The frequency control register holds the period, with a ~2ms increment. 174*1cdb4c47SGwendal Grignou * Therefore the smallest frequency is 4MHz / (2047 * 8192), 175*1cdb4c47SGwendal Grignou * The fastest is 4MHz / 8192. 176*1cdb4c47SGwendal Grignou * The interval is not linear, but given there is 2047 possible value, 177*1cdb4c47SGwendal Grignou * Returns the fake increment of (Max-Min)/2047 178*1cdb4c47SGwendal Grignou */ 179*1cdb4c47SGwendal Grignou static const struct { 180*1cdb4c47SGwendal Grignou int val; 181*1cdb4c47SGwendal Grignou int val2; 182*1cdb4c47SGwendal Grignou } sx9360_samp_freq_interval[] = { 183*1cdb4c47SGwendal Grignou { 0, 281250 }, /* 4MHz / (8192 * 2047) */ 184*1cdb4c47SGwendal Grignou { 0, 281250 }, 185*1cdb4c47SGwendal Grignou { 448, 281250 }, /* 4MHz / 8192 */ 186*1cdb4c47SGwendal Grignou }; 187*1cdb4c47SGwendal Grignou 188*1cdb4c47SGwendal Grignou static const struct regmap_range sx9360_writable_reg_ranges[] = { 189*1cdb4c47SGwendal Grignou /* 190*1cdb4c47SGwendal Grignou * To set COMPSTAT for compensation, even if datasheet says register is 191*1cdb4c47SGwendal Grignou * RO. 192*1cdb4c47SGwendal Grignou */ 193*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_STAT, SX9360_REG_IRQ_CFG), 194*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_GNRL_CTRL0, SX9360_REG_GNRL_CTRL2), 195*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_PARAM1_PHM), 196*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL5), 197*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_REF_CORR0, SX9360_REG_REF_CORR1), 198*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_OFFSET_PMR_MSB, SX9360_REG_OFFSET_PMR_LSB), 199*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_RESET, SX9360_REG_RESET), 200*1cdb4c47SGwendal Grignou }; 201*1cdb4c47SGwendal Grignou 202*1cdb4c47SGwendal Grignou static const struct regmap_access_table sx9360_writeable_regs = { 203*1cdb4c47SGwendal Grignou .yes_ranges = sx9360_writable_reg_ranges, 204*1cdb4c47SGwendal Grignou .n_yes_ranges = ARRAY_SIZE(sx9360_writable_reg_ranges), 205*1cdb4c47SGwendal Grignou }; 206*1cdb4c47SGwendal Grignou 207*1cdb4c47SGwendal Grignou /* 208*1cdb4c47SGwendal Grignou * All allocated registers are readable, so we just list unallocated 209*1cdb4c47SGwendal Grignou * ones. 210*1cdb4c47SGwendal Grignou */ 211*1cdb4c47SGwendal Grignou static const struct regmap_range sx9360_non_readable_reg_ranges[] = { 212*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_IRQ_CFG + 1, SX9360_REG_GNRL_CTRL0 - 1), 213*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_GNRL_CTRL2 + 1, SX9360_REG_AFE_CTRL1 - 1), 214*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_AFE_PARAM1_PHM + 1, 215*1cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL0_PHR - 1), 216*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_PROX_CTRL5 + 1, SX9360_REG_REF_CORR0 - 1), 217*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_REF_CORR1 + 1, 218*1cdb4c47SGwendal Grignou SX9360_REG_USEFUL_PHR_MSB - 1), 219*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_USE_FILTER_LSB + 1, SX9360_REG_RESET - 1), 220*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_RESET + 1, SX9360_REG_WHOAMI - 1), 221*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_WHOAMI + 1, SX9360_REG_REVISION - 1), 222*1cdb4c47SGwendal Grignou }; 223*1cdb4c47SGwendal Grignou 224*1cdb4c47SGwendal Grignou static const struct regmap_access_table sx9360_readable_regs = { 225*1cdb4c47SGwendal Grignou .no_ranges = sx9360_non_readable_reg_ranges, 226*1cdb4c47SGwendal Grignou .n_no_ranges = ARRAY_SIZE(sx9360_non_readable_reg_ranges), 227*1cdb4c47SGwendal Grignou }; 228*1cdb4c47SGwendal Grignou 229*1cdb4c47SGwendal Grignou static const struct regmap_range sx9360_volatile_reg_ranges[] = { 230*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_IRQ_SRC, SX9360_REG_STAT), 231*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_USEFUL_PHR_MSB, SX9360_REG_USE_FILTER_LSB), 232*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_WHOAMI, SX9360_REG_WHOAMI), 233*1cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_REVISION, SX9360_REG_REVISION), 234*1cdb4c47SGwendal Grignou }; 235*1cdb4c47SGwendal Grignou 236*1cdb4c47SGwendal Grignou static const struct regmap_access_table sx9360_volatile_regs = { 237*1cdb4c47SGwendal Grignou .yes_ranges = sx9360_volatile_reg_ranges, 238*1cdb4c47SGwendal Grignou .n_yes_ranges = ARRAY_SIZE(sx9360_volatile_reg_ranges), 239*1cdb4c47SGwendal Grignou }; 240*1cdb4c47SGwendal Grignou 241*1cdb4c47SGwendal Grignou static const struct regmap_config sx9360_regmap_config = { 242*1cdb4c47SGwendal Grignou .reg_bits = 8, 243*1cdb4c47SGwendal Grignou .val_bits = 8, 244*1cdb4c47SGwendal Grignou 245*1cdb4c47SGwendal Grignou .max_register = SX9360_REG_REVISION, 246*1cdb4c47SGwendal Grignou .cache_type = REGCACHE_RBTREE, 247*1cdb4c47SGwendal Grignou 248*1cdb4c47SGwendal Grignou .wr_table = &sx9360_writeable_regs, 249*1cdb4c47SGwendal Grignou .rd_table = &sx9360_readable_regs, 250*1cdb4c47SGwendal Grignou .volatile_table = &sx9360_volatile_regs, 251*1cdb4c47SGwendal Grignou }; 252*1cdb4c47SGwendal Grignou 253*1cdb4c47SGwendal Grignou static int sx9360_read_prox_data(struct sx_common_data *data, 254*1cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, 255*1cdb4c47SGwendal Grignou __be16 *val) 256*1cdb4c47SGwendal Grignou { 257*1cdb4c47SGwendal Grignou return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val)); 258*1cdb4c47SGwendal Grignou } 259*1cdb4c47SGwendal Grignou 260*1cdb4c47SGwendal Grignou /* 261*1cdb4c47SGwendal Grignou * If we have no interrupt support, we have to wait for a scan period 262*1cdb4c47SGwendal Grignou * after enabling a channel to get a result. 263*1cdb4c47SGwendal Grignou */ 264*1cdb4c47SGwendal Grignou static int sx9360_wait_for_sample(struct sx_common_data *data) 265*1cdb4c47SGwendal Grignou { 266*1cdb4c47SGwendal Grignou int ret; 267*1cdb4c47SGwendal Grignou __be16 buf; 268*1cdb4c47SGwendal Grignou 269*1cdb4c47SGwendal Grignou ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1, 270*1cdb4c47SGwendal Grignou &buf, sizeof(buf)); 271*1cdb4c47SGwendal Grignou if (ret < 0) 272*1cdb4c47SGwendal Grignou return ret; 273*1cdb4c47SGwendal Grignou msleep(SX9360_REG_GNRL_REG_2_PERIOD_MS(be16_to_cpu(buf))); 274*1cdb4c47SGwendal Grignou 275*1cdb4c47SGwendal Grignou return 0; 276*1cdb4c47SGwendal Grignou } 277*1cdb4c47SGwendal Grignou 278*1cdb4c47SGwendal Grignou static int sx9360_read_gain(struct sx_common_data *data, 279*1cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, int *val) 280*1cdb4c47SGwendal Grignou { 281*1cdb4c47SGwendal Grignou unsigned int reg, regval; 282*1cdb4c47SGwendal Grignou int ret; 283*1cdb4c47SGwendal Grignou 284*1cdb4c47SGwendal Grignou reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel; 285*1cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, reg, ®val); 286*1cdb4c47SGwendal Grignou if (ret) 287*1cdb4c47SGwendal Grignou return ret; 288*1cdb4c47SGwendal Grignou 289*1cdb4c47SGwendal Grignou *val = 1 << FIELD_GET(SX9360_REG_PROX_CTRL0_GAIN_MASK, regval); 290*1cdb4c47SGwendal Grignou 291*1cdb4c47SGwendal Grignou return IIO_VAL_INT; 292*1cdb4c47SGwendal Grignou } 293*1cdb4c47SGwendal Grignou 294*1cdb4c47SGwendal Grignou static int sx9360_read_samp_freq(struct sx_common_data *data, 295*1cdb4c47SGwendal Grignou int *val, int *val2) 296*1cdb4c47SGwendal Grignou { 297*1cdb4c47SGwendal Grignou int ret, divisor; 298*1cdb4c47SGwendal Grignou __be16 buf; 299*1cdb4c47SGwendal Grignou 300*1cdb4c47SGwendal Grignou ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1, 301*1cdb4c47SGwendal Grignou &buf, sizeof(buf)); 302*1cdb4c47SGwendal Grignou if (ret < 0) 303*1cdb4c47SGwendal Grignou return ret; 304*1cdb4c47SGwendal Grignou divisor = be16_to_cpu(buf); 305*1cdb4c47SGwendal Grignou if (divisor == 0) { 306*1cdb4c47SGwendal Grignou *val = 0; 307*1cdb4c47SGwendal Grignou return IIO_VAL_INT; 308*1cdb4c47SGwendal Grignou } 309*1cdb4c47SGwendal Grignou 310*1cdb4c47SGwendal Grignou *val = SX9360_FOSC_HZ; 311*1cdb4c47SGwendal Grignou *val2 = divisor * 8192; 312*1cdb4c47SGwendal Grignou 313*1cdb4c47SGwendal Grignou return IIO_VAL_FRACTIONAL; 314*1cdb4c47SGwendal Grignou } 315*1cdb4c47SGwendal Grignou 316*1cdb4c47SGwendal Grignou static int sx9360_read_raw(struct iio_dev *indio_dev, 317*1cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, 318*1cdb4c47SGwendal Grignou int *val, int *val2, long mask) 319*1cdb4c47SGwendal Grignou { 320*1cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 321*1cdb4c47SGwendal Grignou int ret; 322*1cdb4c47SGwendal Grignou 323*1cdb4c47SGwendal Grignou switch (mask) { 324*1cdb4c47SGwendal Grignou case IIO_CHAN_INFO_RAW: 325*1cdb4c47SGwendal Grignou ret = iio_device_claim_direct_mode(indio_dev); 326*1cdb4c47SGwendal Grignou if (ret) 327*1cdb4c47SGwendal Grignou return ret; 328*1cdb4c47SGwendal Grignou 329*1cdb4c47SGwendal Grignou ret = sx_common_read_proximity(data, chan, val); 330*1cdb4c47SGwendal Grignou iio_device_release_direct_mode(indio_dev); 331*1cdb4c47SGwendal Grignou return ret; 332*1cdb4c47SGwendal Grignou case IIO_CHAN_INFO_HARDWAREGAIN: 333*1cdb4c47SGwendal Grignou ret = iio_device_claim_direct_mode(indio_dev); 334*1cdb4c47SGwendal Grignou if (ret) 335*1cdb4c47SGwendal Grignou return ret; 336*1cdb4c47SGwendal Grignou 337*1cdb4c47SGwendal Grignou ret = sx9360_read_gain(data, chan, val); 338*1cdb4c47SGwendal Grignou iio_device_release_direct_mode(indio_dev); 339*1cdb4c47SGwendal Grignou return ret; 340*1cdb4c47SGwendal Grignou case IIO_CHAN_INFO_SAMP_FREQ: 341*1cdb4c47SGwendal Grignou return sx9360_read_samp_freq(data, val, val2); 342*1cdb4c47SGwendal Grignou default: 343*1cdb4c47SGwendal Grignou return -EINVAL; 344*1cdb4c47SGwendal Grignou } 345*1cdb4c47SGwendal Grignou } 346*1cdb4c47SGwendal Grignou 347*1cdb4c47SGwendal Grignou static const char *sx9360_channel_labels[SX9360_NUM_CHANNELS] = { 348*1cdb4c47SGwendal Grignou "reference", "main", 349*1cdb4c47SGwendal Grignou }; 350*1cdb4c47SGwendal Grignou 351*1cdb4c47SGwendal Grignou static int sx9360_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, 352*1cdb4c47SGwendal Grignou char *label) 353*1cdb4c47SGwendal Grignou { 354*1cdb4c47SGwendal Grignou return sysfs_emit(label, "%s\n", sx9360_channel_labels[chan->channel]); 355*1cdb4c47SGwendal Grignou } 356*1cdb4c47SGwendal Grignou 357*1cdb4c47SGwendal Grignou static const int sx9360_gain_vals[] = { 1, 2, 4, 8 }; 358*1cdb4c47SGwendal Grignou 359*1cdb4c47SGwendal Grignou static int sx9360_read_avail(struct iio_dev *indio_dev, 360*1cdb4c47SGwendal Grignou struct iio_chan_spec const *chan, 361*1cdb4c47SGwendal Grignou const int **vals, int *type, int *length, 362*1cdb4c47SGwendal Grignou long mask) 363*1cdb4c47SGwendal Grignou { 364*1cdb4c47SGwendal Grignou if (chan->type != IIO_PROXIMITY) 365*1cdb4c47SGwendal Grignou return -EINVAL; 366*1cdb4c47SGwendal Grignou 367*1cdb4c47SGwendal Grignou switch (mask) { 368*1cdb4c47SGwendal Grignou case IIO_CHAN_INFO_HARDWAREGAIN: 369*1cdb4c47SGwendal Grignou *type = IIO_VAL_INT; 370*1cdb4c47SGwendal Grignou *length = ARRAY_SIZE(sx9360_gain_vals); 371*1cdb4c47SGwendal Grignou *vals = sx9360_gain_vals; 372*1cdb4c47SGwendal Grignou return IIO_AVAIL_LIST; 373*1cdb4c47SGwendal Grignou case IIO_CHAN_INFO_SAMP_FREQ: 374*1cdb4c47SGwendal Grignou *type = IIO_VAL_INT_PLUS_MICRO; 375*1cdb4c47SGwendal Grignou *length = ARRAY_SIZE(sx9360_samp_freq_interval) * 2; 376*1cdb4c47SGwendal Grignou *vals = (int *)sx9360_samp_freq_interval; 377*1cdb4c47SGwendal Grignou return IIO_AVAIL_RANGE; 378*1cdb4c47SGwendal Grignou default: 379*1cdb4c47SGwendal Grignou return -EINVAL; 380*1cdb4c47SGwendal Grignou } 381*1cdb4c47SGwendal Grignou } 382*1cdb4c47SGwendal Grignou 383*1cdb4c47SGwendal Grignou static int sx9360_set_samp_freq(struct sx_common_data *data, 384*1cdb4c47SGwendal Grignou int val, int val2) 385*1cdb4c47SGwendal Grignou { 386*1cdb4c47SGwendal Grignou int ret, reg; 387*1cdb4c47SGwendal Grignou __be16 buf; 388*1cdb4c47SGwendal Grignou 389*1cdb4c47SGwendal Grignou reg = val * 8192 / SX9360_FOSC_HZ + val2 * 8192 / (SX9360_FOSC_MHZ); 390*1cdb4c47SGwendal Grignou buf = cpu_to_be16(reg); 391*1cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 392*1cdb4c47SGwendal Grignou 393*1cdb4c47SGwendal Grignou ret = regmap_bulk_write(data->regmap, SX9360_REG_GNRL_CTRL1, &buf, 394*1cdb4c47SGwendal Grignou sizeof(buf)); 395*1cdb4c47SGwendal Grignou 396*1cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 397*1cdb4c47SGwendal Grignou 398*1cdb4c47SGwendal Grignou return ret; 399*1cdb4c47SGwendal Grignou } 400*1cdb4c47SGwendal Grignou 401*1cdb4c47SGwendal Grignou static int sx9360_read_thresh(struct sx_common_data *data, int *val) 402*1cdb4c47SGwendal Grignou { 403*1cdb4c47SGwendal Grignou unsigned int regval; 404*1cdb4c47SGwendal Grignou int ret; 405*1cdb4c47SGwendal Grignou 406*1cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL5, ®val); 407*1cdb4c47SGwendal Grignou if (ret) 408*1cdb4c47SGwendal Grignou return ret; 409*1cdb4c47SGwendal Grignou 410*1cdb4c47SGwendal Grignou if (regval <= 1) 411*1cdb4c47SGwendal Grignou *val = regval; 412*1cdb4c47SGwendal Grignou else 413*1cdb4c47SGwendal Grignou *val = (regval * regval) / 2; 414*1cdb4c47SGwendal Grignou 415*1cdb4c47SGwendal Grignou return IIO_VAL_INT; 416*1cdb4c47SGwendal Grignou } 417*1cdb4c47SGwendal Grignou 418*1cdb4c47SGwendal Grignou static int sx9360_read_hysteresis(struct sx_common_data *data, int *val) 419*1cdb4c47SGwendal Grignou { 420*1cdb4c47SGwendal Grignou unsigned int regval, pthresh; 421*1cdb4c47SGwendal Grignou int ret; 422*1cdb4c47SGwendal Grignou 423*1cdb4c47SGwendal Grignou ret = sx9360_read_thresh(data, &pthresh); 424*1cdb4c47SGwendal Grignou if (ret < 0) 425*1cdb4c47SGwendal Grignou return ret; 426*1cdb4c47SGwendal Grignou 427*1cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 428*1cdb4c47SGwendal Grignou if (ret) 429*1cdb4c47SGwendal Grignou return ret; 430*1cdb4c47SGwendal Grignou 431*1cdb4c47SGwendal Grignou regval = FIELD_GET(SX9360_REG_PROX_CTRL4_HYST_MASK, regval); 432*1cdb4c47SGwendal Grignou if (!regval) 433*1cdb4c47SGwendal Grignou *val = 0; 434*1cdb4c47SGwendal Grignou else 435*1cdb4c47SGwendal Grignou *val = pthresh >> (5 - regval); 436*1cdb4c47SGwendal Grignou 437*1cdb4c47SGwendal Grignou return IIO_VAL_INT; 438*1cdb4c47SGwendal Grignou } 439*1cdb4c47SGwendal Grignou 440*1cdb4c47SGwendal Grignou static int sx9360_read_far_debounce(struct sx_common_data *data, int *val) 441*1cdb4c47SGwendal Grignou { 442*1cdb4c47SGwendal Grignou unsigned int regval; 443*1cdb4c47SGwendal Grignou int ret; 444*1cdb4c47SGwendal Grignou 445*1cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 446*1cdb4c47SGwendal Grignou if (ret) 447*1cdb4c47SGwendal Grignou return ret; 448*1cdb4c47SGwendal Grignou 449*1cdb4c47SGwendal Grignou regval = FIELD_GET(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, regval); 450*1cdb4c47SGwendal Grignou if (regval) 451*1cdb4c47SGwendal Grignou *val = 1 << regval; 452*1cdb4c47SGwendal Grignou else 453*1cdb4c47SGwendal Grignou *val = 0; 454*1cdb4c47SGwendal Grignou 455*1cdb4c47SGwendal Grignou return IIO_VAL_INT; 456*1cdb4c47SGwendal Grignou } 457*1cdb4c47SGwendal Grignou 458*1cdb4c47SGwendal Grignou static int sx9360_read_close_debounce(struct sx_common_data *data, int *val) 459*1cdb4c47SGwendal Grignou { 460*1cdb4c47SGwendal Grignou unsigned int regval; 461*1cdb4c47SGwendal Grignou int ret; 462*1cdb4c47SGwendal Grignou 463*1cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 464*1cdb4c47SGwendal Grignou if (ret) 465*1cdb4c47SGwendal Grignou return ret; 466*1cdb4c47SGwendal Grignou 467*1cdb4c47SGwendal Grignou regval = FIELD_GET(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, regval); 468*1cdb4c47SGwendal Grignou if (regval) 469*1cdb4c47SGwendal Grignou *val = 1 << regval; 470*1cdb4c47SGwendal Grignou else 471*1cdb4c47SGwendal Grignou *val = 0; 472*1cdb4c47SGwendal Grignou 473*1cdb4c47SGwendal Grignou return IIO_VAL_INT; 474*1cdb4c47SGwendal Grignou } 475*1cdb4c47SGwendal Grignou 476*1cdb4c47SGwendal Grignou static int sx9360_read_event_val(struct iio_dev *indio_dev, 477*1cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, 478*1cdb4c47SGwendal Grignou enum iio_event_type type, 479*1cdb4c47SGwendal Grignou enum iio_event_direction dir, 480*1cdb4c47SGwendal Grignou enum iio_event_info info, int *val, int *val2) 481*1cdb4c47SGwendal Grignou { 482*1cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 483*1cdb4c47SGwendal Grignou 484*1cdb4c47SGwendal Grignou if (chan->type != IIO_PROXIMITY) 485*1cdb4c47SGwendal Grignou return -EINVAL; 486*1cdb4c47SGwendal Grignou 487*1cdb4c47SGwendal Grignou switch (info) { 488*1cdb4c47SGwendal Grignou case IIO_EV_INFO_VALUE: 489*1cdb4c47SGwendal Grignou return sx9360_read_thresh(data, val); 490*1cdb4c47SGwendal Grignou case IIO_EV_INFO_PERIOD: 491*1cdb4c47SGwendal Grignou switch (dir) { 492*1cdb4c47SGwendal Grignou case IIO_EV_DIR_RISING: 493*1cdb4c47SGwendal Grignou return sx9360_read_far_debounce(data, val); 494*1cdb4c47SGwendal Grignou case IIO_EV_DIR_FALLING: 495*1cdb4c47SGwendal Grignou return sx9360_read_close_debounce(data, val); 496*1cdb4c47SGwendal Grignou default: 497*1cdb4c47SGwendal Grignou return -EINVAL; 498*1cdb4c47SGwendal Grignou } 499*1cdb4c47SGwendal Grignou case IIO_EV_INFO_HYSTERESIS: 500*1cdb4c47SGwendal Grignou return sx9360_read_hysteresis(data, val); 501*1cdb4c47SGwendal Grignou default: 502*1cdb4c47SGwendal Grignou return -EINVAL; 503*1cdb4c47SGwendal Grignou } 504*1cdb4c47SGwendal Grignou } 505*1cdb4c47SGwendal Grignou 506*1cdb4c47SGwendal Grignou static int sx9360_write_thresh(struct sx_common_data *data, int _val) 507*1cdb4c47SGwendal Grignou { 508*1cdb4c47SGwendal Grignou unsigned int val = _val; 509*1cdb4c47SGwendal Grignou int ret; 510*1cdb4c47SGwendal Grignou 511*1cdb4c47SGwendal Grignou if (val >= 1) 512*1cdb4c47SGwendal Grignou val = int_sqrt(2 * val); 513*1cdb4c47SGwendal Grignou 514*1cdb4c47SGwendal Grignou if (val > 0xff) 515*1cdb4c47SGwendal Grignou return -EINVAL; 516*1cdb4c47SGwendal Grignou 517*1cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 518*1cdb4c47SGwendal Grignou ret = regmap_write(data->regmap, SX9360_REG_PROX_CTRL5, val); 519*1cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 520*1cdb4c47SGwendal Grignou 521*1cdb4c47SGwendal Grignou return ret; 522*1cdb4c47SGwendal Grignou } 523*1cdb4c47SGwendal Grignou 524*1cdb4c47SGwendal Grignou static int sx9360_write_hysteresis(struct sx_common_data *data, int _val) 525*1cdb4c47SGwendal Grignou { 526*1cdb4c47SGwendal Grignou unsigned int hyst, val = _val; 527*1cdb4c47SGwendal Grignou int ret, pthresh; 528*1cdb4c47SGwendal Grignou 529*1cdb4c47SGwendal Grignou ret = sx9360_read_thresh(data, &pthresh); 530*1cdb4c47SGwendal Grignou if (ret < 0) 531*1cdb4c47SGwendal Grignou return ret; 532*1cdb4c47SGwendal Grignou 533*1cdb4c47SGwendal Grignou if (val == 0) 534*1cdb4c47SGwendal Grignou hyst = 0; 535*1cdb4c47SGwendal Grignou else if (val >= pthresh >> 2) 536*1cdb4c47SGwendal Grignou hyst = 3; 537*1cdb4c47SGwendal Grignou else if (val >= pthresh >> 3) 538*1cdb4c47SGwendal Grignou hyst = 2; 539*1cdb4c47SGwendal Grignou else if (val >= pthresh >> 4) 540*1cdb4c47SGwendal Grignou hyst = 1; 541*1cdb4c47SGwendal Grignou else 542*1cdb4c47SGwendal Grignou return -EINVAL; 543*1cdb4c47SGwendal Grignou 544*1cdb4c47SGwendal Grignou hyst = FIELD_PREP(SX9360_REG_PROX_CTRL4_HYST_MASK, hyst); 545*1cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 546*1cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 547*1cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL4_HYST_MASK, hyst); 548*1cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 549*1cdb4c47SGwendal Grignou 550*1cdb4c47SGwendal Grignou return ret; 551*1cdb4c47SGwendal Grignou } 552*1cdb4c47SGwendal Grignou 553*1cdb4c47SGwendal Grignou static int sx9360_write_far_debounce(struct sx_common_data *data, int _val) 554*1cdb4c47SGwendal Grignou { 555*1cdb4c47SGwendal Grignou unsigned int regval, val = _val; 556*1cdb4c47SGwendal Grignou int ret; 557*1cdb4c47SGwendal Grignou 558*1cdb4c47SGwendal Grignou if (val > 0) 559*1cdb4c47SGwendal Grignou val = ilog2(val); 560*1cdb4c47SGwendal Grignou if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val)) 561*1cdb4c47SGwendal Grignou return -EINVAL; 562*1cdb4c47SGwendal Grignou 563*1cdb4c47SGwendal Grignou regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val); 564*1cdb4c47SGwendal Grignou 565*1cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 566*1cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 567*1cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, 568*1cdb4c47SGwendal Grignou regval); 569*1cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 570*1cdb4c47SGwendal Grignou 571*1cdb4c47SGwendal Grignou return ret; 572*1cdb4c47SGwendal Grignou } 573*1cdb4c47SGwendal Grignou 574*1cdb4c47SGwendal Grignou static int sx9360_write_close_debounce(struct sx_common_data *data, int _val) 575*1cdb4c47SGwendal Grignou { 576*1cdb4c47SGwendal Grignou unsigned int regval, val = _val; 577*1cdb4c47SGwendal Grignou int ret; 578*1cdb4c47SGwendal Grignou 579*1cdb4c47SGwendal Grignou if (val > 0) 580*1cdb4c47SGwendal Grignou val = ilog2(val); 581*1cdb4c47SGwendal Grignou if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val)) 582*1cdb4c47SGwendal Grignou return -EINVAL; 583*1cdb4c47SGwendal Grignou 584*1cdb4c47SGwendal Grignou regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val); 585*1cdb4c47SGwendal Grignou 586*1cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 587*1cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 588*1cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, 589*1cdb4c47SGwendal Grignou regval); 590*1cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 591*1cdb4c47SGwendal Grignou 592*1cdb4c47SGwendal Grignou return ret; 593*1cdb4c47SGwendal Grignou } 594*1cdb4c47SGwendal Grignou 595*1cdb4c47SGwendal Grignou static int sx9360_write_event_val(struct iio_dev *indio_dev, 596*1cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, 597*1cdb4c47SGwendal Grignou enum iio_event_type type, 598*1cdb4c47SGwendal Grignou enum iio_event_direction dir, 599*1cdb4c47SGwendal Grignou enum iio_event_info info, int val, int val2) 600*1cdb4c47SGwendal Grignou { 601*1cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 602*1cdb4c47SGwendal Grignou 603*1cdb4c47SGwendal Grignou if (chan->type != IIO_PROXIMITY) 604*1cdb4c47SGwendal Grignou return -EINVAL; 605*1cdb4c47SGwendal Grignou 606*1cdb4c47SGwendal Grignou switch (info) { 607*1cdb4c47SGwendal Grignou case IIO_EV_INFO_VALUE: 608*1cdb4c47SGwendal Grignou return sx9360_write_thresh(data, val); 609*1cdb4c47SGwendal Grignou case IIO_EV_INFO_PERIOD: 610*1cdb4c47SGwendal Grignou switch (dir) { 611*1cdb4c47SGwendal Grignou case IIO_EV_DIR_RISING: 612*1cdb4c47SGwendal Grignou return sx9360_write_far_debounce(data, val); 613*1cdb4c47SGwendal Grignou case IIO_EV_DIR_FALLING: 614*1cdb4c47SGwendal Grignou return sx9360_write_close_debounce(data, val); 615*1cdb4c47SGwendal Grignou default: 616*1cdb4c47SGwendal Grignou return -EINVAL; 617*1cdb4c47SGwendal Grignou } 618*1cdb4c47SGwendal Grignou case IIO_EV_INFO_HYSTERESIS: 619*1cdb4c47SGwendal Grignou return sx9360_write_hysteresis(data, val); 620*1cdb4c47SGwendal Grignou default: 621*1cdb4c47SGwendal Grignou return -EINVAL; 622*1cdb4c47SGwendal Grignou } 623*1cdb4c47SGwendal Grignou } 624*1cdb4c47SGwendal Grignou 625*1cdb4c47SGwendal Grignou static int sx9360_write_gain(struct sx_common_data *data, 626*1cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, int val) 627*1cdb4c47SGwendal Grignou { 628*1cdb4c47SGwendal Grignou unsigned int gain, reg; 629*1cdb4c47SGwendal Grignou int ret; 630*1cdb4c47SGwendal Grignou 631*1cdb4c47SGwendal Grignou gain = ilog2(val); 632*1cdb4c47SGwendal Grignou reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel; 633*1cdb4c47SGwendal Grignou gain = FIELD_PREP(SX9360_REG_PROX_CTRL0_GAIN_MASK, gain); 634*1cdb4c47SGwendal Grignou 635*1cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 636*1cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, reg, 637*1cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL0_GAIN_MASK, 638*1cdb4c47SGwendal Grignou gain); 639*1cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 640*1cdb4c47SGwendal Grignou 641*1cdb4c47SGwendal Grignou return ret; 642*1cdb4c47SGwendal Grignou } 643*1cdb4c47SGwendal Grignou 644*1cdb4c47SGwendal Grignou static int sx9360_write_raw(struct iio_dev *indio_dev, 645*1cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, int val, int val2, 646*1cdb4c47SGwendal Grignou long mask) 647*1cdb4c47SGwendal Grignou { 648*1cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 649*1cdb4c47SGwendal Grignou 650*1cdb4c47SGwendal Grignou switch (mask) { 651*1cdb4c47SGwendal Grignou case IIO_CHAN_INFO_SAMP_FREQ: 652*1cdb4c47SGwendal Grignou return sx9360_set_samp_freq(data, val, val2); 653*1cdb4c47SGwendal Grignou case IIO_CHAN_INFO_HARDWAREGAIN: 654*1cdb4c47SGwendal Grignou return sx9360_write_gain(data, chan, val); 655*1cdb4c47SGwendal Grignou default: 656*1cdb4c47SGwendal Grignou return -EINVAL; 657*1cdb4c47SGwendal Grignou } 658*1cdb4c47SGwendal Grignou } 659*1cdb4c47SGwendal Grignou 660*1cdb4c47SGwendal Grignou /* Activate all channels and perform an initial compensation. */ 661*1cdb4c47SGwendal Grignou static int sx9360_init_compensation(struct iio_dev *indio_dev) 662*1cdb4c47SGwendal Grignou { 663*1cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 664*1cdb4c47SGwendal Grignou unsigned int val; 665*1cdb4c47SGwendal Grignou int ret; 666*1cdb4c47SGwendal Grignou 667*1cdb4c47SGwendal Grignou /* run the compensation phase on all channels */ 668*1cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_STAT, 669*1cdb4c47SGwendal Grignou SX9360_REG_STAT_COMPSTAT_MASK, 670*1cdb4c47SGwendal Grignou SX9360_REG_STAT_COMPSTAT_MASK); 671*1cdb4c47SGwendal Grignou if (ret) 672*1cdb4c47SGwendal Grignou return ret; 673*1cdb4c47SGwendal Grignou 674*1cdb4c47SGwendal Grignou return regmap_read_poll_timeout(data->regmap, SX9360_REG_STAT, val, 675*1cdb4c47SGwendal Grignou !(val & SX9360_REG_STAT_COMPSTAT_MASK), 676*1cdb4c47SGwendal Grignou 20000, 2000000); 677*1cdb4c47SGwendal Grignou } 678*1cdb4c47SGwendal Grignou 679*1cdb4c47SGwendal Grignou static int sx9360_check_whoami(struct device *dev, struct iio_dev *indio_dev) 680*1cdb4c47SGwendal Grignou { 681*1cdb4c47SGwendal Grignou /* 682*1cdb4c47SGwendal Grignou * Only one sensor for this driver. Assuming the device tree 683*1cdb4c47SGwendal Grignou * is correct, just set the sensor name. 684*1cdb4c47SGwendal Grignou */ 685*1cdb4c47SGwendal Grignou indio_dev->name = "sx9360"; 686*1cdb4c47SGwendal Grignou return 0; 687*1cdb4c47SGwendal Grignou } 688*1cdb4c47SGwendal Grignou 689*1cdb4c47SGwendal Grignou static const struct sx_common_chip_info sx9360_chip_info = { 690*1cdb4c47SGwendal Grignou .reg_stat = SX9360_REG_STAT, 691*1cdb4c47SGwendal Grignou .reg_irq_msk = SX9360_REG_IRQ_MSK, 692*1cdb4c47SGwendal Grignou .reg_enable_chan = SX9360_REG_GNRL_CTRL0, 693*1cdb4c47SGwendal Grignou .reg_reset = SX9360_REG_RESET, 694*1cdb4c47SGwendal Grignou 695*1cdb4c47SGwendal Grignou .mask_enable_chan = SX9360_REG_GNRL_CTRL0_PHEN_MASK, 696*1cdb4c47SGwendal Grignou .stat_offset = 3, 697*1cdb4c47SGwendal Grignou .num_channels = SX9360_NUM_CHANNELS, 698*1cdb4c47SGwendal Grignou 699*1cdb4c47SGwendal Grignou .ops = { 700*1cdb4c47SGwendal Grignou .read_prox_data = sx9360_read_prox_data, 701*1cdb4c47SGwendal Grignou .check_whoami = sx9360_check_whoami, 702*1cdb4c47SGwendal Grignou .init_compensation = sx9360_init_compensation, 703*1cdb4c47SGwendal Grignou .wait_for_sample = sx9360_wait_for_sample, 704*1cdb4c47SGwendal Grignou }, 705*1cdb4c47SGwendal Grignou 706*1cdb4c47SGwendal Grignou .iio_channels = sx9360_channels, 707*1cdb4c47SGwendal Grignou .num_iio_channels = ARRAY_SIZE(sx9360_channels), 708*1cdb4c47SGwendal Grignou .iio_info = { 709*1cdb4c47SGwendal Grignou .read_raw = sx9360_read_raw, 710*1cdb4c47SGwendal Grignou .read_avail = sx9360_read_avail, 711*1cdb4c47SGwendal Grignou .read_label = sx9360_read_label, 712*1cdb4c47SGwendal Grignou .read_event_value = sx9360_read_event_val, 713*1cdb4c47SGwendal Grignou .write_event_value = sx9360_write_event_val, 714*1cdb4c47SGwendal Grignou .write_raw = sx9360_write_raw, 715*1cdb4c47SGwendal Grignou .read_event_config = sx_common_read_event_config, 716*1cdb4c47SGwendal Grignou .write_event_config = sx_common_write_event_config, 717*1cdb4c47SGwendal Grignou }, 718*1cdb4c47SGwendal Grignou }; 719*1cdb4c47SGwendal Grignou 720*1cdb4c47SGwendal Grignou static int sx9360_probe(struct i2c_client *client) 721*1cdb4c47SGwendal Grignou { 722*1cdb4c47SGwendal Grignou return sx_common_probe(client, &sx9360_chip_info, &sx9360_regmap_config); 723*1cdb4c47SGwendal Grignou } 724*1cdb4c47SGwendal Grignou 725*1cdb4c47SGwendal Grignou static int __maybe_unused sx9360_suspend(struct device *dev) 726*1cdb4c47SGwendal Grignou { 727*1cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 728*1cdb4c47SGwendal Grignou unsigned int regval; 729*1cdb4c47SGwendal Grignou int ret; 730*1cdb4c47SGwendal Grignou 731*1cdb4c47SGwendal Grignou disable_irq_nosync(data->client->irq); 732*1cdb4c47SGwendal Grignou 733*1cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 734*1cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_GNRL_CTRL0, ®val); 735*1cdb4c47SGwendal Grignou 736*1cdb4c47SGwendal Grignou data->suspend_ctrl = 737*1cdb4c47SGwendal Grignou FIELD_GET(SX9360_REG_GNRL_CTRL0_PHEN_MASK, regval); 738*1cdb4c47SGwendal Grignou 739*1cdb4c47SGwendal Grignou if (ret < 0) 740*1cdb4c47SGwendal Grignou goto out; 741*1cdb4c47SGwendal Grignou 742*1cdb4c47SGwendal Grignou /* Disable all phases, send the device to sleep. */ 743*1cdb4c47SGwendal Grignou ret = regmap_write(data->regmap, SX9360_REG_GNRL_CTRL0, 0); 744*1cdb4c47SGwendal Grignou 745*1cdb4c47SGwendal Grignou out: 746*1cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 747*1cdb4c47SGwendal Grignou return ret; 748*1cdb4c47SGwendal Grignou } 749*1cdb4c47SGwendal Grignou 750*1cdb4c47SGwendal Grignou static int __maybe_unused sx9360_resume(struct device *dev) 751*1cdb4c47SGwendal Grignou { 752*1cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 753*1cdb4c47SGwendal Grignou int ret; 754*1cdb4c47SGwendal Grignou 755*1cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 756*1cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_GNRL_CTRL0, 757*1cdb4c47SGwendal Grignou SX9360_REG_GNRL_CTRL0_PHEN_MASK, 758*1cdb4c47SGwendal Grignou data->suspend_ctrl); 759*1cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 760*1cdb4c47SGwendal Grignou if (ret) 761*1cdb4c47SGwendal Grignou return ret; 762*1cdb4c47SGwendal Grignou 763*1cdb4c47SGwendal Grignou enable_irq(data->client->irq); 764*1cdb4c47SGwendal Grignou return 0; 765*1cdb4c47SGwendal Grignou } 766*1cdb4c47SGwendal Grignou 767*1cdb4c47SGwendal Grignou static SIMPLE_DEV_PM_OPS(sx9360_pm_ops, sx9360_suspend, sx9360_resume); 768*1cdb4c47SGwendal Grignou 769*1cdb4c47SGwendal Grignou static const struct acpi_device_id sx9360_acpi_match[] = { 770*1cdb4c47SGwendal Grignou { "STH9360", SX9360_WHOAMI_VALUE }, 771*1cdb4c47SGwendal Grignou { } 772*1cdb4c47SGwendal Grignou }; 773*1cdb4c47SGwendal Grignou MODULE_DEVICE_TABLE(acpi, sx9360_acpi_match); 774*1cdb4c47SGwendal Grignou 775*1cdb4c47SGwendal Grignou static const struct of_device_id sx9360_of_match[] = { 776*1cdb4c47SGwendal Grignou { .compatible = "semtech,sx9360", (void *)SX9360_WHOAMI_VALUE }, 777*1cdb4c47SGwendal Grignou { } 778*1cdb4c47SGwendal Grignou }; 779*1cdb4c47SGwendal Grignou MODULE_DEVICE_TABLE(of, sx9360_of_match); 780*1cdb4c47SGwendal Grignou 781*1cdb4c47SGwendal Grignou static const struct i2c_device_id sx9360_id[] = { 782*1cdb4c47SGwendal Grignou {"sx9360", SX9360_WHOAMI_VALUE }, 783*1cdb4c47SGwendal Grignou { } 784*1cdb4c47SGwendal Grignou }; 785*1cdb4c47SGwendal Grignou MODULE_DEVICE_TABLE(i2c, sx9360_id); 786*1cdb4c47SGwendal Grignou 787*1cdb4c47SGwendal Grignou static struct i2c_driver sx9360_driver = { 788*1cdb4c47SGwendal Grignou .driver = { 789*1cdb4c47SGwendal Grignou .name = "sx9360", 790*1cdb4c47SGwendal Grignou .acpi_match_table = sx9360_acpi_match, 791*1cdb4c47SGwendal Grignou .of_match_table = sx9360_of_match, 792*1cdb4c47SGwendal Grignou .pm = &sx9360_pm_ops, 793*1cdb4c47SGwendal Grignou 794*1cdb4c47SGwendal Grignou /* 795*1cdb4c47SGwendal Grignou * Lots of i2c transfers in probe + over 200 ms waiting in 796*1cdb4c47SGwendal Grignou * sx9360_init_compensation() mean a slow probe; prefer async 797*1cdb4c47SGwendal Grignou * so we don't delay boot if we're builtin to the kernel. 798*1cdb4c47SGwendal Grignou */ 799*1cdb4c47SGwendal Grignou .probe_type = PROBE_PREFER_ASYNCHRONOUS, 800*1cdb4c47SGwendal Grignou }, 801*1cdb4c47SGwendal Grignou .probe_new = sx9360_probe, 802*1cdb4c47SGwendal Grignou .id_table = sx9360_id, 803*1cdb4c47SGwendal Grignou }; 804*1cdb4c47SGwendal Grignou module_i2c_driver(sx9360_driver); 805*1cdb4c47SGwendal Grignou 806*1cdb4c47SGwendal Grignou MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>"); 807*1cdb4c47SGwendal Grignou MODULE_DESCRIPTION("Driver for Semtech SX9360 proximity sensor"); 808*1cdb4c47SGwendal Grignou MODULE_LICENSE("GPL v2"); 809*1cdb4c47SGwendal Grignou MODULE_IMPORT_NS(SEMTECH_PROX); 810