11cdb4c47SGwendal Grignou // SPDX-License-Identifier: GPL-2.0 21cdb4c47SGwendal Grignou /* 31cdb4c47SGwendal Grignou * Copyright 2021 Google LLC. 41cdb4c47SGwendal Grignou * 51cdb4c47SGwendal Grignou * Driver for Semtech's SX9360 capacitive proximity/button solution. 61cdb4c47SGwendal Grignou * Based on SX9360 driver and copy of datasheet at: 71cdb4c47SGwendal Grignou * https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf 81cdb4c47SGwendal Grignou */ 91cdb4c47SGwendal Grignou 101cdb4c47SGwendal Grignou #include <linux/acpi.h> 111cdb4c47SGwendal Grignou #include <linux/bits.h> 121cdb4c47SGwendal Grignou #include <linux/bitfield.h> 131cdb4c47SGwendal Grignou #include <linux/delay.h> 141cdb4c47SGwendal Grignou #include <linux/i2c.h> 151cdb4c47SGwendal Grignou #include <linux/interrupt.h> 161cdb4c47SGwendal Grignou #include <linux/kernel.h> 171cdb4c47SGwendal Grignou #include <linux/log2.h> 181cdb4c47SGwendal Grignou #include <linux/mod_devicetable.h> 191cdb4c47SGwendal Grignou #include <linux/module.h> 201cdb4c47SGwendal Grignou #include <linux/pm.h> 2102d83fa6SGwendal Grignou #include <linux/property.h> 221cdb4c47SGwendal Grignou #include <linux/regmap.h> 231cdb4c47SGwendal Grignou 241cdb4c47SGwendal Grignou #include <linux/iio/iio.h> 251cdb4c47SGwendal Grignou 261cdb4c47SGwendal Grignou #include "sx_common.h" 271cdb4c47SGwendal Grignou 281cdb4c47SGwendal Grignou /* Nominal Oscillator Frequency. */ 291cdb4c47SGwendal Grignou #define SX9360_FOSC_MHZ 4 301cdb4c47SGwendal Grignou #define SX9360_FOSC_HZ (SX9360_FOSC_MHZ * 1000000) 311cdb4c47SGwendal Grignou 321cdb4c47SGwendal Grignou /* Register definitions. */ 331cdb4c47SGwendal Grignou #define SX9360_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC 341cdb4c47SGwendal Grignou #define SX9360_REG_STAT 0x01 351cdb4c47SGwendal Grignou #define SX9360_REG_STAT_COMPSTAT_MASK GENMASK(2, 1) 361cdb4c47SGwendal Grignou #define SX9360_REG_IRQ_MSK 0x02 371cdb4c47SGwendal Grignou #define SX9360_CONVDONE_IRQ BIT(0) 381cdb4c47SGwendal Grignou #define SX9360_FAR_IRQ BIT(2) 391cdb4c47SGwendal Grignou #define SX9360_CLOSE_IRQ BIT(3) 401cdb4c47SGwendal Grignou #define SX9360_REG_IRQ_CFG 0x03 411cdb4c47SGwendal Grignou 421cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL0 0x10 431cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL0_PHEN_MASK GENMASK(1, 0) 441cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL1 0x11 451cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL1_SCANPERIOD_MASK GENMASK(2, 0) 461cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL2 0x12 471cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_CTRL2_PERIOD_102MS 0x32 481cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_REG_2_PERIOD_MS(_r) \ 491cdb4c47SGwendal Grignou (((_r) * 8192) / (SX9360_FOSC_HZ / 1000)) 501cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_FREQ_2_REG(_f) (((_f) * 8192) / SX9360_FOSC_HZ) 511cdb4c47SGwendal Grignou #define SX9360_REG_GNRL_REG_2_FREQ(_r) (SX9360_FOSC_HZ / ((_r) * 8192)) 521cdb4c47SGwendal Grignou 531cdb4c47SGwendal Grignou #define SX9360_REG_AFE_CTRL1 0x21 541cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_PHR 0x22 551cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM1_PHR 0x23 561cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_PHM 0x24 571cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_RSVD 0x08 581cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_RESOLUTION_MASK GENMASK(2, 0) 591cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM0_RESOLUTION_128 0x02 601cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM1_PHM 0x25 611cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF 0x40 621cdb4c47SGwendal Grignou #define SX9360_REG_AFE_PARAM1_FREQ_83_33HZ 0x06 631cdb4c47SGwendal Grignou 641cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_PHR 0x40 651cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_PHM 0x41 661cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3) 671cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_GAIN_1 0x80 6802d83fa6SGwendal Grignou #define SX9360_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0) 691cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL0_RAWFILT_1P50 0x01 701cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL1 0x42 711cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_MASK GENMASK(5, 3) 721cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K 0x20 731cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL2 0x43 741cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL2_AVGDEB_MASK GENMASK(7, 6) 751cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES 0x40 761cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K 0x20 771cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3 0x44 781cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_MASK GENMASK(5, 3) 791cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 0x08 801cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK GENMASK(2, 0) 811cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256 0x04 821cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL4 0x45 831cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL4_HYST_MASK GENMASK(5, 4) 841cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK GENMASK(3, 2) 851cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK GENMASK(1, 0) 861cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL5 0x46 871cdb4c47SGwendal Grignou #define SX9360_REG_PROX_CTRL5_PROXTHRESH_32 0x08 881cdb4c47SGwendal Grignou 891cdb4c47SGwendal Grignou #define SX9360_REG_REF_CORR0 0x60 901cdb4c47SGwendal Grignou #define SX9360_REG_REF_CORR1 0x61 911cdb4c47SGwendal Grignou 921cdb4c47SGwendal Grignou #define SX9360_REG_USEFUL_PHR_MSB 0x90 931cdb4c47SGwendal Grignou #define SX9360_REG_USEFUL_PHR_LSB 0x91 941cdb4c47SGwendal Grignou 951cdb4c47SGwendal Grignou #define SX9360_REG_OFFSET_PMR_MSB 0x92 961cdb4c47SGwendal Grignou #define SX9360_REG_OFFSET_PMR_LSB 0x93 971cdb4c47SGwendal Grignou 981cdb4c47SGwendal Grignou #define SX9360_REG_USEFUL_PHM_MSB 0x94 991cdb4c47SGwendal Grignou #define SX9360_REG_USEFUL_PHM_LSB 0x95 1001cdb4c47SGwendal Grignou 1011cdb4c47SGwendal Grignou #define SX9360_REG_AVG_PHM_MSB 0x96 1021cdb4c47SGwendal Grignou #define SX9360_REG_AVG_PHM_LSB 0x97 1031cdb4c47SGwendal Grignou 1041cdb4c47SGwendal Grignou #define SX9360_REG_DIFF_PHM_MSB 0x98 1051cdb4c47SGwendal Grignou #define SX9360_REG_DIFF_PHM_LSB 0x99 1061cdb4c47SGwendal Grignou 1071cdb4c47SGwendal Grignou #define SX9360_REG_OFFSET_PHM_MSB 0x9a 1081cdb4c47SGwendal Grignou #define SX9360_REG_OFFSET_PHM_LSB 0x9b 1091cdb4c47SGwendal Grignou 1101cdb4c47SGwendal Grignou #define SX9360_REG_USE_FILTER_MSB 0x9a 1111cdb4c47SGwendal Grignou #define SX9360_REG_USE_FILTER_LSB 0x9b 1121cdb4c47SGwendal Grignou 1131cdb4c47SGwendal Grignou #define SX9360_REG_RESET 0xcf 1141cdb4c47SGwendal Grignou /* Write this to REG_RESET to do a soft reset. */ 1151cdb4c47SGwendal Grignou #define SX9360_SOFT_RESET 0xde 1161cdb4c47SGwendal Grignou 1171cdb4c47SGwendal Grignou #define SX9360_REG_WHOAMI 0xfa 1181cdb4c47SGwendal Grignou #define SX9360_WHOAMI_VALUE 0x60 1191cdb4c47SGwendal Grignou 1201cdb4c47SGwendal Grignou #define SX9360_REG_REVISION 0xfe 1211cdb4c47SGwendal Grignou 1221cdb4c47SGwendal Grignou /* 2 channels, Phase Reference and Measurement. */ 1231cdb4c47SGwendal Grignou #define SX9360_NUM_CHANNELS 2 1241cdb4c47SGwendal Grignou 1251cdb4c47SGwendal Grignou static const struct iio_chan_spec sx9360_channels[] = { 1261cdb4c47SGwendal Grignou { 1271cdb4c47SGwendal Grignou .type = IIO_PROXIMITY, 1281cdb4c47SGwendal Grignou .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1291cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_HARDWAREGAIN), 1301cdb4c47SGwendal Grignou .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 1311cdb4c47SGwendal Grignou .info_mask_separate_available = 1321cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_HARDWAREGAIN), 1331cdb4c47SGwendal Grignou .info_mask_shared_by_all_available = 1341cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_SAMP_FREQ), 1351cdb4c47SGwendal Grignou .indexed = 1, 1361cdb4c47SGwendal Grignou .address = SX9360_REG_USEFUL_PHR_MSB, 1371cdb4c47SGwendal Grignou .channel = 0, 1381cdb4c47SGwendal Grignou .scan_index = 0, 1391cdb4c47SGwendal Grignou .scan_type = { 1401cdb4c47SGwendal Grignou .sign = 's', 1411cdb4c47SGwendal Grignou .realbits = 12, 1421cdb4c47SGwendal Grignou .storagebits = 16, 1431cdb4c47SGwendal Grignou .endianness = IIO_BE, 1441cdb4c47SGwendal Grignou }, 1451cdb4c47SGwendal Grignou }, 1461cdb4c47SGwendal Grignou { 1471cdb4c47SGwendal Grignou .type = IIO_PROXIMITY, 1481cdb4c47SGwendal Grignou .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1491cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_HARDWAREGAIN), 1501cdb4c47SGwendal Grignou .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 1511cdb4c47SGwendal Grignou .info_mask_separate_available = 1521cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_HARDWAREGAIN), 1531cdb4c47SGwendal Grignou .info_mask_shared_by_all_available = 1541cdb4c47SGwendal Grignou BIT(IIO_CHAN_INFO_SAMP_FREQ), 1551cdb4c47SGwendal Grignou .indexed = 1, 1561cdb4c47SGwendal Grignou .address = SX9360_REG_USEFUL_PHM_MSB, 1571cdb4c47SGwendal Grignou .event_spec = sx_common_events, 1581cdb4c47SGwendal Grignou .num_event_specs = ARRAY_SIZE(sx_common_events), 1591cdb4c47SGwendal Grignou .channel = 1, 1601cdb4c47SGwendal Grignou .scan_index = 1, 1611cdb4c47SGwendal Grignou .scan_type = { 1621cdb4c47SGwendal Grignou .sign = 's', 1631cdb4c47SGwendal Grignou .realbits = 12, 1641cdb4c47SGwendal Grignou .storagebits = 16, 1651cdb4c47SGwendal Grignou .endianness = IIO_BE, 1661cdb4c47SGwendal Grignou }, 1671cdb4c47SGwendal Grignou }, 1681cdb4c47SGwendal Grignou IIO_CHAN_SOFT_TIMESTAMP(2), 1691cdb4c47SGwendal Grignou }; 1701cdb4c47SGwendal Grignou 1711cdb4c47SGwendal Grignou /* 1721cdb4c47SGwendal Grignou * Each entry contains the integer part (val) and the fractional part, in micro 1731cdb4c47SGwendal Grignou * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO. 1741cdb4c47SGwendal Grignou * 1751cdb4c47SGwendal Grignou * The frequency control register holds the period, with a ~2ms increment. 1761cdb4c47SGwendal Grignou * Therefore the smallest frequency is 4MHz / (2047 * 8192), 1771cdb4c47SGwendal Grignou * The fastest is 4MHz / 8192. 1781cdb4c47SGwendal Grignou * The interval is not linear, but given there is 2047 possible value, 1791cdb4c47SGwendal Grignou * Returns the fake increment of (Max-Min)/2047 1801cdb4c47SGwendal Grignou */ 1811cdb4c47SGwendal Grignou static const struct { 1821cdb4c47SGwendal Grignou int val; 1831cdb4c47SGwendal Grignou int val2; 1841cdb4c47SGwendal Grignou } sx9360_samp_freq_interval[] = { 1851cdb4c47SGwendal Grignou { 0, 281250 }, /* 4MHz / (8192 * 2047) */ 1861cdb4c47SGwendal Grignou { 0, 281250 }, 1871cdb4c47SGwendal Grignou { 448, 281250 }, /* 4MHz / 8192 */ 1881cdb4c47SGwendal Grignou }; 1891cdb4c47SGwendal Grignou 1901cdb4c47SGwendal Grignou static const struct regmap_range sx9360_writable_reg_ranges[] = { 1911cdb4c47SGwendal Grignou /* 1921cdb4c47SGwendal Grignou * To set COMPSTAT for compensation, even if datasheet says register is 1931cdb4c47SGwendal Grignou * RO. 1941cdb4c47SGwendal Grignou */ 1951cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_STAT, SX9360_REG_IRQ_CFG), 1961cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_GNRL_CTRL0, SX9360_REG_GNRL_CTRL2), 1971cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_PARAM1_PHM), 1981cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL5), 1991cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_REF_CORR0, SX9360_REG_REF_CORR1), 2001cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_OFFSET_PMR_MSB, SX9360_REG_OFFSET_PMR_LSB), 2011cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_RESET, SX9360_REG_RESET), 2021cdb4c47SGwendal Grignou }; 2031cdb4c47SGwendal Grignou 2041cdb4c47SGwendal Grignou static const struct regmap_access_table sx9360_writeable_regs = { 2051cdb4c47SGwendal Grignou .yes_ranges = sx9360_writable_reg_ranges, 2061cdb4c47SGwendal Grignou .n_yes_ranges = ARRAY_SIZE(sx9360_writable_reg_ranges), 2071cdb4c47SGwendal Grignou }; 2081cdb4c47SGwendal Grignou 2091cdb4c47SGwendal Grignou /* 2101cdb4c47SGwendal Grignou * All allocated registers are readable, so we just list unallocated 2111cdb4c47SGwendal Grignou * ones. 2121cdb4c47SGwendal Grignou */ 2131cdb4c47SGwendal Grignou static const struct regmap_range sx9360_non_readable_reg_ranges[] = { 2141cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_IRQ_CFG + 1, SX9360_REG_GNRL_CTRL0 - 1), 2151cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_GNRL_CTRL2 + 1, SX9360_REG_AFE_CTRL1 - 1), 2161cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_AFE_PARAM1_PHM + 1, 2171cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL0_PHR - 1), 2181cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_PROX_CTRL5 + 1, SX9360_REG_REF_CORR0 - 1), 2191cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_REF_CORR1 + 1, 2201cdb4c47SGwendal Grignou SX9360_REG_USEFUL_PHR_MSB - 1), 2211cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_USE_FILTER_LSB + 1, SX9360_REG_RESET - 1), 2221cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_RESET + 1, SX9360_REG_WHOAMI - 1), 2231cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_WHOAMI + 1, SX9360_REG_REVISION - 1), 2241cdb4c47SGwendal Grignou }; 2251cdb4c47SGwendal Grignou 2261cdb4c47SGwendal Grignou static const struct regmap_access_table sx9360_readable_regs = { 2271cdb4c47SGwendal Grignou .no_ranges = sx9360_non_readable_reg_ranges, 2281cdb4c47SGwendal Grignou .n_no_ranges = ARRAY_SIZE(sx9360_non_readable_reg_ranges), 2291cdb4c47SGwendal Grignou }; 2301cdb4c47SGwendal Grignou 2311cdb4c47SGwendal Grignou static const struct regmap_range sx9360_volatile_reg_ranges[] = { 2321cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_IRQ_SRC, SX9360_REG_STAT), 2331cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_USEFUL_PHR_MSB, SX9360_REG_USE_FILTER_LSB), 2341cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_WHOAMI, SX9360_REG_WHOAMI), 2351cdb4c47SGwendal Grignou regmap_reg_range(SX9360_REG_REVISION, SX9360_REG_REVISION), 2361cdb4c47SGwendal Grignou }; 2371cdb4c47SGwendal Grignou 2381cdb4c47SGwendal Grignou static const struct regmap_access_table sx9360_volatile_regs = { 2391cdb4c47SGwendal Grignou .yes_ranges = sx9360_volatile_reg_ranges, 2401cdb4c47SGwendal Grignou .n_yes_ranges = ARRAY_SIZE(sx9360_volatile_reg_ranges), 2411cdb4c47SGwendal Grignou }; 2421cdb4c47SGwendal Grignou 2431cdb4c47SGwendal Grignou static const struct regmap_config sx9360_regmap_config = { 2441cdb4c47SGwendal Grignou .reg_bits = 8, 2451cdb4c47SGwendal Grignou .val_bits = 8, 2461cdb4c47SGwendal Grignou 2471cdb4c47SGwendal Grignou .max_register = SX9360_REG_REVISION, 2481cdb4c47SGwendal Grignou .cache_type = REGCACHE_RBTREE, 2491cdb4c47SGwendal Grignou 2501cdb4c47SGwendal Grignou .wr_table = &sx9360_writeable_regs, 2511cdb4c47SGwendal Grignou .rd_table = &sx9360_readable_regs, 2521cdb4c47SGwendal Grignou .volatile_table = &sx9360_volatile_regs, 2531cdb4c47SGwendal Grignou }; 2541cdb4c47SGwendal Grignou 2551cdb4c47SGwendal Grignou static int sx9360_read_prox_data(struct sx_common_data *data, 2561cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, 2571cdb4c47SGwendal Grignou __be16 *val) 2581cdb4c47SGwendal Grignou { 2591cdb4c47SGwendal Grignou return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val)); 2601cdb4c47SGwendal Grignou } 2611cdb4c47SGwendal Grignou 2621cdb4c47SGwendal Grignou /* 2631cdb4c47SGwendal Grignou * If we have no interrupt support, we have to wait for a scan period 2641cdb4c47SGwendal Grignou * after enabling a channel to get a result. 2651cdb4c47SGwendal Grignou */ 2661cdb4c47SGwendal Grignou static int sx9360_wait_for_sample(struct sx_common_data *data) 2671cdb4c47SGwendal Grignou { 2681cdb4c47SGwendal Grignou int ret; 2691cdb4c47SGwendal Grignou __be16 buf; 2701cdb4c47SGwendal Grignou 2711cdb4c47SGwendal Grignou ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1, 2721cdb4c47SGwendal Grignou &buf, sizeof(buf)); 2731cdb4c47SGwendal Grignou if (ret < 0) 2741cdb4c47SGwendal Grignou return ret; 2751cdb4c47SGwendal Grignou msleep(SX9360_REG_GNRL_REG_2_PERIOD_MS(be16_to_cpu(buf))); 2761cdb4c47SGwendal Grignou 2771cdb4c47SGwendal Grignou return 0; 2781cdb4c47SGwendal Grignou } 2791cdb4c47SGwendal Grignou 2801cdb4c47SGwendal Grignou static int sx9360_read_gain(struct sx_common_data *data, 2811cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, int *val) 2821cdb4c47SGwendal Grignou { 2831cdb4c47SGwendal Grignou unsigned int reg, regval; 2841cdb4c47SGwendal Grignou int ret; 2851cdb4c47SGwendal Grignou 2861cdb4c47SGwendal Grignou reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel; 2871cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, reg, ®val); 2881cdb4c47SGwendal Grignou if (ret) 2891cdb4c47SGwendal Grignou return ret; 2901cdb4c47SGwendal Grignou 2911cdb4c47SGwendal Grignou *val = 1 << FIELD_GET(SX9360_REG_PROX_CTRL0_GAIN_MASK, regval); 2921cdb4c47SGwendal Grignou 2931cdb4c47SGwendal Grignou return IIO_VAL_INT; 2941cdb4c47SGwendal Grignou } 2951cdb4c47SGwendal Grignou 2961cdb4c47SGwendal Grignou static int sx9360_read_samp_freq(struct sx_common_data *data, 2971cdb4c47SGwendal Grignou int *val, int *val2) 2981cdb4c47SGwendal Grignou { 2991cdb4c47SGwendal Grignou int ret, divisor; 3001cdb4c47SGwendal Grignou __be16 buf; 3011cdb4c47SGwendal Grignou 3021cdb4c47SGwendal Grignou ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1, 3031cdb4c47SGwendal Grignou &buf, sizeof(buf)); 3041cdb4c47SGwendal Grignou if (ret < 0) 3051cdb4c47SGwendal Grignou return ret; 3061cdb4c47SGwendal Grignou divisor = be16_to_cpu(buf); 3071cdb4c47SGwendal Grignou if (divisor == 0) { 3081cdb4c47SGwendal Grignou *val = 0; 3091cdb4c47SGwendal Grignou return IIO_VAL_INT; 3101cdb4c47SGwendal Grignou } 3111cdb4c47SGwendal Grignou 3121cdb4c47SGwendal Grignou *val = SX9360_FOSC_HZ; 3131cdb4c47SGwendal Grignou *val2 = divisor * 8192; 3141cdb4c47SGwendal Grignou 3151cdb4c47SGwendal Grignou return IIO_VAL_FRACTIONAL; 3161cdb4c47SGwendal Grignou } 3171cdb4c47SGwendal Grignou 3181cdb4c47SGwendal Grignou static int sx9360_read_raw(struct iio_dev *indio_dev, 3191cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, 3201cdb4c47SGwendal Grignou int *val, int *val2, long mask) 3211cdb4c47SGwendal Grignou { 3221cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 3231cdb4c47SGwendal Grignou int ret; 3241cdb4c47SGwendal Grignou 3251cdb4c47SGwendal Grignou switch (mask) { 3261cdb4c47SGwendal Grignou case IIO_CHAN_INFO_RAW: 3271cdb4c47SGwendal Grignou ret = iio_device_claim_direct_mode(indio_dev); 3281cdb4c47SGwendal Grignou if (ret) 3291cdb4c47SGwendal Grignou return ret; 3301cdb4c47SGwendal Grignou 3311cdb4c47SGwendal Grignou ret = sx_common_read_proximity(data, chan, val); 3321cdb4c47SGwendal Grignou iio_device_release_direct_mode(indio_dev); 3331cdb4c47SGwendal Grignou return ret; 3341cdb4c47SGwendal Grignou case IIO_CHAN_INFO_HARDWAREGAIN: 3351cdb4c47SGwendal Grignou ret = iio_device_claim_direct_mode(indio_dev); 3361cdb4c47SGwendal Grignou if (ret) 3371cdb4c47SGwendal Grignou return ret; 3381cdb4c47SGwendal Grignou 3391cdb4c47SGwendal Grignou ret = sx9360_read_gain(data, chan, val); 3401cdb4c47SGwendal Grignou iio_device_release_direct_mode(indio_dev); 3411cdb4c47SGwendal Grignou return ret; 3421cdb4c47SGwendal Grignou case IIO_CHAN_INFO_SAMP_FREQ: 3431cdb4c47SGwendal Grignou return sx9360_read_samp_freq(data, val, val2); 3441cdb4c47SGwendal Grignou default: 3451cdb4c47SGwendal Grignou return -EINVAL; 3461cdb4c47SGwendal Grignou } 3471cdb4c47SGwendal Grignou } 3481cdb4c47SGwendal Grignou 3491cdb4c47SGwendal Grignou static const char *sx9360_channel_labels[SX9360_NUM_CHANNELS] = { 3501cdb4c47SGwendal Grignou "reference", "main", 3511cdb4c47SGwendal Grignou }; 3521cdb4c47SGwendal Grignou 3531cdb4c47SGwendal Grignou static int sx9360_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, 3541cdb4c47SGwendal Grignou char *label) 3551cdb4c47SGwendal Grignou { 3561cdb4c47SGwendal Grignou return sysfs_emit(label, "%s\n", sx9360_channel_labels[chan->channel]); 3571cdb4c47SGwendal Grignou } 3581cdb4c47SGwendal Grignou 3591cdb4c47SGwendal Grignou static const int sx9360_gain_vals[] = { 1, 2, 4, 8 }; 3601cdb4c47SGwendal Grignou 3611cdb4c47SGwendal Grignou static int sx9360_read_avail(struct iio_dev *indio_dev, 3621cdb4c47SGwendal Grignou struct iio_chan_spec const *chan, 3631cdb4c47SGwendal Grignou const int **vals, int *type, int *length, 3641cdb4c47SGwendal Grignou long mask) 3651cdb4c47SGwendal Grignou { 3661cdb4c47SGwendal Grignou if (chan->type != IIO_PROXIMITY) 3671cdb4c47SGwendal Grignou return -EINVAL; 3681cdb4c47SGwendal Grignou 3691cdb4c47SGwendal Grignou switch (mask) { 3701cdb4c47SGwendal Grignou case IIO_CHAN_INFO_HARDWAREGAIN: 3711cdb4c47SGwendal Grignou *type = IIO_VAL_INT; 3721cdb4c47SGwendal Grignou *length = ARRAY_SIZE(sx9360_gain_vals); 3731cdb4c47SGwendal Grignou *vals = sx9360_gain_vals; 3741cdb4c47SGwendal Grignou return IIO_AVAIL_LIST; 3751cdb4c47SGwendal Grignou case IIO_CHAN_INFO_SAMP_FREQ: 3761cdb4c47SGwendal Grignou *type = IIO_VAL_INT_PLUS_MICRO; 3771cdb4c47SGwendal Grignou *length = ARRAY_SIZE(sx9360_samp_freq_interval) * 2; 3781cdb4c47SGwendal Grignou *vals = (int *)sx9360_samp_freq_interval; 3791cdb4c47SGwendal Grignou return IIO_AVAIL_RANGE; 3801cdb4c47SGwendal Grignou default: 3811cdb4c47SGwendal Grignou return -EINVAL; 3821cdb4c47SGwendal Grignou } 3831cdb4c47SGwendal Grignou } 3841cdb4c47SGwendal Grignou 3851cdb4c47SGwendal Grignou static int sx9360_set_samp_freq(struct sx_common_data *data, 3861cdb4c47SGwendal Grignou int val, int val2) 3871cdb4c47SGwendal Grignou { 3881cdb4c47SGwendal Grignou int ret, reg; 3891cdb4c47SGwendal Grignou __be16 buf; 3901cdb4c47SGwendal Grignou 3911cdb4c47SGwendal Grignou reg = val * 8192 / SX9360_FOSC_HZ + val2 * 8192 / (SX9360_FOSC_MHZ); 3921cdb4c47SGwendal Grignou buf = cpu_to_be16(reg); 3931cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 3941cdb4c47SGwendal Grignou 3951cdb4c47SGwendal Grignou ret = regmap_bulk_write(data->regmap, SX9360_REG_GNRL_CTRL1, &buf, 3961cdb4c47SGwendal Grignou sizeof(buf)); 3971cdb4c47SGwendal Grignou 3981cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 3991cdb4c47SGwendal Grignou 4001cdb4c47SGwendal Grignou return ret; 4011cdb4c47SGwendal Grignou } 4021cdb4c47SGwendal Grignou 4031cdb4c47SGwendal Grignou static int sx9360_read_thresh(struct sx_common_data *data, int *val) 4041cdb4c47SGwendal Grignou { 4051cdb4c47SGwendal Grignou unsigned int regval; 4061cdb4c47SGwendal Grignou int ret; 4071cdb4c47SGwendal Grignou 4081cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL5, ®val); 4091cdb4c47SGwendal Grignou if (ret) 4101cdb4c47SGwendal Grignou return ret; 4111cdb4c47SGwendal Grignou 4121cdb4c47SGwendal Grignou if (regval <= 1) 4131cdb4c47SGwendal Grignou *val = regval; 4141cdb4c47SGwendal Grignou else 4151cdb4c47SGwendal Grignou *val = (regval * regval) / 2; 4161cdb4c47SGwendal Grignou 4171cdb4c47SGwendal Grignou return IIO_VAL_INT; 4181cdb4c47SGwendal Grignou } 4191cdb4c47SGwendal Grignou 4201cdb4c47SGwendal Grignou static int sx9360_read_hysteresis(struct sx_common_data *data, int *val) 4211cdb4c47SGwendal Grignou { 4221cdb4c47SGwendal Grignou unsigned int regval, pthresh; 4231cdb4c47SGwendal Grignou int ret; 4241cdb4c47SGwendal Grignou 4251cdb4c47SGwendal Grignou ret = sx9360_read_thresh(data, &pthresh); 4261cdb4c47SGwendal Grignou if (ret < 0) 4271cdb4c47SGwendal Grignou return ret; 4281cdb4c47SGwendal Grignou 4291cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 4301cdb4c47SGwendal Grignou if (ret) 4311cdb4c47SGwendal Grignou return ret; 4321cdb4c47SGwendal Grignou 4331cdb4c47SGwendal Grignou regval = FIELD_GET(SX9360_REG_PROX_CTRL4_HYST_MASK, regval); 4341cdb4c47SGwendal Grignou if (!regval) 4351cdb4c47SGwendal Grignou *val = 0; 4361cdb4c47SGwendal Grignou else 4371cdb4c47SGwendal Grignou *val = pthresh >> (5 - regval); 4381cdb4c47SGwendal Grignou 4391cdb4c47SGwendal Grignou return IIO_VAL_INT; 4401cdb4c47SGwendal Grignou } 4411cdb4c47SGwendal Grignou 4421cdb4c47SGwendal Grignou static int sx9360_read_far_debounce(struct sx_common_data *data, int *val) 4431cdb4c47SGwendal Grignou { 4441cdb4c47SGwendal Grignou unsigned int regval; 4451cdb4c47SGwendal Grignou int ret; 4461cdb4c47SGwendal Grignou 4471cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 4481cdb4c47SGwendal Grignou if (ret) 4491cdb4c47SGwendal Grignou return ret; 4501cdb4c47SGwendal Grignou 4511cdb4c47SGwendal Grignou regval = FIELD_GET(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, regval); 4521cdb4c47SGwendal Grignou if (regval) 4531cdb4c47SGwendal Grignou *val = 1 << regval; 4541cdb4c47SGwendal Grignou else 4551cdb4c47SGwendal Grignou *val = 0; 4561cdb4c47SGwendal Grignou 4571cdb4c47SGwendal Grignou return IIO_VAL_INT; 4581cdb4c47SGwendal Grignou } 4591cdb4c47SGwendal Grignou 4601cdb4c47SGwendal Grignou static int sx9360_read_close_debounce(struct sx_common_data *data, int *val) 4611cdb4c47SGwendal Grignou { 4621cdb4c47SGwendal Grignou unsigned int regval; 4631cdb4c47SGwendal Grignou int ret; 4641cdb4c47SGwendal Grignou 4651cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val); 4661cdb4c47SGwendal Grignou if (ret) 4671cdb4c47SGwendal Grignou return ret; 4681cdb4c47SGwendal Grignou 4691cdb4c47SGwendal Grignou regval = FIELD_GET(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, regval); 4701cdb4c47SGwendal Grignou if (regval) 4711cdb4c47SGwendal Grignou *val = 1 << regval; 4721cdb4c47SGwendal Grignou else 4731cdb4c47SGwendal Grignou *val = 0; 4741cdb4c47SGwendal Grignou 4751cdb4c47SGwendal Grignou return IIO_VAL_INT; 4761cdb4c47SGwendal Grignou } 4771cdb4c47SGwendal Grignou 4781cdb4c47SGwendal Grignou static int sx9360_read_event_val(struct iio_dev *indio_dev, 4791cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, 4801cdb4c47SGwendal Grignou enum iio_event_type type, 4811cdb4c47SGwendal Grignou enum iio_event_direction dir, 4821cdb4c47SGwendal Grignou enum iio_event_info info, int *val, int *val2) 4831cdb4c47SGwendal Grignou { 4841cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 4851cdb4c47SGwendal Grignou 4861cdb4c47SGwendal Grignou if (chan->type != IIO_PROXIMITY) 4871cdb4c47SGwendal Grignou return -EINVAL; 4881cdb4c47SGwendal Grignou 4891cdb4c47SGwendal Grignou switch (info) { 4901cdb4c47SGwendal Grignou case IIO_EV_INFO_VALUE: 4911cdb4c47SGwendal Grignou return sx9360_read_thresh(data, val); 4921cdb4c47SGwendal Grignou case IIO_EV_INFO_PERIOD: 4931cdb4c47SGwendal Grignou switch (dir) { 4941cdb4c47SGwendal Grignou case IIO_EV_DIR_RISING: 4951cdb4c47SGwendal Grignou return sx9360_read_far_debounce(data, val); 4961cdb4c47SGwendal Grignou case IIO_EV_DIR_FALLING: 4971cdb4c47SGwendal Grignou return sx9360_read_close_debounce(data, val); 4981cdb4c47SGwendal Grignou default: 4991cdb4c47SGwendal Grignou return -EINVAL; 5001cdb4c47SGwendal Grignou } 5011cdb4c47SGwendal Grignou case IIO_EV_INFO_HYSTERESIS: 5021cdb4c47SGwendal Grignou return sx9360_read_hysteresis(data, val); 5031cdb4c47SGwendal Grignou default: 5041cdb4c47SGwendal Grignou return -EINVAL; 5051cdb4c47SGwendal Grignou } 5061cdb4c47SGwendal Grignou } 5071cdb4c47SGwendal Grignou 5081cdb4c47SGwendal Grignou static int sx9360_write_thresh(struct sx_common_data *data, int _val) 5091cdb4c47SGwendal Grignou { 5101cdb4c47SGwendal Grignou unsigned int val = _val; 5111cdb4c47SGwendal Grignou int ret; 5121cdb4c47SGwendal Grignou 5131cdb4c47SGwendal Grignou if (val >= 1) 5141cdb4c47SGwendal Grignou val = int_sqrt(2 * val); 5151cdb4c47SGwendal Grignou 5161cdb4c47SGwendal Grignou if (val > 0xff) 5171cdb4c47SGwendal Grignou return -EINVAL; 5181cdb4c47SGwendal Grignou 5191cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 5201cdb4c47SGwendal Grignou ret = regmap_write(data->regmap, SX9360_REG_PROX_CTRL5, val); 5211cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 5221cdb4c47SGwendal Grignou 5231cdb4c47SGwendal Grignou return ret; 5241cdb4c47SGwendal Grignou } 5251cdb4c47SGwendal Grignou 5261cdb4c47SGwendal Grignou static int sx9360_write_hysteresis(struct sx_common_data *data, int _val) 5271cdb4c47SGwendal Grignou { 5281cdb4c47SGwendal Grignou unsigned int hyst, val = _val; 5291cdb4c47SGwendal Grignou int ret, pthresh; 5301cdb4c47SGwendal Grignou 5311cdb4c47SGwendal Grignou ret = sx9360_read_thresh(data, &pthresh); 5321cdb4c47SGwendal Grignou if (ret < 0) 5331cdb4c47SGwendal Grignou return ret; 5341cdb4c47SGwendal Grignou 5351cdb4c47SGwendal Grignou if (val == 0) 5361cdb4c47SGwendal Grignou hyst = 0; 5371cdb4c47SGwendal Grignou else if (val >= pthresh >> 2) 5381cdb4c47SGwendal Grignou hyst = 3; 5391cdb4c47SGwendal Grignou else if (val >= pthresh >> 3) 5401cdb4c47SGwendal Grignou hyst = 2; 5411cdb4c47SGwendal Grignou else if (val >= pthresh >> 4) 5421cdb4c47SGwendal Grignou hyst = 1; 5431cdb4c47SGwendal Grignou else 5441cdb4c47SGwendal Grignou return -EINVAL; 5451cdb4c47SGwendal Grignou 5461cdb4c47SGwendal Grignou hyst = FIELD_PREP(SX9360_REG_PROX_CTRL4_HYST_MASK, hyst); 5471cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 5481cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 5491cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL4_HYST_MASK, hyst); 5501cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 5511cdb4c47SGwendal Grignou 5521cdb4c47SGwendal Grignou return ret; 5531cdb4c47SGwendal Grignou } 5541cdb4c47SGwendal Grignou 5551cdb4c47SGwendal Grignou static int sx9360_write_far_debounce(struct sx_common_data *data, int _val) 5561cdb4c47SGwendal Grignou { 5571cdb4c47SGwendal Grignou unsigned int regval, val = _val; 5581cdb4c47SGwendal Grignou int ret; 5591cdb4c47SGwendal Grignou 5601cdb4c47SGwendal Grignou if (val > 0) 5611cdb4c47SGwendal Grignou val = ilog2(val); 5621cdb4c47SGwendal Grignou if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val)) 5631cdb4c47SGwendal Grignou return -EINVAL; 5641cdb4c47SGwendal Grignou 5651cdb4c47SGwendal Grignou regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val); 5661cdb4c47SGwendal Grignou 5671cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 5681cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 5691cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, 5701cdb4c47SGwendal Grignou regval); 5711cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 5721cdb4c47SGwendal Grignou 5731cdb4c47SGwendal Grignou return ret; 5741cdb4c47SGwendal Grignou } 5751cdb4c47SGwendal Grignou 5761cdb4c47SGwendal Grignou static int sx9360_write_close_debounce(struct sx_common_data *data, int _val) 5771cdb4c47SGwendal Grignou { 5781cdb4c47SGwendal Grignou unsigned int regval, val = _val; 5791cdb4c47SGwendal Grignou int ret; 5801cdb4c47SGwendal Grignou 5811cdb4c47SGwendal Grignou if (val > 0) 5821cdb4c47SGwendal Grignou val = ilog2(val); 5831cdb4c47SGwendal Grignou if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val)) 5841cdb4c47SGwendal Grignou return -EINVAL; 5851cdb4c47SGwendal Grignou 5861cdb4c47SGwendal Grignou regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val); 5871cdb4c47SGwendal Grignou 5881cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 5891cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4, 5901cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, 5911cdb4c47SGwendal Grignou regval); 5921cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 5931cdb4c47SGwendal Grignou 5941cdb4c47SGwendal Grignou return ret; 5951cdb4c47SGwendal Grignou } 5961cdb4c47SGwendal Grignou 5971cdb4c47SGwendal Grignou static int sx9360_write_event_val(struct iio_dev *indio_dev, 5981cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, 5991cdb4c47SGwendal Grignou enum iio_event_type type, 6001cdb4c47SGwendal Grignou enum iio_event_direction dir, 6011cdb4c47SGwendal Grignou enum iio_event_info info, int val, int val2) 6021cdb4c47SGwendal Grignou { 6031cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 6041cdb4c47SGwendal Grignou 6051cdb4c47SGwendal Grignou if (chan->type != IIO_PROXIMITY) 6061cdb4c47SGwendal Grignou return -EINVAL; 6071cdb4c47SGwendal Grignou 6081cdb4c47SGwendal Grignou switch (info) { 6091cdb4c47SGwendal Grignou case IIO_EV_INFO_VALUE: 6101cdb4c47SGwendal Grignou return sx9360_write_thresh(data, val); 6111cdb4c47SGwendal Grignou case IIO_EV_INFO_PERIOD: 6121cdb4c47SGwendal Grignou switch (dir) { 6131cdb4c47SGwendal Grignou case IIO_EV_DIR_RISING: 6141cdb4c47SGwendal Grignou return sx9360_write_far_debounce(data, val); 6151cdb4c47SGwendal Grignou case IIO_EV_DIR_FALLING: 6161cdb4c47SGwendal Grignou return sx9360_write_close_debounce(data, val); 6171cdb4c47SGwendal Grignou default: 6181cdb4c47SGwendal Grignou return -EINVAL; 6191cdb4c47SGwendal Grignou } 6201cdb4c47SGwendal Grignou case IIO_EV_INFO_HYSTERESIS: 6211cdb4c47SGwendal Grignou return sx9360_write_hysteresis(data, val); 6221cdb4c47SGwendal Grignou default: 6231cdb4c47SGwendal Grignou return -EINVAL; 6241cdb4c47SGwendal Grignou } 6251cdb4c47SGwendal Grignou } 6261cdb4c47SGwendal Grignou 6271cdb4c47SGwendal Grignou static int sx9360_write_gain(struct sx_common_data *data, 6281cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, int val) 6291cdb4c47SGwendal Grignou { 6301cdb4c47SGwendal Grignou unsigned int gain, reg; 6311cdb4c47SGwendal Grignou int ret; 6321cdb4c47SGwendal Grignou 6331cdb4c47SGwendal Grignou gain = ilog2(val); 6341cdb4c47SGwendal Grignou reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel; 6351cdb4c47SGwendal Grignou gain = FIELD_PREP(SX9360_REG_PROX_CTRL0_GAIN_MASK, gain); 6361cdb4c47SGwendal Grignou 6371cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 6381cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, reg, 6391cdb4c47SGwendal Grignou SX9360_REG_PROX_CTRL0_GAIN_MASK, 6401cdb4c47SGwendal Grignou gain); 6411cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 6421cdb4c47SGwendal Grignou 6431cdb4c47SGwendal Grignou return ret; 6441cdb4c47SGwendal Grignou } 6451cdb4c47SGwendal Grignou 6461cdb4c47SGwendal Grignou static int sx9360_write_raw(struct iio_dev *indio_dev, 6471cdb4c47SGwendal Grignou const struct iio_chan_spec *chan, int val, int val2, 6481cdb4c47SGwendal Grignou long mask) 6491cdb4c47SGwendal Grignou { 6501cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 6511cdb4c47SGwendal Grignou 6521cdb4c47SGwendal Grignou switch (mask) { 6531cdb4c47SGwendal Grignou case IIO_CHAN_INFO_SAMP_FREQ: 6541cdb4c47SGwendal Grignou return sx9360_set_samp_freq(data, val, val2); 6551cdb4c47SGwendal Grignou case IIO_CHAN_INFO_HARDWAREGAIN: 6561cdb4c47SGwendal Grignou return sx9360_write_gain(data, chan, val); 6571cdb4c47SGwendal Grignou default: 6581cdb4c47SGwendal Grignou return -EINVAL; 6591cdb4c47SGwendal Grignou } 6601cdb4c47SGwendal Grignou } 6611cdb4c47SGwendal Grignou 66202d83fa6SGwendal Grignou static const struct sx_common_reg_default sx9360_default_regs[] = { 66302d83fa6SGwendal Grignou { SX9360_REG_IRQ_MSK, 0x00 }, 66402d83fa6SGwendal Grignou { SX9360_REG_IRQ_CFG, 0x00 }, 66502d83fa6SGwendal Grignou /* 66602d83fa6SGwendal Grignou * The lower 2 bits should not be set as it enable sensors measurements. 66702d83fa6SGwendal Grignou * Turning the detection on before the configuration values are set to 66802d83fa6SGwendal Grignou * good values can cause the device to return erroneous readings. 66902d83fa6SGwendal Grignou */ 67002d83fa6SGwendal Grignou { SX9360_REG_GNRL_CTRL0, 0x00 }, 67102d83fa6SGwendal Grignou { SX9360_REG_GNRL_CTRL1, 0x00 }, 67202d83fa6SGwendal Grignou { SX9360_REG_GNRL_CTRL2, SX9360_REG_GNRL_CTRL2_PERIOD_102MS }, 67302d83fa6SGwendal Grignou 67402d83fa6SGwendal Grignou { SX9360_REG_AFE_CTRL1, 0x00 }, 67502d83fa6SGwendal Grignou { SX9360_REG_AFE_PARAM0_PHR, SX9360_REG_AFE_PARAM0_RSVD | 67602d83fa6SGwendal Grignou SX9360_REG_AFE_PARAM0_RESOLUTION_128 }, 67702d83fa6SGwendal Grignou { SX9360_REG_AFE_PARAM1_PHR, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | 67802d83fa6SGwendal Grignou SX9360_REG_AFE_PARAM1_FREQ_83_33HZ }, 67902d83fa6SGwendal Grignou { SX9360_REG_AFE_PARAM0_PHM, SX9360_REG_AFE_PARAM0_RSVD | 68002d83fa6SGwendal Grignou SX9360_REG_AFE_PARAM0_RESOLUTION_128 }, 68102d83fa6SGwendal Grignou { SX9360_REG_AFE_PARAM1_PHM, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | 68202d83fa6SGwendal Grignou SX9360_REG_AFE_PARAM1_FREQ_83_33HZ }, 68302d83fa6SGwendal Grignou 68402d83fa6SGwendal Grignou { SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL0_GAIN_1 | 68502d83fa6SGwendal Grignou SX9360_REG_PROX_CTRL0_RAWFILT_1P50 }, 68602d83fa6SGwendal Grignou { SX9360_REG_PROX_CTRL0_PHM, SX9360_REG_PROX_CTRL0_GAIN_1 | 68702d83fa6SGwendal Grignou SX9360_REG_PROX_CTRL0_RAWFILT_1P50 }, 68802d83fa6SGwendal Grignou { SX9360_REG_PROX_CTRL1, SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K }, 68902d83fa6SGwendal Grignou { SX9360_REG_PROX_CTRL2, SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES | 69002d83fa6SGwendal Grignou SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K }, 69102d83fa6SGwendal Grignou { SX9360_REG_PROX_CTRL3, SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 | 69202d83fa6SGwendal Grignou SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256 }, 69302d83fa6SGwendal Grignou { SX9360_REG_PROX_CTRL4, 0x00 }, 69402d83fa6SGwendal Grignou { SX9360_REG_PROX_CTRL5, SX9360_REG_PROX_CTRL5_PROXTHRESH_32 }, 69502d83fa6SGwendal Grignou }; 69602d83fa6SGwendal Grignou 6971cdb4c47SGwendal Grignou /* Activate all channels and perform an initial compensation. */ 6981cdb4c47SGwendal Grignou static int sx9360_init_compensation(struct iio_dev *indio_dev) 6991cdb4c47SGwendal Grignou { 7001cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(indio_dev); 7011cdb4c47SGwendal Grignou unsigned int val; 7021cdb4c47SGwendal Grignou int ret; 7031cdb4c47SGwendal Grignou 7041cdb4c47SGwendal Grignou /* run the compensation phase on all channels */ 7051cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_STAT, 7061cdb4c47SGwendal Grignou SX9360_REG_STAT_COMPSTAT_MASK, 7071cdb4c47SGwendal Grignou SX9360_REG_STAT_COMPSTAT_MASK); 7081cdb4c47SGwendal Grignou if (ret) 7091cdb4c47SGwendal Grignou return ret; 7101cdb4c47SGwendal Grignou 7111cdb4c47SGwendal Grignou return regmap_read_poll_timeout(data->regmap, SX9360_REG_STAT, val, 7121cdb4c47SGwendal Grignou !(val & SX9360_REG_STAT_COMPSTAT_MASK), 7131cdb4c47SGwendal Grignou 20000, 2000000); 7141cdb4c47SGwendal Grignou } 7151cdb4c47SGwendal Grignou 71602d83fa6SGwendal Grignou static const struct sx_common_reg_default * 71702d83fa6SGwendal Grignou sx9360_get_default_reg(struct device *dev, int idx, 71802d83fa6SGwendal Grignou struct sx_common_reg_default *reg_def) 71902d83fa6SGwendal Grignou { 72002d83fa6SGwendal Grignou u32 raw = 0, pos = 0; 72102d83fa6SGwendal Grignou int ret; 72202d83fa6SGwendal Grignou 72302d83fa6SGwendal Grignou memcpy(reg_def, &sx9360_default_regs[idx], sizeof(*reg_def)); 72402d83fa6SGwendal Grignou switch (reg_def->reg) { 72502d83fa6SGwendal Grignou case SX9360_REG_AFE_PARAM0_PHR: 72602d83fa6SGwendal Grignou case SX9360_REG_AFE_PARAM0_PHM: 72702d83fa6SGwendal Grignou ret = device_property_read_u32(dev, "semtech,resolution", &raw); 72802d83fa6SGwendal Grignou if (ret) 72902d83fa6SGwendal Grignou break; 73002d83fa6SGwendal Grignou 73102d83fa6SGwendal Grignou raw = ilog2(raw) - 3; 73202d83fa6SGwendal Grignou 73302d83fa6SGwendal Grignou reg_def->def &= ~SX9360_REG_AFE_PARAM0_RESOLUTION_MASK; 73402d83fa6SGwendal Grignou reg_def->def |= FIELD_PREP(SX9360_REG_AFE_PARAM0_RESOLUTION_MASK, raw); 73502d83fa6SGwendal Grignou break; 73602d83fa6SGwendal Grignou case SX9360_REG_PROX_CTRL0_PHR: 73702d83fa6SGwendal Grignou case SX9360_REG_PROX_CTRL0_PHM: 73802d83fa6SGwendal Grignou ret = device_property_read_u32(dev, "semtech,proxraw-strength", &raw); 73902d83fa6SGwendal Grignou if (ret) 74002d83fa6SGwendal Grignou break; 74102d83fa6SGwendal Grignou 74202d83fa6SGwendal Grignou reg_def->def &= ~SX9360_REG_PROX_CTRL0_RAWFILT_MASK; 74302d83fa6SGwendal Grignou reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL0_RAWFILT_MASK, raw); 74402d83fa6SGwendal Grignou break; 74502d83fa6SGwendal Grignou case SX9360_REG_PROX_CTRL3: 74602d83fa6SGwendal Grignou ret = device_property_read_u32(dev, "semtech,avg-pos-strength", 74702d83fa6SGwendal Grignou &pos); 74802d83fa6SGwendal Grignou if (ret) 74902d83fa6SGwendal Grignou break; 75002d83fa6SGwendal Grignou 75102d83fa6SGwendal Grignou /* Powers of 2, except for a gap between 16 and 64 */ 75202d83fa6SGwendal Grignou raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3); 75302d83fa6SGwendal Grignou reg_def->def &= ~SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK; 75402d83fa6SGwendal Grignou reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK, raw); 75502d83fa6SGwendal Grignou break; 75602d83fa6SGwendal Grignou } 75702d83fa6SGwendal Grignou 75802d83fa6SGwendal Grignou return reg_def; 75902d83fa6SGwendal Grignou } 76002d83fa6SGwendal Grignou 7611cdb4c47SGwendal Grignou static int sx9360_check_whoami(struct device *dev, struct iio_dev *indio_dev) 7621cdb4c47SGwendal Grignou { 7631cdb4c47SGwendal Grignou /* 7641cdb4c47SGwendal Grignou * Only one sensor for this driver. Assuming the device tree 7651cdb4c47SGwendal Grignou * is correct, just set the sensor name. 7661cdb4c47SGwendal Grignou */ 7671cdb4c47SGwendal Grignou indio_dev->name = "sx9360"; 7681cdb4c47SGwendal Grignou return 0; 7691cdb4c47SGwendal Grignou } 7701cdb4c47SGwendal Grignou 7711cdb4c47SGwendal Grignou static const struct sx_common_chip_info sx9360_chip_info = { 7721cdb4c47SGwendal Grignou .reg_stat = SX9360_REG_STAT, 7731cdb4c47SGwendal Grignou .reg_irq_msk = SX9360_REG_IRQ_MSK, 7741cdb4c47SGwendal Grignou .reg_enable_chan = SX9360_REG_GNRL_CTRL0, 7751cdb4c47SGwendal Grignou .reg_reset = SX9360_REG_RESET, 7761cdb4c47SGwendal Grignou 7771cdb4c47SGwendal Grignou .mask_enable_chan = SX9360_REG_GNRL_CTRL0_PHEN_MASK, 778*19d32860SJongpil Jung .stat_offset = 2, 7791cdb4c47SGwendal Grignou .num_channels = SX9360_NUM_CHANNELS, 78002d83fa6SGwendal Grignou .num_default_regs = ARRAY_SIZE(sx9360_default_regs), 7811cdb4c47SGwendal Grignou 7821cdb4c47SGwendal Grignou .ops = { 7831cdb4c47SGwendal Grignou .read_prox_data = sx9360_read_prox_data, 7841cdb4c47SGwendal Grignou .check_whoami = sx9360_check_whoami, 7851cdb4c47SGwendal Grignou .init_compensation = sx9360_init_compensation, 7861cdb4c47SGwendal Grignou .wait_for_sample = sx9360_wait_for_sample, 78702d83fa6SGwendal Grignou .get_default_reg = sx9360_get_default_reg, 7881cdb4c47SGwendal Grignou }, 7891cdb4c47SGwendal Grignou 7901cdb4c47SGwendal Grignou .iio_channels = sx9360_channels, 7911cdb4c47SGwendal Grignou .num_iio_channels = ARRAY_SIZE(sx9360_channels), 7921cdb4c47SGwendal Grignou .iio_info = { 7931cdb4c47SGwendal Grignou .read_raw = sx9360_read_raw, 7941cdb4c47SGwendal Grignou .read_avail = sx9360_read_avail, 7951cdb4c47SGwendal Grignou .read_label = sx9360_read_label, 7961cdb4c47SGwendal Grignou .read_event_value = sx9360_read_event_val, 7971cdb4c47SGwendal Grignou .write_event_value = sx9360_write_event_val, 7981cdb4c47SGwendal Grignou .write_raw = sx9360_write_raw, 7991cdb4c47SGwendal Grignou .read_event_config = sx_common_read_event_config, 8001cdb4c47SGwendal Grignou .write_event_config = sx_common_write_event_config, 8011cdb4c47SGwendal Grignou }, 8021cdb4c47SGwendal Grignou }; 8031cdb4c47SGwendal Grignou 8041cdb4c47SGwendal Grignou static int sx9360_probe(struct i2c_client *client) 8051cdb4c47SGwendal Grignou { 8061cdb4c47SGwendal Grignou return sx_common_probe(client, &sx9360_chip_info, &sx9360_regmap_config); 8071cdb4c47SGwendal Grignou } 8081cdb4c47SGwendal Grignou 8091cdb4c47SGwendal Grignou static int __maybe_unused sx9360_suspend(struct device *dev) 8101cdb4c47SGwendal Grignou { 8111cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 8121cdb4c47SGwendal Grignou unsigned int regval; 8131cdb4c47SGwendal Grignou int ret; 8141cdb4c47SGwendal Grignou 8151cdb4c47SGwendal Grignou disable_irq_nosync(data->client->irq); 8161cdb4c47SGwendal Grignou 8171cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 8181cdb4c47SGwendal Grignou ret = regmap_read(data->regmap, SX9360_REG_GNRL_CTRL0, ®val); 8191cdb4c47SGwendal Grignou 8201cdb4c47SGwendal Grignou data->suspend_ctrl = 8211cdb4c47SGwendal Grignou FIELD_GET(SX9360_REG_GNRL_CTRL0_PHEN_MASK, regval); 8221cdb4c47SGwendal Grignou 8231cdb4c47SGwendal Grignou if (ret < 0) 8241cdb4c47SGwendal Grignou goto out; 8251cdb4c47SGwendal Grignou 8261cdb4c47SGwendal Grignou /* Disable all phases, send the device to sleep. */ 8271cdb4c47SGwendal Grignou ret = regmap_write(data->regmap, SX9360_REG_GNRL_CTRL0, 0); 8281cdb4c47SGwendal Grignou 8291cdb4c47SGwendal Grignou out: 8301cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 8311cdb4c47SGwendal Grignou return ret; 8321cdb4c47SGwendal Grignou } 8331cdb4c47SGwendal Grignou 8341cdb4c47SGwendal Grignou static int __maybe_unused sx9360_resume(struct device *dev) 8351cdb4c47SGwendal Grignou { 8361cdb4c47SGwendal Grignou struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 8371cdb4c47SGwendal Grignou int ret; 8381cdb4c47SGwendal Grignou 8391cdb4c47SGwendal Grignou mutex_lock(&data->mutex); 8401cdb4c47SGwendal Grignou ret = regmap_update_bits(data->regmap, SX9360_REG_GNRL_CTRL0, 8411cdb4c47SGwendal Grignou SX9360_REG_GNRL_CTRL0_PHEN_MASK, 8421cdb4c47SGwendal Grignou data->suspend_ctrl); 8431cdb4c47SGwendal Grignou mutex_unlock(&data->mutex); 8441cdb4c47SGwendal Grignou if (ret) 8451cdb4c47SGwendal Grignou return ret; 8461cdb4c47SGwendal Grignou 8471cdb4c47SGwendal Grignou enable_irq(data->client->irq); 8481cdb4c47SGwendal Grignou return 0; 8491cdb4c47SGwendal Grignou } 8501cdb4c47SGwendal Grignou 8511cdb4c47SGwendal Grignou static SIMPLE_DEV_PM_OPS(sx9360_pm_ops, sx9360_suspend, sx9360_resume); 8521cdb4c47SGwendal Grignou 8531cdb4c47SGwendal Grignou static const struct acpi_device_id sx9360_acpi_match[] = { 8541cdb4c47SGwendal Grignou { "STH9360", SX9360_WHOAMI_VALUE }, 8551cdb4c47SGwendal Grignou { } 8561cdb4c47SGwendal Grignou }; 8571cdb4c47SGwendal Grignou MODULE_DEVICE_TABLE(acpi, sx9360_acpi_match); 8581cdb4c47SGwendal Grignou 8591cdb4c47SGwendal Grignou static const struct of_device_id sx9360_of_match[] = { 8601cdb4c47SGwendal Grignou { .compatible = "semtech,sx9360", (void *)SX9360_WHOAMI_VALUE }, 8611cdb4c47SGwendal Grignou { } 8621cdb4c47SGwendal Grignou }; 8631cdb4c47SGwendal Grignou MODULE_DEVICE_TABLE(of, sx9360_of_match); 8641cdb4c47SGwendal Grignou 8651cdb4c47SGwendal Grignou static const struct i2c_device_id sx9360_id[] = { 8661cdb4c47SGwendal Grignou {"sx9360", SX9360_WHOAMI_VALUE }, 8671cdb4c47SGwendal Grignou { } 8681cdb4c47SGwendal Grignou }; 8691cdb4c47SGwendal Grignou MODULE_DEVICE_TABLE(i2c, sx9360_id); 8701cdb4c47SGwendal Grignou 8711cdb4c47SGwendal Grignou static struct i2c_driver sx9360_driver = { 8721cdb4c47SGwendal Grignou .driver = { 8731cdb4c47SGwendal Grignou .name = "sx9360", 8741cdb4c47SGwendal Grignou .acpi_match_table = sx9360_acpi_match, 8751cdb4c47SGwendal Grignou .of_match_table = sx9360_of_match, 8761cdb4c47SGwendal Grignou .pm = &sx9360_pm_ops, 8771cdb4c47SGwendal Grignou 8781cdb4c47SGwendal Grignou /* 8791cdb4c47SGwendal Grignou * Lots of i2c transfers in probe + over 200 ms waiting in 8801cdb4c47SGwendal Grignou * sx9360_init_compensation() mean a slow probe; prefer async 8811cdb4c47SGwendal Grignou * so we don't delay boot if we're builtin to the kernel. 8821cdb4c47SGwendal Grignou */ 8831cdb4c47SGwendal Grignou .probe_type = PROBE_PREFER_ASYNCHRONOUS, 8841cdb4c47SGwendal Grignou }, 8851cdb4c47SGwendal Grignou .probe_new = sx9360_probe, 8861cdb4c47SGwendal Grignou .id_table = sx9360_id, 8871cdb4c47SGwendal Grignou }; 8881cdb4c47SGwendal Grignou module_i2c_driver(sx9360_driver); 8891cdb4c47SGwendal Grignou 8901cdb4c47SGwendal Grignou MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>"); 8911cdb4c47SGwendal Grignou MODULE_DESCRIPTION("Driver for Semtech SX9360 proximity sensor"); 8921cdb4c47SGwendal Grignou MODULE_LICENSE("GPL v2"); 8931cdb4c47SGwendal Grignou MODULE_IMPORT_NS(SEMTECH_PROX); 894