1121354b2SSong Qiang // SPDX-License-Identifier: GPL-2.0 2121354b2SSong Qiang /* 3121354b2SSong Qiang * PNI RM3100 3-axis geomagnetic sensor driver core. 4121354b2SSong Qiang * 5121354b2SSong Qiang * Copyright (C) 2018 Song Qiang <songqiang1304521@gmail.com> 6121354b2SSong Qiang * 7121354b2SSong Qiang * User Manual available at 8121354b2SSong Qiang * <https://www.pnicorp.com/download/rm3100-user-manual/> 9121354b2SSong Qiang * 10121354b2SSong Qiang * TODO: event generation, pm. 11121354b2SSong Qiang */ 12121354b2SSong Qiang 13121354b2SSong Qiang #include <linux/delay.h> 14121354b2SSong Qiang #include <linux/interrupt.h> 15121354b2SSong Qiang #include <linux/module.h> 16121354b2SSong Qiang #include <linux/slab.h> 17121354b2SSong Qiang 18121354b2SSong Qiang #include <linux/iio/buffer.h> 19121354b2SSong Qiang #include <linux/iio/iio.h> 20121354b2SSong Qiang #include <linux/iio/sysfs.h> 21121354b2SSong Qiang #include <linux/iio/trigger.h> 22121354b2SSong Qiang #include <linux/iio/triggered_buffer.h> 23121354b2SSong Qiang #include <linux/iio/trigger_consumer.h> 24121354b2SSong Qiang 25dfe3da0bSAndy Shevchenko #include <asm/unaligned.h> 26dfe3da0bSAndy Shevchenko 27121354b2SSong Qiang #include "rm3100.h" 28121354b2SSong Qiang 29121354b2SSong Qiang /* Cycle Count Registers. */ 30121354b2SSong Qiang #define RM3100_REG_CC_X 0x05 31121354b2SSong Qiang #define RM3100_REG_CC_Y 0x07 32121354b2SSong Qiang #define RM3100_REG_CC_Z 0x09 33121354b2SSong Qiang 34121354b2SSong Qiang /* Poll Measurement Mode register. */ 35121354b2SSong Qiang #define RM3100_REG_POLL 0x00 36121354b2SSong Qiang #define RM3100_POLL_X BIT(4) 37121354b2SSong Qiang #define RM3100_POLL_Y BIT(5) 38121354b2SSong Qiang #define RM3100_POLL_Z BIT(6) 39121354b2SSong Qiang 40121354b2SSong Qiang /* Continuous Measurement Mode register. */ 41121354b2SSong Qiang #define RM3100_REG_CMM 0x01 42121354b2SSong Qiang #define RM3100_CMM_START BIT(0) 43121354b2SSong Qiang #define RM3100_CMM_X BIT(4) 44121354b2SSong Qiang #define RM3100_CMM_Y BIT(5) 45121354b2SSong Qiang #define RM3100_CMM_Z BIT(6) 46121354b2SSong Qiang 47121354b2SSong Qiang /* TiMe Rate Configuration register. */ 48121354b2SSong Qiang #define RM3100_REG_TMRC 0x0B 49121354b2SSong Qiang #define RM3100_TMRC_OFFSET 0x92 50121354b2SSong Qiang 51121354b2SSong Qiang /* Result Status register. */ 52121354b2SSong Qiang #define RM3100_REG_STATUS 0x34 53121354b2SSong Qiang #define RM3100_STATUS_DRDY BIT(7) 54121354b2SSong Qiang 55121354b2SSong Qiang /* Measurement result registers. */ 56121354b2SSong Qiang #define RM3100_REG_MX2 0x24 57121354b2SSong Qiang #define RM3100_REG_MY2 0x27 58121354b2SSong Qiang #define RM3100_REG_MZ2 0x2a 59121354b2SSong Qiang 60121354b2SSong Qiang #define RM3100_W_REG_START RM3100_REG_POLL 61121354b2SSong Qiang #define RM3100_W_REG_END RM3100_REG_TMRC 62121354b2SSong Qiang #define RM3100_R_REG_START RM3100_REG_POLL 63121354b2SSong Qiang #define RM3100_R_REG_END RM3100_REG_STATUS 64121354b2SSong Qiang #define RM3100_V_REG_START RM3100_REG_POLL 65121354b2SSong Qiang #define RM3100_V_REG_END RM3100_REG_STATUS 66121354b2SSong Qiang 67121354b2SSong Qiang /* 68121354b2SSong Qiang * This is computed by hand, is the sum of channel storage bits and padding 69121354b2SSong Qiang * bits, which is 4+4+4+12=24 in here. 70121354b2SSong Qiang */ 71121354b2SSong Qiang #define RM3100_SCAN_BYTES 24 72121354b2SSong Qiang 73121354b2SSong Qiang #define RM3100_CMM_AXIS_SHIFT 4 74121354b2SSong Qiang 75121354b2SSong Qiang struct rm3100_data { 76121354b2SSong Qiang struct regmap *regmap; 77121354b2SSong Qiang struct completion measuring_done; 78121354b2SSong Qiang bool use_interrupt; 79121354b2SSong Qiang int conversion_time; 80121354b2SSong Qiang int scale; 81121354b2SSong Qiang u8 buffer[RM3100_SCAN_BYTES]; 82121354b2SSong Qiang struct iio_trigger *drdy_trig; 83121354b2SSong Qiang 84121354b2SSong Qiang /* 85121354b2SSong Qiang * This lock is for protecting the consistency of series of i2c 86121354b2SSong Qiang * operations, that is, to make sure a measurement process will 87121354b2SSong Qiang * not be interrupted by a set frequency operation, which should 88121354b2SSong Qiang * be taken where a series of i2c operation starts, released where 89121354b2SSong Qiang * the operation ends. 90121354b2SSong Qiang */ 91121354b2SSong Qiang struct mutex lock; 92121354b2SSong Qiang }; 93121354b2SSong Qiang 94121354b2SSong Qiang static const struct regmap_range rm3100_readable_ranges[] = { 95121354b2SSong Qiang regmap_reg_range(RM3100_R_REG_START, RM3100_R_REG_END), 96121354b2SSong Qiang }; 97121354b2SSong Qiang 98121354b2SSong Qiang const struct regmap_access_table rm3100_readable_table = { 99121354b2SSong Qiang .yes_ranges = rm3100_readable_ranges, 100121354b2SSong Qiang .n_yes_ranges = ARRAY_SIZE(rm3100_readable_ranges), 101121354b2SSong Qiang }; 102121354b2SSong Qiang EXPORT_SYMBOL_GPL(rm3100_readable_table); 103121354b2SSong Qiang 104121354b2SSong Qiang static const struct regmap_range rm3100_writable_ranges[] = { 105121354b2SSong Qiang regmap_reg_range(RM3100_W_REG_START, RM3100_W_REG_END), 106121354b2SSong Qiang }; 107121354b2SSong Qiang 108121354b2SSong Qiang const struct regmap_access_table rm3100_writable_table = { 109121354b2SSong Qiang .yes_ranges = rm3100_writable_ranges, 110121354b2SSong Qiang .n_yes_ranges = ARRAY_SIZE(rm3100_writable_ranges), 111121354b2SSong Qiang }; 112121354b2SSong Qiang EXPORT_SYMBOL_GPL(rm3100_writable_table); 113121354b2SSong Qiang 114121354b2SSong Qiang static const struct regmap_range rm3100_volatile_ranges[] = { 115121354b2SSong Qiang regmap_reg_range(RM3100_V_REG_START, RM3100_V_REG_END), 116121354b2SSong Qiang }; 117121354b2SSong Qiang 118121354b2SSong Qiang const struct regmap_access_table rm3100_volatile_table = { 119121354b2SSong Qiang .yes_ranges = rm3100_volatile_ranges, 120121354b2SSong Qiang .n_yes_ranges = ARRAY_SIZE(rm3100_volatile_ranges), 121121354b2SSong Qiang }; 122121354b2SSong Qiang EXPORT_SYMBOL_GPL(rm3100_volatile_table); 123121354b2SSong Qiang 124121354b2SSong Qiang static irqreturn_t rm3100_thread_fn(int irq, void *d) 125121354b2SSong Qiang { 126121354b2SSong Qiang struct iio_dev *indio_dev = d; 127121354b2SSong Qiang struct rm3100_data *data = iio_priv(indio_dev); 128121354b2SSong Qiang 129121354b2SSong Qiang /* 130121354b2SSong Qiang * Write operation to any register or read operation 131121354b2SSong Qiang * to first byte of results will clear the interrupt. 132121354b2SSong Qiang */ 133121354b2SSong Qiang regmap_write(data->regmap, RM3100_REG_POLL, 0); 134121354b2SSong Qiang 135121354b2SSong Qiang return IRQ_HANDLED; 136121354b2SSong Qiang } 137121354b2SSong Qiang 138121354b2SSong Qiang static irqreturn_t rm3100_irq_handler(int irq, void *d) 139121354b2SSong Qiang { 140121354b2SSong Qiang struct iio_dev *indio_dev = d; 141121354b2SSong Qiang struct rm3100_data *data = iio_priv(indio_dev); 142121354b2SSong Qiang 143121354b2SSong Qiang switch (indio_dev->currentmode) { 144121354b2SSong Qiang case INDIO_DIRECT_MODE: 145121354b2SSong Qiang complete(&data->measuring_done); 146121354b2SSong Qiang break; 147121354b2SSong Qiang case INDIO_BUFFER_TRIGGERED: 148121354b2SSong Qiang iio_trigger_poll(data->drdy_trig); 149121354b2SSong Qiang break; 150121354b2SSong Qiang default: 151121354b2SSong Qiang dev_err(indio_dev->dev.parent, 152121354b2SSong Qiang "device mode out of control, current mode: %d", 153121354b2SSong Qiang indio_dev->currentmode); 154121354b2SSong Qiang } 155121354b2SSong Qiang 156121354b2SSong Qiang return IRQ_WAKE_THREAD; 157121354b2SSong Qiang } 158121354b2SSong Qiang 159121354b2SSong Qiang static int rm3100_wait_measurement(struct rm3100_data *data) 160121354b2SSong Qiang { 161121354b2SSong Qiang struct regmap *regmap = data->regmap; 162121354b2SSong Qiang unsigned int val; 163121354b2SSong Qiang int tries = 20; 164121354b2SSong Qiang int ret; 165121354b2SSong Qiang 166121354b2SSong Qiang /* 167121354b2SSong Qiang * A read cycle of 400kbits i2c bus is about 20us, plus the time 168121354b2SSong Qiang * used for scheduling, a read cycle of fast mode of this device 169121354b2SSong Qiang * can reach 1.7ms, it may be possible for data to arrive just 170121354b2SSong Qiang * after we check the RM3100_REG_STATUS. In this case, irq_handler is 171121354b2SSong Qiang * called before measuring_done is reinitialized, it will wait 172121354b2SSong Qiang * forever for data that has already been ready. 173121354b2SSong Qiang * Reinitialize measuring_done before looking up makes sure we 174121354b2SSong Qiang * will always capture interrupt no matter when it happens. 175121354b2SSong Qiang */ 176121354b2SSong Qiang if (data->use_interrupt) 177121354b2SSong Qiang reinit_completion(&data->measuring_done); 178121354b2SSong Qiang 179121354b2SSong Qiang ret = regmap_read(regmap, RM3100_REG_STATUS, &val); 180121354b2SSong Qiang if (ret < 0) 181121354b2SSong Qiang return ret; 182121354b2SSong Qiang 183121354b2SSong Qiang if ((val & RM3100_STATUS_DRDY) != RM3100_STATUS_DRDY) { 184121354b2SSong Qiang if (data->use_interrupt) { 185121354b2SSong Qiang ret = wait_for_completion_timeout(&data->measuring_done, 186121354b2SSong Qiang msecs_to_jiffies(data->conversion_time)); 187121354b2SSong Qiang if (!ret) 188121354b2SSong Qiang return -ETIMEDOUT; 189121354b2SSong Qiang } else { 190121354b2SSong Qiang do { 191121354b2SSong Qiang usleep_range(1000, 5000); 192121354b2SSong Qiang 193121354b2SSong Qiang ret = regmap_read(regmap, RM3100_REG_STATUS, 194121354b2SSong Qiang &val); 195121354b2SSong Qiang if (ret < 0) 196121354b2SSong Qiang return ret; 197121354b2SSong Qiang 198121354b2SSong Qiang if (val & RM3100_STATUS_DRDY) 199121354b2SSong Qiang break; 200121354b2SSong Qiang } while (--tries); 201121354b2SSong Qiang if (!tries) 202121354b2SSong Qiang return -ETIMEDOUT; 203121354b2SSong Qiang } 204121354b2SSong Qiang } 205121354b2SSong Qiang return 0; 206121354b2SSong Qiang } 207121354b2SSong Qiang 208121354b2SSong Qiang static int rm3100_read_mag(struct rm3100_data *data, int idx, int *val) 209121354b2SSong Qiang { 210121354b2SSong Qiang struct regmap *regmap = data->regmap; 211121354b2SSong Qiang u8 buffer[3]; 212121354b2SSong Qiang int ret; 213121354b2SSong Qiang 214121354b2SSong Qiang mutex_lock(&data->lock); 215121354b2SSong Qiang ret = regmap_write(regmap, RM3100_REG_POLL, BIT(4 + idx)); 216121354b2SSong Qiang if (ret < 0) 217121354b2SSong Qiang goto unlock_return; 218121354b2SSong Qiang 219121354b2SSong Qiang ret = rm3100_wait_measurement(data); 220121354b2SSong Qiang if (ret < 0) 221121354b2SSong Qiang goto unlock_return; 222121354b2SSong Qiang 223121354b2SSong Qiang ret = regmap_bulk_read(regmap, RM3100_REG_MX2 + 3 * idx, buffer, 3); 224121354b2SSong Qiang if (ret < 0) 225121354b2SSong Qiang goto unlock_return; 226121354b2SSong Qiang mutex_unlock(&data->lock); 227121354b2SSong Qiang 228dfe3da0bSAndy Shevchenko *val = sign_extend32(get_unaligned_be24(&buffer[0]), 23); 229121354b2SSong Qiang 230121354b2SSong Qiang return IIO_VAL_INT; 231121354b2SSong Qiang 232121354b2SSong Qiang unlock_return: 233121354b2SSong Qiang mutex_unlock(&data->lock); 234121354b2SSong Qiang return ret; 235121354b2SSong Qiang } 236121354b2SSong Qiang 237121354b2SSong Qiang #define RM3100_CHANNEL(axis, idx) \ 238121354b2SSong Qiang { \ 239121354b2SSong Qiang .type = IIO_MAGN, \ 240121354b2SSong Qiang .modified = 1, \ 241121354b2SSong Qiang .channel2 = IIO_MOD_##axis, \ 242121354b2SSong Qiang .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 243121354b2SSong Qiang .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 244121354b2SSong Qiang BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 245121354b2SSong Qiang .scan_index = idx, \ 246121354b2SSong Qiang .scan_type = { \ 247121354b2SSong Qiang .sign = 's', \ 248121354b2SSong Qiang .realbits = 24, \ 249121354b2SSong Qiang .storagebits = 32, \ 250121354b2SSong Qiang .shift = 8, \ 251121354b2SSong Qiang .endianness = IIO_BE, \ 252121354b2SSong Qiang }, \ 253121354b2SSong Qiang } 254121354b2SSong Qiang 255121354b2SSong Qiang static const struct iio_chan_spec rm3100_channels[] = { 256121354b2SSong Qiang RM3100_CHANNEL(X, 0), 257121354b2SSong Qiang RM3100_CHANNEL(Y, 1), 258121354b2SSong Qiang RM3100_CHANNEL(Z, 2), 259121354b2SSong Qiang IIO_CHAN_SOFT_TIMESTAMP(3), 260121354b2SSong Qiang }; 261121354b2SSong Qiang 262121354b2SSong Qiang static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 263121354b2SSong Qiang "600 300 150 75 37 18 9 4.5 2.3 1.2 0.6 0.3 0.015 0.075" 264121354b2SSong Qiang ); 265121354b2SSong Qiang 266121354b2SSong Qiang static struct attribute *rm3100_attributes[] = { 267121354b2SSong Qiang &iio_const_attr_sampling_frequency_available.dev_attr.attr, 268121354b2SSong Qiang NULL, 269121354b2SSong Qiang }; 270121354b2SSong Qiang 271121354b2SSong Qiang static const struct attribute_group rm3100_attribute_group = { 272121354b2SSong Qiang .attrs = rm3100_attributes, 273121354b2SSong Qiang }; 274121354b2SSong Qiang 275121354b2SSong Qiang #define RM3100_SAMP_NUM 14 276121354b2SSong Qiang 277121354b2SSong Qiang /* 278121354b2SSong Qiang * Frequency : rm3100_samp_rates[][0].rm3100_samp_rates[][1]Hz. 279121354b2SSong Qiang * Time between reading: rm3100_sam_rates[][2]ms. 280121354b2SSong Qiang * The first one is actually 1.7ms. 281121354b2SSong Qiang */ 282121354b2SSong Qiang static const int rm3100_samp_rates[RM3100_SAMP_NUM][3] = { 283121354b2SSong Qiang {600, 0, 2}, {300, 0, 3}, {150, 0, 7}, {75, 0, 13}, {37, 0, 27}, 284121354b2SSong Qiang {18, 0, 55}, {9, 0, 110}, {4, 500000, 220}, {2, 300000, 440}, 285121354b2SSong Qiang {1, 200000, 800}, {0, 600000, 1600}, {0, 300000, 3300}, 286121354b2SSong Qiang {0, 15000, 6700}, {0, 75000, 13000} 287121354b2SSong Qiang }; 288121354b2SSong Qiang 289121354b2SSong Qiang static int rm3100_get_samp_freq(struct rm3100_data *data, int *val, int *val2) 290121354b2SSong Qiang { 291121354b2SSong Qiang unsigned int tmp; 292121354b2SSong Qiang int ret; 293121354b2SSong Qiang 294121354b2SSong Qiang mutex_lock(&data->lock); 295121354b2SSong Qiang ret = regmap_read(data->regmap, RM3100_REG_TMRC, &tmp); 296121354b2SSong Qiang mutex_unlock(&data->lock); 297121354b2SSong Qiang if (ret < 0) 298121354b2SSong Qiang return ret; 299121354b2SSong Qiang *val = rm3100_samp_rates[tmp - RM3100_TMRC_OFFSET][0]; 300121354b2SSong Qiang *val2 = rm3100_samp_rates[tmp - RM3100_TMRC_OFFSET][1]; 301121354b2SSong Qiang 302121354b2SSong Qiang return IIO_VAL_INT_PLUS_MICRO; 303121354b2SSong Qiang } 304121354b2SSong Qiang 305121354b2SSong Qiang static int rm3100_set_cycle_count(struct rm3100_data *data, int val) 306121354b2SSong Qiang { 307121354b2SSong Qiang int ret; 308121354b2SSong Qiang u8 i; 309121354b2SSong Qiang 310121354b2SSong Qiang for (i = 0; i < 3; i++) { 311121354b2SSong Qiang ret = regmap_write(data->regmap, RM3100_REG_CC_X + 2 * i, val); 312121354b2SSong Qiang if (ret < 0) 313121354b2SSong Qiang return ret; 314121354b2SSong Qiang } 315121354b2SSong Qiang 316121354b2SSong Qiang /* 317121354b2SSong Qiang * The scale of this sensor depends on the cycle count value, these 318121354b2SSong Qiang * three values are corresponding to the cycle count value 50, 100, 319121354b2SSong Qiang * 200. scale = output / gain * 10^4. 320121354b2SSong Qiang */ 321121354b2SSong Qiang switch (val) { 322121354b2SSong Qiang case 50: 323121354b2SSong Qiang data->scale = 500; 324121354b2SSong Qiang break; 325121354b2SSong Qiang case 100: 326121354b2SSong Qiang data->scale = 263; 327121354b2SSong Qiang break; 328121354b2SSong Qiang /* 329121354b2SSong Qiang * case 200: 330121354b2SSong Qiang * This function will never be called by users' code, so here we 331121354b2SSong Qiang * assume that it will never get a wrong parameter. 332121354b2SSong Qiang */ 333121354b2SSong Qiang default: 334121354b2SSong Qiang data->scale = 133; 335121354b2SSong Qiang } 336121354b2SSong Qiang 337121354b2SSong Qiang return 0; 338121354b2SSong Qiang } 339121354b2SSong Qiang 340121354b2SSong Qiang static int rm3100_set_samp_freq(struct iio_dev *indio_dev, int val, int val2) 341121354b2SSong Qiang { 342121354b2SSong Qiang struct rm3100_data *data = iio_priv(indio_dev); 343121354b2SSong Qiang struct regmap *regmap = data->regmap; 344121354b2SSong Qiang unsigned int cycle_count; 345121354b2SSong Qiang int ret; 346121354b2SSong Qiang int i; 347121354b2SSong Qiang 348121354b2SSong Qiang mutex_lock(&data->lock); 349121354b2SSong Qiang /* All cycle count registers use the same value. */ 350121354b2SSong Qiang ret = regmap_read(regmap, RM3100_REG_CC_X, &cycle_count); 351121354b2SSong Qiang if (ret < 0) 352121354b2SSong Qiang goto unlock_return; 353121354b2SSong Qiang 354121354b2SSong Qiang for (i = 0; i < RM3100_SAMP_NUM; i++) { 355121354b2SSong Qiang if (val == rm3100_samp_rates[i][0] && 356121354b2SSong Qiang val2 == rm3100_samp_rates[i][1]) 357121354b2SSong Qiang break; 358121354b2SSong Qiang } 359121354b2SSong Qiang if (i == RM3100_SAMP_NUM) { 360121354b2SSong Qiang ret = -EINVAL; 361121354b2SSong Qiang goto unlock_return; 362121354b2SSong Qiang } 363121354b2SSong Qiang 364121354b2SSong Qiang ret = regmap_write(regmap, RM3100_REG_TMRC, i + RM3100_TMRC_OFFSET); 365121354b2SSong Qiang if (ret < 0) 366121354b2SSong Qiang goto unlock_return; 367121354b2SSong Qiang 368121354b2SSong Qiang /* Checking if cycle count registers need changing. */ 369121354b2SSong Qiang if (val == 600 && cycle_count == 200) { 370121354b2SSong Qiang ret = rm3100_set_cycle_count(data, 100); 371121354b2SSong Qiang if (ret < 0) 372121354b2SSong Qiang goto unlock_return; 373121354b2SSong Qiang } else if (val != 600 && cycle_count == 100) { 374121354b2SSong Qiang ret = rm3100_set_cycle_count(data, 200); 375121354b2SSong Qiang if (ret < 0) 376121354b2SSong Qiang goto unlock_return; 377121354b2SSong Qiang } 378121354b2SSong Qiang 379121354b2SSong Qiang if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) { 380121354b2SSong Qiang /* Writing TMRC registers requires CMM reset. */ 381121354b2SSong Qiang ret = regmap_write(regmap, RM3100_REG_CMM, 0); 382121354b2SSong Qiang if (ret < 0) 383121354b2SSong Qiang goto unlock_return; 384121354b2SSong Qiang ret = regmap_write(data->regmap, RM3100_REG_CMM, 385121354b2SSong Qiang (*indio_dev->active_scan_mask & 0x7) << 386121354b2SSong Qiang RM3100_CMM_AXIS_SHIFT | RM3100_CMM_START); 387121354b2SSong Qiang if (ret < 0) 388121354b2SSong Qiang goto unlock_return; 389121354b2SSong Qiang } 390121354b2SSong Qiang mutex_unlock(&data->lock); 391121354b2SSong Qiang 392121354b2SSong Qiang data->conversion_time = rm3100_samp_rates[i][2] * 2; 393121354b2SSong Qiang return 0; 394121354b2SSong Qiang 395121354b2SSong Qiang unlock_return: 396121354b2SSong Qiang mutex_unlock(&data->lock); 397121354b2SSong Qiang return ret; 398121354b2SSong Qiang } 399121354b2SSong Qiang 400121354b2SSong Qiang static int rm3100_read_raw(struct iio_dev *indio_dev, 401121354b2SSong Qiang const struct iio_chan_spec *chan, 402121354b2SSong Qiang int *val, int *val2, long mask) 403121354b2SSong Qiang { 404121354b2SSong Qiang struct rm3100_data *data = iio_priv(indio_dev); 405121354b2SSong Qiang int ret; 406121354b2SSong Qiang 407121354b2SSong Qiang switch (mask) { 408121354b2SSong Qiang case IIO_CHAN_INFO_RAW: 409121354b2SSong Qiang ret = iio_device_claim_direct_mode(indio_dev); 410121354b2SSong Qiang if (ret < 0) 411121354b2SSong Qiang return ret; 412121354b2SSong Qiang 413121354b2SSong Qiang ret = rm3100_read_mag(data, chan->scan_index, val); 414121354b2SSong Qiang iio_device_release_direct_mode(indio_dev); 415121354b2SSong Qiang 416121354b2SSong Qiang return ret; 417121354b2SSong Qiang case IIO_CHAN_INFO_SCALE: 418121354b2SSong Qiang *val = 0; 419121354b2SSong Qiang *val2 = data->scale; 420121354b2SSong Qiang 421121354b2SSong Qiang return IIO_VAL_INT_PLUS_MICRO; 422121354b2SSong Qiang case IIO_CHAN_INFO_SAMP_FREQ: 423121354b2SSong Qiang return rm3100_get_samp_freq(data, val, val2); 424121354b2SSong Qiang default: 425121354b2SSong Qiang return -EINVAL; 426121354b2SSong Qiang } 427121354b2SSong Qiang } 428121354b2SSong Qiang 429121354b2SSong Qiang static int rm3100_write_raw(struct iio_dev *indio_dev, 430121354b2SSong Qiang struct iio_chan_spec const *chan, 431121354b2SSong Qiang int val, int val2, long mask) 432121354b2SSong Qiang { 433121354b2SSong Qiang switch (mask) { 434121354b2SSong Qiang case IIO_CHAN_INFO_SAMP_FREQ: 435121354b2SSong Qiang return rm3100_set_samp_freq(indio_dev, val, val2); 436121354b2SSong Qiang default: 437121354b2SSong Qiang return -EINVAL; 438121354b2SSong Qiang } 439121354b2SSong Qiang } 440121354b2SSong Qiang 441121354b2SSong Qiang static const struct iio_info rm3100_info = { 442121354b2SSong Qiang .attrs = &rm3100_attribute_group, 443121354b2SSong Qiang .read_raw = rm3100_read_raw, 444121354b2SSong Qiang .write_raw = rm3100_write_raw, 445121354b2SSong Qiang }; 446121354b2SSong Qiang 447121354b2SSong Qiang static int rm3100_buffer_preenable(struct iio_dev *indio_dev) 448121354b2SSong Qiang { 449121354b2SSong Qiang struct rm3100_data *data = iio_priv(indio_dev); 450121354b2SSong Qiang 451121354b2SSong Qiang /* Starting channels enabled. */ 452121354b2SSong Qiang return regmap_write(data->regmap, RM3100_REG_CMM, 453121354b2SSong Qiang (*indio_dev->active_scan_mask & 0x7) << RM3100_CMM_AXIS_SHIFT | 454121354b2SSong Qiang RM3100_CMM_START); 455121354b2SSong Qiang } 456121354b2SSong Qiang 457121354b2SSong Qiang static int rm3100_buffer_postdisable(struct iio_dev *indio_dev) 458121354b2SSong Qiang { 459121354b2SSong Qiang struct rm3100_data *data = iio_priv(indio_dev); 460121354b2SSong Qiang 461121354b2SSong Qiang return regmap_write(data->regmap, RM3100_REG_CMM, 0); 462121354b2SSong Qiang } 463121354b2SSong Qiang 464121354b2SSong Qiang static const struct iio_buffer_setup_ops rm3100_buffer_ops = { 465121354b2SSong Qiang .preenable = rm3100_buffer_preenable, 466121354b2SSong Qiang .postdisable = rm3100_buffer_postdisable, 467121354b2SSong Qiang }; 468121354b2SSong Qiang 469121354b2SSong Qiang static irqreturn_t rm3100_trigger_handler(int irq, void *p) 470121354b2SSong Qiang { 471121354b2SSong Qiang struct iio_poll_func *pf = p; 472121354b2SSong Qiang struct iio_dev *indio_dev = pf->indio_dev; 473121354b2SSong Qiang unsigned long scan_mask = *indio_dev->active_scan_mask; 474121354b2SSong Qiang unsigned int mask_len = indio_dev->masklength; 475121354b2SSong Qiang struct rm3100_data *data = iio_priv(indio_dev); 476121354b2SSong Qiang struct regmap *regmap = data->regmap; 477121354b2SSong Qiang int ret, i, bit; 478121354b2SSong Qiang 479121354b2SSong Qiang mutex_lock(&data->lock); 480121354b2SSong Qiang switch (scan_mask) { 481121354b2SSong Qiang case BIT(0) | BIT(1) | BIT(2): 482121354b2SSong Qiang ret = regmap_bulk_read(regmap, RM3100_REG_MX2, data->buffer, 9); 483121354b2SSong Qiang mutex_unlock(&data->lock); 484121354b2SSong Qiang if (ret < 0) 485121354b2SSong Qiang goto done; 486121354b2SSong Qiang /* Convert XXXYYYZZZxxx to XXXxYYYxZZZx. x for paddings. */ 487121354b2SSong Qiang for (i = 2; i > 0; i--) 488121354b2SSong Qiang memmove(data->buffer + i * 4, data->buffer + i * 3, 3); 489121354b2SSong Qiang break; 490121354b2SSong Qiang case BIT(0) | BIT(1): 491121354b2SSong Qiang ret = regmap_bulk_read(regmap, RM3100_REG_MX2, data->buffer, 6); 492121354b2SSong Qiang mutex_unlock(&data->lock); 493121354b2SSong Qiang if (ret < 0) 494121354b2SSong Qiang goto done; 495121354b2SSong Qiang memmove(data->buffer + 4, data->buffer + 3, 3); 496121354b2SSong Qiang break; 497121354b2SSong Qiang case BIT(1) | BIT(2): 498121354b2SSong Qiang ret = regmap_bulk_read(regmap, RM3100_REG_MY2, data->buffer, 6); 499121354b2SSong Qiang mutex_unlock(&data->lock); 500121354b2SSong Qiang if (ret < 0) 501121354b2SSong Qiang goto done; 502121354b2SSong Qiang memmove(data->buffer + 4, data->buffer + 3, 3); 503121354b2SSong Qiang break; 504121354b2SSong Qiang case BIT(0) | BIT(2): 505121354b2SSong Qiang ret = regmap_bulk_read(regmap, RM3100_REG_MX2, data->buffer, 9); 506121354b2SSong Qiang mutex_unlock(&data->lock); 507121354b2SSong Qiang if (ret < 0) 508121354b2SSong Qiang goto done; 509121354b2SSong Qiang memmove(data->buffer + 4, data->buffer + 6, 3); 510121354b2SSong Qiang break; 511121354b2SSong Qiang default: 512121354b2SSong Qiang for_each_set_bit(bit, &scan_mask, mask_len) { 513121354b2SSong Qiang ret = regmap_bulk_read(regmap, RM3100_REG_MX2 + 3 * bit, 514121354b2SSong Qiang data->buffer, 3); 515121354b2SSong Qiang if (ret < 0) { 516121354b2SSong Qiang mutex_unlock(&data->lock); 517121354b2SSong Qiang goto done; 518121354b2SSong Qiang } 519121354b2SSong Qiang } 520121354b2SSong Qiang mutex_unlock(&data->lock); 521121354b2SSong Qiang } 522121354b2SSong Qiang /* 523121354b2SSong Qiang * Always using the same buffer so that we wouldn't need to set the 524121354b2SSong Qiang * paddings to 0 in case of leaking any data. 525121354b2SSong Qiang */ 526121354b2SSong Qiang iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 527121354b2SSong Qiang pf->timestamp); 528121354b2SSong Qiang done: 529121354b2SSong Qiang iio_trigger_notify_done(indio_dev->trig); 530121354b2SSong Qiang 531121354b2SSong Qiang return IRQ_HANDLED; 532121354b2SSong Qiang } 533121354b2SSong Qiang 534121354b2SSong Qiang int rm3100_common_probe(struct device *dev, struct regmap *regmap, int irq) 535121354b2SSong Qiang { 536121354b2SSong Qiang struct iio_dev *indio_dev; 537121354b2SSong Qiang struct rm3100_data *data; 538121354b2SSong Qiang unsigned int tmp; 539121354b2SSong Qiang int ret; 540121354b2SSong Qiang 541121354b2SSong Qiang indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 542121354b2SSong Qiang if (!indio_dev) 543121354b2SSong Qiang return -ENOMEM; 544121354b2SSong Qiang 545121354b2SSong Qiang data = iio_priv(indio_dev); 546121354b2SSong Qiang data->regmap = regmap; 547121354b2SSong Qiang 548121354b2SSong Qiang mutex_init(&data->lock); 549121354b2SSong Qiang 550121354b2SSong Qiang indio_dev->name = "rm3100"; 551121354b2SSong Qiang indio_dev->info = &rm3100_info; 552121354b2SSong Qiang indio_dev->channels = rm3100_channels; 553121354b2SSong Qiang indio_dev->num_channels = ARRAY_SIZE(rm3100_channels); 554121354b2SSong Qiang indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; 555121354b2SSong Qiang indio_dev->currentmode = INDIO_DIRECT_MODE; 556121354b2SSong Qiang 557121354b2SSong Qiang if (!irq) 558121354b2SSong Qiang data->use_interrupt = false; 559121354b2SSong Qiang else { 560121354b2SSong Qiang data->use_interrupt = true; 561121354b2SSong Qiang 562121354b2SSong Qiang init_completion(&data->measuring_done); 563121354b2SSong Qiang ret = devm_request_threaded_irq(dev, 564121354b2SSong Qiang irq, 565121354b2SSong Qiang rm3100_irq_handler, 566121354b2SSong Qiang rm3100_thread_fn, 567121354b2SSong Qiang IRQF_TRIGGER_HIGH | 568121354b2SSong Qiang IRQF_ONESHOT, 569121354b2SSong Qiang indio_dev->name, 570121354b2SSong Qiang indio_dev); 571121354b2SSong Qiang if (ret < 0) { 572121354b2SSong Qiang dev_err(dev, "request irq line failed.\n"); 573121354b2SSong Qiang return ret; 574121354b2SSong Qiang } 575121354b2SSong Qiang 576121354b2SSong Qiang data->drdy_trig = devm_iio_trigger_alloc(dev, "%s-drdy%d", 577121354b2SSong Qiang indio_dev->name, 578*15ea2878SJonathan Cameron iio_device_id(indio_dev)); 579121354b2SSong Qiang if (!data->drdy_trig) 580121354b2SSong Qiang return -ENOMEM; 581121354b2SSong Qiang 582121354b2SSong Qiang ret = devm_iio_trigger_register(dev, data->drdy_trig); 583121354b2SSong Qiang if (ret < 0) 584121354b2SSong Qiang return ret; 585121354b2SSong Qiang } 586121354b2SSong Qiang 587121354b2SSong Qiang ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 588121354b2SSong Qiang &iio_pollfunc_store_time, 589121354b2SSong Qiang rm3100_trigger_handler, 590121354b2SSong Qiang &rm3100_buffer_ops); 591121354b2SSong Qiang if (ret < 0) 592121354b2SSong Qiang return ret; 593121354b2SSong Qiang 594121354b2SSong Qiang ret = regmap_read(regmap, RM3100_REG_TMRC, &tmp); 595121354b2SSong Qiang if (ret < 0) 596121354b2SSong Qiang return ret; 597121354b2SSong Qiang /* Initializing max wait time, which is double conversion time. */ 598121354b2SSong Qiang data->conversion_time = rm3100_samp_rates[tmp - RM3100_TMRC_OFFSET][2] 599121354b2SSong Qiang * 2; 600121354b2SSong Qiang 601121354b2SSong Qiang /* Cycle count values may not be what we want. */ 602121354b2SSong Qiang if ((tmp - RM3100_TMRC_OFFSET) == 0) 603121354b2SSong Qiang rm3100_set_cycle_count(data, 100); 604121354b2SSong Qiang else 605121354b2SSong Qiang rm3100_set_cycle_count(data, 200); 606121354b2SSong Qiang 607121354b2SSong Qiang return devm_iio_device_register(dev, indio_dev); 608121354b2SSong Qiang } 609121354b2SSong Qiang EXPORT_SYMBOL_GPL(rm3100_common_probe); 610121354b2SSong Qiang 611121354b2SSong Qiang MODULE_AUTHOR("Song Qiang <songqiang1304521@gmail.com>"); 612121354b2SSong Qiang MODULE_DESCRIPTION("PNI RM3100 3-axis magnetometer i2c driver"); 613121354b2SSong Qiang MODULE_LICENSE("GPL v2"); 614