1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Support for QST QMC6308 3-Axis Magnetic Sensor on I2C bus. 4 * 5 * Copyright (C) 2026 Jorijn van der Graaf <jorijnvdgraaf@catcrafts.net> 6 * 7 * Datasheet available at 8 * <https://qstcorp.com/upload/pdf/202202/13-52-15%20QMC6308%20Datasheet%20Rev.%20F(1).pdf> 9 */ 10 11 #include <linux/array_size.h> 12 #include <linux/bitfield.h> 13 #include <linux/bits.h> 14 #include <linux/cleanup.h> 15 #include <linux/delay.h> 16 #include <linux/dev_printk.h> 17 #include <linux/err.h> 18 #include <linux/i2c.h> 19 #include <linux/module.h> 20 #include <linux/mutex.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/time.h> 25 #include <linux/types.h> 26 27 #include <asm/byteorder.h> 28 29 #include <linux/iio/iio.h> 30 31 #define QMC6308_REG_ID 0x00 32 #define QMC6308_REG_X_LSB 0x01 33 #define QMC6308_REG_STATUS 0x09 34 #define QMC6308_REG_CTRL1 0x0A 35 #define QMC6308_REG_CTRL2 0x0B 36 #define QMC6308_REG_CTRL3 0x0D 37 #define QMC6308_REG_CTRL4 0x29 38 39 #define QMC6308_CHIP_ID 0x80 40 41 /* Control register 1 */ 42 #define QMC6308_MODE_MASK GENMASK(1, 0) 43 #define QMC6308_ODR_MASK GENMASK(3, 2) 44 #define QMC6308_OSR1_MASK GENMASK(5, 4) 45 #define QMC6308_OSR2_MASK GENMASK(7, 6) 46 47 #define QMC6308_MODE_SUSPEND 0x00 48 #define QMC6308_MODE_NORMAL 0x01 49 50 #define QMC6308_ODR_10HZ 0x00 51 #define QMC6308_ODR_50HZ 0x01 52 #define QMC6308_ODR_100HZ 0x02 53 #define QMC6308_ODR_200HZ 0x03 54 55 #define QMC6308_OSR1_8 0x00 56 #define QMC6308_OSR1_4 0x01 57 #define QMC6308_OSR1_2 0x02 58 #define QMC6308_OSR1_1 0x03 59 60 /* Control register 2 */ 61 #define QMC6308_SET_RESET_MASK GENMASK(1, 0) 62 #define QMC6308_RNG_MASK GENMASK(3, 2) 63 #define QMC6308_SELF_TEST BIT(6) 64 #define QMC6308_SOFT_RST BIT(7) 65 66 #define QMC6308_SET_RESET_ON 0x00 67 68 #define QMC6308_RNG_30G 0x00 69 #define QMC6308_RNG_12G 0x01 70 #define QMC6308_RNG_8G 0x02 71 #define QMC6308_RNG_2G 0x03 72 73 /* Status register */ 74 #define QMC6308_STATUS_DRDY BIT(0) 75 #define QMC6308_STATUS_OVFL BIT(1) 76 77 /* Power-on completion time (datasheet Table 7) */ 78 #define QMC6308_POR_US 250 79 80 #define QMC6308_AUTOSUSPEND_DELAY_MS 500 81 82 struct qmc6308_data { 83 struct regmap *regmap; 84 /* Protect data->range/odr/osr and serialize measurements */ 85 struct mutex mutex; 86 struct iio_mount_matrix orientation; 87 u8 range; 88 u8 odr; 89 u8 osr; 90 }; 91 92 enum qmc6308_axis { 93 QMC6308_AXIS_X, 94 QMC6308_AXIS_Y, 95 QMC6308_AXIS_Z, 96 }; 97 98 static const int qmc6308_odr_avail[] = { 99 [QMC6308_ODR_10HZ] = 10, 100 [QMC6308_ODR_50HZ] = 50, 101 [QMC6308_ODR_100HZ] = 100, 102 [QMC6308_ODR_200HZ] = 200, 103 }; 104 105 static const int qmc6308_osr1_avail[] = { 106 [QMC6308_OSR1_8] = 8, 107 [QMC6308_OSR1_4] = 4, 108 [QMC6308_OSR1_2] = 2, 109 [QMC6308_OSR1_1] = 1, 110 }; 111 112 /* 113 * Sensitivity is 1000/2500/3750/15000 LSB/Gauss for the 114 * +-30/12/8/2 Gauss ranges respectively. 115 */ 116 static const int qmc6308_scales[][2] = { 117 [QMC6308_RNG_30G] = { 0, 1000000 }, 118 [QMC6308_RNG_12G] = { 0, 400000 }, 119 [QMC6308_RNG_8G] = { 0, 266667 }, 120 [QMC6308_RNG_2G] = { 0, 66667 }, 121 }; 122 123 static int qmc6308_set_mode(struct qmc6308_data *data, unsigned int mode) 124 { 125 return regmap_update_bits(data->regmap, QMC6308_REG_CTRL1, 126 QMC6308_MODE_MASK, 127 FIELD_PREP(QMC6308_MODE_MASK, mode)); 128 } 129 130 static int qmc6308_take_measurement(struct iio_dev *indio_dev, int index, 131 int *val) 132 { 133 struct qmc6308_data *data = iio_priv(indio_dev); 134 struct device *dev = regmap_get_device(data->regmap); 135 unsigned int status; 136 __le16 buf[3]; 137 int ret; 138 139 PM_RUNTIME_ACQUIRE_AUTOSUSPEND(dev, pm); 140 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 141 if (ret) { 142 dev_err(dev, "Failed to power on (%d)\n", ret); 143 return ret; 144 } 145 146 guard(mutex)(&data->mutex); 147 148 /* 149 * Reading the status register clears DRDY, which is why the poll 150 * and the data read stay under one mutex hold. A runtime resume 151 * clears DRDY too, so a sample converted before the last suspend 152 * is never returned here. 153 * 154 * The timeout is 50ms of headroom over the slowest ODR (10Hz). 155 */ 156 ret = regmap_read_poll_timeout(data->regmap, QMC6308_REG_STATUS, 157 status, (status & QMC6308_STATUS_DRDY), 158 2 * USEC_PER_MSEC, 159 150 * USEC_PER_MSEC); 160 if (ret) 161 return ret; 162 163 ret = regmap_bulk_read(data->regmap, QMC6308_REG_X_LSB, buf, 164 sizeof(buf)); 165 if (ret) 166 return ret; 167 168 if (status & QMC6308_STATUS_OVFL) 169 return -ERANGE; 170 171 *val = (s16)le16_to_cpu(buf[index]); 172 173 return 0; 174 } 175 176 static int qmc6308_read_raw(struct iio_dev *indio_dev, 177 const struct iio_chan_spec *chan, 178 int *val, int *val2, long mask) 179 { 180 struct qmc6308_data *data = iio_priv(indio_dev); 181 int ret; 182 183 switch (mask) { 184 case IIO_CHAN_INFO_RAW: 185 ret = qmc6308_take_measurement(indio_dev, chan->address, val); 186 if (ret) 187 return ret; 188 return IIO_VAL_INT; 189 case IIO_CHAN_INFO_SCALE: { 190 guard(mutex)(&data->mutex); 191 192 *val = qmc6308_scales[data->range][0]; 193 *val2 = qmc6308_scales[data->range][1]; 194 195 return IIO_VAL_INT_PLUS_NANO; 196 } 197 case IIO_CHAN_INFO_SAMP_FREQ: { 198 guard(mutex)(&data->mutex); 199 200 *val = qmc6308_odr_avail[data->odr]; 201 202 return IIO_VAL_INT; 203 } 204 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { 205 guard(mutex)(&data->mutex); 206 207 *val = qmc6308_osr1_avail[data->osr]; 208 209 return IIO_VAL_INT; 210 } 211 default: 212 return -EINVAL; 213 } 214 } 215 216 static int qmc6308_write_raw(struct iio_dev *indio_dev, 217 const struct iio_chan_spec *chan, 218 int val, int val2, long mask) 219 { 220 struct qmc6308_data *data = iio_priv(indio_dev); 221 unsigned int status; 222 unsigned int i; 223 int ret; 224 225 switch (mask) { 226 case IIO_CHAN_INFO_SCALE: { 227 if (val != 0) 228 return -EINVAL; 229 230 for (i = 0; i < ARRAY_SIZE(qmc6308_scales); i++) { 231 if (val2 == qmc6308_scales[i][1]) 232 break; 233 } 234 if (i == ARRAY_SIZE(qmc6308_scales)) 235 return -EINVAL; 236 237 guard(mutex)(&data->mutex); 238 239 ret = regmap_update_bits(data->regmap, QMC6308_REG_CTRL2, 240 QMC6308_RNG_MASK, 241 FIELD_PREP(QMC6308_RNG_MASK, i)); 242 if (ret) 243 return ret; 244 245 data->range = i; 246 247 /* 248 * The data registers still hold (and DRDY still 249 * advertises) a sample converted at the previous range; 250 * discard it so that a read does not pair old-range data 251 * with the new scale. A conversion already in flight may 252 * still complete at the old range, so this narrows the 253 * window rather than closing it. The range change itself 254 * took effect, so only log a failure here: an error 255 * would mislead userspace about an effective write. 256 */ 257 ret = regmap_read(data->regmap, QMC6308_REG_STATUS, 258 &status); 259 if (ret) 260 dev_warn(regmap_get_device(data->regmap), 261 "Failed to discard stale sample (%d)\n", ret); 262 263 return 0; 264 } 265 case IIO_CHAN_INFO_SAMP_FREQ: { 266 for (i = 0; i < ARRAY_SIZE(qmc6308_odr_avail); i++) { 267 if (val == qmc6308_odr_avail[i]) 268 break; 269 } 270 if (i == ARRAY_SIZE(qmc6308_odr_avail)) 271 return -EINVAL; 272 273 guard(mutex)(&data->mutex); 274 275 ret = regmap_update_bits(data->regmap, QMC6308_REG_CTRL1, 276 QMC6308_ODR_MASK, 277 FIELD_PREP(QMC6308_ODR_MASK, i)); 278 if (ret) 279 return ret; 280 281 data->odr = i; 282 283 return 0; 284 } 285 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { 286 for (i = 0; i < ARRAY_SIZE(qmc6308_osr1_avail); i++) { 287 if (val == qmc6308_osr1_avail[i]) 288 break; 289 } 290 if (i == ARRAY_SIZE(qmc6308_osr1_avail)) 291 return -EINVAL; 292 293 guard(mutex)(&data->mutex); 294 295 ret = regmap_update_bits(data->regmap, QMC6308_REG_CTRL1, 296 QMC6308_OSR1_MASK, 297 FIELD_PREP(QMC6308_OSR1_MASK, i)); 298 if (ret) 299 return ret; 300 301 data->osr = i; 302 303 return 0; 304 } 305 default: 306 return -EINVAL; 307 } 308 } 309 310 static int qmc6308_read_avail(struct iio_dev *indio_dev, 311 struct iio_chan_spec const *chan, 312 const int **vals, int *type, int *length, 313 long mask) 314 { 315 switch (mask) { 316 case IIO_CHAN_INFO_SAMP_FREQ: 317 *vals = qmc6308_odr_avail; 318 *type = IIO_VAL_INT; 319 *length = ARRAY_SIZE(qmc6308_odr_avail); 320 return IIO_AVAIL_LIST; 321 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 322 *vals = qmc6308_osr1_avail; 323 *type = IIO_VAL_INT; 324 *length = ARRAY_SIZE(qmc6308_osr1_avail); 325 return IIO_AVAIL_LIST; 326 case IIO_CHAN_INFO_SCALE: 327 *vals = (const int *)qmc6308_scales; 328 *type = IIO_VAL_INT_PLUS_NANO; 329 *length = ARRAY_SIZE(qmc6308_scales) * 2; 330 return IIO_AVAIL_LIST; 331 default: 332 return -EINVAL; 333 } 334 } 335 336 static int qmc6308_write_raw_get_fmt(struct iio_dev *indio_dev, 337 struct iio_chan_spec const *chan, 338 long mask) 339 { 340 switch (mask) { 341 case IIO_CHAN_INFO_SCALE: 342 return IIO_VAL_INT_PLUS_NANO; 343 default: 344 return IIO_VAL_INT; 345 } 346 } 347 348 static const struct iio_mount_matrix * 349 qmc6308_get_mount_matrix(const struct iio_dev *indio_dev, 350 const struct iio_chan_spec *chan) 351 { 352 struct qmc6308_data *data = iio_priv(indio_dev); 353 354 return &data->orientation; 355 } 356 357 static const struct iio_chan_spec_ext_info qmc6308_ext_info[] = { 358 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, qmc6308_get_mount_matrix), 359 { } 360 }; 361 362 static const struct iio_info qmc6308_info = { 363 .read_raw = qmc6308_read_raw, 364 .write_raw = qmc6308_write_raw, 365 .read_avail = qmc6308_read_avail, 366 .write_raw_get_fmt = qmc6308_write_raw_get_fmt, 367 }; 368 369 static int qmc6308_init(struct qmc6308_data *data) 370 { 371 struct regmap *map = data->regmap; 372 unsigned int reg; 373 int ret; 374 375 ret = regmap_read(map, QMC6308_REG_ID, ®); 376 if (ret) 377 return ret; 378 379 /* Allow unknown IDs so that fallback compatibles work */ 380 if (reg != QMC6308_CHIP_ID) 381 dev_warn(regmap_get_device(map), 382 "Unknown chip id: 0x%02x, continuing\n", reg); 383 384 /* The SOFT_RST bit is not auto-cleared and must be written back 0 */ 385 ret = regmap_write(map, QMC6308_REG_CTRL2, QMC6308_SOFT_RST); 386 if (ret) 387 return ret; 388 389 /* 390 * The datasheet gives no soft-reset completion figure; reuse the 391 * power-on time as a conservative bound. 392 */ 393 fsleep(QMC6308_POR_US); 394 395 data->range = QMC6308_RNG_30G; 396 data->odr = QMC6308_ODR_50HZ; 397 data->osr = QMC6308_OSR1_8; 398 399 ret = regmap_write(map, QMC6308_REG_CTRL2, 400 FIELD_PREP(QMC6308_SET_RESET_MASK, 401 QMC6308_SET_RESET_ON) | 402 FIELD_PREP(QMC6308_RNG_MASK, data->range)); 403 if (ret) 404 return ret; 405 406 /* OSR2 (second-stage filter) set to its power-on default of 0 */ 407 return regmap_write(map, QMC6308_REG_CTRL1, 408 FIELD_PREP(QMC6308_MODE_MASK, 409 QMC6308_MODE_NORMAL) | 410 FIELD_PREP(QMC6308_ODR_MASK, data->odr) | 411 FIELD_PREP(QMC6308_OSR1_MASK, data->osr) | 412 FIELD_PREP(QMC6308_OSR2_MASK, 0)); 413 } 414 415 static void qmc6308_power_down_action(void *priv) 416 { 417 struct qmc6308_data *data = priv; 418 419 if (!pm_runtime_status_suspended(regmap_get_device(data->regmap))) 420 qmc6308_set_mode(data, QMC6308_MODE_SUSPEND); 421 } 422 423 static bool qmc6308_volatile_reg(struct device *dev, unsigned int reg) 424 { 425 return reg >= QMC6308_REG_X_LSB && reg <= QMC6308_REG_STATUS; 426 } 427 428 static bool qmc6308_writable_reg(struct device *dev, unsigned int reg) 429 { 430 switch (reg) { 431 case QMC6308_REG_CTRL1: 432 case QMC6308_REG_CTRL2: 433 case QMC6308_REG_CTRL3: 434 case QMC6308_REG_CTRL4: 435 return true; 436 default: 437 return false; 438 } 439 } 440 441 static const struct regmap_config qmc6308_regmap_config = { 442 .reg_bits = 8, 443 .val_bits = 8, 444 .max_register = QMC6308_REG_CTRL4, 445 .cache_type = REGCACHE_MAPLE, 446 .volatile_reg = qmc6308_volatile_reg, 447 .writeable_reg = qmc6308_writable_reg, 448 }; 449 450 #define QMC6308_CHANNEL(_axis) \ 451 { \ 452 .type = IIO_MAGN, \ 453 .modified = 1, \ 454 .channel2 = IIO_MOD_##_axis, \ 455 .address = QMC6308_AXIS_##_axis, \ 456 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 457 .info_mask_shared_by_type = \ 458 BIT(IIO_CHAN_INFO_SCALE) | \ 459 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 460 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 461 .info_mask_shared_by_type_available = \ 462 BIT(IIO_CHAN_INFO_SCALE) | \ 463 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 464 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 465 .ext_info = qmc6308_ext_info, \ 466 } 467 468 static const struct iio_chan_spec qmc6308_channels[] = { 469 QMC6308_CHANNEL(X), 470 QMC6308_CHANNEL(Y), 471 QMC6308_CHANNEL(Z), 472 }; 473 474 static int qmc6308_probe(struct i2c_client *client) 475 { 476 struct device *dev = &client->dev; 477 struct qmc6308_data *data; 478 struct iio_dev *indio_dev; 479 struct regmap *map; 480 int ret; 481 482 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 483 if (!indio_dev) 484 return -ENOMEM; 485 486 i2c_set_clientdata(client, indio_dev); 487 488 map = devm_regmap_init_i2c(client, &qmc6308_regmap_config); 489 if (IS_ERR(map)) 490 return dev_err_probe(dev, PTR_ERR(map), 491 "regmap initialization failed\n"); 492 493 ret = devm_regulator_get_enable(dev, "vdd"); 494 if (ret) 495 return dev_err_probe(dev, ret, 496 "Failed to enable VDD regulator\n"); 497 498 fsleep(QMC6308_POR_US); 499 500 data = iio_priv(indio_dev); 501 data->regmap = map; 502 503 ret = devm_mutex_init(dev, &data->mutex); 504 if (ret) 505 return ret; 506 507 ret = iio_read_mount_matrix(dev, &data->orientation); 508 if (ret) 509 return dev_err_probe(dev, ret, 510 "Failed to read mount matrix\n"); 511 512 indio_dev->name = "qmc6308"; 513 indio_dev->info = &qmc6308_info; 514 indio_dev->channels = qmc6308_channels; 515 indio_dev->num_channels = ARRAY_SIZE(qmc6308_channels); 516 indio_dev->modes = INDIO_DIRECT_MODE; 517 518 ret = qmc6308_init(data); 519 if (ret) 520 return dev_err_probe(dev, ret, "qmc6308 init failed\n"); 521 522 ret = pm_runtime_set_active(dev); 523 if (ret) 524 return ret; 525 526 ret = devm_add_action_or_reset(dev, qmc6308_power_down_action, data); 527 if (ret) 528 return ret; 529 530 pm_runtime_use_autosuspend(dev); 531 pm_runtime_set_autosuspend_delay(dev, QMC6308_AUTOSUSPEND_DELAY_MS); 532 533 ret = devm_pm_runtime_enable(dev); 534 if (ret) 535 return ret; 536 537 return devm_iio_device_register(dev, indio_dev); 538 } 539 540 static int qmc6308_runtime_suspend(struct device *dev) 541 { 542 struct iio_dev *indio_dev = dev_get_drvdata(dev); 543 struct qmc6308_data *data = iio_priv(indio_dev); 544 545 return qmc6308_set_mode(data, QMC6308_MODE_SUSPEND); 546 } 547 548 static int qmc6308_runtime_resume(struct device *dev) 549 { 550 struct iio_dev *indio_dev = dev_get_drvdata(dev); 551 struct qmc6308_data *data = iio_priv(indio_dev); 552 unsigned int status; 553 int ret; 554 555 ret = qmc6308_set_mode(data, QMC6308_MODE_NORMAL); 556 if (ret) 557 return ret; 558 559 /* 560 * DRDY may still be set for a sample converted before the last 561 * suspend; reading the status register clears it so the next 562 * measurement waits for fresh data. 563 */ 564 ret = regmap_read(data->regmap, QMC6308_REG_STATUS, &status); 565 if (ret) { 566 /* Best effort to leave the chip in a consistent state */ 567 qmc6308_set_mode(data, QMC6308_MODE_SUSPEND); 568 } 569 570 return ret; 571 } 572 573 static DEFINE_RUNTIME_DEV_PM_OPS(qmc6308_pm_ops, qmc6308_runtime_suspend, 574 qmc6308_runtime_resume, NULL); 575 576 static const struct of_device_id qmc6308_match[] = { 577 { .compatible = "qstcorp,qmc6308" }, 578 { } 579 }; 580 MODULE_DEVICE_TABLE(of, qmc6308_match); 581 582 static const struct i2c_device_id qmc6308_id[] = { 583 { .name = "qmc6308" }, 584 { } 585 }; 586 MODULE_DEVICE_TABLE(i2c, qmc6308_id); 587 588 static struct i2c_driver qmc6308_driver = { 589 .driver = { 590 .name = "qmc6308", 591 .of_match_table = qmc6308_match, 592 .pm = pm_ptr(&qmc6308_pm_ops), 593 }, 594 .id_table = qmc6308_id, 595 .probe = qmc6308_probe, 596 }; 597 module_i2c_driver(qmc6308_driver); 598 599 MODULE_DESCRIPTION("QST QMC6308 3-Axis Magnetic Sensor driver"); 600 MODULE_AUTHOR("Jorijn van der Graaf <jorijnvdgraaf@catcrafts.net>"); 601 MODULE_LICENSE("GPL"); 602