1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 /* 3 * Support for QST QMC5883L 3-Axis Magnetic Sensor on I2C bus. 4 * 5 * Copyright (C) 2026 Siratul Islam <siratul.islam@linux.dev> 6 * 7 * Datasheet available at 8 * <https://www.qstcorp.com/upload/pdf/202512/13-52-04%20QMC5883L%20Datasheet%20Rev.%20B.pdf> 9 */ 10 11 #include <linux/array_size.h> 12 #include <linux/bitfield.h> 13 #include <linux/bits.h> 14 #include <linux/cleanup.h> 15 #include <linux/delay.h> 16 #include <linux/dev_printk.h> 17 #include <linux/err.h> 18 #include <linux/i2c.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/time.h> 24 #include <linux/types.h> 25 26 #include <asm/byteorder.h> 27 28 #include <linux/iio/iio.h> 29 30 #define QMC5883L_REG_X_LSB 0x00 31 #define QMC5883L_REG_STATUS1 0x06 32 #define QMC5883L_REG_CTRL1 0x09 33 #define QMC5883L_REG_CTRL2 0x0A 34 #define QMC5883L_REG_SET_RESET 0x0B 35 #define QMC5883L_REG_ID 0x0D 36 37 #define QMC5883L_CHIP_ID 0xFF 38 39 #define QMC5883L_MODE_MASK GENMASK(1, 0) 40 #define QMC5883L_ODR_MASK GENMASK(3, 2) 41 #define QMC5883L_RNG_MASK GENMASK(5, 4) 42 #define QMC5883L_OSR_MASK GENMASK(7, 6) 43 44 #define QMC5883L_MODE_STANDBY 0x00 45 #define QMC5883L_MODE_CONT 0x01 46 47 #define QMC5883L_ODR_10HZ 0x00 48 #define QMC5883L_ODR_50HZ 0x01 49 #define QMC5883L_ODR_100HZ 0x02 50 #define QMC5883L_ODR_200HZ 0x03 51 52 #define QMC5883L_RNG_2G 0x00 53 #define QMC5883L_RNG_8G 0x01 54 55 #define QMC5883L_OSR_512 0x00 56 #define QMC5883L_OSR_256 0x01 57 #define QMC5883L_OSR_128 0x02 58 #define QMC5883L_OSR_64 0x03 59 60 #define QMC5883L_STATUS_DRDY BIT(0) 61 #define QMC5883L_STATUS_OVL BIT(1) 62 63 #define QMC5883L_SET_RESET_VAL BIT(0) 64 #define QMC5883L_INT_DISABLE BIT(0) 65 #define QMC5883L_SOFT_RESET BIT(7) 66 67 #define QMC5883L_PORT_US 350 68 69 struct qmc5883l_data { 70 struct regmap *regmap; 71 /* 72 * Protect data->range/odr/osr. 73 * Protect poll and read during measurement. 74 */ 75 struct mutex mutex; 76 u8 range; 77 u8 odr; 78 u8 osr; 79 }; 80 81 enum qmc5883l_chan { 82 QMC5883L_AXIS_X, 83 QMC5883L_AXIS_Y, 84 QMC5883L_AXIS_Z, 85 }; 86 87 static const int qmc5883l_odr_avail[] = { 10, 50, 100, 200 }; 88 89 static const int qmc5883l_osr_avail[] = { 512, 256, 128, 64 }; 90 91 static const int qmc5883l_scales[][2] = { 92 [QMC5883L_RNG_2G] = { 0, 83333 }, 93 [QMC5883L_RNG_8G] = { 0, 333333 }, 94 }; 95 96 static int qmc5883l_take_measurement(struct iio_dev *indio_dev, int index, 97 int *val) 98 { 99 struct qmc5883l_data *data = iio_priv(indio_dev); 100 struct regmap *map = data->regmap; 101 unsigned int status; 102 __le16 buf[3]; 103 int ret; 104 105 guard(mutex) (&data->mutex); 106 107 /* 50ms headroom over the slowest ODR (10Hz) */ 108 ret = regmap_read_poll_timeout(map, QMC5883L_REG_STATUS1, 109 status, (status & QMC5883L_STATUS_DRDY), 110 2 * USEC_PER_MSEC, 150 * USEC_PER_MSEC); 111 if (ret) 112 return ret; 113 114 ret = regmap_bulk_read(map, QMC5883L_REG_X_LSB, buf, sizeof(buf)); 115 if (ret) 116 return ret; 117 118 if (status & QMC5883L_STATUS_OVL) 119 return -ERANGE; 120 121 *val = (s16)le16_to_cpu(buf[index]); 122 123 return 0; 124 } 125 126 static int qmc5883l_read_raw(struct iio_dev *indio_dev, 127 const struct iio_chan_spec *chan, 128 int *val, int *val2, long mask) 129 { 130 struct qmc5883l_data *data = iio_priv(indio_dev); 131 int ret; 132 133 switch (mask) { 134 case IIO_CHAN_INFO_RAW: 135 ret = qmc5883l_take_measurement(indio_dev, chan->address, val); 136 if (ret) 137 return ret; 138 return IIO_VAL_INT; 139 case IIO_CHAN_INFO_SCALE: { 140 guard(mutex)(&data->mutex); 141 142 *val = qmc5883l_scales[data->range][0]; 143 *val2 = qmc5883l_scales[data->range][1]; 144 145 return IIO_VAL_INT_PLUS_NANO; 146 } 147 case IIO_CHAN_INFO_SAMP_FREQ: { 148 guard(mutex)(&data->mutex); 149 150 switch (data->odr) { 151 case QMC5883L_ODR_200HZ: 152 *val = 200; 153 break; 154 case QMC5883L_ODR_100HZ: 155 *val = 100; 156 break; 157 case QMC5883L_ODR_50HZ: 158 *val = 50; 159 break; 160 case QMC5883L_ODR_10HZ: 161 *val = 10; 162 break; 163 default: 164 return -EINVAL; 165 } 166 167 return IIO_VAL_INT; 168 } 169 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { 170 guard(mutex)(&data->mutex); 171 172 switch (data->osr) { 173 case QMC5883L_OSR_64: 174 *val = 64; 175 break; 176 case QMC5883L_OSR_128: 177 *val = 128; 178 break; 179 case QMC5883L_OSR_256: 180 *val = 256; 181 break; 182 case QMC5883L_OSR_512: 183 *val = 512; 184 break; 185 default: 186 return -EINVAL; 187 } 188 189 return IIO_VAL_INT; 190 } 191 default: 192 return -EINVAL; 193 } 194 } 195 196 static int qmc5883l_write_raw(struct iio_dev *indio_dev, 197 const struct iio_chan_spec *chan, 198 int val, int val2, long mask) 199 { 200 struct qmc5883l_data *data = iio_priv(indio_dev); 201 u8 rng, osr, odr; 202 int ret; 203 204 switch (mask) { 205 case IIO_CHAN_INFO_SCALE: { 206 if (val != 0) 207 return -EINVAL; 208 209 if (val2 == qmc5883l_scales[QMC5883L_RNG_2G][1]) 210 rng = QMC5883L_RNG_2G; 211 else if (val2 == qmc5883l_scales[QMC5883L_RNG_8G][1]) 212 rng = QMC5883L_RNG_8G; 213 else 214 return -EINVAL; 215 216 guard(mutex)(&data->mutex); 217 218 ret = regmap_update_bits(data->regmap, QMC5883L_REG_CTRL1, 219 QMC5883L_RNG_MASK, 220 FIELD_PREP(QMC5883L_RNG_MASK, rng)); 221 if (ret) 222 return ret; 223 224 data->range = rng; 225 226 return 0; 227 } 228 case IIO_CHAN_INFO_SAMP_FREQ: { 229 switch (val) { 230 case 200: 231 odr = QMC5883L_ODR_200HZ; 232 break; 233 case 100: 234 odr = QMC5883L_ODR_100HZ; 235 break; 236 case 50: 237 odr = QMC5883L_ODR_50HZ; 238 break; 239 case 10: 240 odr = QMC5883L_ODR_10HZ; 241 break; 242 default: 243 return -EINVAL; 244 } 245 246 guard(mutex)(&data->mutex); 247 248 ret = regmap_update_bits(data->regmap, QMC5883L_REG_CTRL1, 249 QMC5883L_ODR_MASK, 250 FIELD_PREP(QMC5883L_ODR_MASK, odr)); 251 if (ret) 252 return ret; 253 254 data->odr = odr; 255 256 return 0; 257 } 258 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { 259 switch (val) { 260 case 64: 261 osr = QMC5883L_OSR_64; 262 break; 263 case 128: 264 osr = QMC5883L_OSR_128; 265 break; 266 case 256: 267 osr = QMC5883L_OSR_256; 268 break; 269 case 512: 270 osr = QMC5883L_OSR_512; 271 break; 272 default: 273 return -EINVAL; 274 } 275 276 guard(mutex)(&data->mutex); 277 278 ret = regmap_update_bits(data->regmap, QMC5883L_REG_CTRL1, 279 QMC5883L_OSR_MASK, 280 FIELD_PREP(QMC5883L_OSR_MASK, osr)); 281 if (ret) 282 return ret; 283 284 data->osr = osr; 285 286 return 0; 287 } 288 default: 289 return -EINVAL; 290 } 291 } 292 293 static int qmc5883l_read_avail(struct iio_dev *indio_dev, 294 struct iio_chan_spec const *chan, 295 const int **vals, int *type, int *length, 296 long mask) 297 { 298 switch (mask) { 299 case IIO_CHAN_INFO_SAMP_FREQ: 300 *vals = qmc5883l_odr_avail; 301 *type = IIO_VAL_INT; 302 *length = ARRAY_SIZE(qmc5883l_odr_avail); 303 return IIO_AVAIL_LIST; 304 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 305 *vals = qmc5883l_osr_avail; 306 *type = IIO_VAL_INT; 307 *length = ARRAY_SIZE(qmc5883l_osr_avail); 308 return IIO_AVAIL_LIST; 309 case IIO_CHAN_INFO_SCALE: 310 *vals = (const int *)qmc5883l_scales; 311 *type = IIO_VAL_INT_PLUS_NANO; 312 *length = ARRAY_SIZE(qmc5883l_scales) * 2; 313 return IIO_AVAIL_LIST; 314 default: 315 return -EINVAL; 316 } 317 } 318 319 static int qmc5883l_write_raw_get_fmt(struct iio_dev *indio_dev, 320 struct iio_chan_spec const *chan, 321 long mask) 322 { 323 switch (mask) { 324 case IIO_CHAN_INFO_SCALE: 325 return IIO_VAL_INT_PLUS_NANO; 326 default: 327 return IIO_VAL_INT; 328 } 329 } 330 331 static const struct iio_info qmc5883l_info = { 332 .read_raw = qmc5883l_read_raw, 333 .write_raw = qmc5883l_write_raw, 334 .read_avail = qmc5883l_read_avail, 335 .write_raw_get_fmt = qmc5883l_write_raw_get_fmt, 336 }; 337 338 static int qmc5883l_init(struct qmc5883l_data *data) 339 { 340 struct regmap *map = data->regmap; 341 unsigned int reg; 342 int ret; 343 344 ret = regmap_read(map, QMC5883L_REG_ID, ®); 345 if (ret) 346 return ret; 347 348 /* Not failing because rev 1.0 had this register reserved */ 349 if (reg != QMC5883L_CHIP_ID) 350 dev_warn(regmap_get_device(map), 351 "Unknown chip id: 0x%02x, continuing\n", reg); 352 353 ret = regmap_write(map, QMC5883L_REG_CTRL2, QMC5883L_SOFT_RESET); 354 if (ret) 355 return ret; 356 357 /* Use POR completion time as a conservative bound */ 358 fsleep(QMC5883L_PORT_US); 359 360 /* DRDY pin not used in this version of the driver */ 361 ret = regmap_write(map, QMC5883L_REG_CTRL2, QMC5883L_INT_DISABLE); 362 if (ret) 363 return ret; 364 365 ret = regmap_write(map, QMC5883L_REG_SET_RESET, QMC5883L_SET_RESET_VAL); 366 if (ret) 367 return ret; 368 369 data->odr = QMC5883L_ODR_50HZ; 370 data->range = QMC5883L_RNG_2G; 371 data->osr = QMC5883L_OSR_64; 372 373 return regmap_write(map, QMC5883L_REG_CTRL1, 374 FIELD_PREP(QMC5883L_MODE_MASK, QMC5883L_MODE_CONT) | 375 FIELD_PREP(QMC5883L_ODR_MASK, data->odr) | 376 FIELD_PREP(QMC5883L_RNG_MASK, data->range) | 377 FIELD_PREP(QMC5883L_OSR_MASK, data->osr)); 378 } 379 380 static void qmc5883l_power_down_action(void *priv) 381 { 382 struct qmc5883l_data *data = priv; 383 384 regmap_update_bits(data->regmap, QMC5883L_REG_CTRL1, 385 QMC5883L_MODE_MASK, 386 FIELD_PREP(QMC5883L_MODE_MASK, QMC5883L_MODE_STANDBY)); 387 } 388 389 static bool qmc5883l_volatile_reg(struct device *dev, unsigned int reg) 390 { 391 return reg <= QMC5883L_REG_STATUS1; 392 } 393 394 static bool qmc5883l_writable_reg(struct device *dev, unsigned int reg) 395 { 396 switch (reg) { 397 case QMC5883L_REG_CTRL1: 398 case QMC5883L_REG_CTRL2: 399 case QMC5883L_REG_SET_RESET: 400 return true; 401 default: 402 return false; 403 } 404 } 405 406 static const struct regmap_config qmc5883l_regmap_config = { 407 .reg_bits = 8, 408 .val_bits = 8, 409 .max_register = QMC5883L_REG_ID, 410 .cache_type = REGCACHE_MAPLE, 411 .volatile_reg = qmc5883l_volatile_reg, 412 .writeable_reg = qmc5883l_writable_reg, 413 }; 414 415 #define QMC5883L_CHANNEL(_axis) \ 416 { \ 417 .type = IIO_MAGN, \ 418 .modified = 1, \ 419 .channel2 = IIO_MOD_##_axis, \ 420 .address = QMC5883L_AXIS_##_axis, \ 421 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 422 .info_mask_shared_by_type = \ 423 BIT(IIO_CHAN_INFO_SCALE) | \ 424 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 425 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 426 .info_mask_shared_by_type_available = \ 427 BIT(IIO_CHAN_INFO_SCALE) | \ 428 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 429 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 430 } 431 432 static const struct iio_chan_spec qmc5883l_channels[] = { 433 QMC5883L_CHANNEL(X), 434 QMC5883L_CHANNEL(Y), 435 QMC5883L_CHANNEL(Z), 436 }; 437 438 static int qmc5883l_probe(struct i2c_client *client) 439 { 440 struct device *dev = &client->dev; 441 struct qmc5883l_data *data; 442 struct iio_dev *indio_dev; 443 struct regmap *map; 444 int ret; 445 446 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 447 if (!indio_dev) 448 return -ENOMEM; 449 450 map = devm_regmap_init_i2c(client, &qmc5883l_regmap_config); 451 if (IS_ERR(map)) 452 return dev_err_probe(dev, PTR_ERR(map), 453 "regmap initialization failed\n"); 454 455 ret = devm_regulator_get_enable(dev, "vdd"); 456 if (ret) 457 return dev_err_probe(dev, ret, 458 "Failed to enable VDD regulator\n"); 459 460 ret = devm_regulator_get_enable(dev, "vddio"); 461 if (ret) 462 return dev_err_probe(dev, ret, 463 "Failed to enable VDDIO regulator\n"); 464 465 /* POR completion time max per datasheet Table 7 */ 466 fsleep(QMC5883L_PORT_US); 467 468 data = iio_priv(indio_dev); 469 data->regmap = map; 470 471 ret = devm_mutex_init(dev, &data->mutex); 472 if (ret) 473 return ret; 474 475 indio_dev->name = "qmc5883l"; 476 indio_dev->info = &qmc5883l_info; 477 indio_dev->channels = qmc5883l_channels; 478 indio_dev->num_channels = ARRAY_SIZE(qmc5883l_channels); 479 indio_dev->modes = INDIO_DIRECT_MODE; 480 481 ret = qmc5883l_init(data); 482 if (ret) 483 return dev_err_probe(dev, ret, "qmc5883l init failed\n"); 484 485 ret = devm_add_action_or_reset(dev, qmc5883l_power_down_action, data); 486 if (ret) 487 return ret; 488 489 return devm_iio_device_register(dev, indio_dev); 490 } 491 492 static const struct of_device_id qmc5883l_match[] = { 493 { .compatible = "qstcorp,qmc5883l" }, 494 { } 495 }; 496 MODULE_DEVICE_TABLE(of, qmc5883l_match); 497 498 static const struct i2c_device_id qmc5883l_id[] = { 499 { .name = "qmc5883l" }, 500 { } 501 }; 502 MODULE_DEVICE_TABLE(i2c, qmc5883l_id); 503 504 static struct i2c_driver qmc5883l_driver = { 505 .driver = { 506 .name = "qmc5883l", 507 .of_match_table = qmc5883l_match, 508 }, 509 .id_table = qmc5883l_id, 510 .probe = qmc5883l_probe, 511 }; 512 module_i2c_driver(qmc5883l_driver); 513 514 MODULE_DESCRIPTION("QST QMC5883L 3-Axis Magnetic Sensor driver"); 515 MODULE_AUTHOR("Siratul Islam <siratul.islam@linux.dev>"); 516 MODULE_LICENSE("Dual BSD/GPL"); 517