12025cf9eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2c91746a2SIrina Tirdea /*
3c91746a2SIrina Tirdea * Bosch BMC150 three-axis magnetic field sensor driver
4c91746a2SIrina Tirdea *
5c91746a2SIrina Tirdea * Copyright (c) 2015, Intel Corporation.
6c91746a2SIrina Tirdea *
7c91746a2SIrina Tirdea * This code is based on bmm050_api.c authored by contact@bosch.sensortec.com:
8c91746a2SIrina Tirdea *
9c91746a2SIrina Tirdea * (C) Copyright 2011~2014 Bosch Sensortec GmbH All Rights Reserved
10c91746a2SIrina Tirdea */
11c91746a2SIrina Tirdea
12c91746a2SIrina Tirdea #include <linux/module.h>
13c91746a2SIrina Tirdea #include <linux/i2c.h>
14c91746a2SIrina Tirdea #include <linux/interrupt.h>
15c91746a2SIrina Tirdea #include <linux/delay.h>
16c91746a2SIrina Tirdea #include <linux/slab.h>
17c91746a2SIrina Tirdea #include <linux/acpi.h>
18c91746a2SIrina Tirdea #include <linux/pm.h>
19c91746a2SIrina Tirdea #include <linux/pm_runtime.h>
20c91746a2SIrina Tirdea #include <linux/iio/iio.h>
21c91746a2SIrina Tirdea #include <linux/iio/sysfs.h>
22c91746a2SIrina Tirdea #include <linux/iio/buffer.h>
23c91746a2SIrina Tirdea #include <linux/iio/events.h>
24c91746a2SIrina Tirdea #include <linux/iio/trigger.h>
25c91746a2SIrina Tirdea #include <linux/iio/trigger_consumer.h>
26c91746a2SIrina Tirdea #include <linux/iio/triggered_buffer.h>
27c91746a2SIrina Tirdea #include <linux/regmap.h>
28cce4f160SStephan Gerhold #include <linux/regulator/consumer.h>
29c91746a2SIrina Tirdea
30761b7910SDaniel Baluta #include "bmc150_magn.h"
31761b7910SDaniel Baluta
32c91746a2SIrina Tirdea #define BMC150_MAGN_DRV_NAME "bmc150_magn"
33c91746a2SIrina Tirdea #define BMC150_MAGN_IRQ_NAME "bmc150_magn_event"
34c91746a2SIrina Tirdea
35c91746a2SIrina Tirdea #define BMC150_MAGN_REG_CHIP_ID 0x40
36c91746a2SIrina Tirdea #define BMC150_MAGN_CHIP_ID_VAL 0x32
37c91746a2SIrina Tirdea
38c91746a2SIrina Tirdea #define BMC150_MAGN_REG_X_L 0x42
39c91746a2SIrina Tirdea #define BMC150_MAGN_REG_X_M 0x43
40c91746a2SIrina Tirdea #define BMC150_MAGN_REG_Y_L 0x44
41c91746a2SIrina Tirdea #define BMC150_MAGN_REG_Y_M 0x45
42c91746a2SIrina Tirdea #define BMC150_MAGN_SHIFT_XY_L 3
43c91746a2SIrina Tirdea #define BMC150_MAGN_REG_Z_L 0x46
44c91746a2SIrina Tirdea #define BMC150_MAGN_REG_Z_M 0x47
45c91746a2SIrina Tirdea #define BMC150_MAGN_SHIFT_Z_L 1
46c91746a2SIrina Tirdea #define BMC150_MAGN_REG_RHALL_L 0x48
47c91746a2SIrina Tirdea #define BMC150_MAGN_REG_RHALL_M 0x49
48c91746a2SIrina Tirdea #define BMC150_MAGN_SHIFT_RHALL_L 2
49c91746a2SIrina Tirdea
50c91746a2SIrina Tirdea #define BMC150_MAGN_REG_INT_STATUS 0x4A
51c91746a2SIrina Tirdea
52c91746a2SIrina Tirdea #define BMC150_MAGN_REG_POWER 0x4B
53c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_POWER_CTL BIT(0)
54c91746a2SIrina Tirdea
55c91746a2SIrina Tirdea #define BMC150_MAGN_REG_OPMODE_ODR 0x4C
56c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_OPMODE GENMASK(2, 1)
57c91746a2SIrina Tirdea #define BMC150_MAGN_SHIFT_OPMODE 1
58c91746a2SIrina Tirdea #define BMC150_MAGN_MODE_NORMAL 0x00
59c91746a2SIrina Tirdea #define BMC150_MAGN_MODE_FORCED 0x01
60c91746a2SIrina Tirdea #define BMC150_MAGN_MODE_SLEEP 0x03
61c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_ODR GENMASK(5, 3)
62c91746a2SIrina Tirdea #define BMC150_MAGN_SHIFT_ODR 3
63c91746a2SIrina Tirdea
64c91746a2SIrina Tirdea #define BMC150_MAGN_REG_INT 0x4D
65c91746a2SIrina Tirdea
66c91746a2SIrina Tirdea #define BMC150_MAGN_REG_INT_DRDY 0x4E
67c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_DRDY_EN BIT(7)
68c91746a2SIrina Tirdea #define BMC150_MAGN_SHIFT_DRDY_EN 7
69c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_DRDY_INT3 BIT(6)
70c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_DRDY_Z_EN BIT(5)
71c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_DRDY_Y_EN BIT(4)
72c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_DRDY_X_EN BIT(3)
73c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_DRDY_DR_POLARITY BIT(2)
74c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_DRDY_LATCHING BIT(1)
75c91746a2SIrina Tirdea #define BMC150_MAGN_MASK_DRDY_INT3_POLARITY BIT(0)
76c91746a2SIrina Tirdea
77c91746a2SIrina Tirdea #define BMC150_MAGN_REG_LOW_THRESH 0x4F
78c91746a2SIrina Tirdea #define BMC150_MAGN_REG_HIGH_THRESH 0x50
79c91746a2SIrina Tirdea #define BMC150_MAGN_REG_REP_XY 0x51
80c91746a2SIrina Tirdea #define BMC150_MAGN_REG_REP_Z 0x52
811506f3cdSHartmut Knaack #define BMC150_MAGN_REG_REP_DATAMASK GENMASK(7, 0)
82c91746a2SIrina Tirdea
83c91746a2SIrina Tirdea #define BMC150_MAGN_REG_TRIM_START 0x5D
84c91746a2SIrina Tirdea #define BMC150_MAGN_REG_TRIM_END 0x71
85c91746a2SIrina Tirdea
86c91746a2SIrina Tirdea #define BMC150_MAGN_XY_OVERFLOW_VAL -4096
87c91746a2SIrina Tirdea #define BMC150_MAGN_Z_OVERFLOW_VAL -16384
88c91746a2SIrina Tirdea
89c91746a2SIrina Tirdea /* Time from SUSPEND to SLEEP */
90c91746a2SIrina Tirdea #define BMC150_MAGN_START_UP_TIME_MS 3
91c91746a2SIrina Tirdea
92c91746a2SIrina Tirdea #define BMC150_MAGN_AUTO_SUSPEND_DELAY_MS 2000
93c91746a2SIrina Tirdea
94c91746a2SIrina Tirdea #define BMC150_MAGN_REGVAL_TO_REPXY(regval) (((regval) * 2) + 1)
95c91746a2SIrina Tirdea #define BMC150_MAGN_REGVAL_TO_REPZ(regval) ((regval) + 1)
96c91746a2SIrina Tirdea #define BMC150_MAGN_REPXY_TO_REGVAL(rep) (((rep) - 1) / 2)
97c91746a2SIrina Tirdea #define BMC150_MAGN_REPZ_TO_REGVAL(rep) ((rep) - 1)
98c91746a2SIrina Tirdea
99c91746a2SIrina Tirdea enum bmc150_magn_axis {
100c91746a2SIrina Tirdea AXIS_X,
101c91746a2SIrina Tirdea AXIS_Y,
102c91746a2SIrina Tirdea AXIS_Z,
103c91746a2SIrina Tirdea RHALL,
104c91746a2SIrina Tirdea AXIS_XYZ_MAX = RHALL,
105c91746a2SIrina Tirdea AXIS_XYZR_MAX,
106c91746a2SIrina Tirdea };
107c91746a2SIrina Tirdea
108c91746a2SIrina Tirdea enum bmc150_magn_power_modes {
109c91746a2SIrina Tirdea BMC150_MAGN_POWER_MODE_SUSPEND,
110c91746a2SIrina Tirdea BMC150_MAGN_POWER_MODE_SLEEP,
111c91746a2SIrina Tirdea BMC150_MAGN_POWER_MODE_NORMAL,
112c91746a2SIrina Tirdea };
113c91746a2SIrina Tirdea
114c91746a2SIrina Tirdea struct bmc150_magn_trim_regs {
115c91746a2SIrina Tirdea s8 x1;
116c91746a2SIrina Tirdea s8 y1;
117c91746a2SIrina Tirdea __le16 reserved1;
118c91746a2SIrina Tirdea u8 reserved2;
119c91746a2SIrina Tirdea __le16 z4;
120c91746a2SIrina Tirdea s8 x2;
121c91746a2SIrina Tirdea s8 y2;
122c91746a2SIrina Tirdea __le16 reserved3;
123c91746a2SIrina Tirdea __le16 z2;
124c91746a2SIrina Tirdea __le16 z1;
125c91746a2SIrina Tirdea __le16 xyz1;
126c91746a2SIrina Tirdea __le16 z3;
127c91746a2SIrina Tirdea s8 xy2;
128c91746a2SIrina Tirdea u8 xy1;
129c91746a2SIrina Tirdea } __packed;
130c91746a2SIrina Tirdea
131c91746a2SIrina Tirdea struct bmc150_magn_data {
132761b7910SDaniel Baluta struct device *dev;
133c91746a2SIrina Tirdea /*
134c91746a2SIrina Tirdea * 1. Protect this structure.
135c91746a2SIrina Tirdea * 2. Serialize sequences that power on/off the device and access HW.
136c91746a2SIrina Tirdea */
137c91746a2SIrina Tirdea struct mutex mutex;
138c91746a2SIrina Tirdea struct regmap *regmap;
139cce4f160SStephan Gerhold struct regulator_bulk_data regulators[2];
140d9842c77SH. Nikolaus Schaller struct iio_mount_matrix orientation;
1417692088fSJonathan Cameron /* Ensure timestamp is naturally aligned */
1427692088fSJonathan Cameron struct {
1437692088fSJonathan Cameron s32 chans[3];
1447692088fSJonathan Cameron s64 timestamp __aligned(8);
1457692088fSJonathan Cameron } scan;
146c91746a2SIrina Tirdea struct iio_trigger *dready_trig;
147c91746a2SIrina Tirdea bool dready_trigger_on;
1485990dc97SIrina Tirdea int max_odr;
149761b7910SDaniel Baluta int irq;
150c91746a2SIrina Tirdea };
151c91746a2SIrina Tirdea
152c91746a2SIrina Tirdea static const struct {
153c91746a2SIrina Tirdea int freq;
154c91746a2SIrina Tirdea u8 reg_val;
155c91746a2SIrina Tirdea } bmc150_magn_samp_freq_table[] = { {2, 0x01},
156c91746a2SIrina Tirdea {6, 0x02},
157c91746a2SIrina Tirdea {8, 0x03},
158c91746a2SIrina Tirdea {10, 0x00},
159c91746a2SIrina Tirdea {15, 0x04},
160c91746a2SIrina Tirdea {20, 0x05},
161c91746a2SIrina Tirdea {25, 0x06},
162c91746a2SIrina Tirdea {30, 0x07} };
163c91746a2SIrina Tirdea
164c91746a2SIrina Tirdea enum bmc150_magn_presets {
165c91746a2SIrina Tirdea LOW_POWER_PRESET,
166c91746a2SIrina Tirdea REGULAR_PRESET,
167c91746a2SIrina Tirdea ENHANCED_REGULAR_PRESET,
168c91746a2SIrina Tirdea HIGH_ACCURACY_PRESET
169c91746a2SIrina Tirdea };
170c91746a2SIrina Tirdea
171c91746a2SIrina Tirdea static const struct bmc150_magn_preset {
172c91746a2SIrina Tirdea u8 rep_xy;
173c91746a2SIrina Tirdea u8 rep_z;
174c91746a2SIrina Tirdea u8 odr;
175c91746a2SIrina Tirdea } bmc150_magn_presets_table[] = {
176c91746a2SIrina Tirdea [LOW_POWER_PRESET] = {3, 3, 10},
177c91746a2SIrina Tirdea [REGULAR_PRESET] = {9, 15, 10},
178c91746a2SIrina Tirdea [ENHANCED_REGULAR_PRESET] = {15, 27, 10},
179c91746a2SIrina Tirdea [HIGH_ACCURACY_PRESET] = {47, 83, 20},
180c91746a2SIrina Tirdea };
181c91746a2SIrina Tirdea
182c91746a2SIrina Tirdea #define BMC150_MAGN_DEFAULT_PRESET REGULAR_PRESET
183c91746a2SIrina Tirdea
bmc150_magn_is_writeable_reg(struct device * dev,unsigned int reg)184c91746a2SIrina Tirdea static bool bmc150_magn_is_writeable_reg(struct device *dev, unsigned int reg)
185c91746a2SIrina Tirdea {
186c91746a2SIrina Tirdea switch (reg) {
187c91746a2SIrina Tirdea case BMC150_MAGN_REG_POWER:
188c91746a2SIrina Tirdea case BMC150_MAGN_REG_OPMODE_ODR:
189c91746a2SIrina Tirdea case BMC150_MAGN_REG_INT:
190c91746a2SIrina Tirdea case BMC150_MAGN_REG_INT_DRDY:
191c91746a2SIrina Tirdea case BMC150_MAGN_REG_LOW_THRESH:
192c91746a2SIrina Tirdea case BMC150_MAGN_REG_HIGH_THRESH:
193c91746a2SIrina Tirdea case BMC150_MAGN_REG_REP_XY:
194c91746a2SIrina Tirdea case BMC150_MAGN_REG_REP_Z:
195c91746a2SIrina Tirdea return true;
196c91746a2SIrina Tirdea default:
197c91746a2SIrina Tirdea return false;
198b3b3ef6aSTom Rix }
199c91746a2SIrina Tirdea }
200c91746a2SIrina Tirdea
bmc150_magn_is_volatile_reg(struct device * dev,unsigned int reg)201c91746a2SIrina Tirdea static bool bmc150_magn_is_volatile_reg(struct device *dev, unsigned int reg)
202c91746a2SIrina Tirdea {
203c91746a2SIrina Tirdea switch (reg) {
204c91746a2SIrina Tirdea case BMC150_MAGN_REG_X_L:
205c91746a2SIrina Tirdea case BMC150_MAGN_REG_X_M:
206c91746a2SIrina Tirdea case BMC150_MAGN_REG_Y_L:
207c91746a2SIrina Tirdea case BMC150_MAGN_REG_Y_M:
208c91746a2SIrina Tirdea case BMC150_MAGN_REG_Z_L:
209c91746a2SIrina Tirdea case BMC150_MAGN_REG_Z_M:
210c91746a2SIrina Tirdea case BMC150_MAGN_REG_RHALL_L:
211c91746a2SIrina Tirdea case BMC150_MAGN_REG_RHALL_M:
212c91746a2SIrina Tirdea case BMC150_MAGN_REG_INT_STATUS:
213c91746a2SIrina Tirdea return true;
214c91746a2SIrina Tirdea default:
215c91746a2SIrina Tirdea return false;
216c91746a2SIrina Tirdea }
217c91746a2SIrina Tirdea }
218c91746a2SIrina Tirdea
219761b7910SDaniel Baluta const struct regmap_config bmc150_magn_regmap_config = {
220c91746a2SIrina Tirdea .reg_bits = 8,
221c91746a2SIrina Tirdea .val_bits = 8,
222c91746a2SIrina Tirdea
223c91746a2SIrina Tirdea .max_register = BMC150_MAGN_REG_TRIM_END,
224c91746a2SIrina Tirdea .cache_type = REGCACHE_RBTREE,
225c91746a2SIrina Tirdea
226c91746a2SIrina Tirdea .writeable_reg = bmc150_magn_is_writeable_reg,
227c91746a2SIrina Tirdea .volatile_reg = bmc150_magn_is_volatile_reg,
228c91746a2SIrina Tirdea };
22947d6cae0SJonathan Cameron EXPORT_SYMBOL_NS(bmc150_magn_regmap_config, IIO_BMC150_MAGN);
230c91746a2SIrina Tirdea
bmc150_magn_set_power_mode(struct bmc150_magn_data * data,enum bmc150_magn_power_modes mode,bool state)231c91746a2SIrina Tirdea static int bmc150_magn_set_power_mode(struct bmc150_magn_data *data,
232c91746a2SIrina Tirdea enum bmc150_magn_power_modes mode,
233c91746a2SIrina Tirdea bool state)
234c91746a2SIrina Tirdea {
235c91746a2SIrina Tirdea int ret;
236c91746a2SIrina Tirdea
237c91746a2SIrina Tirdea switch (mode) {
238c91746a2SIrina Tirdea case BMC150_MAGN_POWER_MODE_SUSPEND:
239c91746a2SIrina Tirdea ret = regmap_update_bits(data->regmap, BMC150_MAGN_REG_POWER,
240c91746a2SIrina Tirdea BMC150_MAGN_MASK_POWER_CTL, !state);
241c91746a2SIrina Tirdea if (ret < 0)
242c91746a2SIrina Tirdea return ret;
243c91746a2SIrina Tirdea usleep_range(BMC150_MAGN_START_UP_TIME_MS * 1000, 20000);
244c91746a2SIrina Tirdea return 0;
245c91746a2SIrina Tirdea case BMC150_MAGN_POWER_MODE_SLEEP:
246c91746a2SIrina Tirdea return regmap_update_bits(data->regmap,
247c91746a2SIrina Tirdea BMC150_MAGN_REG_OPMODE_ODR,
248c91746a2SIrina Tirdea BMC150_MAGN_MASK_OPMODE,
249c91746a2SIrina Tirdea BMC150_MAGN_MODE_SLEEP <<
250c91746a2SIrina Tirdea BMC150_MAGN_SHIFT_OPMODE);
251c91746a2SIrina Tirdea case BMC150_MAGN_POWER_MODE_NORMAL:
252c91746a2SIrina Tirdea return regmap_update_bits(data->regmap,
253c91746a2SIrina Tirdea BMC150_MAGN_REG_OPMODE_ODR,
254c91746a2SIrina Tirdea BMC150_MAGN_MASK_OPMODE,
255c91746a2SIrina Tirdea BMC150_MAGN_MODE_NORMAL <<
256c91746a2SIrina Tirdea BMC150_MAGN_SHIFT_OPMODE);
257c91746a2SIrina Tirdea }
258c91746a2SIrina Tirdea
259c91746a2SIrina Tirdea return -EINVAL;
260c91746a2SIrina Tirdea }
261c91746a2SIrina Tirdea
bmc150_magn_set_power_state(struct bmc150_magn_data * data,bool on)262c91746a2SIrina Tirdea static int bmc150_magn_set_power_state(struct bmc150_magn_data *data, bool on)
263c91746a2SIrina Tirdea {
264c91746a2SIrina Tirdea #ifdef CONFIG_PM
265c91746a2SIrina Tirdea int ret;
266c91746a2SIrina Tirdea
267c91746a2SIrina Tirdea if (on) {
268264da512SJonathan Cameron ret = pm_runtime_resume_and_get(data->dev);
269c91746a2SIrina Tirdea } else {
270761b7910SDaniel Baluta pm_runtime_mark_last_busy(data->dev);
271761b7910SDaniel Baluta ret = pm_runtime_put_autosuspend(data->dev);
272c91746a2SIrina Tirdea }
273c91746a2SIrina Tirdea
274c91746a2SIrina Tirdea if (ret < 0) {
275761b7910SDaniel Baluta dev_err(data->dev,
276c91746a2SIrina Tirdea "failed to change power state to %d\n", on);
277c91746a2SIrina Tirdea return ret;
278c91746a2SIrina Tirdea }
279c91746a2SIrina Tirdea #endif
280c91746a2SIrina Tirdea
281c91746a2SIrina Tirdea return 0;
282c91746a2SIrina Tirdea }
283c91746a2SIrina Tirdea
bmc150_magn_get_odr(struct bmc150_magn_data * data,int * val)284c91746a2SIrina Tirdea static int bmc150_magn_get_odr(struct bmc150_magn_data *data, int *val)
285c91746a2SIrina Tirdea {
286c91746a2SIrina Tirdea int ret, reg_val;
287c91746a2SIrina Tirdea u8 i, odr_val;
288c91746a2SIrina Tirdea
289c91746a2SIrina Tirdea ret = regmap_read(data->regmap, BMC150_MAGN_REG_OPMODE_ODR, ®_val);
290c91746a2SIrina Tirdea if (ret < 0)
291c91746a2SIrina Tirdea return ret;
292c91746a2SIrina Tirdea odr_val = (reg_val & BMC150_MAGN_MASK_ODR) >> BMC150_MAGN_SHIFT_ODR;
293c91746a2SIrina Tirdea
294c91746a2SIrina Tirdea for (i = 0; i < ARRAY_SIZE(bmc150_magn_samp_freq_table); i++)
295c91746a2SIrina Tirdea if (bmc150_magn_samp_freq_table[i].reg_val == odr_val) {
296c91746a2SIrina Tirdea *val = bmc150_magn_samp_freq_table[i].freq;
297c91746a2SIrina Tirdea return 0;
298c91746a2SIrina Tirdea }
299c91746a2SIrina Tirdea
300c91746a2SIrina Tirdea return -EINVAL;
301c91746a2SIrina Tirdea }
302c91746a2SIrina Tirdea
bmc150_magn_set_odr(struct bmc150_magn_data * data,int val)303c91746a2SIrina Tirdea static int bmc150_magn_set_odr(struct bmc150_magn_data *data, int val)
304c91746a2SIrina Tirdea {
305c91746a2SIrina Tirdea int ret;
306c91746a2SIrina Tirdea u8 i;
307c91746a2SIrina Tirdea
308c91746a2SIrina Tirdea for (i = 0; i < ARRAY_SIZE(bmc150_magn_samp_freq_table); i++) {
309c91746a2SIrina Tirdea if (bmc150_magn_samp_freq_table[i].freq == val) {
310c91746a2SIrina Tirdea ret = regmap_update_bits(data->regmap,
311c91746a2SIrina Tirdea BMC150_MAGN_REG_OPMODE_ODR,
312c91746a2SIrina Tirdea BMC150_MAGN_MASK_ODR,
313c91746a2SIrina Tirdea bmc150_magn_samp_freq_table[i].
314c91746a2SIrina Tirdea reg_val <<
315c91746a2SIrina Tirdea BMC150_MAGN_SHIFT_ODR);
316c91746a2SIrina Tirdea if (ret < 0)
317c91746a2SIrina Tirdea return ret;
318c91746a2SIrina Tirdea return 0;
319c91746a2SIrina Tirdea }
320c91746a2SIrina Tirdea }
321c91746a2SIrina Tirdea
322c91746a2SIrina Tirdea return -EINVAL;
323c91746a2SIrina Tirdea }
324c91746a2SIrina Tirdea
bmc150_magn_set_max_odr(struct bmc150_magn_data * data,int rep_xy,int rep_z,int odr)3255990dc97SIrina Tirdea static int bmc150_magn_set_max_odr(struct bmc150_magn_data *data, int rep_xy,
3265990dc97SIrina Tirdea int rep_z, int odr)
3275990dc97SIrina Tirdea {
3285990dc97SIrina Tirdea int ret, reg_val, max_odr;
3295990dc97SIrina Tirdea
3305990dc97SIrina Tirdea if (rep_xy <= 0) {
3315990dc97SIrina Tirdea ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_XY,
3325990dc97SIrina Tirdea ®_val);
3335990dc97SIrina Tirdea if (ret < 0)
3345990dc97SIrina Tirdea return ret;
3355990dc97SIrina Tirdea rep_xy = BMC150_MAGN_REGVAL_TO_REPXY(reg_val);
3365990dc97SIrina Tirdea }
3375990dc97SIrina Tirdea if (rep_z <= 0) {
3385990dc97SIrina Tirdea ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_Z,
3395990dc97SIrina Tirdea ®_val);
3405990dc97SIrina Tirdea if (ret < 0)
3415990dc97SIrina Tirdea return ret;
3425990dc97SIrina Tirdea rep_z = BMC150_MAGN_REGVAL_TO_REPZ(reg_val);
3435990dc97SIrina Tirdea }
3445990dc97SIrina Tirdea if (odr <= 0) {
3455990dc97SIrina Tirdea ret = bmc150_magn_get_odr(data, &odr);
3465990dc97SIrina Tirdea if (ret < 0)
3475990dc97SIrina Tirdea return ret;
3485990dc97SIrina Tirdea }
3495990dc97SIrina Tirdea /* the maximum selectable read-out frequency from datasheet */
3505990dc97SIrina Tirdea max_odr = 1000000 / (145 * rep_xy + 500 * rep_z + 980);
3515990dc97SIrina Tirdea if (odr > max_odr) {
352761b7910SDaniel Baluta dev_err(data->dev,
3535990dc97SIrina Tirdea "Can't set oversampling with sampling freq %d\n",
3545990dc97SIrina Tirdea odr);
3555990dc97SIrina Tirdea return -EINVAL;
3565990dc97SIrina Tirdea }
3575990dc97SIrina Tirdea data->max_odr = max_odr;
3585990dc97SIrina Tirdea
3595990dc97SIrina Tirdea return 0;
3605990dc97SIrina Tirdea }
3615990dc97SIrina Tirdea
bmc150_magn_compensate_x(struct bmc150_magn_trim_regs * tregs,s16 x,u16 rhall)362c91746a2SIrina Tirdea static s32 bmc150_magn_compensate_x(struct bmc150_magn_trim_regs *tregs, s16 x,
363c91746a2SIrina Tirdea u16 rhall)
364c91746a2SIrina Tirdea {
365c91746a2SIrina Tirdea s16 val;
366c91746a2SIrina Tirdea u16 xyz1 = le16_to_cpu(tregs->xyz1);
367c91746a2SIrina Tirdea
368c91746a2SIrina Tirdea if (x == BMC150_MAGN_XY_OVERFLOW_VAL)
369c91746a2SIrina Tirdea return S32_MIN;
370c91746a2SIrina Tirdea
371c91746a2SIrina Tirdea if (!rhall)
372c91746a2SIrina Tirdea rhall = xyz1;
373c91746a2SIrina Tirdea
374c91746a2SIrina Tirdea val = ((s16)(((u16)((((s32)xyz1) << 14) / rhall)) - ((u16)0x4000)));
375c91746a2SIrina Tirdea val = ((s16)((((s32)x) * ((((((((s32)tregs->xy2) * ((((s32)val) *
376c91746a2SIrina Tirdea ((s32)val)) >> 7)) + (((s32)val) *
377c91746a2SIrina Tirdea ((s32)(((s16)tregs->xy1) << 7)))) >> 9) + ((s32)0x100000)) *
378c91746a2SIrina Tirdea ((s32)(((s16)tregs->x2) + ((s16)0xA0)))) >> 12)) >> 13)) +
379c91746a2SIrina Tirdea (((s16)tregs->x1) << 3);
380c91746a2SIrina Tirdea
381c91746a2SIrina Tirdea return (s32)val;
382c91746a2SIrina Tirdea }
383c91746a2SIrina Tirdea
bmc150_magn_compensate_y(struct bmc150_magn_trim_regs * tregs,s16 y,u16 rhall)384c91746a2SIrina Tirdea static s32 bmc150_magn_compensate_y(struct bmc150_magn_trim_regs *tregs, s16 y,
385c91746a2SIrina Tirdea u16 rhall)
386c91746a2SIrina Tirdea {
387c91746a2SIrina Tirdea s16 val;
388c91746a2SIrina Tirdea u16 xyz1 = le16_to_cpu(tregs->xyz1);
389c91746a2SIrina Tirdea
390c91746a2SIrina Tirdea if (y == BMC150_MAGN_XY_OVERFLOW_VAL)
391c91746a2SIrina Tirdea return S32_MIN;
392c91746a2SIrina Tirdea
393c91746a2SIrina Tirdea if (!rhall)
394c91746a2SIrina Tirdea rhall = xyz1;
395c91746a2SIrina Tirdea
396c91746a2SIrina Tirdea val = ((s16)(((u16)((((s32)xyz1) << 14) / rhall)) - ((u16)0x4000)));
397c91746a2SIrina Tirdea val = ((s16)((((s32)y) * ((((((((s32)tregs->xy2) * ((((s32)val) *
398c91746a2SIrina Tirdea ((s32)val)) >> 7)) + (((s32)val) *
399c91746a2SIrina Tirdea ((s32)(((s16)tregs->xy1) << 7)))) >> 9) + ((s32)0x100000)) *
400c91746a2SIrina Tirdea ((s32)(((s16)tregs->y2) + ((s16)0xA0)))) >> 12)) >> 13)) +
401c91746a2SIrina Tirdea (((s16)tregs->y1) << 3);
402c91746a2SIrina Tirdea
403c91746a2SIrina Tirdea return (s32)val;
404c91746a2SIrina Tirdea }
405c91746a2SIrina Tirdea
bmc150_magn_compensate_z(struct bmc150_magn_trim_regs * tregs,s16 z,u16 rhall)406c91746a2SIrina Tirdea static s32 bmc150_magn_compensate_z(struct bmc150_magn_trim_regs *tregs, s16 z,
407c91746a2SIrina Tirdea u16 rhall)
408c91746a2SIrina Tirdea {
409c91746a2SIrina Tirdea s32 val;
410c91746a2SIrina Tirdea u16 xyz1 = le16_to_cpu(tregs->xyz1);
411c91746a2SIrina Tirdea u16 z1 = le16_to_cpu(tregs->z1);
412c91746a2SIrina Tirdea s16 z2 = le16_to_cpu(tregs->z2);
413c91746a2SIrina Tirdea s16 z3 = le16_to_cpu(tregs->z3);
414c91746a2SIrina Tirdea s16 z4 = le16_to_cpu(tregs->z4);
415c91746a2SIrina Tirdea
416c91746a2SIrina Tirdea if (z == BMC150_MAGN_Z_OVERFLOW_VAL)
417c91746a2SIrina Tirdea return S32_MIN;
418c91746a2SIrina Tirdea
419c91746a2SIrina Tirdea val = (((((s32)(z - z4)) << 15) - ((((s32)z3) * ((s32)(((s16)rhall) -
420c91746a2SIrina Tirdea ((s16)xyz1)))) >> 2)) / (z2 + ((s16)(((((s32)z1) *
421c91746a2SIrina Tirdea ((((s16)rhall) << 1))) + (1 << 15)) >> 16))));
422c91746a2SIrina Tirdea
423c91746a2SIrina Tirdea return val;
424c91746a2SIrina Tirdea }
425c91746a2SIrina Tirdea
bmc150_magn_read_xyz(struct bmc150_magn_data * data,s32 * buffer)426c91746a2SIrina Tirdea static int bmc150_magn_read_xyz(struct bmc150_magn_data *data, s32 *buffer)
427c91746a2SIrina Tirdea {
428c91746a2SIrina Tirdea int ret;
429c91746a2SIrina Tirdea __le16 values[AXIS_XYZR_MAX];
430c91746a2SIrina Tirdea s16 raw_x, raw_y, raw_z;
431c91746a2SIrina Tirdea u16 rhall;
432c91746a2SIrina Tirdea struct bmc150_magn_trim_regs tregs;
433c91746a2SIrina Tirdea
434c91746a2SIrina Tirdea ret = regmap_bulk_read(data->regmap, BMC150_MAGN_REG_X_L,
435c91746a2SIrina Tirdea values, sizeof(values));
436c91746a2SIrina Tirdea if (ret < 0)
437c91746a2SIrina Tirdea return ret;
438c91746a2SIrina Tirdea
439c91746a2SIrina Tirdea raw_x = (s16)le16_to_cpu(values[AXIS_X]) >> BMC150_MAGN_SHIFT_XY_L;
440c91746a2SIrina Tirdea raw_y = (s16)le16_to_cpu(values[AXIS_Y]) >> BMC150_MAGN_SHIFT_XY_L;
441c91746a2SIrina Tirdea raw_z = (s16)le16_to_cpu(values[AXIS_Z]) >> BMC150_MAGN_SHIFT_Z_L;
442c91746a2SIrina Tirdea rhall = le16_to_cpu(values[RHALL]) >> BMC150_MAGN_SHIFT_RHALL_L;
443c91746a2SIrina Tirdea
444c91746a2SIrina Tirdea ret = regmap_bulk_read(data->regmap, BMC150_MAGN_REG_TRIM_START,
445c91746a2SIrina Tirdea &tregs, sizeof(tregs));
446c91746a2SIrina Tirdea if (ret < 0)
447c91746a2SIrina Tirdea return ret;
448c91746a2SIrina Tirdea
449c91746a2SIrina Tirdea buffer[AXIS_X] = bmc150_magn_compensate_x(&tregs, raw_x, rhall);
450c91746a2SIrina Tirdea buffer[AXIS_Y] = bmc150_magn_compensate_y(&tregs, raw_y, rhall);
451c91746a2SIrina Tirdea buffer[AXIS_Z] = bmc150_magn_compensate_z(&tregs, raw_z, rhall);
452c91746a2SIrina Tirdea
453c91746a2SIrina Tirdea return 0;
454c91746a2SIrina Tirdea }
455c91746a2SIrina Tirdea
bmc150_magn_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)456c91746a2SIrina Tirdea static int bmc150_magn_read_raw(struct iio_dev *indio_dev,
457c91746a2SIrina Tirdea struct iio_chan_spec const *chan,
458c91746a2SIrina Tirdea int *val, int *val2, long mask)
459c91746a2SIrina Tirdea {
460c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
4615990dc97SIrina Tirdea int ret, tmp;
462c91746a2SIrina Tirdea s32 values[AXIS_XYZ_MAX];
463c91746a2SIrina Tirdea
464c91746a2SIrina Tirdea switch (mask) {
465c91746a2SIrina Tirdea case IIO_CHAN_INFO_RAW:
466c91746a2SIrina Tirdea if (iio_buffer_enabled(indio_dev))
467c91746a2SIrina Tirdea return -EBUSY;
468c91746a2SIrina Tirdea mutex_lock(&data->mutex);
469c91746a2SIrina Tirdea
470c91746a2SIrina Tirdea ret = bmc150_magn_set_power_state(data, true);
471c91746a2SIrina Tirdea if (ret < 0) {
472c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
473c91746a2SIrina Tirdea return ret;
474c91746a2SIrina Tirdea }
475c91746a2SIrina Tirdea
476c91746a2SIrina Tirdea ret = bmc150_magn_read_xyz(data, values);
477c91746a2SIrina Tirdea if (ret < 0) {
478c91746a2SIrina Tirdea bmc150_magn_set_power_state(data, false);
479c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
480c91746a2SIrina Tirdea return ret;
481c91746a2SIrina Tirdea }
482c91746a2SIrina Tirdea *val = values[chan->scan_index];
483c91746a2SIrina Tirdea
484c91746a2SIrina Tirdea ret = bmc150_magn_set_power_state(data, false);
485c91746a2SIrina Tirdea if (ret < 0) {
486c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
487c91746a2SIrina Tirdea return ret;
488c91746a2SIrina Tirdea }
489c91746a2SIrina Tirdea
490c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
491c91746a2SIrina Tirdea return IIO_VAL_INT;
492c91746a2SIrina Tirdea case IIO_CHAN_INFO_SCALE:
493c91746a2SIrina Tirdea /*
494c91746a2SIrina Tirdea * The API/driver performs an off-chip temperature
495c91746a2SIrina Tirdea * compensation and outputs x/y/z magnetic field data in
496c91746a2SIrina Tirdea * 16 LSB/uT to the upper application layer.
497c91746a2SIrina Tirdea */
498c91746a2SIrina Tirdea *val = 0;
499c91746a2SIrina Tirdea *val2 = 625;
500c91746a2SIrina Tirdea return IIO_VAL_INT_PLUS_MICRO;
501c91746a2SIrina Tirdea case IIO_CHAN_INFO_SAMP_FREQ:
502c91746a2SIrina Tirdea ret = bmc150_magn_get_odr(data, val);
503c91746a2SIrina Tirdea if (ret < 0)
504c91746a2SIrina Tirdea return ret;
505c91746a2SIrina Tirdea return IIO_VAL_INT;
5065990dc97SIrina Tirdea case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
5075990dc97SIrina Tirdea switch (chan->channel2) {
5085990dc97SIrina Tirdea case IIO_MOD_X:
5095990dc97SIrina Tirdea case IIO_MOD_Y:
5105990dc97SIrina Tirdea ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_XY,
5115990dc97SIrina Tirdea &tmp);
5125990dc97SIrina Tirdea if (ret < 0)
5135990dc97SIrina Tirdea return ret;
5145990dc97SIrina Tirdea *val = BMC150_MAGN_REGVAL_TO_REPXY(tmp);
5155990dc97SIrina Tirdea return IIO_VAL_INT;
5165990dc97SIrina Tirdea case IIO_MOD_Z:
5175990dc97SIrina Tirdea ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_Z,
5185990dc97SIrina Tirdea &tmp);
5195990dc97SIrina Tirdea if (ret < 0)
5205990dc97SIrina Tirdea return ret;
5215990dc97SIrina Tirdea *val = BMC150_MAGN_REGVAL_TO_REPZ(tmp);
5225990dc97SIrina Tirdea return IIO_VAL_INT;
5235990dc97SIrina Tirdea default:
5245990dc97SIrina Tirdea return -EINVAL;
5255990dc97SIrina Tirdea }
526c91746a2SIrina Tirdea default:
527c91746a2SIrina Tirdea return -EINVAL;
528c91746a2SIrina Tirdea }
529c91746a2SIrina Tirdea }
530c91746a2SIrina Tirdea
bmc150_magn_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)531c91746a2SIrina Tirdea static int bmc150_magn_write_raw(struct iio_dev *indio_dev,
532c91746a2SIrina Tirdea struct iio_chan_spec const *chan,
533c91746a2SIrina Tirdea int val, int val2, long mask)
534c91746a2SIrina Tirdea {
535c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
536c91746a2SIrina Tirdea int ret;
537c91746a2SIrina Tirdea
538c91746a2SIrina Tirdea switch (mask) {
539c91746a2SIrina Tirdea case IIO_CHAN_INFO_SAMP_FREQ:
5405990dc97SIrina Tirdea if (val > data->max_odr)
5415990dc97SIrina Tirdea return -EINVAL;
542c91746a2SIrina Tirdea mutex_lock(&data->mutex);
543c91746a2SIrina Tirdea ret = bmc150_magn_set_odr(data, val);
544c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
545c91746a2SIrina Tirdea return ret;
5465990dc97SIrina Tirdea case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
5475990dc97SIrina Tirdea switch (chan->channel2) {
5485990dc97SIrina Tirdea case IIO_MOD_X:
5495990dc97SIrina Tirdea case IIO_MOD_Y:
5505990dc97SIrina Tirdea if (val < 1 || val > 511)
5515990dc97SIrina Tirdea return -EINVAL;
5525990dc97SIrina Tirdea mutex_lock(&data->mutex);
5535990dc97SIrina Tirdea ret = bmc150_magn_set_max_odr(data, val, 0, 0);
5545990dc97SIrina Tirdea if (ret < 0) {
5555990dc97SIrina Tirdea mutex_unlock(&data->mutex);
5565990dc97SIrina Tirdea return ret;
5575990dc97SIrina Tirdea }
5585990dc97SIrina Tirdea ret = regmap_update_bits(data->regmap,
5595990dc97SIrina Tirdea BMC150_MAGN_REG_REP_XY,
5601506f3cdSHartmut Knaack BMC150_MAGN_REG_REP_DATAMASK,
5615990dc97SIrina Tirdea BMC150_MAGN_REPXY_TO_REGVAL
5625990dc97SIrina Tirdea (val));
5635990dc97SIrina Tirdea mutex_unlock(&data->mutex);
5645990dc97SIrina Tirdea return ret;
5655990dc97SIrina Tirdea case IIO_MOD_Z:
5665990dc97SIrina Tirdea if (val < 1 || val > 256)
5675990dc97SIrina Tirdea return -EINVAL;
5685990dc97SIrina Tirdea mutex_lock(&data->mutex);
5695990dc97SIrina Tirdea ret = bmc150_magn_set_max_odr(data, 0, val, 0);
5705990dc97SIrina Tirdea if (ret < 0) {
5715990dc97SIrina Tirdea mutex_unlock(&data->mutex);
5725990dc97SIrina Tirdea return ret;
5735990dc97SIrina Tirdea }
5745990dc97SIrina Tirdea ret = regmap_update_bits(data->regmap,
5755990dc97SIrina Tirdea BMC150_MAGN_REG_REP_Z,
5761506f3cdSHartmut Knaack BMC150_MAGN_REG_REP_DATAMASK,
5775990dc97SIrina Tirdea BMC150_MAGN_REPZ_TO_REGVAL
5785990dc97SIrina Tirdea (val));
5795990dc97SIrina Tirdea mutex_unlock(&data->mutex);
5805990dc97SIrina Tirdea return ret;
5815990dc97SIrina Tirdea default:
5825990dc97SIrina Tirdea return -EINVAL;
5835990dc97SIrina Tirdea }
584c91746a2SIrina Tirdea default:
585c91746a2SIrina Tirdea return -EINVAL;
586c91746a2SIrina Tirdea }
587c91746a2SIrina Tirdea }
588c91746a2SIrina Tirdea
bmc150_magn_show_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)5895990dc97SIrina Tirdea static ssize_t bmc150_magn_show_samp_freq_avail(struct device *dev,
5905990dc97SIrina Tirdea struct device_attribute *attr,
5915990dc97SIrina Tirdea char *buf)
5925990dc97SIrina Tirdea {
5935990dc97SIrina Tirdea struct iio_dev *indio_dev = dev_to_iio_dev(dev);
5945990dc97SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
5955990dc97SIrina Tirdea size_t len = 0;
5965990dc97SIrina Tirdea u8 i;
5975990dc97SIrina Tirdea
5985990dc97SIrina Tirdea for (i = 0; i < ARRAY_SIZE(bmc150_magn_samp_freq_table); i++) {
5995990dc97SIrina Tirdea if (bmc150_magn_samp_freq_table[i].freq > data->max_odr)
6005990dc97SIrina Tirdea break;
6015990dc97SIrina Tirdea len += scnprintf(buf + len, PAGE_SIZE - len, "%d ",
6025990dc97SIrina Tirdea bmc150_magn_samp_freq_table[i].freq);
6035990dc97SIrina Tirdea }
6045990dc97SIrina Tirdea /* replace last space with a newline */
6055990dc97SIrina Tirdea buf[len - 1] = '\n';
6065990dc97SIrina Tirdea
6075990dc97SIrina Tirdea return len;
6085990dc97SIrina Tirdea }
6095990dc97SIrina Tirdea
610d9842c77SH. Nikolaus Schaller static const struct iio_mount_matrix *
bmc150_magn_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)611d9842c77SH. Nikolaus Schaller bmc150_magn_get_mount_matrix(const struct iio_dev *indio_dev,
612d9842c77SH. Nikolaus Schaller const struct iio_chan_spec *chan)
613d9842c77SH. Nikolaus Schaller {
614d9842c77SH. Nikolaus Schaller struct bmc150_magn_data *data = iio_priv(indio_dev);
615d9842c77SH. Nikolaus Schaller
616d9842c77SH. Nikolaus Schaller return &data->orientation;
617d9842c77SH. Nikolaus Schaller }
618d9842c77SH. Nikolaus Schaller
619d9842c77SH. Nikolaus Schaller static const struct iio_chan_spec_ext_info bmc150_magn_ext_info[] = {
620d9842c77SH. Nikolaus Schaller IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_magn_get_mount_matrix),
621d9842c77SH. Nikolaus Schaller { }
622d9842c77SH. Nikolaus Schaller };
623d9842c77SH. Nikolaus Schaller
6245990dc97SIrina Tirdea static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(bmc150_magn_show_samp_freq_avail);
625c91746a2SIrina Tirdea
626c91746a2SIrina Tirdea static struct attribute *bmc150_magn_attributes[] = {
6275990dc97SIrina Tirdea &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
628c91746a2SIrina Tirdea NULL,
629c91746a2SIrina Tirdea };
630c91746a2SIrina Tirdea
631c91746a2SIrina Tirdea static const struct attribute_group bmc150_magn_attrs_group = {
632c91746a2SIrina Tirdea .attrs = bmc150_magn_attributes,
633c91746a2SIrina Tirdea };
634c91746a2SIrina Tirdea
635c91746a2SIrina Tirdea #define BMC150_MAGN_CHANNEL(_axis) { \
636c91746a2SIrina Tirdea .type = IIO_MAGN, \
637c91746a2SIrina Tirdea .modified = 1, \
638c91746a2SIrina Tirdea .channel2 = IIO_MOD_##_axis, \
6395990dc97SIrina Tirdea .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
6405990dc97SIrina Tirdea BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
641c91746a2SIrina Tirdea .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
642c91746a2SIrina Tirdea BIT(IIO_CHAN_INFO_SCALE), \
643c91746a2SIrina Tirdea .scan_index = AXIS_##_axis, \
644c91746a2SIrina Tirdea .scan_type = { \
645c91746a2SIrina Tirdea .sign = 's', \
646c91746a2SIrina Tirdea .realbits = 32, \
647c91746a2SIrina Tirdea .storagebits = 32, \
648c91746a2SIrina Tirdea .endianness = IIO_LE \
649c91746a2SIrina Tirdea }, \
650d9842c77SH. Nikolaus Schaller .ext_info = bmc150_magn_ext_info, \
651c91746a2SIrina Tirdea }
652c91746a2SIrina Tirdea
653c91746a2SIrina Tirdea static const struct iio_chan_spec bmc150_magn_channels[] = {
654c91746a2SIrina Tirdea BMC150_MAGN_CHANNEL(X),
655c91746a2SIrina Tirdea BMC150_MAGN_CHANNEL(Y),
656c91746a2SIrina Tirdea BMC150_MAGN_CHANNEL(Z),
657c91746a2SIrina Tirdea IIO_CHAN_SOFT_TIMESTAMP(3),
658c91746a2SIrina Tirdea };
659c91746a2SIrina Tirdea
660c91746a2SIrina Tirdea static const struct iio_info bmc150_magn_info = {
661c91746a2SIrina Tirdea .attrs = &bmc150_magn_attrs_group,
662c91746a2SIrina Tirdea .read_raw = bmc150_magn_read_raw,
663c91746a2SIrina Tirdea .write_raw = bmc150_magn_write_raw,
664c91746a2SIrina Tirdea };
665c91746a2SIrina Tirdea
66647764c79SHartmut Knaack static const unsigned long bmc150_magn_scan_masks[] = {
66747764c79SHartmut Knaack BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
66847764c79SHartmut Knaack 0};
669c91746a2SIrina Tirdea
bmc150_magn_trigger_handler(int irq,void * p)670c91746a2SIrina Tirdea static irqreturn_t bmc150_magn_trigger_handler(int irq, void *p)
671c91746a2SIrina Tirdea {
672c91746a2SIrina Tirdea struct iio_poll_func *pf = p;
673c91746a2SIrina Tirdea struct iio_dev *indio_dev = pf->indio_dev;
674c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
675c91746a2SIrina Tirdea int ret;
676c91746a2SIrina Tirdea
677c91746a2SIrina Tirdea mutex_lock(&data->mutex);
6787692088fSJonathan Cameron ret = bmc150_magn_read_xyz(data, data->scan.chans);
679c91746a2SIrina Tirdea if (ret < 0)
680c91746a2SIrina Tirdea goto err;
681c91746a2SIrina Tirdea
6827692088fSJonathan Cameron iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
683c91746a2SIrina Tirdea pf->timestamp);
684c91746a2SIrina Tirdea
685c91746a2SIrina Tirdea err:
6863021678aSHartmut Knaack mutex_unlock(&data->mutex);
6879d174b49SVlad Dogaru iio_trigger_notify_done(indio_dev->trig);
688c91746a2SIrina Tirdea
689c91746a2SIrina Tirdea return IRQ_HANDLED;
690c91746a2SIrina Tirdea }
691c91746a2SIrina Tirdea
bmc150_magn_init(struct bmc150_magn_data * data)692c91746a2SIrina Tirdea static int bmc150_magn_init(struct bmc150_magn_data *data)
693c91746a2SIrina Tirdea {
694c91746a2SIrina Tirdea int ret, chip_id;
695c91746a2SIrina Tirdea struct bmc150_magn_preset preset;
696c91746a2SIrina Tirdea
697cce4f160SStephan Gerhold ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
698cce4f160SStephan Gerhold data->regulators);
699cce4f160SStephan Gerhold if (ret < 0) {
700cce4f160SStephan Gerhold dev_err(data->dev, "Failed to enable regulators: %d\n", ret);
701cce4f160SStephan Gerhold return ret;
702cce4f160SStephan Gerhold }
703cce4f160SStephan Gerhold /*
704cce4f160SStephan Gerhold * 3ms power-on time according to datasheet, let's better
705cce4f160SStephan Gerhold * be safe than sorry and set this delay to 5ms.
706cce4f160SStephan Gerhold */
707cce4f160SStephan Gerhold msleep(5);
708cce4f160SStephan Gerhold
709c91746a2SIrina Tirdea ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND,
710c91746a2SIrina Tirdea false);
711c91746a2SIrina Tirdea if (ret < 0) {
712761b7910SDaniel Baluta dev_err(data->dev,
713c91746a2SIrina Tirdea "Failed to bring up device from suspend mode\n");
714cce4f160SStephan Gerhold goto err_regulator_disable;
715c91746a2SIrina Tirdea }
716c91746a2SIrina Tirdea
717c91746a2SIrina Tirdea ret = regmap_read(data->regmap, BMC150_MAGN_REG_CHIP_ID, &chip_id);
718c91746a2SIrina Tirdea if (ret < 0) {
719761b7910SDaniel Baluta dev_err(data->dev, "Failed reading chip id\n");
720c91746a2SIrina Tirdea goto err_poweroff;
721c91746a2SIrina Tirdea }
722c91746a2SIrina Tirdea if (chip_id != BMC150_MAGN_CHIP_ID_VAL) {
723761b7910SDaniel Baluta dev_err(data->dev, "Invalid chip id 0x%x\n", chip_id);
724c91746a2SIrina Tirdea ret = -ENODEV;
725c91746a2SIrina Tirdea goto err_poweroff;
726c91746a2SIrina Tirdea }
727761b7910SDaniel Baluta dev_dbg(data->dev, "Chip id %x\n", chip_id);
728c91746a2SIrina Tirdea
729c91746a2SIrina Tirdea preset = bmc150_magn_presets_table[BMC150_MAGN_DEFAULT_PRESET];
730c91746a2SIrina Tirdea ret = bmc150_magn_set_odr(data, preset.odr);
731c91746a2SIrina Tirdea if (ret < 0) {
732761b7910SDaniel Baluta dev_err(data->dev, "Failed to set ODR to %d\n",
733c91746a2SIrina Tirdea preset.odr);
734c91746a2SIrina Tirdea goto err_poweroff;
735c91746a2SIrina Tirdea }
736c91746a2SIrina Tirdea
737c91746a2SIrina Tirdea ret = regmap_write(data->regmap, BMC150_MAGN_REG_REP_XY,
738c91746a2SIrina Tirdea BMC150_MAGN_REPXY_TO_REGVAL(preset.rep_xy));
739c91746a2SIrina Tirdea if (ret < 0) {
740761b7910SDaniel Baluta dev_err(data->dev, "Failed to set REP XY to %d\n",
741c91746a2SIrina Tirdea preset.rep_xy);
742c91746a2SIrina Tirdea goto err_poweroff;
743c91746a2SIrina Tirdea }
744c91746a2SIrina Tirdea
745c91746a2SIrina Tirdea ret = regmap_write(data->regmap, BMC150_MAGN_REG_REP_Z,
746c91746a2SIrina Tirdea BMC150_MAGN_REPZ_TO_REGVAL(preset.rep_z));
747c91746a2SIrina Tirdea if (ret < 0) {
748761b7910SDaniel Baluta dev_err(data->dev, "Failed to set REP Z to %d\n",
749c91746a2SIrina Tirdea preset.rep_z);
750c91746a2SIrina Tirdea goto err_poweroff;
751c91746a2SIrina Tirdea }
752c91746a2SIrina Tirdea
7535990dc97SIrina Tirdea ret = bmc150_magn_set_max_odr(data, preset.rep_xy, preset.rep_z,
7545990dc97SIrina Tirdea preset.odr);
7555990dc97SIrina Tirdea if (ret < 0)
7565990dc97SIrina Tirdea goto err_poweroff;
7575990dc97SIrina Tirdea
758c91746a2SIrina Tirdea ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL,
759c91746a2SIrina Tirdea true);
760c91746a2SIrina Tirdea if (ret < 0) {
761761b7910SDaniel Baluta dev_err(data->dev, "Failed to power on device\n");
762c91746a2SIrina Tirdea goto err_poweroff;
763c91746a2SIrina Tirdea }
764c91746a2SIrina Tirdea
765c91746a2SIrina Tirdea return 0;
766c91746a2SIrina Tirdea
767c91746a2SIrina Tirdea err_poweroff:
768c91746a2SIrina Tirdea bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true);
769cce4f160SStephan Gerhold err_regulator_disable:
770cce4f160SStephan Gerhold regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators);
771c91746a2SIrina Tirdea return ret;
772c91746a2SIrina Tirdea }
773c91746a2SIrina Tirdea
bmc150_magn_reset_intr(struct bmc150_magn_data * data)774c91746a2SIrina Tirdea static int bmc150_magn_reset_intr(struct bmc150_magn_data *data)
775c91746a2SIrina Tirdea {
776c91746a2SIrina Tirdea int tmp;
777c91746a2SIrina Tirdea
778c91746a2SIrina Tirdea /*
779c91746a2SIrina Tirdea * Data Ready (DRDY) is always cleared after
780c91746a2SIrina Tirdea * readout of data registers ends.
781c91746a2SIrina Tirdea */
782c91746a2SIrina Tirdea return regmap_read(data->regmap, BMC150_MAGN_REG_X_L, &tmp);
783c91746a2SIrina Tirdea }
784c91746a2SIrina Tirdea
bmc150_magn_trig_reen(struct iio_trigger * trig)785eca8523aSJonathan Cameron static void bmc150_magn_trig_reen(struct iio_trigger *trig)
786c91746a2SIrina Tirdea {
787c91746a2SIrina Tirdea struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
788c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
789c91746a2SIrina Tirdea int ret;
790c91746a2SIrina Tirdea
791c91746a2SIrina Tirdea if (!data->dready_trigger_on)
792eca8523aSJonathan Cameron return;
793c91746a2SIrina Tirdea
794c91746a2SIrina Tirdea mutex_lock(&data->mutex);
795c91746a2SIrina Tirdea ret = bmc150_magn_reset_intr(data);
796c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
797eca8523aSJonathan Cameron if (ret)
798eca8523aSJonathan Cameron dev_err(data->dev, "Failed to reset interrupt\n");
799c91746a2SIrina Tirdea }
800c91746a2SIrina Tirdea
bmc150_magn_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)801c91746a2SIrina Tirdea static int bmc150_magn_data_rdy_trigger_set_state(struct iio_trigger *trig,
802c91746a2SIrina Tirdea bool state)
803c91746a2SIrina Tirdea {
804c91746a2SIrina Tirdea struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
805c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
806c91746a2SIrina Tirdea int ret = 0;
807c91746a2SIrina Tirdea
808c91746a2SIrina Tirdea mutex_lock(&data->mutex);
809c91746a2SIrina Tirdea if (state == data->dready_trigger_on)
810c91746a2SIrina Tirdea goto err_unlock;
811c91746a2SIrina Tirdea
812c91746a2SIrina Tirdea ret = regmap_update_bits(data->regmap, BMC150_MAGN_REG_INT_DRDY,
813c91746a2SIrina Tirdea BMC150_MAGN_MASK_DRDY_EN,
814c91746a2SIrina Tirdea state << BMC150_MAGN_SHIFT_DRDY_EN);
815c91746a2SIrina Tirdea if (ret < 0)
8165ab744d0SIrina Tirdea goto err_unlock;
817c91746a2SIrina Tirdea
818c91746a2SIrina Tirdea data->dready_trigger_on = state;
819c91746a2SIrina Tirdea
820c91746a2SIrina Tirdea if (state) {
821c91746a2SIrina Tirdea ret = bmc150_magn_reset_intr(data);
822c91746a2SIrina Tirdea if (ret < 0)
8235ab744d0SIrina Tirdea goto err_unlock;
824c91746a2SIrina Tirdea }
825c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
826c91746a2SIrina Tirdea
827c91746a2SIrina Tirdea return 0;
828c91746a2SIrina Tirdea
829c91746a2SIrina Tirdea err_unlock:
830c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
831c91746a2SIrina Tirdea return ret;
832c91746a2SIrina Tirdea }
833c91746a2SIrina Tirdea
834c91746a2SIrina Tirdea static const struct iio_trigger_ops bmc150_magn_trigger_ops = {
835c91746a2SIrina Tirdea .set_trigger_state = bmc150_magn_data_rdy_trigger_set_state,
836eca8523aSJonathan Cameron .reenable = bmc150_magn_trig_reen,
837c91746a2SIrina Tirdea };
838c91746a2SIrina Tirdea
bmc150_magn_buffer_preenable(struct iio_dev * indio_dev)8399d174b49SVlad Dogaru static int bmc150_magn_buffer_preenable(struct iio_dev *indio_dev)
8409d174b49SVlad Dogaru {
8419d174b49SVlad Dogaru struct bmc150_magn_data *data = iio_priv(indio_dev);
8429d174b49SVlad Dogaru
8439d174b49SVlad Dogaru return bmc150_magn_set_power_state(data, true);
8449d174b49SVlad Dogaru }
8459d174b49SVlad Dogaru
bmc150_magn_buffer_postdisable(struct iio_dev * indio_dev)8469d174b49SVlad Dogaru static int bmc150_magn_buffer_postdisable(struct iio_dev *indio_dev)
8479d174b49SVlad Dogaru {
8489d174b49SVlad Dogaru struct bmc150_magn_data *data = iio_priv(indio_dev);
8499d174b49SVlad Dogaru
8509d174b49SVlad Dogaru return bmc150_magn_set_power_state(data, false);
8519d174b49SVlad Dogaru }
8529d174b49SVlad Dogaru
8539d174b49SVlad Dogaru static const struct iio_buffer_setup_ops bmc150_magn_buffer_setup_ops = {
8549d174b49SVlad Dogaru .preenable = bmc150_magn_buffer_preenable,
8559d174b49SVlad Dogaru .postdisable = bmc150_magn_buffer_postdisable,
8569d174b49SVlad Dogaru };
8579d174b49SVlad Dogaru
bmc150_magn_match_acpi_device(struct device * dev)858c91746a2SIrina Tirdea static const char *bmc150_magn_match_acpi_device(struct device *dev)
859c91746a2SIrina Tirdea {
860c91746a2SIrina Tirdea const struct acpi_device_id *id;
861c91746a2SIrina Tirdea
862c91746a2SIrina Tirdea id = acpi_match_device(dev->driver->acpi_match_table, dev);
863c91746a2SIrina Tirdea if (!id)
864c91746a2SIrina Tirdea return NULL;
865c91746a2SIrina Tirdea
866c91746a2SIrina Tirdea return dev_name(dev);
867c91746a2SIrina Tirdea }
868c91746a2SIrina Tirdea
bmc150_magn_probe(struct device * dev,struct regmap * regmap,int irq,const char * name)869761b7910SDaniel Baluta int bmc150_magn_probe(struct device *dev, struct regmap *regmap,
870761b7910SDaniel Baluta int irq, const char *name)
871c91746a2SIrina Tirdea {
872c91746a2SIrina Tirdea struct bmc150_magn_data *data;
873c91746a2SIrina Tirdea struct iio_dev *indio_dev;
874c91746a2SIrina Tirdea int ret;
875c91746a2SIrina Tirdea
876761b7910SDaniel Baluta indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
877c91746a2SIrina Tirdea if (!indio_dev)
878c91746a2SIrina Tirdea return -ENOMEM;
879c91746a2SIrina Tirdea
880c91746a2SIrina Tirdea data = iio_priv(indio_dev);
881761b7910SDaniel Baluta dev_set_drvdata(dev, indio_dev);
882761b7910SDaniel Baluta data->regmap = regmap;
883761b7910SDaniel Baluta data->irq = irq;
884761b7910SDaniel Baluta data->dev = dev;
885c91746a2SIrina Tirdea
886cce4f160SStephan Gerhold data->regulators[0].supply = "vdd";
887cce4f160SStephan Gerhold data->regulators[1].supply = "vddio";
888cce4f160SStephan Gerhold ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(data->regulators),
889cce4f160SStephan Gerhold data->regulators);
890cce4f160SStephan Gerhold if (ret)
891cce4f160SStephan Gerhold return dev_err_probe(dev, ret, "failed to get regulators\n");
892cce4f160SStephan Gerhold
893b892770aSAndy Shevchenko ret = iio_read_mount_matrix(dev, &data->orientation);
894d9842c77SH. Nikolaus Schaller if (ret)
895d9842c77SH. Nikolaus Schaller return ret;
896d9842c77SH. Nikolaus Schaller
897761b7910SDaniel Baluta if (!name && ACPI_HANDLE(dev))
898761b7910SDaniel Baluta name = bmc150_magn_match_acpi_device(dev);
899c91746a2SIrina Tirdea
900c91746a2SIrina Tirdea mutex_init(&data->mutex);
901c91746a2SIrina Tirdea
902c91746a2SIrina Tirdea ret = bmc150_magn_init(data);
903c91746a2SIrina Tirdea if (ret < 0)
904c91746a2SIrina Tirdea return ret;
905c91746a2SIrina Tirdea
906c91746a2SIrina Tirdea indio_dev->channels = bmc150_magn_channels;
907c91746a2SIrina Tirdea indio_dev->num_channels = ARRAY_SIZE(bmc150_magn_channels);
908c91746a2SIrina Tirdea indio_dev->available_scan_masks = bmc150_magn_scan_masks;
909c91746a2SIrina Tirdea indio_dev->name = name;
910c91746a2SIrina Tirdea indio_dev->modes = INDIO_DIRECT_MODE;
911c91746a2SIrina Tirdea indio_dev->info = &bmc150_magn_info;
912c91746a2SIrina Tirdea
913761b7910SDaniel Baluta if (irq > 0) {
914761b7910SDaniel Baluta data->dready_trig = devm_iio_trigger_alloc(dev,
915c91746a2SIrina Tirdea "%s-dev%d",
916c91746a2SIrina Tirdea indio_dev->name,
91715ea2878SJonathan Cameron iio_device_id(indio_dev));
918c91746a2SIrina Tirdea if (!data->dready_trig) {
919c91746a2SIrina Tirdea ret = -ENOMEM;
920761b7910SDaniel Baluta dev_err(dev, "iio trigger alloc failed\n");
921c91746a2SIrina Tirdea goto err_poweroff;
922c91746a2SIrina Tirdea }
923c91746a2SIrina Tirdea
924c91746a2SIrina Tirdea data->dready_trig->ops = &bmc150_magn_trigger_ops;
925c91746a2SIrina Tirdea iio_trigger_set_drvdata(data->dready_trig, indio_dev);
926c91746a2SIrina Tirdea ret = iio_trigger_register(data->dready_trig);
927c91746a2SIrina Tirdea if (ret) {
928761b7910SDaniel Baluta dev_err(dev, "iio trigger register failed\n");
929c91746a2SIrina Tirdea goto err_poweroff;
930c91746a2SIrina Tirdea }
931c91746a2SIrina Tirdea
932761b7910SDaniel Baluta ret = request_threaded_irq(irq,
933c91746a2SIrina Tirdea iio_trigger_generic_data_rdy_poll,
934c91746a2SIrina Tirdea NULL,
935c91746a2SIrina Tirdea IRQF_TRIGGER_RISING | IRQF_ONESHOT,
936c91746a2SIrina Tirdea BMC150_MAGN_IRQ_NAME,
937c91746a2SIrina Tirdea data->dready_trig);
938c91746a2SIrina Tirdea if (ret < 0) {
939761b7910SDaniel Baluta dev_err(dev, "request irq %d failed\n", irq);
9409d174b49SVlad Dogaru goto err_trigger_unregister;
941c91746a2SIrina Tirdea }
942c91746a2SIrina Tirdea }
943c91746a2SIrina Tirdea
9449d174b49SVlad Dogaru ret = iio_triggered_buffer_setup(indio_dev,
9459d174b49SVlad Dogaru iio_pollfunc_store_time,
9469d174b49SVlad Dogaru bmc150_magn_trigger_handler,
9479d174b49SVlad Dogaru &bmc150_magn_buffer_setup_ops);
9489d174b49SVlad Dogaru if (ret < 0) {
949761b7910SDaniel Baluta dev_err(dev, "iio triggered buffer setup failed\n");
9509d174b49SVlad Dogaru goto err_free_irq;
9519d174b49SVlad Dogaru }
9529d174b49SVlad Dogaru
953761b7910SDaniel Baluta ret = pm_runtime_set_active(dev);
954c91746a2SIrina Tirdea if (ret)
9557d0ead5cSAdriana Reus goto err_buffer_cleanup;
956c91746a2SIrina Tirdea
957761b7910SDaniel Baluta pm_runtime_enable(dev);
958761b7910SDaniel Baluta pm_runtime_set_autosuspend_delay(dev,
959c91746a2SIrina Tirdea BMC150_MAGN_AUTO_SUSPEND_DELAY_MS);
960761b7910SDaniel Baluta pm_runtime_use_autosuspend(dev);
961c91746a2SIrina Tirdea
9627d0ead5cSAdriana Reus ret = iio_device_register(indio_dev);
9637d0ead5cSAdriana Reus if (ret < 0) {
964761b7910SDaniel Baluta dev_err(dev, "unable to register iio device\n");
965632fe0bbSMiaoqian Lin goto err_pm_cleanup;
9667d0ead5cSAdriana Reus }
967c91746a2SIrina Tirdea
968761b7910SDaniel Baluta dev_dbg(dev, "Registered device %s\n", name);
969c91746a2SIrina Tirdea return 0;
970c91746a2SIrina Tirdea
971632fe0bbSMiaoqian Lin err_pm_cleanup:
972632fe0bbSMiaoqian Lin pm_runtime_dont_use_autosuspend(dev);
973264da512SJonathan Cameron pm_runtime_disable(dev);
9749d174b49SVlad Dogaru err_buffer_cleanup:
9759d174b49SVlad Dogaru iio_triggered_buffer_cleanup(indio_dev);
976c91746a2SIrina Tirdea err_free_irq:
977761b7910SDaniel Baluta if (irq > 0)
978761b7910SDaniel Baluta free_irq(irq, data->dready_trig);
979c91746a2SIrina Tirdea err_trigger_unregister:
980c91746a2SIrina Tirdea if (data->dready_trig)
981c91746a2SIrina Tirdea iio_trigger_unregister(data->dready_trig);
982c91746a2SIrina Tirdea err_poweroff:
983c91746a2SIrina Tirdea bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true);
984c91746a2SIrina Tirdea return ret;
985c91746a2SIrina Tirdea }
98647d6cae0SJonathan Cameron EXPORT_SYMBOL_NS(bmc150_magn_probe, IIO_BMC150_MAGN);
987c91746a2SIrina Tirdea
bmc150_magn_remove(struct device * dev)988*d04d46ddSUwe Kleine-König void bmc150_magn_remove(struct device *dev)
989c91746a2SIrina Tirdea {
990761b7910SDaniel Baluta struct iio_dev *indio_dev = dev_get_drvdata(dev);
991c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
992c91746a2SIrina Tirdea
9937d0ead5cSAdriana Reus iio_device_unregister(indio_dev);
9947d0ead5cSAdriana Reus
995761b7910SDaniel Baluta pm_runtime_disable(dev);
996761b7910SDaniel Baluta pm_runtime_set_suspended(dev);
997c91746a2SIrina Tirdea
9989d174b49SVlad Dogaru iio_triggered_buffer_cleanup(indio_dev);
999c91746a2SIrina Tirdea
1000761b7910SDaniel Baluta if (data->irq > 0)
1001761b7910SDaniel Baluta free_irq(data->irq, data->dready_trig);
1002c91746a2SIrina Tirdea
10039d174b49SVlad Dogaru if (data->dready_trig)
1004c91746a2SIrina Tirdea iio_trigger_unregister(data->dready_trig);
1005c91746a2SIrina Tirdea
1006c91746a2SIrina Tirdea mutex_lock(&data->mutex);
1007c91746a2SIrina Tirdea bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true);
1008c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
1009c91746a2SIrina Tirdea
1010cce4f160SStephan Gerhold regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators);
1011c91746a2SIrina Tirdea }
101247d6cae0SJonathan Cameron EXPORT_SYMBOL_NS(bmc150_magn_remove, IIO_BMC150_MAGN);
1013c91746a2SIrina Tirdea
1014c91746a2SIrina Tirdea #ifdef CONFIG_PM
bmc150_magn_runtime_suspend(struct device * dev)1015c91746a2SIrina Tirdea static int bmc150_magn_runtime_suspend(struct device *dev)
1016c91746a2SIrina Tirdea {
1017761b7910SDaniel Baluta struct iio_dev *indio_dev = dev_get_drvdata(dev);
1018c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
1019c91746a2SIrina Tirdea int ret;
1020c91746a2SIrina Tirdea
1021c91746a2SIrina Tirdea mutex_lock(&data->mutex);
1022c91746a2SIrina Tirdea ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SLEEP,
1023c91746a2SIrina Tirdea true);
1024c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
1025c91746a2SIrina Tirdea if (ret < 0) {
1026761b7910SDaniel Baluta dev_err(dev, "powering off device failed\n");
1027c91746a2SIrina Tirdea return ret;
1028c91746a2SIrina Tirdea }
1029c91746a2SIrina Tirdea return 0;
1030c91746a2SIrina Tirdea }
1031c91746a2SIrina Tirdea
1032019cc46dSIrina Tirdea /*
1033019cc46dSIrina Tirdea * Should be called with data->mutex held.
1034019cc46dSIrina Tirdea */
bmc150_magn_runtime_resume(struct device * dev)1035c91746a2SIrina Tirdea static int bmc150_magn_runtime_resume(struct device *dev)
1036c91746a2SIrina Tirdea {
1037761b7910SDaniel Baluta struct iio_dev *indio_dev = dev_get_drvdata(dev);
1038c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
1039c91746a2SIrina Tirdea
1040c91746a2SIrina Tirdea return bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL,
1041c91746a2SIrina Tirdea true);
1042c91746a2SIrina Tirdea }
1043c91746a2SIrina Tirdea #endif
1044c91746a2SIrina Tirdea
1045c91746a2SIrina Tirdea #ifdef CONFIG_PM_SLEEP
bmc150_magn_suspend(struct device * dev)1046c91746a2SIrina Tirdea static int bmc150_magn_suspend(struct device *dev)
1047c91746a2SIrina Tirdea {
1048761b7910SDaniel Baluta struct iio_dev *indio_dev = dev_get_drvdata(dev);
1049c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
1050c91746a2SIrina Tirdea int ret;
1051c91746a2SIrina Tirdea
1052c91746a2SIrina Tirdea mutex_lock(&data->mutex);
1053c91746a2SIrina Tirdea ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SLEEP,
1054c91746a2SIrina Tirdea true);
1055c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
1056c91746a2SIrina Tirdea
1057c91746a2SIrina Tirdea return ret;
1058c91746a2SIrina Tirdea }
1059c91746a2SIrina Tirdea
bmc150_magn_resume(struct device * dev)1060c91746a2SIrina Tirdea static int bmc150_magn_resume(struct device *dev)
1061c91746a2SIrina Tirdea {
1062761b7910SDaniel Baluta struct iio_dev *indio_dev = dev_get_drvdata(dev);
1063c91746a2SIrina Tirdea struct bmc150_magn_data *data = iio_priv(indio_dev);
1064c91746a2SIrina Tirdea int ret;
1065c91746a2SIrina Tirdea
1066c91746a2SIrina Tirdea mutex_lock(&data->mutex);
1067c91746a2SIrina Tirdea ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL,
1068c91746a2SIrina Tirdea true);
1069c91746a2SIrina Tirdea mutex_unlock(&data->mutex);
1070c91746a2SIrina Tirdea
1071c91746a2SIrina Tirdea return ret;
1072c91746a2SIrina Tirdea }
1073c91746a2SIrina Tirdea #endif
1074c91746a2SIrina Tirdea
1075761b7910SDaniel Baluta const struct dev_pm_ops bmc150_magn_pm_ops = {
1076c91746a2SIrina Tirdea SET_SYSTEM_SLEEP_PM_OPS(bmc150_magn_suspend, bmc150_magn_resume)
1077c91746a2SIrina Tirdea SET_RUNTIME_PM_OPS(bmc150_magn_runtime_suspend,
1078c91746a2SIrina Tirdea bmc150_magn_runtime_resume, NULL)
1079c91746a2SIrina Tirdea };
108047d6cae0SJonathan Cameron EXPORT_SYMBOL_NS(bmc150_magn_pm_ops, IIO_BMC150_MAGN);
1081c91746a2SIrina Tirdea
1082c91746a2SIrina Tirdea MODULE_AUTHOR("Irina Tirdea <irina.tirdea@intel.com>");
1083c91746a2SIrina Tirdea MODULE_LICENSE("GPL v2");
1084761b7910SDaniel Baluta MODULE_DESCRIPTION("BMC150 magnetometer core driver");
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