1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * tcs3472.c - Support for TAOS TCS3472 color light-to-digital converter 4 * 5 * Copyright (c) 2013 Peter Meerwald <pmeerw@pmeerw.net> 6 * 7 * Color light sensor with 16-bit channels for red, green, blue, clear); 8 * 7-bit I2C slave address 0x39 (TCS34721, TCS34723) or 0x29 (TCS34725, 9 * TCS34727) 10 * 11 * Datasheet: http://ams.com/eng/content/download/319364/1117183/file/TCS3472_Datasheet_EN_v2.pdf 12 */ 13 14 #include <linux/cleanup.h> 15 #include <linux/delay.h> 16 #include <linux/i2c.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/pm.h> 20 #include <linux/units.h> 21 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/events.h> 24 #include <linux/iio/iio.h> 25 #include <linux/iio/sysfs.h> 26 #include <linux/iio/trigger_consumer.h> 27 #include <linux/iio/triggered_buffer.h> 28 29 #define TCS3472_DRV_NAME "tcs3472" 30 31 #define TCS3472_COMMAND BIT(7) 32 #define TCS3472_AUTO_INCR BIT(5) 33 #define TCS3472_SPECIAL_FUNC (BIT(5) | BIT(6)) 34 35 #define TCS3472_INTR_CLEAR (TCS3472_COMMAND | TCS3472_SPECIAL_FUNC | 0x06) 36 37 #define TCS3472_ENABLE (TCS3472_COMMAND | 0x00) 38 #define TCS3472_ATIME (TCS3472_COMMAND | 0x01) 39 #define TCS3472_WTIME (TCS3472_COMMAND | 0x03) 40 #define TCS3472_AILT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x04) 41 #define TCS3472_AIHT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x06) 42 #define TCS3472_PERS (TCS3472_COMMAND | 0x0c) 43 #define TCS3472_CONFIG (TCS3472_COMMAND | 0x0d) 44 #define TCS3472_CONTROL (TCS3472_COMMAND | 0x0f) 45 #define TCS3472_ID (TCS3472_COMMAND | 0x12) 46 #define TCS3472_STATUS (TCS3472_COMMAND | 0x13) 47 #define TCS3472_CDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x14) 48 #define TCS3472_RDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x16) 49 #define TCS3472_GDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x18) 50 #define TCS3472_BDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x1a) 51 52 #define TCS3472_STATUS_AINT BIT(4) 53 #define TCS3472_STATUS_AVALID BIT(0) 54 #define TCS3472_ENABLE_AIEN BIT(4) 55 #define TCS3472_ENABLE_WEN BIT(3) 56 #define TCS3472_ENABLE_AEN BIT(1) 57 #define TCS3472_ENABLE_PON BIT(0) 58 #define TCS3472_ENABLE_RUN \ 59 (TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON | TCS3472_ENABLE_WEN) 60 #define TCS3472_CONTROL_AGAIN_MASK (BIT(0) | BIT(1)) 61 #define TCS3472_CONFIG_WLONG BIT(1) 62 63 #define TCS3472_ATIME_TO_US(atime) (((256) - (atime)) * 2400) 64 65 struct tcs3472_data { 66 struct i2c_client *client; 67 struct mutex lock; 68 int target_freq_hz; 69 int target_freq_uhz; 70 u16 low_thresh; 71 u16 high_thresh; 72 u8 enable; 73 u8 enable_pre_suspend; 74 u8 control; 75 u8 atime; 76 u8 apers; 77 u8 wtime; 78 bool wlong; 79 }; 80 81 static const struct iio_event_spec tcs3472_events[] = { 82 { 83 .type = IIO_EV_TYPE_THRESH, 84 .dir = IIO_EV_DIR_RISING, 85 .mask_separate = BIT(IIO_EV_INFO_VALUE), 86 }, { 87 .type = IIO_EV_TYPE_THRESH, 88 .dir = IIO_EV_DIR_FALLING, 89 .mask_separate = BIT(IIO_EV_INFO_VALUE), 90 }, { 91 .type = IIO_EV_TYPE_THRESH, 92 .dir = IIO_EV_DIR_EITHER, 93 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | 94 BIT(IIO_EV_INFO_PERIOD), 95 }, 96 }; 97 98 #define TCS3472_CHANNEL(_color, _si, _addr) { \ 99 .type = IIO_INTENSITY, \ 100 .modified = 1, \ 101 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 102 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBSCALE) | \ 103 BIT(IIO_CHAN_INFO_INT_TIME), \ 104 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 105 .channel2 = IIO_MOD_LIGHT_##_color, \ 106 .address = _addr, \ 107 .scan_index = _si, \ 108 .scan_type = { \ 109 .sign = 'u', \ 110 .realbits = 16, \ 111 .storagebits = 16, \ 112 .endianness = IIO_CPU, \ 113 }, \ 114 .event_spec = _si ? NULL : tcs3472_events, \ 115 .num_event_specs = _si ? 0 : ARRAY_SIZE(tcs3472_events), \ 116 } 117 118 static const int tcs3472_agains[] = { 1, 4, 16, 60 }; 119 120 static const struct iio_chan_spec tcs3472_channels[] = { 121 TCS3472_CHANNEL(CLEAR, 0, TCS3472_CDATA), 122 TCS3472_CHANNEL(RED, 1, TCS3472_RDATA), 123 TCS3472_CHANNEL(GREEN, 2, TCS3472_GDATA), 124 TCS3472_CHANNEL(BLUE, 3, TCS3472_BDATA), 125 IIO_CHAN_SOFT_TIMESTAMP(4), 126 }; 127 128 /* 129 * The chip's cycle time is the sum of three components: 130 * - ATIME: the programmable RGBC integration time. 131 * - The fixed RGBC initialization time (2400 us). 132 * - WTIME: the wait time, used only if WEN is set. If WLONG is active, 133 * the wait step is multiplied by 12 (2400 us -> 28800 us). 134 */ 135 static unsigned int tcs3472_cycle_time_us(struct tcs3472_data *data) 136 { 137 unsigned int atime_us = TCS3472_ATIME_TO_US(data->atime); 138 unsigned int init_us = 2400; 139 unsigned int wtime_us; 140 141 if (!(data->enable & TCS3472_ENABLE_WEN)) 142 wtime_us = 0; 143 else if (data->wlong) 144 wtime_us = (256 - data->wtime) * 28800; 145 else 146 wtime_us = (256 - data->wtime) * 2400; 147 148 return atime_us + init_us + wtime_us; 149 } 150 151 /* 152 * Convert a cycle time in microseconds to a frequency in Hz and microhertz. 153 * 154 * Given cycle_us = T (the cycle period in microseconds), the corresponding 155 * frequency is: 156 * f = 1e6 / T [Hz] 157 * 158 * The result is split into the IIO_VAL_INT_PLUS_MICRO format: 159 * val = floor(1e6 / T) [Hz] 160 * val2 = (1e6 mod T) * 1e6 / T [microhertz] 161 */ 162 static void tcs3472_cycle_to_freq(unsigned int cycle_us, int *val, int *val2) 163 { 164 *val = USEC_PER_SEC / cycle_us; 165 *val2 = div_u64((u64)(USEC_PER_SEC % cycle_us) * USEC_PER_SEC, 166 cycle_us); 167 } 168 169 static int tcs3472_req_data(struct tcs3472_data *data) 170 { 171 /* 172 * The worst-case cycle time is reached with ATIME=0x00, WTIME=0x00 173 * and WLONG=1. So: 174 * 614 ms (Max Integration Time) 175 * + 2.4 ms (RGBC Init) 176 * + 7.37 s (Max Wait Time) 177 * = ~ 8 s (Total Max cycle time). 178 * Use that as a polling upper bound; in normal operation the loop 179 * exits as soon as AVALID is set. So the total number of tries in 8 180 * seconds considering a polling period of 20 ms is 400. 181 * Considering a 20% margin due to oscillator tolerance, the total 182 * duration becomes approximately 9.8 seconds, which corresponds to 183 * about 480 steps. Therefore, setting it to 500 appears to be a 184 * reasonable and safe trade-off. 185 */ 186 int tries = 500; 187 int ret; 188 189 while (tries--) { 190 ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS); 191 if (ret < 0) 192 return ret; 193 if (ret & TCS3472_STATUS_AVALID) 194 break; 195 msleep(20); 196 } 197 198 if (tries < 0) { 199 dev_err(&data->client->dev, "data not ready\n"); 200 return -EIO; 201 } 202 203 return 0; 204 } 205 206 static int tcs3472_read_raw(struct iio_dev *indio_dev, 207 struct iio_chan_spec const *chan, 208 int *val, int *val2, long mask) 209 { 210 struct tcs3472_data *data = iio_priv(indio_dev); 211 int ret; 212 213 switch (mask) { 214 case IIO_CHAN_INFO_RAW: 215 if (!iio_device_claim_direct(indio_dev)) 216 return -EBUSY; 217 ret = tcs3472_req_data(data); 218 if (ret < 0) { 219 iio_device_release_direct(indio_dev); 220 return ret; 221 } 222 ret = i2c_smbus_read_word_data(data->client, chan->address); 223 iio_device_release_direct(indio_dev); 224 if (ret < 0) 225 return ret; 226 *val = ret; 227 return IIO_VAL_INT; 228 case IIO_CHAN_INFO_CALIBSCALE: 229 *val = tcs3472_agains[data->control & 230 TCS3472_CONTROL_AGAIN_MASK]; 231 return IIO_VAL_INT; 232 case IIO_CHAN_INFO_INT_TIME: 233 *val = 0; 234 *val2 = TCS3472_ATIME_TO_US(data->atime); 235 return IIO_VAL_INT_PLUS_MICRO; 236 case IIO_CHAN_INFO_SAMP_FREQ: { 237 unsigned int cycle_us; 238 239 guard(mutex)(&data->lock); 240 cycle_us = tcs3472_cycle_time_us(data); 241 tcs3472_cycle_to_freq(cycle_us, val, val2); 242 return IIO_VAL_INT_PLUS_MICRO; 243 } 244 default: 245 return -EINVAL; 246 } 247 } 248 249 /* 250 * __tcs3472_set_sampling_freq() - implementation of sampling frequency 251 * configuration. The caller must hold data->lock. 252 */ 253 static int __tcs3472_set_sampling_freq(struct tcs3472_data *data, 254 int val, int val2) 255 { 256 unsigned int atime_us; 257 unsigned int init_us = 2400; 258 u64 cycle_us; 259 s64 wait_us; 260 int wtime; 261 bool wlong = false; 262 u8 config; 263 int ret; 264 265 if (val < 0 || val2 < 0 || (val == 0 && val2 == 0)) 266 return -EINVAL; 267 268 atime_us = TCS3472_ATIME_TO_US(data->atime); 269 270 /* 271 * cycle_us = 1 / freq, expressed in microseconds. 272 * Numerator: 1 [s] = PSEC_PER_SEC [ps] 273 * Denominator: freq [Hz] * MICROHZ_PER_HZ + val2 [uHz] = freq in [uHz] 274 * Result: ps / uHz = us 275 */ 276 cycle_us = div64_u64(PSEC_PER_SEC, (u64)val * MICROHZ_PER_HZ + val2); 277 278 /* 279 * wait_us can be negative when the requested frequency is too high 280 * to be reached, or very large when the requested frequency is 281 * close to zero. Use s64 to cover the full range: 282 * 283 * cycle_us = PSEC_PER_SEC / (val * MICROHZ_PER_HZ + val2) 284 * 285 * The divisor of the formula above reaches its maximum when 286 * val = val2 = INT_MAX: 287 * INT_MAX * MICROHZ_PER_HZ + INT_MAX = ~2.15e18 288 * so cycle_us_min = floor(1e12 / 2.15e18) = 0. 289 * 290 * The divisor reaches its minimum (1) when val = 0 and val2 = 1, 291 * so cycle_us_max = 1e12 / 1 = 1e12. 292 * 293 * Therefore: 294 * wait_us_min = 0 - 2400 - 612000 = -616800 295 * wait_us_max = 1e12 - 2400 - 2400 = 999999995200 296 * 297 * Both fit comfortably in s64. 298 */ 299 wait_us = (s64)cycle_us - init_us - atime_us; 300 if (wait_us < 2400) { 301 if (data->enable & TCS3472_ENABLE_WEN) { 302 u8 enable = data->enable & ~TCS3472_ENABLE_WEN; 303 304 ret = i2c_smbus_write_byte_data(data->client, 305 TCS3472_ENABLE, enable); 306 if (ret) 307 return ret; 308 309 data->enable = enable; 310 } 311 312 data->target_freq_hz = val; 313 data->target_freq_uhz = val2; 314 return 0; 315 } 316 317 /* 318 * Wait state is needed: make sure WEN is active before programming 319 * WTIME (and possibly WLONG). 320 */ 321 if (!(data->enable & TCS3472_ENABLE_WEN)) { 322 u8 enable = data->enable | TCS3472_ENABLE_WEN; 323 324 ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, 325 enable); 326 if (ret) 327 return ret; 328 329 data->enable = enable; 330 } 331 332 wtime = 256 - DIV_ROUND_CLOSEST_ULL(wait_us, 2400); 333 if (wtime < 0) { 334 /* 335 * If wait_us is too high (so the requested frequency is too 336 * low), the resulting wait exceeds what WTIME can represent 337 * (max 614 ms without WLONG). Enable WLONG, whose step is 12x 338 * longer (28.8 ms instead of 2.4 ms), and recompute. 339 */ 340 wlong = true; 341 wtime = 256 - DIV_ROUND_CLOSEST_ULL(wait_us, 28800); 342 } 343 344 if (wlong != data->wlong) { 345 ret = i2c_smbus_read_byte_data(data->client, TCS3472_CONFIG); 346 if (ret < 0) 347 return ret; 348 349 config = ret; 350 if (wlong) 351 config |= TCS3472_CONFIG_WLONG; 352 else 353 config &= ~TCS3472_CONFIG_WLONG; 354 355 ret = i2c_smbus_write_byte_data(data->client, TCS3472_CONFIG, 356 config); 357 if (ret) 358 return ret; 359 360 data->wlong = wlong; 361 } 362 363 /* 364 * If the requested wait is so long that even WLONG cannot 365 * cover it, wtime may still be negative. Saturate to 0, 366 * which is the largest possible wait (256 * 28.8 ms = 7.37 s). 367 */ 368 wtime = clamp(wtime, 0, 255); 369 ret = i2c_smbus_write_byte_data(data->client, TCS3472_WTIME, wtime); 370 if (ret) 371 return ret; 372 373 data->wtime = wtime; 374 data->target_freq_hz = val; 375 data->target_freq_uhz = val2; 376 377 return 0; 378 } 379 380 static int tcs3472_set_sampling_freq(struct tcs3472_data *data, 381 int val, int val2) 382 { 383 guard(mutex)(&data->lock); 384 return __tcs3472_set_sampling_freq(data, val, val2); 385 } 386 387 static int tcs3472_write_raw(struct iio_dev *indio_dev, 388 struct iio_chan_spec const *chan, 389 int val, int val2, long mask) 390 { 391 struct tcs3472_data *data = iio_priv(indio_dev); 392 int ret; 393 int i; 394 395 switch (mask) { 396 case IIO_CHAN_INFO_CALIBSCALE: 397 if (val2 != 0) 398 return -EINVAL; 399 for (i = 0; i < ARRAY_SIZE(tcs3472_agains); i++) { 400 if (val == tcs3472_agains[i]) { 401 data->control &= ~TCS3472_CONTROL_AGAIN_MASK; 402 data->control |= i; 403 return i2c_smbus_write_byte_data( 404 data->client, TCS3472_CONTROL, 405 data->control); 406 } 407 } 408 return -EINVAL; 409 case IIO_CHAN_INFO_INT_TIME: 410 if (val != 0) 411 return -EINVAL; 412 for (i = 0; i < 256; i++) { 413 if (val2 != (256 - i) * 2400) 414 continue; 415 416 guard(mutex)(&data->lock); 417 418 ret = i2c_smbus_write_byte_data(data->client, 419 TCS3472_ATIME, i); 420 if (ret) 421 return ret; 422 423 data->atime = i; 424 425 /* 426 * ATIME just changed, so the cycle time changed too. 427 * Re-run the sampling frequency logic to recompute 428 * WTIME and preserve the user's last requested 429 * frequency. Lock is already held. 430 */ 431 return __tcs3472_set_sampling_freq(data, 432 data->target_freq_hz, 433 data->target_freq_uhz); 434 } 435 return -EINVAL; 436 case IIO_CHAN_INFO_SAMP_FREQ: 437 return tcs3472_set_sampling_freq(data, val, val2); 438 default: 439 return -EINVAL; 440 } 441 } 442 443 /* 444 * Translation from APERS field value to the number of consecutive out-of-range 445 * clear channel values before an interrupt is generated 446 */ 447 static const int tcs3472_intr_pers[] = { 448 0, 1, 2, 3, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60 449 }; 450 451 static int tcs3472_read_event(struct iio_dev *indio_dev, 452 const struct iio_chan_spec *chan, enum iio_event_type type, 453 enum iio_event_direction dir, enum iio_event_info info, int *val, 454 int *val2) 455 { 456 struct tcs3472_data *data = iio_priv(indio_dev); 457 unsigned int period; 458 459 guard(mutex)(&data->lock); 460 461 switch (info) { 462 case IIO_EV_INFO_VALUE: 463 *val = (dir == IIO_EV_DIR_RISING) ? 464 data->high_thresh : data->low_thresh; 465 return IIO_VAL_INT; 466 case IIO_EV_INFO_PERIOD: 467 period = tcs3472_cycle_time_us(data) * 468 tcs3472_intr_pers[data->apers]; 469 *val = period / USEC_PER_SEC; 470 *val2 = period % USEC_PER_SEC; 471 return IIO_VAL_INT_PLUS_MICRO; 472 default: 473 return -EINVAL; 474 } 475 } 476 477 static int tcs3472_write_event(struct iio_dev *indio_dev, 478 const struct iio_chan_spec *chan, enum iio_event_type type, 479 enum iio_event_direction dir, enum iio_event_info info, int val, 480 int val2) 481 { 482 struct tcs3472_data *data = iio_priv(indio_dev); 483 int ret; 484 u8 command; 485 int period; 486 int i; 487 488 guard(mutex)(&data->lock); 489 490 switch (info) { 491 case IIO_EV_INFO_VALUE: 492 switch (dir) { 493 case IIO_EV_DIR_RISING: 494 command = TCS3472_AIHT; 495 break; 496 case IIO_EV_DIR_FALLING: 497 command = TCS3472_AILT; 498 break; 499 default: 500 return -EINVAL; 501 } 502 ret = i2c_smbus_write_word_data(data->client, command, val); 503 if (ret) 504 return ret; 505 506 if (dir == IIO_EV_DIR_RISING) 507 data->high_thresh = val; 508 else 509 data->low_thresh = val; 510 511 return 0; 512 case IIO_EV_INFO_PERIOD:{ 513 unsigned int cycle_us; 514 515 period = val * USEC_PER_SEC + val2; 516 cycle_us = tcs3472_cycle_time_us(data); 517 for (i = 1; i < ARRAY_SIZE(tcs3472_intr_pers) - 1; i++) { 518 if (period <= cycle_us * tcs3472_intr_pers[i]) 519 break; 520 } 521 ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS, i); 522 if (ret) 523 return ret; 524 525 data->apers = i; 526 527 return 0; 528 } 529 default: 530 return -EINVAL; 531 } 532 } 533 534 static int tcs3472_read_event_config(struct iio_dev *indio_dev, 535 const struct iio_chan_spec *chan, enum iio_event_type type, 536 enum iio_event_direction dir) 537 { 538 struct tcs3472_data *data = iio_priv(indio_dev); 539 540 guard(mutex)(&data->lock); 541 542 return (data->enable & TCS3472_ENABLE_AIEN) ? 1 : 0; 543 } 544 545 static int tcs3472_write_event_config(struct iio_dev *indio_dev, 546 const struct iio_chan_spec *chan, enum iio_event_type type, 547 enum iio_event_direction dir, bool state) 548 { 549 struct tcs3472_data *data = iio_priv(indio_dev); 550 int ret = 0; 551 u8 enable_old; 552 553 guard(mutex)(&data->lock); 554 555 enable_old = data->enable; 556 557 if (state) 558 data->enable |= TCS3472_ENABLE_AIEN; 559 else 560 data->enable &= ~TCS3472_ENABLE_AIEN; 561 562 if (enable_old != data->enable) { 563 ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, 564 data->enable); 565 if (ret) { 566 data->enable = enable_old; 567 return ret; 568 } 569 } 570 571 return 0; 572 } 573 574 static irqreturn_t tcs3472_event_handler(int irq, void *priv) 575 { 576 struct iio_dev *indio_dev = priv; 577 struct tcs3472_data *data = iio_priv(indio_dev); 578 int ret; 579 580 ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS); 581 if (ret >= 0 && (ret & TCS3472_STATUS_AINT)) { 582 iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0, 583 IIO_EV_TYPE_THRESH, 584 IIO_EV_DIR_EITHER), 585 iio_get_time_ns(indio_dev)); 586 587 i2c_smbus_read_byte_data(data->client, TCS3472_INTR_CLEAR); 588 } 589 590 return IRQ_HANDLED; 591 } 592 593 static irqreturn_t tcs3472_trigger_handler(int irq, void *p) 594 { 595 struct iio_poll_func *pf = p; 596 struct iio_dev *indio_dev = pf->indio_dev; 597 struct tcs3472_data *data = iio_priv(indio_dev); 598 int i, j = 0; 599 /* Ensure timestamp is naturally aligned */ 600 struct { 601 u16 chans[4]; 602 aligned_s64 timestamp; 603 } scan = { }; 604 605 int ret = tcs3472_req_data(data); 606 if (ret < 0) 607 goto done; 608 609 iio_for_each_active_channel(indio_dev, i) { 610 ret = i2c_smbus_read_word_data(data->client, 611 TCS3472_CDATA + 2*i); 612 if (ret < 0) 613 goto done; 614 615 scan.chans[j++] = ret; 616 } 617 618 iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan), 619 iio_get_time_ns(indio_dev)); 620 621 done: 622 iio_trigger_notify_done(indio_dev->trig); 623 624 return IRQ_HANDLED; 625 } 626 627 static ssize_t tcs3472_show_int_time_available(struct device *dev, 628 struct device_attribute *attr, 629 char *buf) 630 { 631 size_t len = 0; 632 int i; 633 634 for (i = 1; i <= 256; i++) 635 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06d ", 636 2400 * i); 637 638 /* replace trailing space by newline */ 639 buf[len - 1] = '\n'; 640 641 return len; 642 } 643 644 static IIO_CONST_ATTR(calibscale_available, "1 4 16 60"); 645 static IIO_DEV_ATTR_INT_TIME_AVAIL(tcs3472_show_int_time_available); 646 647 static struct attribute *tcs3472_attributes[] = { 648 &iio_const_attr_calibscale_available.dev_attr.attr, 649 &iio_dev_attr_integration_time_available.dev_attr.attr, 650 NULL 651 }; 652 653 static const struct attribute_group tcs3472_attribute_group = { 654 .attrs = tcs3472_attributes, 655 }; 656 657 static const struct iio_info tcs3472_info = { 658 .read_raw = tcs3472_read_raw, 659 .write_raw = tcs3472_write_raw, 660 .read_event_value = tcs3472_read_event, 661 .write_event_value = tcs3472_write_event, 662 .read_event_config = tcs3472_read_event_config, 663 .write_event_config = tcs3472_write_event_config, 664 .attrs = &tcs3472_attribute_group, 665 }; 666 667 static int tcs3472_powerdown(struct tcs3472_data *data) 668 { 669 int ret; 670 671 guard(mutex)(&data->lock); 672 673 data->enable_pre_suspend = data->enable; 674 675 ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, 676 data->enable & ~TCS3472_ENABLE_RUN); 677 if (ret) 678 return ret; 679 680 return 0; 681 } 682 683 static void tcs3472_powerdown_action(void *data) 684 { 685 tcs3472_powerdown(data); 686 } 687 688 static int tcs3472_probe(struct i2c_client *client) 689 { 690 struct device *dev = &client->dev; 691 struct tcs3472_data *data; 692 struct iio_dev *indio_dev; 693 unsigned int cycle_us; 694 int ret; 695 u8 enable; 696 697 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 698 if (!indio_dev) 699 return -ENOMEM; 700 701 data = iio_priv(indio_dev); 702 i2c_set_clientdata(client, indio_dev); 703 data->client = client; 704 ret = devm_mutex_init(dev, &data->lock); 705 if (ret) 706 return ret; 707 708 indio_dev->info = &tcs3472_info; 709 indio_dev->name = TCS3472_DRV_NAME; 710 indio_dev->channels = tcs3472_channels; 711 indio_dev->num_channels = ARRAY_SIZE(tcs3472_channels); 712 indio_dev->modes = INDIO_DIRECT_MODE; 713 714 ret = i2c_smbus_read_byte_data(data->client, TCS3472_ID); 715 if (ret < 0) 716 return ret; 717 718 if (ret == 0x44) 719 dev_info(dev, "TCS34721/34725 found\n"); 720 else if (ret == 0x4d) 721 dev_info(dev, "TCS34723/34727 found\n"); 722 else 723 return -ENODEV; 724 725 ret = i2c_smbus_read_byte_data(data->client, TCS3472_CONTROL); 726 if (ret < 0) 727 return ret; 728 data->control = ret; 729 730 ret = i2c_smbus_read_byte_data(data->client, TCS3472_ATIME); 731 if (ret < 0) 732 return ret; 733 data->atime = ret; 734 735 ret = i2c_smbus_read_byte_data(data->client, TCS3472_WTIME); 736 if (ret < 0) 737 return ret; 738 data->wtime = ret; 739 740 ret = i2c_smbus_read_byte_data(data->client, TCS3472_CONFIG); 741 if (ret < 0) 742 return ret; 743 data->wlong = (ret & TCS3472_CONFIG_WLONG) ? 1 : 0; 744 745 ret = i2c_smbus_read_word_data(data->client, TCS3472_AILT); 746 if (ret < 0) 747 return ret; 748 data->low_thresh = ret; 749 750 ret = i2c_smbus_read_word_data(data->client, TCS3472_AIHT); 751 if (ret < 0) 752 return ret; 753 data->high_thresh = ret; 754 755 data->apers = 1; 756 ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS, 757 data->apers); 758 if (ret < 0) 759 return ret; 760 761 ret = i2c_smbus_read_byte_data(data->client, TCS3472_ENABLE); 762 if (ret < 0) 763 return ret; 764 765 /* 766 * Enable the chip in its full running state, including WEN. The 767 * actual wait time is controlled by the WTIME and WLONG registers, 768 * which retain their power-on defaults until userspace writes to 769 * sampling_frequency. 770 */ 771 enable = (ret | TCS3472_ENABLE_RUN) & ~TCS3472_ENABLE_AIEN; 772 773 ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, enable); 774 if (ret < 0) 775 return ret; 776 777 data->enable = enable; 778 779 /* 780 * Initialize target frequency from the chip's current state so that 781 * subsequent integration_time changes via IIO_CHAN_INFO_INT_TIME can 782 * preserve a meaningful sampling rate, even before userspace writes 783 * sampling_frequency for the first time. 784 */ 785 cycle_us = tcs3472_cycle_time_us(data); 786 tcs3472_cycle_to_freq(cycle_us, &data->target_freq_hz, 787 &data->target_freq_uhz); 788 789 ret = devm_add_action_or_reset(dev, tcs3472_powerdown_action, data); 790 if (ret) 791 return ret; 792 793 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 794 tcs3472_trigger_handler, NULL); 795 if (ret < 0) 796 return ret; 797 798 if (client->irq) { 799 ret = devm_request_threaded_irq(dev, client->irq, NULL, 800 tcs3472_event_handler, 801 IRQF_TRIGGER_FALLING | 802 IRQF_SHARED | 803 IRQF_ONESHOT, 804 client->name, indio_dev); 805 if (ret) 806 return ret; 807 } 808 809 return devm_iio_device_register(dev, indio_dev); 810 } 811 812 static int tcs3472_suspend(struct device *dev) 813 { 814 struct tcs3472_data *data = iio_priv(i2c_get_clientdata( 815 to_i2c_client(dev))); 816 return tcs3472_powerdown(data); 817 } 818 819 static int tcs3472_resume(struct device *dev) 820 { 821 struct tcs3472_data *data = iio_priv(i2c_get_clientdata( 822 to_i2c_client(dev))); 823 int ret; 824 825 guard(mutex)(&data->lock); 826 827 /* 828 * Restore the full ENABLE register from the snapshot taken in 829 * tcs3472_powerdown(). This preserves the user's last 830 * sampling_frequency configuration (in particular the WEN bit) 831 * across suspend/resume. 832 */ 833 ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, 834 data->enable_pre_suspend); 835 if (ret) 836 return ret; 837 838 data->enable = data->enable_pre_suspend; 839 840 return 0; 841 } 842 843 static DEFINE_SIMPLE_DEV_PM_OPS(tcs3472_pm_ops, tcs3472_suspend, 844 tcs3472_resume); 845 846 static const struct i2c_device_id tcs3472_id[] = { 847 { .name = "tcs3472" }, 848 { } 849 }; 850 MODULE_DEVICE_TABLE(i2c, tcs3472_id); 851 852 static struct i2c_driver tcs3472_driver = { 853 .driver = { 854 .name = TCS3472_DRV_NAME, 855 .pm = pm_sleep_ptr(&tcs3472_pm_ops), 856 }, 857 .probe = tcs3472_probe, 858 .id_table = tcs3472_id, 859 }; 860 module_i2c_driver(tcs3472_driver); 861 862 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 863 MODULE_DESCRIPTION("TCS3472 color light sensors driver"); 864 MODULE_LICENSE("GPL"); 865