1 /* 2 * Copyright (C) 2012 Invensense, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #include <linux/i2c.h> 14 #include <linux/i2c-mux.h> 15 #include <linux/mutex.h> 16 #include <linux/iio/iio.h> 17 #include <linux/iio/buffer.h> 18 #include <linux/regmap.h> 19 #include <linux/iio/sysfs.h> 20 #include <linux/iio/kfifo_buf.h> 21 #include <linux/iio/trigger.h> 22 #include <linux/iio/triggered_buffer.h> 23 #include <linux/iio/trigger_consumer.h> 24 #include <linux/platform_data/invensense_mpu6050.h> 25 26 /** 27 * struct inv_mpu6050_reg_map - Notable registers. 28 * @sample_rate_div: Divider applied to gyro output rate. 29 * @lpf: Configures internal low pass filter. 30 * @accel_lpf: Configures accelerometer low pass filter. 31 * @user_ctrl: Enables/resets the FIFO. 32 * @fifo_en: Determines which data will appear in FIFO. 33 * @gyro_config: gyro config register. 34 * @accl_config: accel config register 35 * @fifo_count_h: Upper byte of FIFO count. 36 * @fifo_r_w: FIFO register. 37 * @raw_gyro: Address of first gyro register. 38 * @raw_accl: Address of first accel register. 39 * @temperature: temperature register 40 * @int_enable: Interrupt enable register. 41 * @int_status: Interrupt status register. 42 * @pwr_mgmt_1: Controls chip's power state and clock source. 43 * @pwr_mgmt_2: Controls power state of individual sensors. 44 * @int_pin_cfg; Controls interrupt pin configuration. 45 * @accl_offset: Controls the accelerometer calibration offset. 46 * @gyro_offset: Controls the gyroscope calibration offset. 47 * @i2c_if: Controls the i2c interface 48 */ 49 struct inv_mpu6050_reg_map { 50 u8 sample_rate_div; 51 u8 lpf; 52 u8 accel_lpf; 53 u8 user_ctrl; 54 u8 fifo_en; 55 u8 gyro_config; 56 u8 accl_config; 57 u8 fifo_count_h; 58 u8 fifo_r_w; 59 u8 raw_gyro; 60 u8 raw_accl; 61 u8 temperature; 62 u8 int_enable; 63 u8 int_status; 64 u8 pwr_mgmt_1; 65 u8 pwr_mgmt_2; 66 u8 int_pin_cfg; 67 u8 accl_offset; 68 u8 gyro_offset; 69 u8 i2c_if; 70 }; 71 72 /*device enum */ 73 enum inv_devices { 74 INV_MPU6050, 75 INV_MPU6500, 76 INV_MPU6515, 77 INV_MPU6000, 78 INV_MPU9150, 79 INV_MPU9250, 80 INV_MPU9255, 81 INV_ICM20608, 82 INV_ICM20602, 83 INV_NUM_PARTS 84 }; 85 86 /** 87 * struct inv_mpu6050_chip_config - Cached chip configuration data. 88 * @fsr: Full scale range. 89 * @lpf: Digital low pass filter frequency. 90 * @accl_fs: accel full scale range. 91 * @accl_fifo_enable: enable accel data output 92 * @gyro_fifo_enable: enable gyro data output 93 * @divider: chip sample rate divider (sample rate divider - 1) 94 */ 95 struct inv_mpu6050_chip_config { 96 unsigned int fsr:2; 97 unsigned int lpf:3; 98 unsigned int accl_fs:2; 99 unsigned int accl_fifo_enable:1; 100 unsigned int gyro_fifo_enable:1; 101 u8 divider; 102 u8 user_ctrl; 103 }; 104 105 /** 106 * struct inv_mpu6050_hw - Other important hardware information. 107 * @whoami: Self identification byte from WHO_AM_I register 108 * @name: name of the chip. 109 * @reg: register map of the chip. 110 * @config: configuration of the chip. 111 */ 112 struct inv_mpu6050_hw { 113 u8 whoami; 114 u8 *name; 115 const struct inv_mpu6050_reg_map *reg; 116 const struct inv_mpu6050_chip_config *config; 117 }; 118 119 /* 120 * struct inv_mpu6050_state - Driver state variables. 121 * @lock: Chip access lock. 122 * @trig: IIO trigger. 123 * @chip_config: Cached attribute information. 124 * @reg: Map of important registers. 125 * @hw: Other hardware-specific information. 126 * @chip_type: chip type. 127 * @plat_data: platform data (deprecated in favor of @orientation). 128 * @orientation: sensor chip orientation relative to main hardware. 129 * @map regmap pointer. 130 * @irq interrupt number. 131 * @irq_mask the int_pin_cfg mask to configure interrupt type. 132 * @chip_period: chip internal period estimation (~1kHz). 133 * @it_timestamp: timestamp from previous interrupt. 134 * @data_timestamp: timestamp for next data sample. 135 * @vddio_supply voltage regulator for the chip. 136 */ 137 struct inv_mpu6050_state { 138 struct mutex lock; 139 struct iio_trigger *trig; 140 struct inv_mpu6050_chip_config chip_config; 141 const struct inv_mpu6050_reg_map *reg; 142 const struct inv_mpu6050_hw *hw; 143 enum inv_devices chip_type; 144 struct i2c_mux_core *muxc; 145 struct i2c_client *mux_client; 146 unsigned int powerup_count; 147 struct inv_mpu6050_platform_data plat_data; 148 struct iio_mount_matrix orientation; 149 struct regmap *map; 150 int irq; 151 u8 irq_mask; 152 unsigned skip_samples; 153 s64 chip_period; 154 s64 it_timestamp; 155 s64 data_timestamp; 156 struct regulator *vddio_supply; 157 }; 158 159 /*register and associated bit definition*/ 160 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 161 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 162 163 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 164 #define INV_MPU6050_REG_CONFIG 0x1A 165 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 166 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 167 168 #define INV_MPU6050_REG_FIFO_EN 0x23 169 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 170 #define INV_MPU6050_BITS_GYRO_OUT 0x70 171 172 #define INV_MPU6050_REG_INT_ENABLE 0x38 173 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 174 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 175 176 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 177 #define INV_MPU6050_REG_TEMPERATURE 0x41 178 #define INV_MPU6050_REG_RAW_GYRO 0x43 179 180 #define INV_MPU6050_REG_INT_STATUS 0x3A 181 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10 182 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01 183 184 #define INV_MPU6050_REG_USER_CTRL 0x6A 185 #define INV_MPU6050_BIT_FIFO_RST 0x04 186 #define INV_MPU6050_BIT_DMP_RST 0x08 187 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 188 #define INV_MPU6050_BIT_FIFO_EN 0x40 189 #define INV_MPU6050_BIT_DMP_EN 0x80 190 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 191 192 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 193 #define INV_MPU6050_BIT_H_RESET 0x80 194 #define INV_MPU6050_BIT_SLEEP 0x40 195 #define INV_MPU6050_BIT_CLK_MASK 0x7 196 197 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 198 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 199 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 200 201 /* ICM20602 register */ 202 #define INV_ICM20602_REG_I2C_IF 0x70 203 #define INV_ICM20602_BIT_I2C_IF_DIS 0x40 204 205 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 206 #define INV_MPU6050_REG_FIFO_R_W 0x74 207 208 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 209 #define INV_MPU6050_FIFO_COUNT_BYTE 2 210 211 /* mpu6500 registers */ 212 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D 213 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 214 215 /* delay time in milliseconds */ 216 #define INV_MPU6050_POWER_UP_TIME 100 217 #define INV_MPU6050_TEMP_UP_TIME 100 218 #define INV_MPU6050_SENSOR_UP_TIME 30 219 220 /* delay time in microseconds */ 221 #define INV_MPU6050_REG_UP_TIME_MIN 5000 222 #define INV_MPU6050_REG_UP_TIME_MAX 10000 223 224 #define INV_MPU6050_TEMP_OFFSET 12421 225 #define INV_MPU6050_TEMP_SCALE 2941 226 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 227 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 228 #define INV_MPU6050_THREE_AXIS 3 229 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 230 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 231 232 /* 6 + 6 round up and plus 8 */ 233 #define INV_MPU6050_OUTPUT_DATA_SIZE 24 234 235 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 236 #define INV_MPU6050_ACTIVE_HIGH 0x00 237 #define INV_MPU6050_ACTIVE_LOW 0x80 238 /* enable level triggering */ 239 #define INV_MPU6050_LATCH_INT_EN 0x20 240 #define INV_MPU6050_BIT_BYPASS_EN 0x2 241 242 /* Allowed timestamp period jitter in percent */ 243 #define INV_MPU6050_TS_PERIOD_JITTER 4 244 245 /* init parameters */ 246 #define INV_MPU6050_INIT_FIFO_RATE 50 247 #define INV_MPU6050_MAX_FIFO_RATE 1000 248 #define INV_MPU6050_MIN_FIFO_RATE 4 249 250 /* chip internal frequency: 1KHz */ 251 #define INV_MPU6050_INTERNAL_FREQ_HZ 1000 252 /* return the frequency divider (chip sample rate divider + 1) */ 253 #define INV_MPU6050_FREQ_DIVIDER(st) \ 254 ((st)->chip_config.divider + 1) 255 /* chip sample rate divider to fifo rate */ 256 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \ 257 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1) 258 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \ 259 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1)) 260 261 #define INV_MPU6050_REG_WHOAMI 117 262 263 #define INV_MPU6000_WHOAMI_VALUE 0x68 264 #define INV_MPU6050_WHOAMI_VALUE 0x68 265 #define INV_MPU6500_WHOAMI_VALUE 0x70 266 #define INV_MPU9150_WHOAMI_VALUE 0x68 267 #define INV_MPU9250_WHOAMI_VALUE 0x71 268 #define INV_MPU9255_WHOAMI_VALUE 0x73 269 #define INV_MPU6515_WHOAMI_VALUE 0x74 270 #define INV_ICM20608_WHOAMI_VALUE 0xAF 271 #define INV_ICM20602_WHOAMI_VALUE 0x12 272 273 /* scan element definition */ 274 enum inv_mpu6050_scan { 275 INV_MPU6050_SCAN_ACCL_X, 276 INV_MPU6050_SCAN_ACCL_Y, 277 INV_MPU6050_SCAN_ACCL_Z, 278 INV_MPU6050_SCAN_GYRO_X, 279 INV_MPU6050_SCAN_GYRO_Y, 280 INV_MPU6050_SCAN_GYRO_Z, 281 INV_MPU6050_SCAN_TIMESTAMP, 282 }; 283 284 enum inv_mpu6050_filter_e { 285 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0, 286 INV_MPU6050_FILTER_188HZ, 287 INV_MPU6050_FILTER_98HZ, 288 INV_MPU6050_FILTER_42HZ, 289 INV_MPU6050_FILTER_20HZ, 290 INV_MPU6050_FILTER_10HZ, 291 INV_MPU6050_FILTER_5HZ, 292 INV_MPU6050_FILTER_2100HZ_NOLPF, 293 NUM_MPU6050_FILTER 294 }; 295 296 /* IIO attribute address */ 297 enum INV_MPU6050_IIO_ATTR_ADDR { 298 ATTR_GYRO_MATRIX, 299 ATTR_ACCL_MATRIX, 300 }; 301 302 enum inv_mpu6050_accl_fs_e { 303 INV_MPU6050_FS_02G = 0, 304 INV_MPU6050_FS_04G, 305 INV_MPU6050_FS_08G, 306 INV_MPU6050_FS_16G, 307 NUM_ACCL_FSR 308 }; 309 310 enum inv_mpu6050_fsr_e { 311 INV_MPU6050_FSR_250DPS = 0, 312 INV_MPU6050_FSR_500DPS, 313 INV_MPU6050_FSR_1000DPS, 314 INV_MPU6050_FSR_2000DPS, 315 NUM_MPU6050_FSR 316 }; 317 318 enum inv_mpu6050_clock_sel_e { 319 INV_CLK_INTERNAL = 0, 320 INV_CLK_PLL, 321 NUM_CLK 322 }; 323 324 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 325 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type); 326 int inv_reset_fifo(struct iio_dev *indio_dev); 327 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); 328 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 329 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 330 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 331 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 332 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 333 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 334 extern const struct dev_pm_ops inv_mpu_pmops; 335