1 /* 2 * Copyright (C) 2012 Invensense, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #include <linux/i2c.h> 14 #include <linux/i2c-mux.h> 15 #include <linux/kfifo.h> 16 #include <linux/spinlock.h> 17 #include <linux/iio/iio.h> 18 #include <linux/iio/buffer.h> 19 #include <linux/regmap.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/kfifo_buf.h> 22 #include <linux/iio/trigger.h> 23 #include <linux/iio/triggered_buffer.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/platform_data/invensense_mpu6050.h> 26 27 /** 28 * struct inv_mpu6050_reg_map - Notable registers. 29 * @sample_rate_div: Divider applied to gyro output rate. 30 * @lpf: Configures internal low pass filter. 31 * @user_ctrl: Enables/resets the FIFO. 32 * @fifo_en: Determines which data will appear in FIFO. 33 * @gyro_config: gyro config register. 34 * @accl_config: accel config register 35 * @fifo_count_h: Upper byte of FIFO count. 36 * @fifo_r_w: FIFO register. 37 * @raw_gyro: Address of first gyro register. 38 * @raw_accl: Address of first accel register. 39 * @temperature: temperature register 40 * @int_enable: Interrupt enable register. 41 * @pwr_mgmt_1: Controls chip's power state and clock source. 42 * @pwr_mgmt_2: Controls power state of individual sensors. 43 * @int_pin_cfg; Controls interrupt pin configuration. 44 * @accl_offset: Controls the accelerometer calibration offset. 45 * @gyro_offset: Controls the gyroscope calibration offset. 46 */ 47 struct inv_mpu6050_reg_map { 48 u8 sample_rate_div; 49 u8 lpf; 50 u8 user_ctrl; 51 u8 fifo_en; 52 u8 gyro_config; 53 u8 accl_config; 54 u8 fifo_count_h; 55 u8 fifo_r_w; 56 u8 raw_gyro; 57 u8 raw_accl; 58 u8 temperature; 59 u8 int_enable; 60 u8 pwr_mgmt_1; 61 u8 pwr_mgmt_2; 62 u8 int_pin_cfg; 63 u8 accl_offset; 64 u8 gyro_offset; 65 }; 66 67 /*device enum */ 68 enum inv_devices { 69 INV_MPU6050, 70 INV_MPU6500, 71 INV_MPU6000, 72 INV_MPU9150, 73 INV_NUM_PARTS 74 }; 75 76 /** 77 * struct inv_mpu6050_chip_config - Cached chip configuration data. 78 * @fsr: Full scale range. 79 * @lpf: Digital low pass filter frequency. 80 * @accl_fs: accel full scale range. 81 * @enable: master enable state. 82 * @accl_fifo_enable: enable accel data output 83 * @gyro_fifo_enable: enable gyro data output 84 * @fifo_rate: FIFO update rate. 85 */ 86 struct inv_mpu6050_chip_config { 87 unsigned int fsr:2; 88 unsigned int lpf:3; 89 unsigned int accl_fs:2; 90 unsigned int enable:1; 91 unsigned int accl_fifo_enable:1; 92 unsigned int gyro_fifo_enable:1; 93 u16 fifo_rate; 94 }; 95 96 /** 97 * struct inv_mpu6050_hw - Other important hardware information. 98 * @whoami: Self identification byte from WHO_AM_I register 99 * @name: name of the chip. 100 * @reg: register map of the chip. 101 * @config: configuration of the chip. 102 */ 103 struct inv_mpu6050_hw { 104 u8 whoami; 105 u8 *name; 106 const struct inv_mpu6050_reg_map *reg; 107 const struct inv_mpu6050_chip_config *config; 108 }; 109 110 /* 111 * struct inv_mpu6050_state - Driver state variables. 112 * @TIMESTAMP_FIFO_SIZE: fifo size for timestamp. 113 * @trig: IIO trigger. 114 * @chip_config: Cached attribute information. 115 * @reg: Map of important registers. 116 * @hw: Other hardware-specific information. 117 * @chip_type: chip type. 118 * @time_stamp_lock: spin lock to time stamp. 119 * @plat_data: platform data (deprecated in favor of @orientation). 120 * @orientation: sensor chip orientation relative to main hardware. 121 * @timestamps: kfifo queue to store time stamp. 122 * @map regmap pointer. 123 * @irq interrupt number. 124 */ 125 struct inv_mpu6050_state { 126 #define TIMESTAMP_FIFO_SIZE 16 127 struct iio_trigger *trig; 128 struct inv_mpu6050_chip_config chip_config; 129 const struct inv_mpu6050_reg_map *reg; 130 const struct inv_mpu6050_hw *hw; 131 enum inv_devices chip_type; 132 spinlock_t time_stamp_lock; 133 struct i2c_mux_core *muxc; 134 struct i2c_client *mux_client; 135 unsigned int powerup_count; 136 struct inv_mpu6050_platform_data plat_data; 137 struct iio_mount_matrix orientation; 138 DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE); 139 struct regmap *map; 140 int irq; 141 }; 142 143 /*register and associated bit definition*/ 144 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 145 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 146 147 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 148 #define INV_MPU6050_REG_CONFIG 0x1A 149 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 150 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 151 152 #define INV_MPU6050_REG_FIFO_EN 0x23 153 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 154 #define INV_MPU6050_BITS_GYRO_OUT 0x70 155 156 #define INV_MPU6050_REG_INT_ENABLE 0x38 157 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 158 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 159 160 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 161 #define INV_MPU6050_REG_TEMPERATURE 0x41 162 #define INV_MPU6050_REG_RAW_GYRO 0x43 163 164 #define INV_MPU6050_REG_USER_CTRL 0x6A 165 #define INV_MPU6050_BIT_FIFO_RST 0x04 166 #define INV_MPU6050_BIT_DMP_RST 0x08 167 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 168 #define INV_MPU6050_BIT_FIFO_EN 0x40 169 #define INV_MPU6050_BIT_DMP_EN 0x80 170 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 171 172 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 173 #define INV_MPU6050_BIT_H_RESET 0x80 174 #define INV_MPU6050_BIT_SLEEP 0x40 175 #define INV_MPU6050_BIT_CLK_MASK 0x7 176 177 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 178 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 179 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 180 181 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 182 #define INV_MPU6050_REG_FIFO_R_W 0x74 183 184 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 185 #define INV_MPU6050_FIFO_COUNT_BYTE 2 186 #define INV_MPU6050_FIFO_THRESHOLD 500 187 188 /* mpu6500 registers */ 189 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 190 191 /* delay time in milliseconds */ 192 #define INV_MPU6050_POWER_UP_TIME 100 193 #define INV_MPU6050_TEMP_UP_TIME 100 194 #define INV_MPU6050_SENSOR_UP_TIME 30 195 196 /* delay time in microseconds */ 197 #define INV_MPU6050_REG_UP_TIME_MIN 5000 198 #define INV_MPU6050_REG_UP_TIME_MAX 10000 199 200 #define INV_MPU6050_TEMP_OFFSET 12421 201 #define INV_MPU6050_TEMP_SCALE 2941 202 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 203 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 204 #define INV_MPU6050_THREE_AXIS 3 205 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 206 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 207 208 /* 6 + 6 round up and plus 8 */ 209 #define INV_MPU6050_OUTPUT_DATA_SIZE 24 210 211 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 212 #define INV_MPU6050_BIT_BYPASS_EN 0x2 213 #define INV_MPU6050_INT_PIN_CFG 0 214 215 /* init parameters */ 216 #define INV_MPU6050_INIT_FIFO_RATE 50 217 #define INV_MPU6050_TIME_STAMP_TOR 5 218 #define INV_MPU6050_MAX_FIFO_RATE 1000 219 #define INV_MPU6050_MIN_FIFO_RATE 4 220 #define INV_MPU6050_ONE_K_HZ 1000 221 222 #define INV_MPU6050_REG_WHOAMI 117 223 224 #define INV_MPU6000_WHOAMI_VALUE 0x68 225 #define INV_MPU6050_WHOAMI_VALUE 0x68 226 #define INV_MPU6500_WHOAMI_VALUE 0x70 227 #define INV_MPU9150_WHOAMI_VALUE 0x68 228 229 /* scan element definition */ 230 enum inv_mpu6050_scan { 231 INV_MPU6050_SCAN_ACCL_X, 232 INV_MPU6050_SCAN_ACCL_Y, 233 INV_MPU6050_SCAN_ACCL_Z, 234 INV_MPU6050_SCAN_GYRO_X, 235 INV_MPU6050_SCAN_GYRO_Y, 236 INV_MPU6050_SCAN_GYRO_Z, 237 INV_MPU6050_SCAN_TIMESTAMP, 238 }; 239 240 enum inv_mpu6050_filter_e { 241 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0, 242 INV_MPU6050_FILTER_188HZ, 243 INV_MPU6050_FILTER_98HZ, 244 INV_MPU6050_FILTER_42HZ, 245 INV_MPU6050_FILTER_20HZ, 246 INV_MPU6050_FILTER_10HZ, 247 INV_MPU6050_FILTER_5HZ, 248 INV_MPU6050_FILTER_2100HZ_NOLPF, 249 NUM_MPU6050_FILTER 250 }; 251 252 /* IIO attribute address */ 253 enum INV_MPU6050_IIO_ATTR_ADDR { 254 ATTR_GYRO_MATRIX, 255 ATTR_ACCL_MATRIX, 256 }; 257 258 enum inv_mpu6050_accl_fs_e { 259 INV_MPU6050_FS_02G = 0, 260 INV_MPU6050_FS_04G, 261 INV_MPU6050_FS_08G, 262 INV_MPU6050_FS_16G, 263 NUM_ACCL_FSR 264 }; 265 266 enum inv_mpu6050_fsr_e { 267 INV_MPU6050_FSR_250DPS = 0, 268 INV_MPU6050_FSR_500DPS, 269 INV_MPU6050_FSR_1000DPS, 270 INV_MPU6050_FSR_2000DPS, 271 NUM_MPU6050_FSR 272 }; 273 274 enum inv_mpu6050_clock_sel_e { 275 INV_CLK_INTERNAL = 0, 276 INV_CLK_PLL, 277 NUM_CLK 278 }; 279 280 irqreturn_t inv_mpu6050_irq_handler(int irq, void *p); 281 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 282 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev); 283 void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st); 284 int inv_reset_fifo(struct iio_dev *indio_dev); 285 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); 286 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 287 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 288 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 289 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 290 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 291 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 292 int inv_mpu_core_remove(struct device *dev); 293 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 294 extern const struct dev_pm_ops inv_mpu_pmops; 295