1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2020 Invensense, Inc. 4 */ 5 6 #ifndef INV_ICM42600_H_ 7 #define INV_ICM42600_H_ 8 9 #include <linux/bits.h> 10 #include <linux/bitfield.h> 11 #include <linux/regmap.h> 12 #include <linux/mutex.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/pm.h> 15 #include <linux/iio/iio.h> 16 #include <linux/iio/common/inv_sensors_timestamp.h> 17 18 #include "inv_icm42600_buffer.h" 19 20 enum inv_icm42600_chip { 21 INV_CHIP_INVALID, 22 INV_CHIP_ICM42600, 23 INV_CHIP_ICM42602, 24 INV_CHIP_ICM42605, 25 INV_CHIP_ICM42686, 26 INV_CHIP_ICM42622, 27 INV_CHIP_ICM42688, 28 INV_CHIP_ICM42631, 29 INV_CHIP_NB, 30 }; 31 32 /* serial bus slew rates */ 33 enum inv_icm42600_slew_rate { 34 INV_ICM42600_SLEW_RATE_20_60NS, 35 INV_ICM42600_SLEW_RATE_12_36NS, 36 INV_ICM42600_SLEW_RATE_6_18NS, 37 INV_ICM42600_SLEW_RATE_4_12NS, 38 INV_ICM42600_SLEW_RATE_2_6NS, 39 INV_ICM42600_SLEW_RATE_INF_2NS, 40 }; 41 42 enum inv_icm42600_sensor_mode { 43 INV_ICM42600_SENSOR_MODE_OFF, 44 INV_ICM42600_SENSOR_MODE_STANDBY, 45 INV_ICM42600_SENSOR_MODE_LOW_POWER, 46 INV_ICM42600_SENSOR_MODE_LOW_NOISE, 47 INV_ICM42600_SENSOR_MODE_NB, 48 }; 49 50 /* gyroscope fullscale values */ 51 enum inv_icm42600_gyro_fs { 52 INV_ICM42600_GYRO_FS_2000DPS, 53 INV_ICM42600_GYRO_FS_1000DPS, 54 INV_ICM42600_GYRO_FS_500DPS, 55 INV_ICM42600_GYRO_FS_250DPS, 56 INV_ICM42600_GYRO_FS_125DPS, 57 INV_ICM42600_GYRO_FS_62_5DPS, 58 INV_ICM42600_GYRO_FS_31_25DPS, 59 INV_ICM42600_GYRO_FS_15_625DPS, 60 INV_ICM42600_GYRO_FS_NB, 61 }; 62 enum inv_icm42686_gyro_fs { 63 INV_ICM42686_GYRO_FS_4000DPS, 64 INV_ICM42686_GYRO_FS_2000DPS, 65 INV_ICM42686_GYRO_FS_1000DPS, 66 INV_ICM42686_GYRO_FS_500DPS, 67 INV_ICM42686_GYRO_FS_250DPS, 68 INV_ICM42686_GYRO_FS_125DPS, 69 INV_ICM42686_GYRO_FS_62_5DPS, 70 INV_ICM42686_GYRO_FS_31_25DPS, 71 INV_ICM42686_GYRO_FS_NB, 72 }; 73 74 /* accelerometer fullscale values */ 75 enum inv_icm42600_accel_fs { 76 INV_ICM42600_ACCEL_FS_16G, 77 INV_ICM42600_ACCEL_FS_8G, 78 INV_ICM42600_ACCEL_FS_4G, 79 INV_ICM42600_ACCEL_FS_2G, 80 INV_ICM42600_ACCEL_FS_NB, 81 }; 82 enum inv_icm42686_accel_fs { 83 INV_ICM42686_ACCEL_FS_32G, 84 INV_ICM42686_ACCEL_FS_16G, 85 INV_ICM42686_ACCEL_FS_8G, 86 INV_ICM42686_ACCEL_FS_4G, 87 INV_ICM42686_ACCEL_FS_2G, 88 INV_ICM42686_ACCEL_FS_NB, 89 }; 90 91 /* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */ 92 enum inv_icm42600_odr { 93 INV_ICM42600_ODR_8KHZ_LN = 3, 94 INV_ICM42600_ODR_4KHZ_LN, 95 INV_ICM42600_ODR_2KHZ_LN, 96 INV_ICM42600_ODR_1KHZ_LN, 97 INV_ICM42600_ODR_200HZ, 98 INV_ICM42600_ODR_100HZ, 99 INV_ICM42600_ODR_50HZ, 100 INV_ICM42600_ODR_25HZ, 101 INV_ICM42600_ODR_12_5HZ, 102 INV_ICM42600_ODR_6_25HZ_LP, 103 INV_ICM42600_ODR_3_125HZ_LP, 104 INV_ICM42600_ODR_1_5625HZ_LP, 105 INV_ICM42600_ODR_500HZ, 106 INV_ICM42600_ODR_NB, 107 }; 108 109 enum inv_icm42600_filter { 110 /* Low-Noise mode sensor data filter (3rd order filter by default) */ 111 INV_ICM42600_FILTER_BW_ODR_DIV_2, 112 113 /* Low-Power mode sensor data filter (averaging) */ 114 INV_ICM42600_FILTER_AVG_1X = 1, 115 INV_ICM42600_FILTER_AVG_16X = 6, 116 }; 117 118 struct inv_icm42600_sensor_conf { 119 int mode; 120 int fs; 121 int odr; 122 int filter; 123 }; 124 #define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1} 125 126 struct inv_icm42600_conf { 127 struct inv_icm42600_sensor_conf gyro; 128 struct inv_icm42600_sensor_conf accel; 129 bool temp_en; 130 }; 131 132 struct inv_icm42600_suspended { 133 enum inv_icm42600_sensor_mode gyro; 134 enum inv_icm42600_sensor_mode accel; 135 bool temp; 136 }; 137 138 struct inv_icm42600_apex { 139 unsigned int on; 140 struct { 141 u64 value; 142 bool enable; 143 } wom; 144 }; 145 146 /** 147 * struct inv_icm42600_state - driver state variables 148 * @lock: lock for serializing multiple registers access. 149 * @chip: chip identifier. 150 * @name: chip name. 151 * @map: regmap pointer. 152 * @vdd_supply: VDD voltage regulator for the chip. 153 * @vddio_supply: I/O voltage regulator for the chip. 154 * @irq: chip irq, required to enable/disable and set wakeup 155 * @orientation: sensor chip orientation relative to main hardware. 156 * @conf: chip sensors configurations. 157 * @suspended: suspended sensors configuration. 158 * @indio_gyro: gyroscope IIO device. 159 * @indio_accel: accelerometer IIO device. 160 * @timestamp: interrupt timestamps. 161 * @apex: APEX (Advanced Pedometer and Event detection) management 162 * @fifo: FIFO management structure. 163 * @buffer: data transfer buffer aligned for DMA. 164 */ 165 struct inv_icm42600_state { 166 struct mutex lock; 167 enum inv_icm42600_chip chip; 168 const char *name; 169 struct regmap *map; 170 struct regulator *vddio_supply; 171 int irq; 172 struct iio_mount_matrix orientation; 173 struct inv_icm42600_conf conf; 174 struct inv_icm42600_suspended suspended; 175 struct iio_dev *indio_gyro; 176 struct iio_dev *indio_accel; 177 struct { 178 s64 gyro; 179 s64 accel; 180 } timestamp; 181 struct inv_icm42600_apex apex; 182 struct inv_icm42600_fifo fifo; 183 u8 buffer[3] __aligned(IIO_DMA_MINALIGN); 184 }; 185 186 187 /** 188 * struct inv_icm42600_sensor_state - sensor state variables 189 * @scales: table of scales. 190 * @scales_len: length (nb of items) of the scales table. 191 * @power_mode: sensor requested power mode (for common frequencies) 192 * @filter: sensor filter. 193 * @ts: timestamp module states. 194 */ 195 struct inv_icm42600_sensor_state { 196 const int *scales; 197 size_t scales_len; 198 enum inv_icm42600_sensor_mode power_mode; 199 enum inv_icm42600_filter filter; 200 struct inv_sensors_timestamp ts; 201 }; 202 203 /* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */ 204 205 /* Bank selection register, available in all banks */ 206 #define INV_ICM42600_REG_BANK_SEL 0x76 207 #define INV_ICM42600_BANK_SEL_MASK GENMASK(2, 0) 208 209 /* User bank 0 (MSB 0x00) */ 210 #define INV_ICM42600_REG_DEVICE_CONFIG 0x0011 211 #define INV_ICM42600_DEVICE_CONFIG_SOFT_RESET BIT(0) 212 213 #define INV_ICM42600_REG_DRIVE_CONFIG 0x0013 214 #define INV_ICM42600_DRIVE_CONFIG_I2C_MASK GENMASK(5, 3) 215 #define INV_ICM42600_DRIVE_CONFIG_I2C(_rate) \ 216 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_I2C_MASK, (_rate)) 217 #define INV_ICM42600_DRIVE_CONFIG_SPI_MASK GENMASK(2, 0) 218 #define INV_ICM42600_DRIVE_CONFIG_SPI(_rate) \ 219 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_SPI_MASK, (_rate)) 220 221 #define INV_ICM42600_REG_INT_CONFIG 0x0014 222 #define INV_ICM42600_INT_CONFIG_INT2_LATCHED BIT(5) 223 #define INV_ICM42600_INT_CONFIG_INT2_PUSH_PULL BIT(4) 224 #define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3) 225 #define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_LOW 0x00 226 #define INV_ICM42600_INT_CONFIG_INT1_LATCHED BIT(2) 227 #define INV_ICM42600_INT_CONFIG_INT1_PUSH_PULL BIT(1) 228 #define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_HIGH BIT(0) 229 #define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_LOW 0x00 230 231 #define INV_ICM42600_REG_FIFO_CONFIG 0x0016 232 #define INV_ICM42600_FIFO_CONFIG_MASK GENMASK(7, 6) 233 #define INV_ICM42600_FIFO_CONFIG_BYPASS \ 234 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 0) 235 #define INV_ICM42600_FIFO_CONFIG_STREAM \ 236 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 1) 237 #define INV_ICM42600_FIFO_CONFIG_STOP_ON_FULL \ 238 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 2) 239 240 /* all sensor data are 16 bits (2 registers wide) in big-endian */ 241 #define INV_ICM42600_REG_TEMP_DATA 0x001D 242 #define INV_ICM42600_REG_ACCEL_DATA_X 0x001F 243 #define INV_ICM42600_REG_ACCEL_DATA_Y 0x0021 244 #define INV_ICM42600_REG_ACCEL_DATA_Z 0x0023 245 #define INV_ICM42600_REG_GYRO_DATA_X 0x0025 246 #define INV_ICM42600_REG_GYRO_DATA_Y 0x0027 247 #define INV_ICM42600_REG_GYRO_DATA_Z 0x0029 248 #define INV_ICM42600_DATA_INVALID -32768 249 250 #define INV_ICM42600_REG_INT_STATUS 0x002D 251 #define INV_ICM42600_INT_STATUS_UI_FSYNC BIT(6) 252 #define INV_ICM42600_INT_STATUS_PLL_RDY BIT(5) 253 #define INV_ICM42600_INT_STATUS_RESET_DONE BIT(4) 254 #define INV_ICM42600_INT_STATUS_DATA_RDY BIT(3) 255 #define INV_ICM42600_INT_STATUS_FIFO_THS BIT(2) 256 #define INV_ICM42600_INT_STATUS_FIFO_FULL BIT(1) 257 #define INV_ICM42600_INT_STATUS_AGC_RDY BIT(0) 258 259 /* 260 * FIFO access registers 261 * FIFO count is 16 bits (2 registers) big-endian 262 * FIFO data is a continuous read register to read FIFO content 263 */ 264 #define INV_ICM42600_REG_FIFO_COUNT 0x002E 265 #define INV_ICM42600_REG_FIFO_DATA 0x0030 266 267 #define INV_ICM42600_REG_INT_STATUS2 0x0037 268 #define INV_ICM42600_INT_STATUS2_SMD_INT BIT(3) 269 #define INV_ICM42600_INT_STATUS2_WOM_INT GENMASK(2, 0) 270 271 #define INV_ICM42600_REG_INT_STATUS3 0x0038 272 #define INV_ICM42600_INT_STATUS3_STEP_DET_INT BIT(5) 273 #define INV_ICM42600_INT_STATUS3_STEP_CNT_OVF_INT BIT(4) 274 #define INV_ICM42600_INT_STATUS3_TILT_DET_INT BIT(3) 275 #define INV_ICM42600_INT_STATUS3_WAKE_INT BIT(2) 276 #define INV_ICM42600_INT_STATUS3_SLEEP_INT BIT(1) 277 #define INV_ICM42600_INT_STATUS3_TAP_DET_INT BIT(0) 278 279 #define INV_ICM42600_REG_SIGNAL_PATH_RESET 0x004B 280 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN BIT(6) 281 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET BIT(5) 282 #define INV_ICM42600_SIGNAL_PATH_RESET_RESET BIT(3) 283 #define INV_ICM42600_SIGNAL_PATH_RESET_TMST_STROBE BIT(2) 284 #define INV_ICM42600_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(1) 285 286 /* default configuration: all data big-endian and fifo count in bytes */ 287 #define INV_ICM42600_REG_INTF_CONFIG0 0x004C 288 #define INV_ICM42600_INTF_CONFIG0_FIFO_HOLD_LAST_DATA BIT(7) 289 #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_REC BIT(6) 290 #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5) 291 #define INV_ICM42600_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4) 292 #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK GENMASK(1, 0) 293 #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS \ 294 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 2) 295 #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS \ 296 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 3) 297 298 #define INV_ICM42600_REG_INTF_CONFIG1 0x004D 299 #define INV_ICM42600_INTF_CONFIG1_ACCEL_LP_CLK_RC BIT(3) 300 301 #define INV_ICM42600_REG_PWR_MGMT0 0x004E 302 #define INV_ICM42600_PWR_MGMT0_TEMP_DIS BIT(5) 303 #define INV_ICM42600_PWR_MGMT0_IDLE BIT(4) 304 #define INV_ICM42600_PWR_MGMT0_GYRO(_mode) \ 305 FIELD_PREP(GENMASK(3, 2), (_mode)) 306 #define INV_ICM42600_PWR_MGMT0_ACCEL(_mode) \ 307 FIELD_PREP(GENMASK(1, 0), (_mode)) 308 309 #define INV_ICM42600_REG_GYRO_CONFIG0 0x004F 310 #define INV_ICM42600_GYRO_CONFIG0_FS(_fs) \ 311 FIELD_PREP(GENMASK(7, 5), (_fs)) 312 #define INV_ICM42600_GYRO_CONFIG0_ODR(_odr) \ 313 FIELD_PREP(GENMASK(3, 0), (_odr)) 314 315 #define INV_ICM42600_REG_ACCEL_CONFIG0 0x0050 316 #define INV_ICM42600_ACCEL_CONFIG0_FS(_fs) \ 317 FIELD_PREP(GENMASK(7, 5), (_fs)) 318 #define INV_ICM42600_ACCEL_CONFIG0_ODR(_odr) \ 319 FIELD_PREP(GENMASK(3, 0), (_odr)) 320 321 #define INV_ICM42600_REG_GYRO_ACCEL_CONFIG0 0x0052 322 #define INV_ICM42600_GYRO_ACCEL_CONFIG0_ACCEL_FILT(_f) \ 323 FIELD_PREP(GENMASK(7, 4), (_f)) 324 #define INV_ICM42600_GYRO_ACCEL_CONFIG0_GYRO_FILT(_f) \ 325 FIELD_PREP(GENMASK(3, 0), (_f)) 326 327 #define INV_ICM42600_REG_TMST_CONFIG 0x0054 328 #define INV_ICM42600_TMST_CONFIG_MASK GENMASK(4, 0) 329 #define INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN BIT(4) 330 #define INV_ICM42600_TMST_CONFIG_TMST_RES_16US BIT(3) 331 #define INV_ICM42600_TMST_CONFIG_TMST_DELTA_EN BIT(2) 332 #define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN BIT(1) 333 #define INV_ICM42600_TMST_CONFIG_TMST_EN BIT(0) 334 335 #define INV_ICM42600_REG_SMD_CONFIG 0x0057 336 #define INV_ICM42600_SMD_CONFIG_WOM_INT_MODE BIT(3) 337 #define INV_ICM42600_SMD_CONFIG_WOM_MODE BIT(2) 338 #define INV_ICM42600_SMD_CONFIG_SMD_MODE_OFF 0x00 339 #define INV_ICM42600_SMD_CONFIG_SMD_MODE_WOM 0x01 340 #define INV_ICM42600_SMD_CONFIG_SMD_MODE_SHORT 0x02 341 #define INV_ICM42600_SMD_CONFIG_SMD_MODE_LONG 0x03 342 343 #define INV_ICM42600_REG_FIFO_CONFIG1 0x005F 344 #define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD BIT(6) 345 #define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH BIT(5) 346 #define INV_ICM42600_FIFO_CONFIG1_TMST_FSYNC_EN BIT(3) 347 #define INV_ICM42600_FIFO_CONFIG1_TEMP_EN BIT(2) 348 #define INV_ICM42600_FIFO_CONFIG1_GYRO_EN BIT(1) 349 #define INV_ICM42600_FIFO_CONFIG1_ACCEL_EN BIT(0) 350 351 /* FIFO watermark is 16 bits (2 registers wide) in little-endian */ 352 #define INV_ICM42600_REG_FIFO_WATERMARK 0x0060 353 #define INV_ICM42600_FIFO_WATERMARK_VAL(_wm) \ 354 cpu_to_le16((_wm) & GENMASK(11, 0)) 355 /* FIFO is 2048 bytes, let 12 samples for reading latency */ 356 #define INV_ICM42600_FIFO_WATERMARK_MAX (2048 - 12 * 16) 357 358 #define INV_ICM42600_REG_INT_CONFIG1 0x0064 359 #define INV_ICM42600_INT_CONFIG1_TPULSE_DURATION BIT(6) 360 #define INV_ICM42600_INT_CONFIG1_TDEASSERT_DISABLE BIT(5) 361 #define INV_ICM42600_INT_CONFIG1_ASYNC_RESET BIT(4) 362 363 #define INV_ICM42600_REG_INT_SOURCE0 0x0065 364 #define INV_ICM42600_INT_SOURCE0_UI_FSYNC_INT1_EN BIT(6) 365 #define INV_ICM42600_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5) 366 #define INV_ICM42600_INT_SOURCE0_RESET_DONE_INT1_EN BIT(4) 367 #define INV_ICM42600_INT_SOURCE0_UI_DRDY_INT1_EN BIT(3) 368 #define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2) 369 #define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1) 370 #define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN BIT(0) 371 372 #define INV_ICM42600_REG_INT_SOURCE1 0x0066 373 #define INV_ICM42600_INT_SOURCE1_I3C_ERROR_INT1_EN BIT(6) 374 #define INV_ICM42600_INT_SOURCE1_SMD_INT1_EN BIT(3) 375 #define INV_ICM42600_INT_SOURCE1_WOM_INT1_EN GENMASK(2, 0) 376 377 #define INV_ICM42600_REG_WHOAMI 0x0075 378 #define INV_ICM42600_WHOAMI_ICM42600 0x40 379 #define INV_ICM42600_WHOAMI_ICM42602 0x41 380 #define INV_ICM42600_WHOAMI_ICM42605 0x42 381 #define INV_ICM42600_WHOAMI_ICM42686 0x44 382 #define INV_ICM42600_WHOAMI_ICM42622 0x46 383 #define INV_ICM42600_WHOAMI_ICM42688 0x47 384 #define INV_ICM42600_WHOAMI_ICM42631 0x5C 385 386 /* User bank 1 (MSB 0x10) */ 387 #define INV_ICM42600_REG_SENSOR_CONFIG0 0x1003 388 #define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE BIT(5) 389 #define INV_ICM42600_SENSOR_CONFIG0_YG_DISABLE BIT(4) 390 #define INV_ICM42600_SENSOR_CONFIG0_XG_DISABLE BIT(3) 391 #define INV_ICM42600_SENSOR_CONFIG0_ZA_DISABLE BIT(2) 392 #define INV_ICM42600_SENSOR_CONFIG0_YA_DISABLE BIT(1) 393 #define INV_ICM42600_SENSOR_CONFIG0_XA_DISABLE BIT(0) 394 395 /* Timestamp value is 20 bits (3 registers) in little-endian */ 396 #define INV_ICM42600_REG_TMSTVAL 0x1062 397 #define INV_ICM42600_TMSTVAL_MASK GENMASK(19, 0) 398 399 #define INV_ICM42600_REG_INTF_CONFIG4 0x107A 400 #define INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY BIT(6) 401 #define INV_ICM42600_INTF_CONFIG4_SPI_AP_4WIRE BIT(1) 402 403 #define INV_ICM42600_REG_INTF_CONFIG6 0x107C 404 #define INV_ICM42600_INTF_CONFIG6_MASK GENMASK(4, 0) 405 #define INV_ICM42600_INTF_CONFIG6_I3C_EN BIT(4) 406 #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_BYTE_EN BIT(3) 407 #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_EN BIT(2) 408 #define INV_ICM42600_INTF_CONFIG6_I3C_DDR_EN BIT(1) 409 #define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN BIT(0) 410 411 /* User bank 4 (MSB 0x40) */ 412 #define INV_ICM42600_REG_ACCEL_WOM_X_THR 0x404A 413 #define INV_ICM42600_REG_ACCEL_WOM_Y_THR 0x404B 414 #define INV_ICM42600_REG_ACCEL_WOM_Z_THR 0x404C 415 416 #define INV_ICM42600_REG_INT_SOURCE8 0x404F 417 #define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN BIT(5) 418 #define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN BIT(4) 419 #define INV_ICM42600_INT_SOURCE8_UI_DRDY_IBI_EN BIT(3) 420 #define INV_ICM42600_INT_SOURCE8_FIFO_THS_IBI_EN BIT(2) 421 #define INV_ICM42600_INT_SOURCE8_FIFO_FULL_IBI_EN BIT(1) 422 #define INV_ICM42600_INT_SOURCE8_AGC_RDY_IBI_EN BIT(0) 423 424 #define INV_ICM42600_REG_OFFSET_USER0 0x4077 425 #define INV_ICM42600_REG_OFFSET_USER1 0x4078 426 #define INV_ICM42600_REG_OFFSET_USER2 0x4079 427 #define INV_ICM42600_REG_OFFSET_USER3 0x407A 428 #define INV_ICM42600_REG_OFFSET_USER4 0x407B 429 #define INV_ICM42600_REG_OFFSET_USER5 0x407C 430 #define INV_ICM42600_REG_OFFSET_USER6 0x407D 431 #define INV_ICM42600_REG_OFFSET_USER7 0x407E 432 #define INV_ICM42600_REG_OFFSET_USER8 0x407F 433 434 /* Sleep times required by the driver */ 435 #define INV_ICM42600_POWER_UP_TIME_MS 100 436 #define INV_ICM42600_RESET_TIME_MS 1 437 #define INV_ICM42600_ACCEL_STARTUP_TIME_MS 20 438 #define INV_ICM42600_GYRO_STARTUP_TIME_MS 60 439 #define INV_ICM42600_GYRO_STOP_TIME_MS 150 440 #define INV_ICM42600_TEMP_STARTUP_TIME_MS 14 441 #define INV_ICM42600_SUSPEND_DELAY_MS 2000 442 443 typedef int (*inv_icm42600_bus_setup)(struct inv_icm42600_state *); 444 445 extern const struct regmap_config inv_icm42600_regmap_config; 446 extern const struct regmap_config inv_icm42600_spi_regmap_config; 447 extern const struct dev_pm_ops inv_icm42600_pm_ops; 448 449 const struct iio_mount_matrix * 450 inv_icm42600_get_mount_matrix(const struct iio_dev *indio_dev, 451 const struct iio_chan_spec *chan); 452 453 u32 inv_icm42600_odr_to_period(enum inv_icm42600_odr odr); 454 455 int inv_icm42600_set_accel_conf(struct inv_icm42600_state *st, 456 struct inv_icm42600_sensor_conf *conf, 457 unsigned int *sleep_ms); 458 459 int inv_icm42600_set_gyro_conf(struct inv_icm42600_state *st, 460 struct inv_icm42600_sensor_conf *conf, 461 unsigned int *sleep_ms); 462 463 int inv_icm42600_set_temp_conf(struct inv_icm42600_state *st, bool enable, 464 unsigned int *sleep_ms); 465 466 int inv_icm42600_enable_wom(struct inv_icm42600_state *st); 467 int inv_icm42600_disable_wom(struct inv_icm42600_state *st); 468 469 int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg, 470 unsigned int writeval, unsigned int *readval); 471 472 int inv_icm42600_core_probe(struct regmap *regmap, int chip, 473 inv_icm42600_bus_setup bus_setup); 474 475 struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st); 476 477 int inv_icm42600_gyro_parse_fifo(struct iio_dev *indio_dev); 478 479 struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st); 480 481 int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev); 482 483 void inv_icm42600_accel_handle_events(struct iio_dev *indio_dev, 484 unsigned int status2, unsigned int status3, 485 s64 timestamp); 486 487 #endif 488