1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BMI160 - Bosch IMU (accel, gyro plus external magnetometer) 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * Copyright (c) 2019, Martin Kelly. 7 * 8 * IIO core driver for BMI160, with support for I2C/SPI busses 9 * 10 * TODO: magnetometer, hardware FIFO 11 */ 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/acpi.h> 15 #include <linux/delay.h> 16 #include <linux/irq.h> 17 #include <linux/of_irq.h> 18 #include <linux/regulator/consumer.h> 19 20 #include <linux/iio/iio.h> 21 #include <linux/iio/triggered_buffer.h> 22 #include <linux/iio/trigger_consumer.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/trigger.h> 26 27 #include "bmi160.h" 28 29 #define BMI160_REG_CHIP_ID 0x00 30 #define BMI160_CHIP_ID_VAL 0xD1 31 32 #define BMI160_REG_PMU_STATUS 0x03 33 34 /* X axis data low byte address, the rest can be obtained using axis offset */ 35 #define BMI160_REG_DATA_MAGN_XOUT_L 0x04 36 #define BMI160_REG_DATA_GYRO_XOUT_L 0x0C 37 #define BMI160_REG_DATA_ACCEL_XOUT_L 0x12 38 39 #define BMI160_REG_ACCEL_CONFIG 0x40 40 #define BMI160_ACCEL_CONFIG_ODR_MASK GENMASK(3, 0) 41 #define BMI160_ACCEL_CONFIG_BWP_MASK GENMASK(6, 4) 42 43 #define BMI160_REG_ACCEL_RANGE 0x41 44 #define BMI160_ACCEL_RANGE_2G 0x03 45 #define BMI160_ACCEL_RANGE_4G 0x05 46 #define BMI160_ACCEL_RANGE_8G 0x08 47 #define BMI160_ACCEL_RANGE_16G 0x0C 48 49 #define BMI160_REG_GYRO_CONFIG 0x42 50 #define BMI160_GYRO_CONFIG_ODR_MASK GENMASK(3, 0) 51 #define BMI160_GYRO_CONFIG_BWP_MASK GENMASK(5, 4) 52 53 #define BMI160_REG_GYRO_RANGE 0x43 54 #define BMI160_GYRO_RANGE_2000DPS 0x00 55 #define BMI160_GYRO_RANGE_1000DPS 0x01 56 #define BMI160_GYRO_RANGE_500DPS 0x02 57 #define BMI160_GYRO_RANGE_250DPS 0x03 58 #define BMI160_GYRO_RANGE_125DPS 0x04 59 60 #define BMI160_REG_CMD 0x7E 61 #define BMI160_CMD_ACCEL_PM_SUSPEND 0x10 62 #define BMI160_CMD_ACCEL_PM_NORMAL 0x11 63 #define BMI160_CMD_ACCEL_PM_LOW_POWER 0x12 64 #define BMI160_CMD_GYRO_PM_SUSPEND 0x14 65 #define BMI160_CMD_GYRO_PM_NORMAL 0x15 66 #define BMI160_CMD_GYRO_PM_FAST_STARTUP 0x17 67 #define BMI160_CMD_SOFTRESET 0xB6 68 69 #define BMI160_REG_INT_EN 0x51 70 #define BMI160_DRDY_INT_EN BIT(4) 71 72 #define BMI160_REG_INT_OUT_CTRL 0x53 73 #define BMI160_INT_OUT_CTRL_MASK 0x0f 74 #define BMI160_INT1_OUT_CTRL_SHIFT 0 75 #define BMI160_INT2_OUT_CTRL_SHIFT 4 76 #define BMI160_EDGE_TRIGGERED BIT(0) 77 #define BMI160_ACTIVE_HIGH BIT(1) 78 #define BMI160_OPEN_DRAIN BIT(2) 79 #define BMI160_OUTPUT_EN BIT(3) 80 81 #define BMI160_REG_INT_LATCH 0x54 82 #define BMI160_INT1_LATCH_MASK BIT(4) 83 #define BMI160_INT2_LATCH_MASK BIT(5) 84 85 /* INT1 and INT2 are in the opposite order as in INT_OUT_CTRL! */ 86 #define BMI160_REG_INT_MAP 0x56 87 #define BMI160_INT1_MAP_DRDY_EN 0x80 88 #define BMI160_INT2_MAP_DRDY_EN 0x08 89 90 #define BMI160_REG_DUMMY 0x7F 91 92 #define BMI160_NORMAL_WRITE_USLEEP 2 93 #define BMI160_SUSPENDED_WRITE_USLEEP 450 94 95 #define BMI160_ACCEL_PMU_MIN_USLEEP 3800 96 #define BMI160_GYRO_PMU_MIN_USLEEP 80000 97 #define BMI160_SOFTRESET_USLEEP 1000 98 99 #define BMI160_CHANNEL(_type, _axis, _index) { \ 100 .type = _type, \ 101 .modified = 1, \ 102 .channel2 = IIO_MOD_##_axis, \ 103 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 104 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 105 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 106 .scan_index = _index, \ 107 .scan_type = { \ 108 .sign = 's', \ 109 .realbits = 16, \ 110 .storagebits = 16, \ 111 .endianness = IIO_LE, \ 112 }, \ 113 .ext_info = bmi160_ext_info, \ 114 } 115 116 /* scan indexes follow DATA register order */ 117 enum bmi160_scan_axis { 118 BMI160_SCAN_EXT_MAGN_X = 0, 119 BMI160_SCAN_EXT_MAGN_Y, 120 BMI160_SCAN_EXT_MAGN_Z, 121 BMI160_SCAN_RHALL, 122 BMI160_SCAN_GYRO_X, 123 BMI160_SCAN_GYRO_Y, 124 BMI160_SCAN_GYRO_Z, 125 BMI160_SCAN_ACCEL_X, 126 BMI160_SCAN_ACCEL_Y, 127 BMI160_SCAN_ACCEL_Z, 128 BMI160_SCAN_TIMESTAMP, 129 }; 130 131 enum bmi160_sensor_type { 132 BMI160_ACCEL = 0, 133 BMI160_GYRO, 134 BMI160_EXT_MAGN, 135 BMI160_NUM_SENSORS /* must be last */ 136 }; 137 138 enum bmi160_int_pin { 139 BMI160_PIN_INT1, 140 BMI160_PIN_INT2 141 }; 142 143 const struct regmap_config bmi160_regmap_config = { 144 .reg_bits = 8, 145 .val_bits = 8, 146 }; 147 EXPORT_SYMBOL(bmi160_regmap_config); 148 149 struct bmi160_regs { 150 u8 data; /* LSB byte register for X-axis */ 151 u8 config; 152 u8 config_odr_mask; 153 u8 config_bwp_mask; 154 u8 range; 155 u8 pmu_cmd_normal; 156 u8 pmu_cmd_suspend; 157 }; 158 159 static struct bmi160_regs bmi160_regs[] = { 160 [BMI160_ACCEL] = { 161 .data = BMI160_REG_DATA_ACCEL_XOUT_L, 162 .config = BMI160_REG_ACCEL_CONFIG, 163 .config_odr_mask = BMI160_ACCEL_CONFIG_ODR_MASK, 164 .config_bwp_mask = BMI160_ACCEL_CONFIG_BWP_MASK, 165 .range = BMI160_REG_ACCEL_RANGE, 166 .pmu_cmd_normal = BMI160_CMD_ACCEL_PM_NORMAL, 167 .pmu_cmd_suspend = BMI160_CMD_ACCEL_PM_SUSPEND, 168 }, 169 [BMI160_GYRO] = { 170 .data = BMI160_REG_DATA_GYRO_XOUT_L, 171 .config = BMI160_REG_GYRO_CONFIG, 172 .config_odr_mask = BMI160_GYRO_CONFIG_ODR_MASK, 173 .config_bwp_mask = BMI160_GYRO_CONFIG_BWP_MASK, 174 .range = BMI160_REG_GYRO_RANGE, 175 .pmu_cmd_normal = BMI160_CMD_GYRO_PM_NORMAL, 176 .pmu_cmd_suspend = BMI160_CMD_GYRO_PM_SUSPEND, 177 }, 178 }; 179 180 static unsigned long bmi160_pmu_time[] = { 181 [BMI160_ACCEL] = BMI160_ACCEL_PMU_MIN_USLEEP, 182 [BMI160_GYRO] = BMI160_GYRO_PMU_MIN_USLEEP, 183 }; 184 185 struct bmi160_scale { 186 u8 bits; 187 int uscale; 188 }; 189 190 struct bmi160_odr { 191 u8 bits; 192 int odr; 193 int uodr; 194 }; 195 196 static const struct bmi160_scale bmi160_accel_scale[] = { 197 { BMI160_ACCEL_RANGE_2G, 598}, 198 { BMI160_ACCEL_RANGE_4G, 1197}, 199 { BMI160_ACCEL_RANGE_8G, 2394}, 200 { BMI160_ACCEL_RANGE_16G, 4788}, 201 }; 202 203 static const struct bmi160_scale bmi160_gyro_scale[] = { 204 { BMI160_GYRO_RANGE_2000DPS, 1065}, 205 { BMI160_GYRO_RANGE_1000DPS, 532}, 206 { BMI160_GYRO_RANGE_500DPS, 266}, 207 { BMI160_GYRO_RANGE_250DPS, 133}, 208 { BMI160_GYRO_RANGE_125DPS, 66}, 209 }; 210 211 struct bmi160_scale_item { 212 const struct bmi160_scale *tbl; 213 int num; 214 }; 215 216 static const struct bmi160_scale_item bmi160_scale_table[] = { 217 [BMI160_ACCEL] = { 218 .tbl = bmi160_accel_scale, 219 .num = ARRAY_SIZE(bmi160_accel_scale), 220 }, 221 [BMI160_GYRO] = { 222 .tbl = bmi160_gyro_scale, 223 .num = ARRAY_SIZE(bmi160_gyro_scale), 224 }, 225 }; 226 227 static const struct bmi160_odr bmi160_accel_odr[] = { 228 {0x01, 0, 781250}, 229 {0x02, 1, 562500}, 230 {0x03, 3, 125000}, 231 {0x04, 6, 250000}, 232 {0x05, 12, 500000}, 233 {0x06, 25, 0}, 234 {0x07, 50, 0}, 235 {0x08, 100, 0}, 236 {0x09, 200, 0}, 237 {0x0A, 400, 0}, 238 {0x0B, 800, 0}, 239 {0x0C, 1600, 0}, 240 }; 241 242 static const struct bmi160_odr bmi160_gyro_odr[] = { 243 {0x06, 25, 0}, 244 {0x07, 50, 0}, 245 {0x08, 100, 0}, 246 {0x09, 200, 0}, 247 {0x0A, 400, 0}, 248 {0x0B, 800, 0}, 249 {0x0C, 1600, 0}, 250 {0x0D, 3200, 0}, 251 }; 252 253 struct bmi160_odr_item { 254 const struct bmi160_odr *tbl; 255 int num; 256 }; 257 258 static const struct bmi160_odr_item bmi160_odr_table[] = { 259 [BMI160_ACCEL] = { 260 .tbl = bmi160_accel_odr, 261 .num = ARRAY_SIZE(bmi160_accel_odr), 262 }, 263 [BMI160_GYRO] = { 264 .tbl = bmi160_gyro_odr, 265 .num = ARRAY_SIZE(bmi160_gyro_odr), 266 }, 267 }; 268 269 static const struct iio_mount_matrix * 270 bmi160_get_mount_matrix(const struct iio_dev *indio_dev, 271 const struct iio_chan_spec *chan) 272 { 273 struct bmi160_data *data = iio_priv(indio_dev); 274 275 return &data->orientation; 276 } 277 278 static const struct iio_chan_spec_ext_info bmi160_ext_info[] = { 279 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmi160_get_mount_matrix), 280 { } 281 }; 282 283 static const struct iio_chan_spec bmi160_channels[] = { 284 BMI160_CHANNEL(IIO_ACCEL, X, BMI160_SCAN_ACCEL_X), 285 BMI160_CHANNEL(IIO_ACCEL, Y, BMI160_SCAN_ACCEL_Y), 286 BMI160_CHANNEL(IIO_ACCEL, Z, BMI160_SCAN_ACCEL_Z), 287 BMI160_CHANNEL(IIO_ANGL_VEL, X, BMI160_SCAN_GYRO_X), 288 BMI160_CHANNEL(IIO_ANGL_VEL, Y, BMI160_SCAN_GYRO_Y), 289 BMI160_CHANNEL(IIO_ANGL_VEL, Z, BMI160_SCAN_GYRO_Z), 290 IIO_CHAN_SOFT_TIMESTAMP(BMI160_SCAN_TIMESTAMP), 291 }; 292 293 static enum bmi160_sensor_type bmi160_to_sensor(enum iio_chan_type iio_type) 294 { 295 switch (iio_type) { 296 case IIO_ACCEL: 297 return BMI160_ACCEL; 298 case IIO_ANGL_VEL: 299 return BMI160_GYRO; 300 default: 301 return -EINVAL; 302 } 303 } 304 305 static 306 int bmi160_set_mode(struct bmi160_data *data, enum bmi160_sensor_type t, 307 bool mode) 308 { 309 int ret; 310 u8 cmd; 311 312 if (mode) 313 cmd = bmi160_regs[t].pmu_cmd_normal; 314 else 315 cmd = bmi160_regs[t].pmu_cmd_suspend; 316 317 ret = regmap_write(data->regmap, BMI160_REG_CMD, cmd); 318 if (ret) 319 return ret; 320 321 usleep_range(bmi160_pmu_time[t], bmi160_pmu_time[t] + 1000); 322 323 return 0; 324 } 325 326 static 327 int bmi160_set_scale(struct bmi160_data *data, enum bmi160_sensor_type t, 328 int uscale) 329 { 330 int i; 331 332 for (i = 0; i < bmi160_scale_table[t].num; i++) 333 if (bmi160_scale_table[t].tbl[i].uscale == uscale) 334 break; 335 336 if (i == bmi160_scale_table[t].num) 337 return -EINVAL; 338 339 return regmap_write(data->regmap, bmi160_regs[t].range, 340 bmi160_scale_table[t].tbl[i].bits); 341 } 342 343 static 344 int bmi160_get_scale(struct bmi160_data *data, enum bmi160_sensor_type t, 345 int *uscale) 346 { 347 int i, ret, val; 348 349 ret = regmap_read(data->regmap, bmi160_regs[t].range, &val); 350 if (ret) 351 return ret; 352 353 for (i = 0; i < bmi160_scale_table[t].num; i++) 354 if (bmi160_scale_table[t].tbl[i].bits == val) { 355 *uscale = bmi160_scale_table[t].tbl[i].uscale; 356 return 0; 357 } 358 359 return -EINVAL; 360 } 361 362 static int bmi160_get_data(struct bmi160_data *data, int chan_type, 363 int axis, int *val) 364 { 365 u8 reg; 366 int ret; 367 __le16 sample; 368 enum bmi160_sensor_type t = bmi160_to_sensor(chan_type); 369 370 reg = bmi160_regs[t].data + (axis - IIO_MOD_X) * sizeof(sample); 371 372 ret = regmap_bulk_read(data->regmap, reg, &sample, sizeof(sample)); 373 if (ret) 374 return ret; 375 376 *val = sign_extend32(le16_to_cpu(sample), 15); 377 378 return 0; 379 } 380 381 static 382 int bmi160_set_odr(struct bmi160_data *data, enum bmi160_sensor_type t, 383 int odr, int uodr) 384 { 385 int i; 386 387 for (i = 0; i < bmi160_odr_table[t].num; i++) 388 if (bmi160_odr_table[t].tbl[i].odr == odr && 389 bmi160_odr_table[t].tbl[i].uodr == uodr) 390 break; 391 392 if (i >= bmi160_odr_table[t].num) 393 return -EINVAL; 394 395 return regmap_update_bits(data->regmap, 396 bmi160_regs[t].config, 397 bmi160_regs[t].config_odr_mask, 398 bmi160_odr_table[t].tbl[i].bits); 399 } 400 401 static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t, 402 int *odr, int *uodr) 403 { 404 int i, val, ret; 405 406 ret = regmap_read(data->regmap, bmi160_regs[t].config, &val); 407 if (ret) 408 return ret; 409 410 val &= bmi160_regs[t].config_odr_mask; 411 412 for (i = 0; i < bmi160_odr_table[t].num; i++) 413 if (val == bmi160_odr_table[t].tbl[i].bits) 414 break; 415 416 if (i >= bmi160_odr_table[t].num) 417 return -EINVAL; 418 419 *odr = bmi160_odr_table[t].tbl[i].odr; 420 *uodr = bmi160_odr_table[t].tbl[i].uodr; 421 422 return 0; 423 } 424 425 static irqreturn_t bmi160_trigger_handler(int irq, void *p) 426 { 427 struct iio_poll_func *pf = p; 428 struct iio_dev *indio_dev = pf->indio_dev; 429 struct bmi160_data *data = iio_priv(indio_dev); 430 int i, ret, j = 0, base = BMI160_REG_DATA_MAGN_XOUT_L; 431 __le16 sample; 432 433 for_each_set_bit(i, indio_dev->active_scan_mask, 434 indio_dev->masklength) { 435 ret = regmap_bulk_read(data->regmap, base + i * sizeof(sample), 436 &sample, sizeof(sample)); 437 if (ret) 438 goto done; 439 data->buf[j++] = sample; 440 } 441 442 iio_push_to_buffers_with_timestamp(indio_dev, data->buf, pf->timestamp); 443 done: 444 iio_trigger_notify_done(indio_dev->trig); 445 return IRQ_HANDLED; 446 } 447 448 static int bmi160_read_raw(struct iio_dev *indio_dev, 449 struct iio_chan_spec const *chan, 450 int *val, int *val2, long mask) 451 { 452 int ret; 453 struct bmi160_data *data = iio_priv(indio_dev); 454 455 switch (mask) { 456 case IIO_CHAN_INFO_RAW: 457 ret = bmi160_get_data(data, chan->type, chan->channel2, val); 458 if (ret) 459 return ret; 460 return IIO_VAL_INT; 461 case IIO_CHAN_INFO_SCALE: 462 *val = 0; 463 ret = bmi160_get_scale(data, 464 bmi160_to_sensor(chan->type), val2); 465 return ret ? ret : IIO_VAL_INT_PLUS_MICRO; 466 case IIO_CHAN_INFO_SAMP_FREQ: 467 ret = bmi160_get_odr(data, bmi160_to_sensor(chan->type), 468 val, val2); 469 return ret ? ret : IIO_VAL_INT_PLUS_MICRO; 470 default: 471 return -EINVAL; 472 } 473 474 return 0; 475 } 476 477 static int bmi160_write_raw(struct iio_dev *indio_dev, 478 struct iio_chan_spec const *chan, 479 int val, int val2, long mask) 480 { 481 struct bmi160_data *data = iio_priv(indio_dev); 482 483 switch (mask) { 484 case IIO_CHAN_INFO_SCALE: 485 return bmi160_set_scale(data, 486 bmi160_to_sensor(chan->type), val2); 487 case IIO_CHAN_INFO_SAMP_FREQ: 488 return bmi160_set_odr(data, bmi160_to_sensor(chan->type), 489 val, val2); 490 default: 491 return -EINVAL; 492 } 493 494 return 0; 495 } 496 497 static 498 IIO_CONST_ATTR(in_accel_sampling_frequency_available, 499 "0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600"); 500 static 501 IIO_CONST_ATTR(in_anglvel_sampling_frequency_available, 502 "25 50 100 200 400 800 1600 3200"); 503 static 504 IIO_CONST_ATTR(in_accel_scale_available, 505 "0.000598 0.001197 0.002394 0.004788"); 506 static 507 IIO_CONST_ATTR(in_anglvel_scale_available, 508 "0.001065 0.000532 0.000266 0.000133 0.000066"); 509 510 static struct attribute *bmi160_attrs[] = { 511 &iio_const_attr_in_accel_sampling_frequency_available.dev_attr.attr, 512 &iio_const_attr_in_anglvel_sampling_frequency_available.dev_attr.attr, 513 &iio_const_attr_in_accel_scale_available.dev_attr.attr, 514 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 515 NULL, 516 }; 517 518 static const struct attribute_group bmi160_attrs_group = { 519 .attrs = bmi160_attrs, 520 }; 521 522 static const struct iio_info bmi160_info = { 523 .read_raw = bmi160_read_raw, 524 .write_raw = bmi160_write_raw, 525 .attrs = &bmi160_attrs_group, 526 }; 527 528 static const char *bmi160_match_acpi_device(struct device *dev) 529 { 530 const struct acpi_device_id *id; 531 532 id = acpi_match_device(dev->driver->acpi_match_table, dev); 533 if (!id) 534 return NULL; 535 536 return dev_name(dev); 537 } 538 539 static int bmi160_write_conf_reg(struct regmap *regmap, unsigned int reg, 540 unsigned int mask, unsigned int bits, 541 unsigned int write_usleep) 542 { 543 int ret; 544 unsigned int val; 545 546 ret = regmap_read(regmap, reg, &val); 547 if (ret) 548 return ret; 549 550 val = (val & ~mask) | bits; 551 552 ret = regmap_write(regmap, reg, val); 553 if (ret) 554 return ret; 555 556 /* 557 * We need to wait after writing before we can write again. See the 558 * datasheet, page 93. 559 */ 560 usleep_range(write_usleep, write_usleep + 1000); 561 562 return 0; 563 } 564 565 static int bmi160_config_pin(struct regmap *regmap, enum bmi160_int_pin pin, 566 bool open_drain, u8 irq_mask, 567 unsigned long write_usleep) 568 { 569 int ret; 570 struct device *dev = regmap_get_device(regmap); 571 u8 int_out_ctrl_shift; 572 u8 int_latch_mask; 573 u8 int_map_mask; 574 u8 int_out_ctrl_mask; 575 u8 int_out_ctrl_bits; 576 const char *pin_name; 577 578 switch (pin) { 579 case BMI160_PIN_INT1: 580 int_out_ctrl_shift = BMI160_INT1_OUT_CTRL_SHIFT; 581 int_latch_mask = BMI160_INT1_LATCH_MASK; 582 int_map_mask = BMI160_INT1_MAP_DRDY_EN; 583 break; 584 case BMI160_PIN_INT2: 585 int_out_ctrl_shift = BMI160_INT2_OUT_CTRL_SHIFT; 586 int_latch_mask = BMI160_INT2_LATCH_MASK; 587 int_map_mask = BMI160_INT2_MAP_DRDY_EN; 588 break; 589 } 590 int_out_ctrl_mask = BMI160_INT_OUT_CTRL_MASK << int_out_ctrl_shift; 591 592 /* 593 * Enable the requested pin with the right settings: 594 * - Push-pull/open-drain 595 * - Active low/high 596 * - Edge/level triggered 597 */ 598 int_out_ctrl_bits = BMI160_OUTPUT_EN; 599 if (open_drain) 600 /* Default is push-pull. */ 601 int_out_ctrl_bits |= BMI160_OPEN_DRAIN; 602 int_out_ctrl_bits |= irq_mask; 603 int_out_ctrl_bits <<= int_out_ctrl_shift; 604 605 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_OUT_CTRL, 606 int_out_ctrl_mask, int_out_ctrl_bits, 607 write_usleep); 608 if (ret) 609 return ret; 610 611 /* Set the pin to input mode with no latching. */ 612 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_LATCH, 613 int_latch_mask, int_latch_mask, 614 write_usleep); 615 if (ret) 616 return ret; 617 618 /* Map interrupts to the requested pin. */ 619 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_MAP, 620 int_map_mask, int_map_mask, 621 write_usleep); 622 if (ret) { 623 switch (pin) { 624 case BMI160_PIN_INT1: 625 pin_name = "INT1"; 626 break; 627 case BMI160_PIN_INT2: 628 pin_name = "INT2"; 629 break; 630 } 631 dev_err(dev, "Failed to configure %s IRQ pin", pin_name); 632 } 633 634 return ret; 635 } 636 637 int bmi160_enable_irq(struct regmap *regmap, bool enable) 638 { 639 unsigned int enable_bit = 0; 640 641 if (enable) 642 enable_bit = BMI160_DRDY_INT_EN; 643 644 return bmi160_write_conf_reg(regmap, BMI160_REG_INT_EN, 645 BMI160_DRDY_INT_EN, enable_bit, 646 BMI160_NORMAL_WRITE_USLEEP); 647 } 648 EXPORT_SYMBOL(bmi160_enable_irq); 649 650 static int bmi160_get_irq(struct device_node *of_node, enum bmi160_int_pin *pin) 651 { 652 int irq; 653 654 /* Use INT1 if possible, otherwise fall back to INT2. */ 655 irq = of_irq_get_byname(of_node, "INT1"); 656 if (irq > 0) { 657 *pin = BMI160_PIN_INT1; 658 return irq; 659 } 660 661 irq = of_irq_get_byname(of_node, "INT2"); 662 if (irq > 0) 663 *pin = BMI160_PIN_INT2; 664 665 return irq; 666 } 667 668 static int bmi160_config_device_irq(struct iio_dev *indio_dev, int irq_type, 669 enum bmi160_int_pin pin) 670 { 671 bool open_drain; 672 u8 irq_mask; 673 struct bmi160_data *data = iio_priv(indio_dev); 674 struct device *dev = regmap_get_device(data->regmap); 675 676 /* Level-triggered, active-low is the default if we set all zeroes. */ 677 if (irq_type == IRQF_TRIGGER_RISING) 678 irq_mask = BMI160_ACTIVE_HIGH | BMI160_EDGE_TRIGGERED; 679 else if (irq_type == IRQF_TRIGGER_FALLING) 680 irq_mask = BMI160_EDGE_TRIGGERED; 681 else if (irq_type == IRQF_TRIGGER_HIGH) 682 irq_mask = BMI160_ACTIVE_HIGH; 683 else if (irq_type == IRQF_TRIGGER_LOW) 684 irq_mask = 0; 685 else { 686 dev_err(&indio_dev->dev, 687 "Invalid interrupt type 0x%x specified\n", irq_type); 688 return -EINVAL; 689 } 690 691 open_drain = of_property_read_bool(dev->of_node, "drive-open-drain"); 692 693 return bmi160_config_pin(data->regmap, pin, open_drain, irq_mask, 694 BMI160_NORMAL_WRITE_USLEEP); 695 } 696 697 static int bmi160_setup_irq(struct iio_dev *indio_dev, int irq, 698 enum bmi160_int_pin pin) 699 { 700 struct irq_data *desc; 701 u32 irq_type; 702 int ret; 703 704 desc = irq_get_irq_data(irq); 705 if (!desc) { 706 dev_err(&indio_dev->dev, "Could not find IRQ %d\n", irq); 707 return -EINVAL; 708 } 709 710 irq_type = irqd_get_trigger_type(desc); 711 712 ret = bmi160_config_device_irq(indio_dev, irq_type, pin); 713 if (ret) 714 return ret; 715 716 return bmi160_probe_trigger(indio_dev, irq, irq_type); 717 } 718 719 static int bmi160_chip_init(struct bmi160_data *data, bool use_spi) 720 { 721 int ret; 722 unsigned int val; 723 struct device *dev = regmap_get_device(data->regmap); 724 725 ret = regulator_bulk_enable(ARRAY_SIZE(data->supplies), data->supplies); 726 if (ret) { 727 dev_err(dev, "Failed to enable regulators: %d\n", ret); 728 return ret; 729 } 730 731 ret = regmap_write(data->regmap, BMI160_REG_CMD, BMI160_CMD_SOFTRESET); 732 if (ret) 733 return ret; 734 735 usleep_range(BMI160_SOFTRESET_USLEEP, BMI160_SOFTRESET_USLEEP + 1); 736 737 /* 738 * CS rising edge is needed before starting SPI, so do a dummy read 739 * See Section 3.2.1, page 86 of the datasheet 740 */ 741 if (use_spi) { 742 ret = regmap_read(data->regmap, BMI160_REG_DUMMY, &val); 743 if (ret) 744 return ret; 745 } 746 747 ret = regmap_read(data->regmap, BMI160_REG_CHIP_ID, &val); 748 if (ret) { 749 dev_err(dev, "Error reading chip id\n"); 750 return ret; 751 } 752 if (val != BMI160_CHIP_ID_VAL) { 753 dev_err(dev, "Wrong chip id, got %x expected %x\n", 754 val, BMI160_CHIP_ID_VAL); 755 return -ENODEV; 756 } 757 758 ret = bmi160_set_mode(data, BMI160_ACCEL, true); 759 if (ret) 760 return ret; 761 762 ret = bmi160_set_mode(data, BMI160_GYRO, true); 763 if (ret) 764 return ret; 765 766 return 0; 767 } 768 769 static int bmi160_data_rdy_trigger_set_state(struct iio_trigger *trig, 770 bool enable) 771 { 772 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 773 struct bmi160_data *data = iio_priv(indio_dev); 774 775 return bmi160_enable_irq(data->regmap, enable); 776 } 777 778 static const struct iio_trigger_ops bmi160_trigger_ops = { 779 .set_trigger_state = &bmi160_data_rdy_trigger_set_state, 780 }; 781 782 int bmi160_probe_trigger(struct iio_dev *indio_dev, int irq, u32 irq_type) 783 { 784 struct bmi160_data *data = iio_priv(indio_dev); 785 int ret; 786 787 data->trig = devm_iio_trigger_alloc(&indio_dev->dev, "%s-dev%d", 788 indio_dev->name, indio_dev->id); 789 790 if (data->trig == NULL) 791 return -ENOMEM; 792 793 ret = devm_request_irq(&indio_dev->dev, irq, 794 &iio_trigger_generic_data_rdy_poll, 795 irq_type, "bmi160", data->trig); 796 if (ret) 797 return ret; 798 799 data->trig->dev.parent = regmap_get_device(data->regmap); 800 data->trig->ops = &bmi160_trigger_ops; 801 iio_trigger_set_drvdata(data->trig, indio_dev); 802 803 ret = devm_iio_trigger_register(&indio_dev->dev, data->trig); 804 if (ret) 805 return ret; 806 807 indio_dev->trig = iio_trigger_get(data->trig); 808 809 return 0; 810 } 811 812 static void bmi160_chip_uninit(void *data) 813 { 814 struct bmi160_data *bmi_data = data; 815 struct device *dev = regmap_get_device(bmi_data->regmap); 816 int ret; 817 818 bmi160_set_mode(bmi_data, BMI160_GYRO, false); 819 bmi160_set_mode(bmi_data, BMI160_ACCEL, false); 820 821 ret = regulator_bulk_disable(ARRAY_SIZE(bmi_data->supplies), 822 bmi_data->supplies); 823 if (ret) 824 dev_err(dev, "Failed to disable regulators: %d\n", ret); 825 } 826 827 int bmi160_core_probe(struct device *dev, struct regmap *regmap, 828 const char *name, bool use_spi) 829 { 830 struct iio_dev *indio_dev; 831 struct bmi160_data *data; 832 int irq; 833 enum bmi160_int_pin int_pin; 834 int ret; 835 836 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 837 if (!indio_dev) 838 return -ENOMEM; 839 840 data = iio_priv(indio_dev); 841 dev_set_drvdata(dev, indio_dev); 842 data->regmap = regmap; 843 844 data->supplies[0].supply = "vdd"; 845 data->supplies[1].supply = "vddio"; 846 ret = devm_regulator_bulk_get(dev, 847 ARRAY_SIZE(data->supplies), 848 data->supplies); 849 if (ret) { 850 dev_err(dev, "Failed to get regulators: %d\n", ret); 851 return ret; 852 } 853 854 ret = iio_read_mount_matrix(dev, "mount-matrix", 855 &data->orientation); 856 if (ret) 857 return ret; 858 859 ret = bmi160_chip_init(data, use_spi); 860 if (ret) 861 return ret; 862 863 ret = devm_add_action_or_reset(dev, bmi160_chip_uninit, data); 864 if (ret) 865 return ret; 866 867 if (!name && ACPI_HANDLE(dev)) 868 name = bmi160_match_acpi_device(dev); 869 870 indio_dev->channels = bmi160_channels; 871 indio_dev->num_channels = ARRAY_SIZE(bmi160_channels); 872 indio_dev->name = name; 873 indio_dev->modes = INDIO_DIRECT_MODE; 874 indio_dev->info = &bmi160_info; 875 876 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 877 iio_pollfunc_store_time, 878 bmi160_trigger_handler, NULL); 879 if (ret) 880 return ret; 881 882 irq = bmi160_get_irq(dev->of_node, &int_pin); 883 if (irq > 0) { 884 ret = bmi160_setup_irq(indio_dev, irq, int_pin); 885 if (ret) 886 dev_err(&indio_dev->dev, "Failed to setup IRQ %d\n", 887 irq); 888 } else { 889 dev_info(&indio_dev->dev, "Not setting up IRQ trigger\n"); 890 } 891 892 return devm_iio_device_register(dev, indio_dev); 893 } 894 EXPORT_SYMBOL_GPL(bmi160_core_probe); 895 896 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>"); 897 MODULE_DESCRIPTION("Bosch BMI160 driver"); 898 MODULE_LICENSE("GPL v2"); 899