1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BMI160 - Bosch IMU (accel, gyro plus external magnetometer) 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * Copyright (c) 2019, Martin Kelly. 7 * 8 * IIO core driver for BMI160, with support for I2C/SPI busses 9 * 10 * TODO: magnetometer, hardware FIFO 11 */ 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/delay.h> 15 #include <linux/irq.h> 16 #include <linux/property.h> 17 #include <linux/regulator/consumer.h> 18 19 #include <linux/iio/iio.h> 20 #include <linux/iio/triggered_buffer.h> 21 #include <linux/iio/trigger_consumer.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/sysfs.h> 24 #include <linux/iio/trigger.h> 25 26 #include "bmi160.h" 27 28 #define BMI160_REG_CHIP_ID 0x00 29 #define BMI120_CHIP_ID_VAL 0xD3 30 #define BMI160_CHIP_ID_VAL 0xD1 31 32 #define BMI160_REG_PMU_STATUS 0x03 33 34 /* X axis data low byte address, the rest can be obtained using axis offset */ 35 #define BMI160_REG_DATA_MAGN_XOUT_L 0x04 36 #define BMI160_REG_DATA_GYRO_XOUT_L 0x0C 37 #define BMI160_REG_DATA_ACCEL_XOUT_L 0x12 38 39 #define BMI160_REG_ACCEL_CONFIG 0x40 40 #define BMI160_ACCEL_CONFIG_ODR_MASK GENMASK(3, 0) 41 #define BMI160_ACCEL_CONFIG_BWP_MASK GENMASK(6, 4) 42 43 #define BMI160_REG_ACCEL_RANGE 0x41 44 #define BMI160_ACCEL_RANGE_2G 0x03 45 #define BMI160_ACCEL_RANGE_4G 0x05 46 #define BMI160_ACCEL_RANGE_8G 0x08 47 #define BMI160_ACCEL_RANGE_16G 0x0C 48 49 #define BMI160_REG_GYRO_CONFIG 0x42 50 #define BMI160_GYRO_CONFIG_ODR_MASK GENMASK(3, 0) 51 #define BMI160_GYRO_CONFIG_BWP_MASK GENMASK(5, 4) 52 53 #define BMI160_REG_GYRO_RANGE 0x43 54 #define BMI160_GYRO_RANGE_2000DPS 0x00 55 #define BMI160_GYRO_RANGE_1000DPS 0x01 56 #define BMI160_GYRO_RANGE_500DPS 0x02 57 #define BMI160_GYRO_RANGE_250DPS 0x03 58 #define BMI160_GYRO_RANGE_125DPS 0x04 59 60 #define BMI160_REG_CMD 0x7E 61 #define BMI160_CMD_ACCEL_PM_SUSPEND 0x10 62 #define BMI160_CMD_ACCEL_PM_NORMAL 0x11 63 #define BMI160_CMD_ACCEL_PM_LOW_POWER 0x12 64 #define BMI160_CMD_GYRO_PM_SUSPEND 0x14 65 #define BMI160_CMD_GYRO_PM_NORMAL 0x15 66 #define BMI160_CMD_GYRO_PM_FAST_STARTUP 0x17 67 #define BMI160_CMD_SOFTRESET 0xB6 68 69 #define BMI160_REG_INT_EN 0x51 70 #define BMI160_DRDY_INT_EN BIT(4) 71 72 #define BMI160_REG_INT_OUT_CTRL 0x53 73 #define BMI160_INT_OUT_CTRL_MASK 0x0f 74 #define BMI160_INT1_OUT_CTRL_SHIFT 0 75 #define BMI160_INT2_OUT_CTRL_SHIFT 4 76 #define BMI160_EDGE_TRIGGERED BIT(0) 77 #define BMI160_ACTIVE_HIGH BIT(1) 78 #define BMI160_OPEN_DRAIN BIT(2) 79 #define BMI160_OUTPUT_EN BIT(3) 80 81 #define BMI160_REG_INT_LATCH 0x54 82 #define BMI160_INT1_LATCH_MASK BIT(4) 83 #define BMI160_INT2_LATCH_MASK BIT(5) 84 85 /* INT1 and INT2 are in the opposite order as in INT_OUT_CTRL! */ 86 #define BMI160_REG_INT_MAP 0x56 87 #define BMI160_INT1_MAP_DRDY_EN 0x80 88 #define BMI160_INT2_MAP_DRDY_EN 0x08 89 90 #define BMI160_REG_DUMMY 0x7F 91 92 #define BMI160_NORMAL_WRITE_USLEEP 2 93 #define BMI160_SUSPENDED_WRITE_USLEEP 450 94 95 #define BMI160_ACCEL_PMU_MIN_USLEEP 3800 96 #define BMI160_GYRO_PMU_MIN_USLEEP 80000 97 #define BMI160_SOFTRESET_USLEEP 1000 98 99 #define BMI160_CHANNEL(_type, _axis, _index) { \ 100 .type = _type, \ 101 .modified = 1, \ 102 .channel2 = IIO_MOD_##_axis, \ 103 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 104 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 105 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 106 .scan_index = _index, \ 107 .scan_type = { \ 108 .sign = 's', \ 109 .realbits = 16, \ 110 .storagebits = 16, \ 111 .endianness = IIO_LE, \ 112 }, \ 113 .ext_info = bmi160_ext_info, \ 114 } 115 116 static const u8 bmi_chip_ids[] = { 117 BMI120_CHIP_ID_VAL, 118 BMI160_CHIP_ID_VAL, 119 }; 120 121 /* scan indexes follow DATA register order */ 122 enum bmi160_scan_axis { 123 BMI160_SCAN_EXT_MAGN_X = 0, 124 BMI160_SCAN_EXT_MAGN_Y, 125 BMI160_SCAN_EXT_MAGN_Z, 126 BMI160_SCAN_RHALL, 127 BMI160_SCAN_GYRO_X, 128 BMI160_SCAN_GYRO_Y, 129 BMI160_SCAN_GYRO_Z, 130 BMI160_SCAN_ACCEL_X, 131 BMI160_SCAN_ACCEL_Y, 132 BMI160_SCAN_ACCEL_Z, 133 BMI160_SCAN_TIMESTAMP, 134 }; 135 136 enum bmi160_sensor_type { 137 BMI160_ACCEL = 0, 138 BMI160_GYRO, 139 BMI160_EXT_MAGN, 140 BMI160_NUM_SENSORS /* must be last */ 141 }; 142 143 enum bmi160_int_pin { 144 BMI160_PIN_INT1, 145 BMI160_PIN_INT2 146 }; 147 148 const struct regmap_config bmi160_regmap_config = { 149 .reg_bits = 8, 150 .val_bits = 8, 151 }; 152 EXPORT_SYMBOL_NS(bmi160_regmap_config, IIO_BMI160); 153 154 struct bmi160_regs { 155 u8 data; /* LSB byte register for X-axis */ 156 u8 config; 157 u8 config_odr_mask; 158 u8 config_bwp_mask; 159 u8 range; 160 u8 pmu_cmd_normal; 161 u8 pmu_cmd_suspend; 162 }; 163 164 static struct bmi160_regs bmi160_regs[] = { 165 [BMI160_ACCEL] = { 166 .data = BMI160_REG_DATA_ACCEL_XOUT_L, 167 .config = BMI160_REG_ACCEL_CONFIG, 168 .config_odr_mask = BMI160_ACCEL_CONFIG_ODR_MASK, 169 .config_bwp_mask = BMI160_ACCEL_CONFIG_BWP_MASK, 170 .range = BMI160_REG_ACCEL_RANGE, 171 .pmu_cmd_normal = BMI160_CMD_ACCEL_PM_NORMAL, 172 .pmu_cmd_suspend = BMI160_CMD_ACCEL_PM_SUSPEND, 173 }, 174 [BMI160_GYRO] = { 175 .data = BMI160_REG_DATA_GYRO_XOUT_L, 176 .config = BMI160_REG_GYRO_CONFIG, 177 .config_odr_mask = BMI160_GYRO_CONFIG_ODR_MASK, 178 .config_bwp_mask = BMI160_GYRO_CONFIG_BWP_MASK, 179 .range = BMI160_REG_GYRO_RANGE, 180 .pmu_cmd_normal = BMI160_CMD_GYRO_PM_NORMAL, 181 .pmu_cmd_suspend = BMI160_CMD_GYRO_PM_SUSPEND, 182 }, 183 }; 184 185 static unsigned long bmi160_pmu_time[] = { 186 [BMI160_ACCEL] = BMI160_ACCEL_PMU_MIN_USLEEP, 187 [BMI160_GYRO] = BMI160_GYRO_PMU_MIN_USLEEP, 188 }; 189 190 struct bmi160_scale { 191 u8 bits; 192 int uscale; 193 }; 194 195 struct bmi160_odr { 196 u8 bits; 197 int odr; 198 int uodr; 199 }; 200 201 static const struct bmi160_scale bmi160_accel_scale[] = { 202 { BMI160_ACCEL_RANGE_2G, 598}, 203 { BMI160_ACCEL_RANGE_4G, 1197}, 204 { BMI160_ACCEL_RANGE_8G, 2394}, 205 { BMI160_ACCEL_RANGE_16G, 4788}, 206 }; 207 208 static const struct bmi160_scale bmi160_gyro_scale[] = { 209 { BMI160_GYRO_RANGE_2000DPS, 1065}, 210 { BMI160_GYRO_RANGE_1000DPS, 532}, 211 { BMI160_GYRO_RANGE_500DPS, 266}, 212 { BMI160_GYRO_RANGE_250DPS, 133}, 213 { BMI160_GYRO_RANGE_125DPS, 66}, 214 }; 215 216 struct bmi160_scale_item { 217 const struct bmi160_scale *tbl; 218 int num; 219 }; 220 221 static const struct bmi160_scale_item bmi160_scale_table[] = { 222 [BMI160_ACCEL] = { 223 .tbl = bmi160_accel_scale, 224 .num = ARRAY_SIZE(bmi160_accel_scale), 225 }, 226 [BMI160_GYRO] = { 227 .tbl = bmi160_gyro_scale, 228 .num = ARRAY_SIZE(bmi160_gyro_scale), 229 }, 230 }; 231 232 static const struct bmi160_odr bmi160_accel_odr[] = { 233 {0x01, 0, 781250}, 234 {0x02, 1, 562500}, 235 {0x03, 3, 125000}, 236 {0x04, 6, 250000}, 237 {0x05, 12, 500000}, 238 {0x06, 25, 0}, 239 {0x07, 50, 0}, 240 {0x08, 100, 0}, 241 {0x09, 200, 0}, 242 {0x0A, 400, 0}, 243 {0x0B, 800, 0}, 244 {0x0C, 1600, 0}, 245 }; 246 247 static const struct bmi160_odr bmi160_gyro_odr[] = { 248 {0x06, 25, 0}, 249 {0x07, 50, 0}, 250 {0x08, 100, 0}, 251 {0x09, 200, 0}, 252 {0x0A, 400, 0}, 253 {0x0B, 800, 0}, 254 {0x0C, 1600, 0}, 255 {0x0D, 3200, 0}, 256 }; 257 258 struct bmi160_odr_item { 259 const struct bmi160_odr *tbl; 260 int num; 261 }; 262 263 static const struct bmi160_odr_item bmi160_odr_table[] = { 264 [BMI160_ACCEL] = { 265 .tbl = bmi160_accel_odr, 266 .num = ARRAY_SIZE(bmi160_accel_odr), 267 }, 268 [BMI160_GYRO] = { 269 .tbl = bmi160_gyro_odr, 270 .num = ARRAY_SIZE(bmi160_gyro_odr), 271 }, 272 }; 273 274 static const struct iio_mount_matrix * 275 bmi160_get_mount_matrix(const struct iio_dev *indio_dev, 276 const struct iio_chan_spec *chan) 277 { 278 struct bmi160_data *data = iio_priv(indio_dev); 279 280 return &data->orientation; 281 } 282 283 static const struct iio_chan_spec_ext_info bmi160_ext_info[] = { 284 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmi160_get_mount_matrix), 285 { } 286 }; 287 288 static const struct iio_chan_spec bmi160_channels[] = { 289 BMI160_CHANNEL(IIO_ACCEL, X, BMI160_SCAN_ACCEL_X), 290 BMI160_CHANNEL(IIO_ACCEL, Y, BMI160_SCAN_ACCEL_Y), 291 BMI160_CHANNEL(IIO_ACCEL, Z, BMI160_SCAN_ACCEL_Z), 292 BMI160_CHANNEL(IIO_ANGL_VEL, X, BMI160_SCAN_GYRO_X), 293 BMI160_CHANNEL(IIO_ANGL_VEL, Y, BMI160_SCAN_GYRO_Y), 294 BMI160_CHANNEL(IIO_ANGL_VEL, Z, BMI160_SCAN_GYRO_Z), 295 IIO_CHAN_SOFT_TIMESTAMP(BMI160_SCAN_TIMESTAMP), 296 }; 297 298 static enum bmi160_sensor_type bmi160_to_sensor(enum iio_chan_type iio_type) 299 { 300 switch (iio_type) { 301 case IIO_ACCEL: 302 return BMI160_ACCEL; 303 case IIO_ANGL_VEL: 304 return BMI160_GYRO; 305 default: 306 return -EINVAL; 307 } 308 } 309 310 static 311 int bmi160_set_mode(struct bmi160_data *data, enum bmi160_sensor_type t, 312 bool mode) 313 { 314 int ret; 315 u8 cmd; 316 317 if (mode) 318 cmd = bmi160_regs[t].pmu_cmd_normal; 319 else 320 cmd = bmi160_regs[t].pmu_cmd_suspend; 321 322 ret = regmap_write(data->regmap, BMI160_REG_CMD, cmd); 323 if (ret) 324 return ret; 325 326 usleep_range(bmi160_pmu_time[t], bmi160_pmu_time[t] + 1000); 327 328 return 0; 329 } 330 331 static 332 int bmi160_set_scale(struct bmi160_data *data, enum bmi160_sensor_type t, 333 int uscale) 334 { 335 int i; 336 337 for (i = 0; i < bmi160_scale_table[t].num; i++) 338 if (bmi160_scale_table[t].tbl[i].uscale == uscale) 339 break; 340 341 if (i == bmi160_scale_table[t].num) 342 return -EINVAL; 343 344 return regmap_write(data->regmap, bmi160_regs[t].range, 345 bmi160_scale_table[t].tbl[i].bits); 346 } 347 348 static 349 int bmi160_get_scale(struct bmi160_data *data, enum bmi160_sensor_type t, 350 int *uscale) 351 { 352 int i, ret, val; 353 354 ret = regmap_read(data->regmap, bmi160_regs[t].range, &val); 355 if (ret) 356 return ret; 357 358 for (i = 0; i < bmi160_scale_table[t].num; i++) 359 if (bmi160_scale_table[t].tbl[i].bits == val) { 360 *uscale = bmi160_scale_table[t].tbl[i].uscale; 361 return 0; 362 } 363 364 return -EINVAL; 365 } 366 367 static int bmi160_get_data(struct bmi160_data *data, int chan_type, 368 int axis, int *val) 369 { 370 u8 reg; 371 int ret; 372 __le16 sample; 373 enum bmi160_sensor_type t = bmi160_to_sensor(chan_type); 374 375 reg = bmi160_regs[t].data + (axis - IIO_MOD_X) * sizeof(sample); 376 377 ret = regmap_bulk_read(data->regmap, reg, &sample, sizeof(sample)); 378 if (ret) 379 return ret; 380 381 *val = sign_extend32(le16_to_cpu(sample), 15); 382 383 return 0; 384 } 385 386 static 387 int bmi160_set_odr(struct bmi160_data *data, enum bmi160_sensor_type t, 388 int odr, int uodr) 389 { 390 int i; 391 392 for (i = 0; i < bmi160_odr_table[t].num; i++) 393 if (bmi160_odr_table[t].tbl[i].odr == odr && 394 bmi160_odr_table[t].tbl[i].uodr == uodr) 395 break; 396 397 if (i >= bmi160_odr_table[t].num) 398 return -EINVAL; 399 400 return regmap_update_bits(data->regmap, 401 bmi160_regs[t].config, 402 bmi160_regs[t].config_odr_mask, 403 bmi160_odr_table[t].tbl[i].bits); 404 } 405 406 static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t, 407 int *odr, int *uodr) 408 { 409 int i, val, ret; 410 411 ret = regmap_read(data->regmap, bmi160_regs[t].config, &val); 412 if (ret) 413 return ret; 414 415 val &= bmi160_regs[t].config_odr_mask; 416 417 for (i = 0; i < bmi160_odr_table[t].num; i++) 418 if (val == bmi160_odr_table[t].tbl[i].bits) 419 break; 420 421 if (i >= bmi160_odr_table[t].num) 422 return -EINVAL; 423 424 *odr = bmi160_odr_table[t].tbl[i].odr; 425 *uodr = bmi160_odr_table[t].tbl[i].uodr; 426 427 return 0; 428 } 429 430 static irqreturn_t bmi160_trigger_handler(int irq, void *p) 431 { 432 struct iio_poll_func *pf = p; 433 struct iio_dev *indio_dev = pf->indio_dev; 434 struct bmi160_data *data = iio_priv(indio_dev); 435 int i, ret, j = 0, base = BMI160_REG_DATA_MAGN_XOUT_L; 436 __le16 sample; 437 438 iio_for_each_active_channel(indio_dev, i) { 439 ret = regmap_bulk_read(data->regmap, base + i * sizeof(sample), 440 &sample, sizeof(sample)); 441 if (ret) 442 goto done; 443 data->buf[j++] = sample; 444 } 445 446 iio_push_to_buffers_with_timestamp(indio_dev, data->buf, pf->timestamp); 447 done: 448 iio_trigger_notify_done(indio_dev->trig); 449 return IRQ_HANDLED; 450 } 451 452 static int bmi160_read_raw(struct iio_dev *indio_dev, 453 struct iio_chan_spec const *chan, 454 int *val, int *val2, long mask) 455 { 456 int ret; 457 struct bmi160_data *data = iio_priv(indio_dev); 458 459 switch (mask) { 460 case IIO_CHAN_INFO_RAW: 461 ret = bmi160_get_data(data, chan->type, chan->channel2, val); 462 if (ret) 463 return ret; 464 return IIO_VAL_INT; 465 case IIO_CHAN_INFO_SCALE: 466 *val = 0; 467 ret = bmi160_get_scale(data, 468 bmi160_to_sensor(chan->type), val2); 469 return ret ? ret : IIO_VAL_INT_PLUS_MICRO; 470 case IIO_CHAN_INFO_SAMP_FREQ: 471 ret = bmi160_get_odr(data, bmi160_to_sensor(chan->type), 472 val, val2); 473 return ret ? ret : IIO_VAL_INT_PLUS_MICRO; 474 default: 475 return -EINVAL; 476 } 477 478 return 0; 479 } 480 481 static int bmi160_write_raw(struct iio_dev *indio_dev, 482 struct iio_chan_spec const *chan, 483 int val, int val2, long mask) 484 { 485 struct bmi160_data *data = iio_priv(indio_dev); 486 487 switch (mask) { 488 case IIO_CHAN_INFO_SCALE: 489 return bmi160_set_scale(data, 490 bmi160_to_sensor(chan->type), val2); 491 case IIO_CHAN_INFO_SAMP_FREQ: 492 return bmi160_set_odr(data, bmi160_to_sensor(chan->type), 493 val, val2); 494 default: 495 return -EINVAL; 496 } 497 498 return 0; 499 } 500 501 static 502 IIO_CONST_ATTR(in_accel_sampling_frequency_available, 503 "0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600"); 504 static 505 IIO_CONST_ATTR(in_anglvel_sampling_frequency_available, 506 "25 50 100 200 400 800 1600 3200"); 507 static 508 IIO_CONST_ATTR(in_accel_scale_available, 509 "0.000598 0.001197 0.002394 0.004788"); 510 static 511 IIO_CONST_ATTR(in_anglvel_scale_available, 512 "0.001065 0.000532 0.000266 0.000133 0.000066"); 513 514 static struct attribute *bmi160_attrs[] = { 515 &iio_const_attr_in_accel_sampling_frequency_available.dev_attr.attr, 516 &iio_const_attr_in_anglvel_sampling_frequency_available.dev_attr.attr, 517 &iio_const_attr_in_accel_scale_available.dev_attr.attr, 518 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 519 NULL, 520 }; 521 522 static const struct attribute_group bmi160_attrs_group = { 523 .attrs = bmi160_attrs, 524 }; 525 526 static const struct iio_info bmi160_info = { 527 .read_raw = bmi160_read_raw, 528 .write_raw = bmi160_write_raw, 529 .attrs = &bmi160_attrs_group, 530 }; 531 532 static int bmi160_write_conf_reg(struct regmap *regmap, unsigned int reg, 533 unsigned int mask, unsigned int bits, 534 unsigned int write_usleep) 535 { 536 int ret; 537 unsigned int val; 538 539 ret = regmap_read(regmap, reg, &val); 540 if (ret) 541 return ret; 542 543 val = (val & ~mask) | bits; 544 545 ret = regmap_write(regmap, reg, val); 546 if (ret) 547 return ret; 548 549 /* 550 * We need to wait after writing before we can write again. See the 551 * datasheet, page 93. 552 */ 553 usleep_range(write_usleep, write_usleep + 1000); 554 555 return 0; 556 } 557 558 static int bmi160_config_pin(struct regmap *regmap, enum bmi160_int_pin pin, 559 bool open_drain, u8 irq_mask, 560 unsigned long write_usleep) 561 { 562 int ret; 563 struct device *dev = regmap_get_device(regmap); 564 u8 int_out_ctrl_shift; 565 u8 int_latch_mask; 566 u8 int_map_mask; 567 u8 int_out_ctrl_mask; 568 u8 int_out_ctrl_bits; 569 const char *pin_name; 570 571 switch (pin) { 572 case BMI160_PIN_INT1: 573 int_out_ctrl_shift = BMI160_INT1_OUT_CTRL_SHIFT; 574 int_latch_mask = BMI160_INT1_LATCH_MASK; 575 int_map_mask = BMI160_INT1_MAP_DRDY_EN; 576 break; 577 case BMI160_PIN_INT2: 578 int_out_ctrl_shift = BMI160_INT2_OUT_CTRL_SHIFT; 579 int_latch_mask = BMI160_INT2_LATCH_MASK; 580 int_map_mask = BMI160_INT2_MAP_DRDY_EN; 581 break; 582 } 583 int_out_ctrl_mask = BMI160_INT_OUT_CTRL_MASK << int_out_ctrl_shift; 584 585 /* 586 * Enable the requested pin with the right settings: 587 * - Push-pull/open-drain 588 * - Active low/high 589 * - Edge/level triggered 590 */ 591 int_out_ctrl_bits = BMI160_OUTPUT_EN; 592 if (open_drain) 593 /* Default is push-pull. */ 594 int_out_ctrl_bits |= BMI160_OPEN_DRAIN; 595 int_out_ctrl_bits |= irq_mask; 596 int_out_ctrl_bits <<= int_out_ctrl_shift; 597 598 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_OUT_CTRL, 599 int_out_ctrl_mask, int_out_ctrl_bits, 600 write_usleep); 601 if (ret) 602 return ret; 603 604 /* Set the pin to input mode with no latching. */ 605 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_LATCH, 606 int_latch_mask, int_latch_mask, 607 write_usleep); 608 if (ret) 609 return ret; 610 611 /* Map interrupts to the requested pin. */ 612 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_MAP, 613 int_map_mask, int_map_mask, 614 write_usleep); 615 if (ret) { 616 switch (pin) { 617 case BMI160_PIN_INT1: 618 pin_name = "INT1"; 619 break; 620 case BMI160_PIN_INT2: 621 pin_name = "INT2"; 622 break; 623 } 624 dev_err(dev, "Failed to configure %s IRQ pin", pin_name); 625 } 626 627 return ret; 628 } 629 630 int bmi160_enable_irq(struct regmap *regmap, bool enable) 631 { 632 unsigned int enable_bit = 0; 633 634 if (enable) 635 enable_bit = BMI160_DRDY_INT_EN; 636 637 return bmi160_write_conf_reg(regmap, BMI160_REG_INT_EN, 638 BMI160_DRDY_INT_EN, enable_bit, 639 BMI160_NORMAL_WRITE_USLEEP); 640 } 641 EXPORT_SYMBOL_NS(bmi160_enable_irq, IIO_BMI160); 642 643 static int bmi160_get_irq(struct fwnode_handle *fwnode, enum bmi160_int_pin *pin) 644 { 645 int irq; 646 647 /* Use INT1 if possible, otherwise fall back to INT2. */ 648 irq = fwnode_irq_get_byname(fwnode, "INT1"); 649 if (irq > 0) { 650 *pin = BMI160_PIN_INT1; 651 return irq; 652 } 653 654 irq = fwnode_irq_get_byname(fwnode, "INT2"); 655 if (irq > 0) 656 *pin = BMI160_PIN_INT2; 657 658 return irq; 659 } 660 661 static int bmi160_config_device_irq(struct iio_dev *indio_dev, int irq_type, 662 enum bmi160_int_pin pin) 663 { 664 bool open_drain; 665 u8 irq_mask; 666 struct bmi160_data *data = iio_priv(indio_dev); 667 struct device *dev = regmap_get_device(data->regmap); 668 669 /* Level-triggered, active-low is the default if we set all zeroes. */ 670 if (irq_type == IRQF_TRIGGER_RISING) 671 irq_mask = BMI160_ACTIVE_HIGH | BMI160_EDGE_TRIGGERED; 672 else if (irq_type == IRQF_TRIGGER_FALLING) 673 irq_mask = BMI160_EDGE_TRIGGERED; 674 else if (irq_type == IRQF_TRIGGER_HIGH) 675 irq_mask = BMI160_ACTIVE_HIGH; 676 else if (irq_type == IRQF_TRIGGER_LOW) 677 irq_mask = 0; 678 else { 679 dev_err(&indio_dev->dev, 680 "Invalid interrupt type 0x%x specified\n", irq_type); 681 return -EINVAL; 682 } 683 684 open_drain = device_property_read_bool(dev, "drive-open-drain"); 685 686 return bmi160_config_pin(data->regmap, pin, open_drain, irq_mask, 687 BMI160_NORMAL_WRITE_USLEEP); 688 } 689 690 static int bmi160_setup_irq(struct iio_dev *indio_dev, int irq, 691 enum bmi160_int_pin pin) 692 { 693 u32 irq_type = irq_get_trigger_type(irq); 694 int ret; 695 696 ret = bmi160_config_device_irq(indio_dev, irq_type, pin); 697 if (ret) 698 return ret; 699 700 return bmi160_probe_trigger(indio_dev, irq, irq_type); 701 } 702 703 static int bmi160_check_chip_id(const u8 chip_id) 704 { 705 for (int i = 0; i < ARRAY_SIZE(bmi_chip_ids); i++) { 706 if (chip_id == bmi_chip_ids[i]) 707 return 0; 708 } 709 710 return -ENODEV; 711 } 712 713 static int bmi160_chip_init(struct bmi160_data *data, bool use_spi) 714 { 715 int ret; 716 unsigned int val; 717 struct device *dev = regmap_get_device(data->regmap); 718 719 ret = regulator_bulk_enable(ARRAY_SIZE(data->supplies), data->supplies); 720 if (ret) { 721 dev_err(dev, "Failed to enable regulators: %d\n", ret); 722 return ret; 723 } 724 725 ret = regmap_write(data->regmap, BMI160_REG_CMD, BMI160_CMD_SOFTRESET); 726 if (ret) 727 goto disable_regulator; 728 729 usleep_range(BMI160_SOFTRESET_USLEEP, BMI160_SOFTRESET_USLEEP + 1); 730 731 /* 732 * CS rising edge is needed before starting SPI, so do a dummy read 733 * See Section 3.2.1, page 86 of the datasheet 734 */ 735 if (use_spi) { 736 ret = regmap_read(data->regmap, BMI160_REG_DUMMY, &val); 737 if (ret) 738 goto disable_regulator; 739 } 740 741 ret = regmap_read(data->regmap, BMI160_REG_CHIP_ID, &val); 742 if (ret) { 743 dev_err(dev, "Error reading chip id\n"); 744 goto disable_regulator; 745 } 746 747 ret = bmi160_check_chip_id(val); 748 if (ret) 749 dev_warn(dev, "Chip id not found: %x\n", val); 750 751 ret = bmi160_set_mode(data, BMI160_ACCEL, true); 752 if (ret) 753 goto disable_regulator; 754 755 ret = bmi160_set_mode(data, BMI160_GYRO, true); 756 if (ret) 757 goto disable_accel; 758 759 return 0; 760 761 disable_accel: 762 bmi160_set_mode(data, BMI160_ACCEL, false); 763 764 disable_regulator: 765 regulator_bulk_disable(ARRAY_SIZE(data->supplies), data->supplies); 766 return ret; 767 } 768 769 static int bmi160_data_rdy_trigger_set_state(struct iio_trigger *trig, 770 bool enable) 771 { 772 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 773 struct bmi160_data *data = iio_priv(indio_dev); 774 775 return bmi160_enable_irq(data->regmap, enable); 776 } 777 778 static const struct iio_trigger_ops bmi160_trigger_ops = { 779 .set_trigger_state = &bmi160_data_rdy_trigger_set_state, 780 }; 781 782 int bmi160_probe_trigger(struct iio_dev *indio_dev, int irq, u32 irq_type) 783 { 784 struct bmi160_data *data = iio_priv(indio_dev); 785 int ret; 786 787 data->trig = devm_iio_trigger_alloc(&indio_dev->dev, "%s-dev%d", 788 indio_dev->name, 789 iio_device_id(indio_dev)); 790 791 if (data->trig == NULL) 792 return -ENOMEM; 793 794 ret = devm_request_irq(&indio_dev->dev, irq, 795 &iio_trigger_generic_data_rdy_poll, 796 irq_type, "bmi160", data->trig); 797 if (ret) 798 return ret; 799 800 data->trig->dev.parent = regmap_get_device(data->regmap); 801 data->trig->ops = &bmi160_trigger_ops; 802 iio_trigger_set_drvdata(data->trig, indio_dev); 803 804 ret = devm_iio_trigger_register(&indio_dev->dev, data->trig); 805 if (ret) 806 return ret; 807 808 indio_dev->trig = iio_trigger_get(data->trig); 809 810 return 0; 811 } 812 813 static void bmi160_chip_uninit(void *data) 814 { 815 struct bmi160_data *bmi_data = data; 816 struct device *dev = regmap_get_device(bmi_data->regmap); 817 int ret; 818 819 bmi160_set_mode(bmi_data, BMI160_GYRO, false); 820 bmi160_set_mode(bmi_data, BMI160_ACCEL, false); 821 822 ret = regulator_bulk_disable(ARRAY_SIZE(bmi_data->supplies), 823 bmi_data->supplies); 824 if (ret) 825 dev_err(dev, "Failed to disable regulators: %d\n", ret); 826 } 827 828 int bmi160_core_probe(struct device *dev, struct regmap *regmap, 829 const char *name, bool use_spi) 830 { 831 struct iio_dev *indio_dev; 832 struct bmi160_data *data; 833 int irq; 834 enum bmi160_int_pin int_pin; 835 int ret; 836 837 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 838 if (!indio_dev) 839 return -ENOMEM; 840 841 data = iio_priv(indio_dev); 842 dev_set_drvdata(dev, indio_dev); 843 data->regmap = regmap; 844 845 data->supplies[0].supply = "vdd"; 846 data->supplies[1].supply = "vddio"; 847 ret = devm_regulator_bulk_get(dev, 848 ARRAY_SIZE(data->supplies), 849 data->supplies); 850 if (ret) { 851 dev_err(dev, "Failed to get regulators: %d\n", ret); 852 return ret; 853 } 854 855 ret = iio_read_mount_matrix(dev, &data->orientation); 856 if (ret) 857 return ret; 858 859 ret = bmi160_chip_init(data, use_spi); 860 if (ret) 861 return ret; 862 863 ret = devm_add_action_or_reset(dev, bmi160_chip_uninit, data); 864 if (ret) 865 return ret; 866 867 indio_dev->channels = bmi160_channels; 868 indio_dev->num_channels = ARRAY_SIZE(bmi160_channels); 869 indio_dev->name = name; 870 indio_dev->modes = INDIO_DIRECT_MODE; 871 indio_dev->info = &bmi160_info; 872 873 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 874 iio_pollfunc_store_time, 875 bmi160_trigger_handler, NULL); 876 if (ret) 877 return ret; 878 879 irq = bmi160_get_irq(dev_fwnode(dev), &int_pin); 880 if (irq > 0) { 881 ret = bmi160_setup_irq(indio_dev, irq, int_pin); 882 if (ret) 883 dev_err(&indio_dev->dev, "Failed to setup IRQ %d\n", 884 irq); 885 } else { 886 dev_info(&indio_dev->dev, "Not setting up IRQ trigger\n"); 887 } 888 889 return devm_iio_device_register(dev, indio_dev); 890 } 891 EXPORT_SYMBOL_NS_GPL(bmi160_core_probe, IIO_BMI160); 892 893 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>"); 894 MODULE_DESCRIPTION("Bosch BMI160 driver"); 895 MODULE_LICENSE("GPL v2"); 896