1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BMI160 - Bosch IMU (accel, gyro plus external magnetometer) 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * Copyright (c) 2019, Martin Kelly. 7 * 8 * IIO core driver for BMI160, with support for I2C/SPI busses 9 * 10 * TODO: magnetometer, hardware FIFO 11 */ 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/delay.h> 15 #include <linux/irq.h> 16 #include <linux/property.h> 17 #include <linux/regulator/consumer.h> 18 19 #include <linux/iio/iio.h> 20 #include <linux/iio/triggered_buffer.h> 21 #include <linux/iio/trigger_consumer.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/sysfs.h> 24 #include <linux/iio/trigger.h> 25 26 #include "bmi160.h" 27 28 #define BMI160_REG_CHIP_ID 0x00 29 #define BMI120_CHIP_ID_VAL 0xD3 30 #define BMI160_CHIP_ID_VAL 0xD1 31 32 #define BMI160_REG_PMU_STATUS 0x03 33 34 /* X axis data low byte address, the rest can be obtained using axis offset */ 35 #define BMI160_REG_DATA_MAGN_XOUT_L 0x04 36 #define BMI160_REG_DATA_GYRO_XOUT_L 0x0C 37 #define BMI160_REG_DATA_ACCEL_XOUT_L 0x12 38 39 #define BMI160_REG_ACCEL_CONFIG 0x40 40 #define BMI160_ACCEL_CONFIG_ODR_MASK GENMASK(3, 0) 41 #define BMI160_ACCEL_CONFIG_BWP_MASK GENMASK(6, 4) 42 43 #define BMI160_REG_ACCEL_RANGE 0x41 44 #define BMI160_ACCEL_RANGE_2G 0x03 45 #define BMI160_ACCEL_RANGE_4G 0x05 46 #define BMI160_ACCEL_RANGE_8G 0x08 47 #define BMI160_ACCEL_RANGE_16G 0x0C 48 49 #define BMI160_REG_GYRO_CONFIG 0x42 50 #define BMI160_GYRO_CONFIG_ODR_MASK GENMASK(3, 0) 51 #define BMI160_GYRO_CONFIG_BWP_MASK GENMASK(5, 4) 52 53 #define BMI160_REG_GYRO_RANGE 0x43 54 #define BMI160_GYRO_RANGE_2000DPS 0x00 55 #define BMI160_GYRO_RANGE_1000DPS 0x01 56 #define BMI160_GYRO_RANGE_500DPS 0x02 57 #define BMI160_GYRO_RANGE_250DPS 0x03 58 #define BMI160_GYRO_RANGE_125DPS 0x04 59 60 #define BMI160_REG_CMD 0x7E 61 #define BMI160_CMD_ACCEL_PM_SUSPEND 0x10 62 #define BMI160_CMD_ACCEL_PM_NORMAL 0x11 63 #define BMI160_CMD_ACCEL_PM_LOW_POWER 0x12 64 #define BMI160_CMD_GYRO_PM_SUSPEND 0x14 65 #define BMI160_CMD_GYRO_PM_NORMAL 0x15 66 #define BMI160_CMD_GYRO_PM_FAST_STARTUP 0x17 67 #define BMI160_CMD_SOFTRESET 0xB6 68 69 #define BMI160_REG_INT_EN 0x51 70 #define BMI160_DRDY_INT_EN BIT(4) 71 72 #define BMI160_REG_INT_OUT_CTRL 0x53 73 #define BMI160_INT_OUT_CTRL_MASK 0x0f 74 #define BMI160_INT1_OUT_CTRL_SHIFT 0 75 #define BMI160_INT2_OUT_CTRL_SHIFT 4 76 #define BMI160_EDGE_TRIGGERED BIT(0) 77 #define BMI160_ACTIVE_HIGH BIT(1) 78 #define BMI160_OPEN_DRAIN BIT(2) 79 #define BMI160_OUTPUT_EN BIT(3) 80 81 #define BMI160_REG_INT_LATCH 0x54 82 #define BMI160_INT1_LATCH_MASK BIT(4) 83 #define BMI160_INT2_LATCH_MASK BIT(5) 84 85 /* INT1 and INT2 are in the opposite order as in INT_OUT_CTRL! */ 86 #define BMI160_REG_INT_MAP 0x56 87 #define BMI160_INT1_MAP_DRDY_EN 0x80 88 #define BMI160_INT2_MAP_DRDY_EN 0x08 89 90 #define BMI160_REG_DUMMY 0x7F 91 92 #define BMI160_NORMAL_WRITE_USLEEP 2 93 #define BMI160_SUSPENDED_WRITE_USLEEP 450 94 95 #define BMI160_ACCEL_PMU_MIN_USLEEP 3800 96 #define BMI160_GYRO_PMU_MIN_USLEEP 80000 97 #define BMI160_SOFTRESET_USLEEP 1000 98 99 #define BMI160_CHANNEL(_type, _axis, _index) { \ 100 .type = _type, \ 101 .modified = 1, \ 102 .channel2 = IIO_MOD_##_axis, \ 103 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 104 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 105 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 106 .scan_index = _index, \ 107 .scan_type = { \ 108 .sign = 's', \ 109 .realbits = 16, \ 110 .storagebits = 16, \ 111 .endianness = IIO_LE, \ 112 }, \ 113 .ext_info = bmi160_ext_info, \ 114 } 115 116 static const u8 bmi_chip_ids[] = { 117 BMI120_CHIP_ID_VAL, 118 BMI160_CHIP_ID_VAL, 119 }; 120 121 /* scan indexes follow DATA register order */ 122 enum bmi160_scan_axis { 123 BMI160_SCAN_EXT_MAGN_X = 0, 124 BMI160_SCAN_EXT_MAGN_Y, 125 BMI160_SCAN_EXT_MAGN_Z, 126 BMI160_SCAN_RHALL, 127 BMI160_SCAN_GYRO_X, 128 BMI160_SCAN_GYRO_Y, 129 BMI160_SCAN_GYRO_Z, 130 BMI160_SCAN_ACCEL_X, 131 BMI160_SCAN_ACCEL_Y, 132 BMI160_SCAN_ACCEL_Z, 133 BMI160_SCAN_TIMESTAMP, 134 }; 135 136 enum bmi160_sensor_type { 137 BMI160_ACCEL = 0, 138 BMI160_GYRO, 139 BMI160_EXT_MAGN, 140 BMI160_NUM_SENSORS /* must be last */ 141 }; 142 143 enum bmi160_int_pin { 144 BMI160_PIN_INT1, 145 BMI160_PIN_INT2 146 }; 147 148 const struct regmap_config bmi160_regmap_config = { 149 .reg_bits = 8, 150 .val_bits = 8, 151 }; 152 EXPORT_SYMBOL_NS(bmi160_regmap_config, IIO_BMI160); 153 154 struct bmi160_regs { 155 u8 data; /* LSB byte register for X-axis */ 156 u8 config; 157 u8 config_odr_mask; 158 u8 config_bwp_mask; 159 u8 range; 160 u8 pmu_cmd_normal; 161 u8 pmu_cmd_suspend; 162 }; 163 164 static struct bmi160_regs bmi160_regs[] = { 165 [BMI160_ACCEL] = { 166 .data = BMI160_REG_DATA_ACCEL_XOUT_L, 167 .config = BMI160_REG_ACCEL_CONFIG, 168 .config_odr_mask = BMI160_ACCEL_CONFIG_ODR_MASK, 169 .config_bwp_mask = BMI160_ACCEL_CONFIG_BWP_MASK, 170 .range = BMI160_REG_ACCEL_RANGE, 171 .pmu_cmd_normal = BMI160_CMD_ACCEL_PM_NORMAL, 172 .pmu_cmd_suspend = BMI160_CMD_ACCEL_PM_SUSPEND, 173 }, 174 [BMI160_GYRO] = { 175 .data = BMI160_REG_DATA_GYRO_XOUT_L, 176 .config = BMI160_REG_GYRO_CONFIG, 177 .config_odr_mask = BMI160_GYRO_CONFIG_ODR_MASK, 178 .config_bwp_mask = BMI160_GYRO_CONFIG_BWP_MASK, 179 .range = BMI160_REG_GYRO_RANGE, 180 .pmu_cmd_normal = BMI160_CMD_GYRO_PM_NORMAL, 181 .pmu_cmd_suspend = BMI160_CMD_GYRO_PM_SUSPEND, 182 }, 183 }; 184 185 static unsigned long bmi160_pmu_time[] = { 186 [BMI160_ACCEL] = BMI160_ACCEL_PMU_MIN_USLEEP, 187 [BMI160_GYRO] = BMI160_GYRO_PMU_MIN_USLEEP, 188 }; 189 190 struct bmi160_scale { 191 u8 bits; 192 int uscale; 193 }; 194 195 struct bmi160_odr { 196 u8 bits; 197 int odr; 198 int uodr; 199 }; 200 201 static const struct bmi160_scale bmi160_accel_scale[] = { 202 { BMI160_ACCEL_RANGE_2G, 598}, 203 { BMI160_ACCEL_RANGE_4G, 1197}, 204 { BMI160_ACCEL_RANGE_8G, 2394}, 205 { BMI160_ACCEL_RANGE_16G, 4788}, 206 }; 207 208 static const struct bmi160_scale bmi160_gyro_scale[] = { 209 { BMI160_GYRO_RANGE_2000DPS, 1065}, 210 { BMI160_GYRO_RANGE_1000DPS, 532}, 211 { BMI160_GYRO_RANGE_500DPS, 266}, 212 { BMI160_GYRO_RANGE_250DPS, 133}, 213 { BMI160_GYRO_RANGE_125DPS, 66}, 214 }; 215 216 struct bmi160_scale_item { 217 const struct bmi160_scale *tbl; 218 int num; 219 }; 220 221 static const struct bmi160_scale_item bmi160_scale_table[] = { 222 [BMI160_ACCEL] = { 223 .tbl = bmi160_accel_scale, 224 .num = ARRAY_SIZE(bmi160_accel_scale), 225 }, 226 [BMI160_GYRO] = { 227 .tbl = bmi160_gyro_scale, 228 .num = ARRAY_SIZE(bmi160_gyro_scale), 229 }, 230 }; 231 232 static const struct bmi160_odr bmi160_accel_odr[] = { 233 {0x01, 0, 781250}, 234 {0x02, 1, 562500}, 235 {0x03, 3, 125000}, 236 {0x04, 6, 250000}, 237 {0x05, 12, 500000}, 238 {0x06, 25, 0}, 239 {0x07, 50, 0}, 240 {0x08, 100, 0}, 241 {0x09, 200, 0}, 242 {0x0A, 400, 0}, 243 {0x0B, 800, 0}, 244 {0x0C, 1600, 0}, 245 }; 246 247 static const struct bmi160_odr bmi160_gyro_odr[] = { 248 {0x06, 25, 0}, 249 {0x07, 50, 0}, 250 {0x08, 100, 0}, 251 {0x09, 200, 0}, 252 {0x0A, 400, 0}, 253 {0x0B, 800, 0}, 254 {0x0C, 1600, 0}, 255 {0x0D, 3200, 0}, 256 }; 257 258 struct bmi160_odr_item { 259 const struct bmi160_odr *tbl; 260 int num; 261 }; 262 263 static const struct bmi160_odr_item bmi160_odr_table[] = { 264 [BMI160_ACCEL] = { 265 .tbl = bmi160_accel_odr, 266 .num = ARRAY_SIZE(bmi160_accel_odr), 267 }, 268 [BMI160_GYRO] = { 269 .tbl = bmi160_gyro_odr, 270 .num = ARRAY_SIZE(bmi160_gyro_odr), 271 }, 272 }; 273 274 static const struct iio_mount_matrix * 275 bmi160_get_mount_matrix(const struct iio_dev *indio_dev, 276 const struct iio_chan_spec *chan) 277 { 278 struct bmi160_data *data = iio_priv(indio_dev); 279 280 return &data->orientation; 281 } 282 283 static const struct iio_chan_spec_ext_info bmi160_ext_info[] = { 284 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmi160_get_mount_matrix), 285 { } 286 }; 287 288 static const struct iio_chan_spec bmi160_channels[] = { 289 BMI160_CHANNEL(IIO_ACCEL, X, BMI160_SCAN_ACCEL_X), 290 BMI160_CHANNEL(IIO_ACCEL, Y, BMI160_SCAN_ACCEL_Y), 291 BMI160_CHANNEL(IIO_ACCEL, Z, BMI160_SCAN_ACCEL_Z), 292 BMI160_CHANNEL(IIO_ANGL_VEL, X, BMI160_SCAN_GYRO_X), 293 BMI160_CHANNEL(IIO_ANGL_VEL, Y, BMI160_SCAN_GYRO_Y), 294 BMI160_CHANNEL(IIO_ANGL_VEL, Z, BMI160_SCAN_GYRO_Z), 295 IIO_CHAN_SOFT_TIMESTAMP(BMI160_SCAN_TIMESTAMP), 296 }; 297 298 static enum bmi160_sensor_type bmi160_to_sensor(enum iio_chan_type iio_type) 299 { 300 switch (iio_type) { 301 case IIO_ACCEL: 302 return BMI160_ACCEL; 303 case IIO_ANGL_VEL: 304 return BMI160_GYRO; 305 default: 306 return -EINVAL; 307 } 308 } 309 310 static 311 int bmi160_set_mode(struct bmi160_data *data, enum bmi160_sensor_type t, 312 bool mode) 313 { 314 int ret; 315 u8 cmd; 316 317 if (mode) 318 cmd = bmi160_regs[t].pmu_cmd_normal; 319 else 320 cmd = bmi160_regs[t].pmu_cmd_suspend; 321 322 ret = regmap_write(data->regmap, BMI160_REG_CMD, cmd); 323 if (ret) 324 return ret; 325 326 usleep_range(bmi160_pmu_time[t], bmi160_pmu_time[t] + 1000); 327 328 return 0; 329 } 330 331 static 332 int bmi160_set_scale(struct bmi160_data *data, enum bmi160_sensor_type t, 333 int uscale) 334 { 335 int i; 336 337 for (i = 0; i < bmi160_scale_table[t].num; i++) 338 if (bmi160_scale_table[t].tbl[i].uscale == uscale) 339 break; 340 341 if (i == bmi160_scale_table[t].num) 342 return -EINVAL; 343 344 return regmap_write(data->regmap, bmi160_regs[t].range, 345 bmi160_scale_table[t].tbl[i].bits); 346 } 347 348 static 349 int bmi160_get_scale(struct bmi160_data *data, enum bmi160_sensor_type t, 350 int *uscale) 351 { 352 int i, ret, val; 353 354 ret = regmap_read(data->regmap, bmi160_regs[t].range, &val); 355 if (ret) 356 return ret; 357 358 for (i = 0; i < bmi160_scale_table[t].num; i++) 359 if (bmi160_scale_table[t].tbl[i].bits == val) { 360 *uscale = bmi160_scale_table[t].tbl[i].uscale; 361 return 0; 362 } 363 364 return -EINVAL; 365 } 366 367 static int bmi160_get_data(struct bmi160_data *data, int chan_type, 368 int axis, int *val) 369 { 370 u8 reg; 371 int ret; 372 __le16 sample; 373 enum bmi160_sensor_type t = bmi160_to_sensor(chan_type); 374 375 reg = bmi160_regs[t].data + (axis - IIO_MOD_X) * sizeof(sample); 376 377 ret = regmap_bulk_read(data->regmap, reg, &sample, sizeof(sample)); 378 if (ret) 379 return ret; 380 381 *val = sign_extend32(le16_to_cpu(sample), 15); 382 383 return 0; 384 } 385 386 static 387 int bmi160_set_odr(struct bmi160_data *data, enum bmi160_sensor_type t, 388 int odr, int uodr) 389 { 390 int i; 391 392 for (i = 0; i < bmi160_odr_table[t].num; i++) 393 if (bmi160_odr_table[t].tbl[i].odr == odr && 394 bmi160_odr_table[t].tbl[i].uodr == uodr) 395 break; 396 397 if (i >= bmi160_odr_table[t].num) 398 return -EINVAL; 399 400 return regmap_update_bits(data->regmap, 401 bmi160_regs[t].config, 402 bmi160_regs[t].config_odr_mask, 403 bmi160_odr_table[t].tbl[i].bits); 404 } 405 406 static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t, 407 int *odr, int *uodr) 408 { 409 int i, val, ret; 410 411 ret = regmap_read(data->regmap, bmi160_regs[t].config, &val); 412 if (ret) 413 return ret; 414 415 val &= bmi160_regs[t].config_odr_mask; 416 417 for (i = 0; i < bmi160_odr_table[t].num; i++) 418 if (val == bmi160_odr_table[t].tbl[i].bits) 419 break; 420 421 if (i >= bmi160_odr_table[t].num) 422 return -EINVAL; 423 424 *odr = bmi160_odr_table[t].tbl[i].odr; 425 *uodr = bmi160_odr_table[t].tbl[i].uodr; 426 427 return 0; 428 } 429 430 static irqreturn_t bmi160_trigger_handler(int irq, void *p) 431 { 432 struct iio_poll_func *pf = p; 433 struct iio_dev *indio_dev = pf->indio_dev; 434 struct bmi160_data *data = iio_priv(indio_dev); 435 int i, ret, j = 0, base = BMI160_REG_DATA_MAGN_XOUT_L; 436 __le16 sample; 437 438 for_each_set_bit(i, indio_dev->active_scan_mask, 439 indio_dev->masklength) { 440 ret = regmap_bulk_read(data->regmap, base + i * sizeof(sample), 441 &sample, sizeof(sample)); 442 if (ret) 443 goto done; 444 data->buf[j++] = sample; 445 } 446 447 iio_push_to_buffers_with_timestamp(indio_dev, data->buf, pf->timestamp); 448 done: 449 iio_trigger_notify_done(indio_dev->trig); 450 return IRQ_HANDLED; 451 } 452 453 static int bmi160_read_raw(struct iio_dev *indio_dev, 454 struct iio_chan_spec const *chan, 455 int *val, int *val2, long mask) 456 { 457 int ret; 458 struct bmi160_data *data = iio_priv(indio_dev); 459 460 switch (mask) { 461 case IIO_CHAN_INFO_RAW: 462 ret = bmi160_get_data(data, chan->type, chan->channel2, val); 463 if (ret) 464 return ret; 465 return IIO_VAL_INT; 466 case IIO_CHAN_INFO_SCALE: 467 *val = 0; 468 ret = bmi160_get_scale(data, 469 bmi160_to_sensor(chan->type), val2); 470 return ret ? ret : IIO_VAL_INT_PLUS_MICRO; 471 case IIO_CHAN_INFO_SAMP_FREQ: 472 ret = bmi160_get_odr(data, bmi160_to_sensor(chan->type), 473 val, val2); 474 return ret ? ret : IIO_VAL_INT_PLUS_MICRO; 475 default: 476 return -EINVAL; 477 } 478 479 return 0; 480 } 481 482 static int bmi160_write_raw(struct iio_dev *indio_dev, 483 struct iio_chan_spec const *chan, 484 int val, int val2, long mask) 485 { 486 struct bmi160_data *data = iio_priv(indio_dev); 487 488 switch (mask) { 489 case IIO_CHAN_INFO_SCALE: 490 return bmi160_set_scale(data, 491 bmi160_to_sensor(chan->type), val2); 492 case IIO_CHAN_INFO_SAMP_FREQ: 493 return bmi160_set_odr(data, bmi160_to_sensor(chan->type), 494 val, val2); 495 default: 496 return -EINVAL; 497 } 498 499 return 0; 500 } 501 502 static 503 IIO_CONST_ATTR(in_accel_sampling_frequency_available, 504 "0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600"); 505 static 506 IIO_CONST_ATTR(in_anglvel_sampling_frequency_available, 507 "25 50 100 200 400 800 1600 3200"); 508 static 509 IIO_CONST_ATTR(in_accel_scale_available, 510 "0.000598 0.001197 0.002394 0.004788"); 511 static 512 IIO_CONST_ATTR(in_anglvel_scale_available, 513 "0.001065 0.000532 0.000266 0.000133 0.000066"); 514 515 static struct attribute *bmi160_attrs[] = { 516 &iio_const_attr_in_accel_sampling_frequency_available.dev_attr.attr, 517 &iio_const_attr_in_anglvel_sampling_frequency_available.dev_attr.attr, 518 &iio_const_attr_in_accel_scale_available.dev_attr.attr, 519 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 520 NULL, 521 }; 522 523 static const struct attribute_group bmi160_attrs_group = { 524 .attrs = bmi160_attrs, 525 }; 526 527 static const struct iio_info bmi160_info = { 528 .read_raw = bmi160_read_raw, 529 .write_raw = bmi160_write_raw, 530 .attrs = &bmi160_attrs_group, 531 }; 532 533 static int bmi160_write_conf_reg(struct regmap *regmap, unsigned int reg, 534 unsigned int mask, unsigned int bits, 535 unsigned int write_usleep) 536 { 537 int ret; 538 unsigned int val; 539 540 ret = regmap_read(regmap, reg, &val); 541 if (ret) 542 return ret; 543 544 val = (val & ~mask) | bits; 545 546 ret = regmap_write(regmap, reg, val); 547 if (ret) 548 return ret; 549 550 /* 551 * We need to wait after writing before we can write again. See the 552 * datasheet, page 93. 553 */ 554 usleep_range(write_usleep, write_usleep + 1000); 555 556 return 0; 557 } 558 559 static int bmi160_config_pin(struct regmap *regmap, enum bmi160_int_pin pin, 560 bool open_drain, u8 irq_mask, 561 unsigned long write_usleep) 562 { 563 int ret; 564 struct device *dev = regmap_get_device(regmap); 565 u8 int_out_ctrl_shift; 566 u8 int_latch_mask; 567 u8 int_map_mask; 568 u8 int_out_ctrl_mask; 569 u8 int_out_ctrl_bits; 570 const char *pin_name; 571 572 switch (pin) { 573 case BMI160_PIN_INT1: 574 int_out_ctrl_shift = BMI160_INT1_OUT_CTRL_SHIFT; 575 int_latch_mask = BMI160_INT1_LATCH_MASK; 576 int_map_mask = BMI160_INT1_MAP_DRDY_EN; 577 break; 578 case BMI160_PIN_INT2: 579 int_out_ctrl_shift = BMI160_INT2_OUT_CTRL_SHIFT; 580 int_latch_mask = BMI160_INT2_LATCH_MASK; 581 int_map_mask = BMI160_INT2_MAP_DRDY_EN; 582 break; 583 } 584 int_out_ctrl_mask = BMI160_INT_OUT_CTRL_MASK << int_out_ctrl_shift; 585 586 /* 587 * Enable the requested pin with the right settings: 588 * - Push-pull/open-drain 589 * - Active low/high 590 * - Edge/level triggered 591 */ 592 int_out_ctrl_bits = BMI160_OUTPUT_EN; 593 if (open_drain) 594 /* Default is push-pull. */ 595 int_out_ctrl_bits |= BMI160_OPEN_DRAIN; 596 int_out_ctrl_bits |= irq_mask; 597 int_out_ctrl_bits <<= int_out_ctrl_shift; 598 599 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_OUT_CTRL, 600 int_out_ctrl_mask, int_out_ctrl_bits, 601 write_usleep); 602 if (ret) 603 return ret; 604 605 /* Set the pin to input mode with no latching. */ 606 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_LATCH, 607 int_latch_mask, int_latch_mask, 608 write_usleep); 609 if (ret) 610 return ret; 611 612 /* Map interrupts to the requested pin. */ 613 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_MAP, 614 int_map_mask, int_map_mask, 615 write_usleep); 616 if (ret) { 617 switch (pin) { 618 case BMI160_PIN_INT1: 619 pin_name = "INT1"; 620 break; 621 case BMI160_PIN_INT2: 622 pin_name = "INT2"; 623 break; 624 } 625 dev_err(dev, "Failed to configure %s IRQ pin", pin_name); 626 } 627 628 return ret; 629 } 630 631 int bmi160_enable_irq(struct regmap *regmap, bool enable) 632 { 633 unsigned int enable_bit = 0; 634 635 if (enable) 636 enable_bit = BMI160_DRDY_INT_EN; 637 638 return bmi160_write_conf_reg(regmap, BMI160_REG_INT_EN, 639 BMI160_DRDY_INT_EN, enable_bit, 640 BMI160_NORMAL_WRITE_USLEEP); 641 } 642 EXPORT_SYMBOL_NS(bmi160_enable_irq, IIO_BMI160); 643 644 static int bmi160_get_irq(struct fwnode_handle *fwnode, enum bmi160_int_pin *pin) 645 { 646 int irq; 647 648 /* Use INT1 if possible, otherwise fall back to INT2. */ 649 irq = fwnode_irq_get_byname(fwnode, "INT1"); 650 if (irq > 0) { 651 *pin = BMI160_PIN_INT1; 652 return irq; 653 } 654 655 irq = fwnode_irq_get_byname(fwnode, "INT2"); 656 if (irq > 0) 657 *pin = BMI160_PIN_INT2; 658 659 return irq; 660 } 661 662 static int bmi160_config_device_irq(struct iio_dev *indio_dev, int irq_type, 663 enum bmi160_int_pin pin) 664 { 665 bool open_drain; 666 u8 irq_mask; 667 struct bmi160_data *data = iio_priv(indio_dev); 668 struct device *dev = regmap_get_device(data->regmap); 669 670 /* Level-triggered, active-low is the default if we set all zeroes. */ 671 if (irq_type == IRQF_TRIGGER_RISING) 672 irq_mask = BMI160_ACTIVE_HIGH | BMI160_EDGE_TRIGGERED; 673 else if (irq_type == IRQF_TRIGGER_FALLING) 674 irq_mask = BMI160_EDGE_TRIGGERED; 675 else if (irq_type == IRQF_TRIGGER_HIGH) 676 irq_mask = BMI160_ACTIVE_HIGH; 677 else if (irq_type == IRQF_TRIGGER_LOW) 678 irq_mask = 0; 679 else { 680 dev_err(&indio_dev->dev, 681 "Invalid interrupt type 0x%x specified\n", irq_type); 682 return -EINVAL; 683 } 684 685 open_drain = device_property_read_bool(dev, "drive-open-drain"); 686 687 return bmi160_config_pin(data->regmap, pin, open_drain, irq_mask, 688 BMI160_NORMAL_WRITE_USLEEP); 689 } 690 691 static int bmi160_setup_irq(struct iio_dev *indio_dev, int irq, 692 enum bmi160_int_pin pin) 693 { 694 struct irq_data *desc; 695 u32 irq_type; 696 int ret; 697 698 desc = irq_get_irq_data(irq); 699 if (!desc) { 700 dev_err(&indio_dev->dev, "Could not find IRQ %d\n", irq); 701 return -EINVAL; 702 } 703 704 irq_type = irqd_get_trigger_type(desc); 705 706 ret = bmi160_config_device_irq(indio_dev, irq_type, pin); 707 if (ret) 708 return ret; 709 710 return bmi160_probe_trigger(indio_dev, irq, irq_type); 711 } 712 713 static int bmi160_check_chip_id(const u8 chip_id) 714 { 715 for (int i = 0; i < ARRAY_SIZE(bmi_chip_ids); i++) { 716 if (chip_id == bmi_chip_ids[i]) 717 return 0; 718 } 719 720 return -ENODEV; 721 } 722 723 static int bmi160_chip_init(struct bmi160_data *data, bool use_spi) 724 { 725 int ret; 726 unsigned int val; 727 struct device *dev = regmap_get_device(data->regmap); 728 729 ret = regulator_bulk_enable(ARRAY_SIZE(data->supplies), data->supplies); 730 if (ret) { 731 dev_err(dev, "Failed to enable regulators: %d\n", ret); 732 return ret; 733 } 734 735 ret = regmap_write(data->regmap, BMI160_REG_CMD, BMI160_CMD_SOFTRESET); 736 if (ret) 737 goto disable_regulator; 738 739 usleep_range(BMI160_SOFTRESET_USLEEP, BMI160_SOFTRESET_USLEEP + 1); 740 741 /* 742 * CS rising edge is needed before starting SPI, so do a dummy read 743 * See Section 3.2.1, page 86 of the datasheet 744 */ 745 if (use_spi) { 746 ret = regmap_read(data->regmap, BMI160_REG_DUMMY, &val); 747 if (ret) 748 goto disable_regulator; 749 } 750 751 ret = regmap_read(data->regmap, BMI160_REG_CHIP_ID, &val); 752 if (ret) { 753 dev_err(dev, "Error reading chip id\n"); 754 goto disable_regulator; 755 } 756 757 ret = bmi160_check_chip_id(val); 758 if (ret) 759 dev_warn(dev, "Chip id not found: %x\n", val); 760 761 ret = bmi160_set_mode(data, BMI160_ACCEL, true); 762 if (ret) 763 goto disable_regulator; 764 765 ret = bmi160_set_mode(data, BMI160_GYRO, true); 766 if (ret) 767 goto disable_accel; 768 769 return 0; 770 771 disable_accel: 772 bmi160_set_mode(data, BMI160_ACCEL, false); 773 774 disable_regulator: 775 regulator_bulk_disable(ARRAY_SIZE(data->supplies), data->supplies); 776 return ret; 777 } 778 779 static int bmi160_data_rdy_trigger_set_state(struct iio_trigger *trig, 780 bool enable) 781 { 782 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 783 struct bmi160_data *data = iio_priv(indio_dev); 784 785 return bmi160_enable_irq(data->regmap, enable); 786 } 787 788 static const struct iio_trigger_ops bmi160_trigger_ops = { 789 .set_trigger_state = &bmi160_data_rdy_trigger_set_state, 790 }; 791 792 int bmi160_probe_trigger(struct iio_dev *indio_dev, int irq, u32 irq_type) 793 { 794 struct bmi160_data *data = iio_priv(indio_dev); 795 int ret; 796 797 data->trig = devm_iio_trigger_alloc(&indio_dev->dev, "%s-dev%d", 798 indio_dev->name, 799 iio_device_id(indio_dev)); 800 801 if (data->trig == NULL) 802 return -ENOMEM; 803 804 ret = devm_request_irq(&indio_dev->dev, irq, 805 &iio_trigger_generic_data_rdy_poll, 806 irq_type, "bmi160", data->trig); 807 if (ret) 808 return ret; 809 810 data->trig->dev.parent = regmap_get_device(data->regmap); 811 data->trig->ops = &bmi160_trigger_ops; 812 iio_trigger_set_drvdata(data->trig, indio_dev); 813 814 ret = devm_iio_trigger_register(&indio_dev->dev, data->trig); 815 if (ret) 816 return ret; 817 818 indio_dev->trig = iio_trigger_get(data->trig); 819 820 return 0; 821 } 822 823 static void bmi160_chip_uninit(void *data) 824 { 825 struct bmi160_data *bmi_data = data; 826 struct device *dev = regmap_get_device(bmi_data->regmap); 827 int ret; 828 829 bmi160_set_mode(bmi_data, BMI160_GYRO, false); 830 bmi160_set_mode(bmi_data, BMI160_ACCEL, false); 831 832 ret = regulator_bulk_disable(ARRAY_SIZE(bmi_data->supplies), 833 bmi_data->supplies); 834 if (ret) 835 dev_err(dev, "Failed to disable regulators: %d\n", ret); 836 } 837 838 int bmi160_core_probe(struct device *dev, struct regmap *regmap, 839 const char *name, bool use_spi) 840 { 841 struct iio_dev *indio_dev; 842 struct bmi160_data *data; 843 int irq; 844 enum bmi160_int_pin int_pin; 845 int ret; 846 847 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 848 if (!indio_dev) 849 return -ENOMEM; 850 851 data = iio_priv(indio_dev); 852 dev_set_drvdata(dev, indio_dev); 853 data->regmap = regmap; 854 855 data->supplies[0].supply = "vdd"; 856 data->supplies[1].supply = "vddio"; 857 ret = devm_regulator_bulk_get(dev, 858 ARRAY_SIZE(data->supplies), 859 data->supplies); 860 if (ret) { 861 dev_err(dev, "Failed to get regulators: %d\n", ret); 862 return ret; 863 } 864 865 ret = iio_read_mount_matrix(dev, &data->orientation); 866 if (ret) 867 return ret; 868 869 ret = bmi160_chip_init(data, use_spi); 870 if (ret) 871 return ret; 872 873 ret = devm_add_action_or_reset(dev, bmi160_chip_uninit, data); 874 if (ret) 875 return ret; 876 877 indio_dev->channels = bmi160_channels; 878 indio_dev->num_channels = ARRAY_SIZE(bmi160_channels); 879 indio_dev->name = name; 880 indio_dev->modes = INDIO_DIRECT_MODE; 881 indio_dev->info = &bmi160_info; 882 883 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 884 iio_pollfunc_store_time, 885 bmi160_trigger_handler, NULL); 886 if (ret) 887 return ret; 888 889 irq = bmi160_get_irq(dev_fwnode(dev), &int_pin); 890 if (irq > 0) { 891 ret = bmi160_setup_irq(indio_dev, irq, int_pin); 892 if (ret) 893 dev_err(&indio_dev->dev, "Failed to setup IRQ %d\n", 894 irq); 895 } else { 896 dev_info(&indio_dev->dev, "Not setting up IRQ trigger\n"); 897 } 898 899 return devm_iio_device_register(dev, indio_dev); 900 } 901 EXPORT_SYMBOL_NS_GPL(bmi160_core_probe, IIO_BMI160); 902 903 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>"); 904 MODULE_DESCRIPTION("Bosch BMI160 driver"); 905 MODULE_LICENSE("GPL v2"); 906