1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ADIS16475 IMU driver 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/debugfs.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/kernel.h> 14 #include <linux/iio/buffer.h> 15 #include <linux/iio/iio.h> 16 #include <linux/iio/imu/adis.h> 17 #include <linux/iio/sysfs.h> 18 #include <linux/iio/trigger_consumer.h> 19 #include <linux/irq.h> 20 #include <linux/lcm.h> 21 #include <linux/math.h> 22 #include <linux/module.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/property.h> 25 #include <linux/spi/spi.h> 26 27 #define ADIS16475_REG_DIAG_STAT 0x02 28 #define ADIS16475_REG_X_GYRO_L 0x04 29 #define ADIS16475_REG_Y_GYRO_L 0x08 30 #define ADIS16475_REG_Z_GYRO_L 0x0C 31 #define ADIS16475_REG_X_ACCEL_L 0x10 32 #define ADIS16475_REG_Y_ACCEL_L 0x14 33 #define ADIS16475_REG_Z_ACCEL_L 0x18 34 #define ADIS16475_REG_TEMP_OUT 0x1c 35 #define ADIS16475_REG_X_DELTANG_L 0x24 36 #define ADIS16475_REG_Y_DELTANG_L 0x28 37 #define ADIS16475_REG_Z_DELTANG_L 0x2C 38 #define ADIS16475_REG_X_DELTVEL_L 0x30 39 #define ADIS16475_REG_Y_DELTVEL_L 0x34 40 #define ADIS16475_REG_Z_DELTVEL_L 0x38 41 #define ADIS16475_REG_X_GYRO_BIAS_L 0x40 42 #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44 43 #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48 44 #define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c 45 #define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50 46 #define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54 47 #define ADIS16475_REG_FILT_CTRL 0x5c 48 #define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0) 49 #define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x) 50 #define ADIS16475_REG_MSG_CTRL 0x60 51 #define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0) 52 #define ADIS16475_MSG_CTRL_DR_POL(x) \ 53 FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x) 54 #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2) 55 #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x) 56 #define ADIS16575_SYNC_4KHZ_MASK BIT(11) 57 #define ADIS16575_SYNC_4KHZ(x) FIELD_PREP(ADIS16575_SYNC_4KHZ_MASK, x) 58 #define ADIS16475_REG_UP_SCALE 0x62 59 #define ADIS16475_REG_DEC_RATE 0x64 60 #define ADIS16475_REG_GLOB_CMD 0x68 61 #define ADIS16475_REG_FIRM_REV 0x6c 62 #define ADIS16475_REG_FIRM_DM 0x6e 63 #define ADIS16475_REG_FIRM_Y 0x70 64 #define ADIS16475_REG_PROD_ID 0x72 65 #define ADIS16475_REG_SERIAL_NUM 0x74 66 #define ADIS16475_REG_FLASH_CNT 0x7c 67 #define ADIS16500_BURST_DATA_SEL_MASK BIT(8) 68 #define ADIS16500_BURST32_MASK BIT(9) 69 #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) 70 /* number of data elements in burst mode */ 71 #define ADIS16475_BURST32_MAX_DATA_NO_TS32 32 72 #define ADIS16575_BURST32_DATA_TS32 34 73 #define ADIS16475_BURST_MAX_DATA 20 74 #define ADIS16475_MAX_SCAN_DATA 20 75 /* spi max speed in brust mode */ 76 #define ADIS16475_BURST_MAX_SPEED 1000000 77 #define ADIS16575_BURST_MAX_SPEED 8000000 78 #define ADIS16475_LSB_DEC_MASK 0 79 #define ADIS16475_LSB_FIR_MASK 1 80 #define ADIS16500_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0) 81 #define ADIS16500_BURST_DATA_SEL_1_CHN_MASK GENMASK(12, 7) 82 #define ADIS16575_MAX_FIFO_WM 511UL 83 #define ADIS16475_REG_FIFO_CTRL 0x5A 84 #define ADIS16575_WM_LVL_MASK GENMASK(15, 4) 85 #define ADIS16575_WM_LVL(x) FIELD_PREP(ADIS16575_WM_LVL_MASK, x) 86 #define ADIS16575_WM_POL_MASK BIT(3) 87 #define ADIS16575_WM_POL(x) FIELD_PREP(ADIS16575_WM_POL_MASK, x) 88 #define ADIS16575_WM_EN_MASK BIT(2) 89 #define ADIS16575_WM_EN(x) FIELD_PREP(ADIS16575_WM_EN_MASK, x) 90 #define ADIS16575_OVERFLOW_MASK BIT(1) 91 #define ADIS16575_STOP_ENQUEUE FIELD_PREP(ADIS16575_OVERFLOW_MASK, 0) 92 #define ADIS16575_OVERWRITE_OLDEST FIELD_PREP(ADIS16575_OVERFLOW_MASK, 1) 93 #define ADIS16575_FIFO_EN_MASK BIT(0) 94 #define ADIS16575_FIFO_EN(x) FIELD_PREP(ADIS16575_FIFO_EN_MASK, x) 95 #define ADIS16575_FIFO_FLUSH_CMD BIT(5) 96 #define ADIS16575_REG_FIFO_CNT 0x3C 97 98 enum { 99 ADIS16475_SYNC_DIRECT = 1, 100 ADIS16475_SYNC_SCALED, 101 ADIS16475_SYNC_OUTPUT, 102 ADIS16475_SYNC_PULSE = 5, 103 }; 104 105 struct adis16475_sync { 106 u16 sync_mode; 107 u16 min_rate; 108 u16 max_rate; 109 }; 110 111 struct adis16475_chip_info { 112 const struct iio_chan_spec *channels; 113 const struct adis16475_sync *sync; 114 const struct adis_data adis_data; 115 const char *name; 116 #define ADIS16475_HAS_BURST32 BIT(0) 117 #define ADIS16475_HAS_BURST_DELTA_DATA BIT(1) 118 #define ADIS16475_HAS_TIMESTAMP32 BIT(2) 119 #define ADIS16475_NEEDS_BURST_REQUEST BIT(3) 120 const long flags; 121 u32 num_channels; 122 u32 gyro_max_val; 123 u32 gyro_max_scale; 124 u32 accel_max_val; 125 u32 accel_max_scale; 126 u32 temp_scale; 127 u32 deltang_max_val; 128 u32 deltvel_max_val; 129 u32 int_clk; 130 u16 max_dec; 131 u8 num_sync; 132 }; 133 134 struct adis16475 { 135 const struct adis16475_chip_info *info; 136 struct adis adis; 137 u32 clk_freq; 138 bool burst32; 139 unsigned long lsb_flag; 140 u16 sync_mode; 141 u16 fifo_watermark; 142 /* Alignment needed for the timestamp */ 143 __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8); 144 }; 145 146 enum { 147 ADIS16475_SCAN_GYRO_X, 148 ADIS16475_SCAN_GYRO_Y, 149 ADIS16475_SCAN_GYRO_Z, 150 ADIS16475_SCAN_ACCEL_X, 151 ADIS16475_SCAN_ACCEL_Y, 152 ADIS16475_SCAN_ACCEL_Z, 153 ADIS16475_SCAN_TEMP, 154 ADIS16475_SCAN_DELTANG_X, 155 ADIS16475_SCAN_DELTANG_Y, 156 ADIS16475_SCAN_DELTANG_Z, 157 ADIS16475_SCAN_DELTVEL_X, 158 ADIS16475_SCAN_DELTVEL_Y, 159 ADIS16475_SCAN_DELTVEL_Z, 160 }; 161 162 static bool low_rate_allow; 163 module_param(low_rate_allow, bool, 0444); 164 MODULE_PARM_DESC(low_rate_allow, 165 "Allow IMU rates below the minimum advisable when external clk is used in SCALED mode (default: N)"); 166 167 #ifdef CONFIG_DEBUG_FS 168 static ssize_t adis16475_show_firmware_revision(struct file *file, 169 char __user *userbuf, 170 size_t count, loff_t *ppos) 171 { 172 struct adis16475 *st = file->private_data; 173 char buf[7]; 174 size_t len; 175 u16 rev; 176 int ret; 177 178 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev); 179 if (ret) 180 return ret; 181 182 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 183 184 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 185 } 186 187 static const struct file_operations adis16475_firmware_revision_fops = { 188 .open = simple_open, 189 .read = adis16475_show_firmware_revision, 190 .llseek = default_llseek, 191 .owner = THIS_MODULE, 192 }; 193 194 static ssize_t adis16475_show_firmware_date(struct file *file, 195 char __user *userbuf, 196 size_t count, loff_t *ppos) 197 { 198 struct adis16475 *st = file->private_data; 199 u16 md, year; 200 char buf[12]; 201 size_t len; 202 int ret; 203 204 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year); 205 if (ret) 206 return ret; 207 208 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md); 209 if (ret) 210 return ret; 211 212 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff, 213 year); 214 215 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 216 } 217 218 static const struct file_operations adis16475_firmware_date_fops = { 219 .open = simple_open, 220 .read = adis16475_show_firmware_date, 221 .llseek = default_llseek, 222 .owner = THIS_MODULE, 223 }; 224 225 static int adis16475_show_serial_number(void *arg, u64 *val) 226 { 227 struct adis16475 *st = arg; 228 u16 serial; 229 int ret; 230 231 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial); 232 if (ret) 233 return ret; 234 235 *val = serial; 236 237 return 0; 238 } 239 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops, 240 adis16475_show_serial_number, NULL, "0x%.4llx\n"); 241 242 static int adis16475_show_product_id(void *arg, u64 *val) 243 { 244 struct adis16475 *st = arg; 245 u16 prod_id; 246 int ret; 247 248 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id); 249 if (ret) 250 return ret; 251 252 *val = prod_id; 253 254 return 0; 255 } 256 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops, 257 adis16475_show_product_id, NULL, "%llu\n"); 258 259 static int adis16475_show_flash_count(void *arg, u64 *val) 260 { 261 struct adis16475 *st = arg; 262 u32 flash_count; 263 int ret; 264 265 ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT, 266 &flash_count); 267 if (ret) 268 return ret; 269 270 *val = flash_count; 271 272 return 0; 273 } 274 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops, 275 adis16475_show_flash_count, NULL, "%lld\n"); 276 277 static void adis16475_debugfs_init(struct iio_dev *indio_dev) 278 { 279 struct adis16475 *st = iio_priv(indio_dev); 280 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 281 282 debugfs_create_file_unsafe("serial_number", 0400, 283 d, st, &adis16475_serial_number_fops); 284 debugfs_create_file_unsafe("product_id", 0400, 285 d, st, &adis16475_product_id_fops); 286 debugfs_create_file_unsafe("flash_count", 0400, 287 d, st, &adis16475_flash_count_fops); 288 debugfs_create_file("firmware_revision", 0400, 289 d, st, &adis16475_firmware_revision_fops); 290 debugfs_create_file("firmware_date", 0400, d, 291 st, &adis16475_firmware_date_fops); 292 } 293 #else 294 static void adis16475_debugfs_init(struct iio_dev *indio_dev) 295 { 296 } 297 #endif 298 299 static int adis16475_get_freq(struct adis16475 *st, u32 *freq) 300 { 301 int ret; 302 u16 dec; 303 u32 sample_rate = st->clk_freq; 304 305 adis_dev_auto_lock(&st->adis); 306 307 if (st->sync_mode == ADIS16475_SYNC_SCALED) { 308 u16 sync_scale; 309 310 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, &sync_scale); 311 if (ret) 312 return ret; 313 314 sample_rate = st->clk_freq * sync_scale; 315 } 316 317 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec); 318 if (ret) 319 return ret; 320 321 *freq = DIV_ROUND_CLOSEST(sample_rate, dec + 1); 322 323 return 0; 324 } 325 326 static int adis16475_set_freq(struct adis16475 *st, const u32 freq) 327 { 328 u16 dec; 329 int ret; 330 u32 sample_rate = st->clk_freq; 331 /* The optimal sample rate for the supported IMUs is between int_clk - 100 and int_clk + 100. */ 332 u32 max_sample_rate = st->info->int_clk * 1000 + 100000; 333 u32 min_sample_rate = st->info->int_clk * 1000 - 100000; 334 335 if (!freq) 336 return -EINVAL; 337 338 adis_dev_auto_lock(&st->adis); 339 /* 340 * When using sync scaled mode, the input clock needs to be scaled so that we have 341 * an IMU sample rate between (optimally) int_clk - 100 and int_clk + 100. 342 * After this, we can use the decimation filter to lower the sampling rate in order 343 * to get what the user wants. 344 * Optimally, the user sample rate is a multiple of both the IMU sample rate and 345 * the input clock. Hence, calculating the sync_scale dynamically gives us better 346 * chances of achieving a perfect/integer value for DEC_RATE. The math here is: 347 * 1. lcm of the input clock and the desired output rate. 348 * 2. get the highest multiple of the previous result lower than the adis max rate. 349 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE 350 * and DEC_RATE (to get the user output rate) 351 */ 352 if (st->sync_mode == ADIS16475_SYNC_SCALED) { 353 unsigned long scaled_rate = lcm(st->clk_freq, freq); 354 int sync_scale; 355 356 /* 357 * If lcm is bigger than the IMU maximum sampling rate there's no perfect 358 * solution. In this case, we get the highest multiple of the input clock 359 * lower than the IMU max sample rate. 360 */ 361 if (scaled_rate > max_sample_rate) 362 scaled_rate = max_sample_rate / st->clk_freq * st->clk_freq; 363 else 364 scaled_rate = max_sample_rate / scaled_rate * scaled_rate; 365 366 /* 367 * This is not an hard requirement but it's not advised to run the IMU 368 * with a sample rate lower than internal clock frequency, due to possible 369 * undersampling issues. However, there are users that might really want 370 * to take the risk. Hence, we provide a module parameter for them. If set, 371 * we allow sample rates lower than internal clock frequency. 372 * By default, we won't allow this and we just roundup the rate to the next 373 * multiple of the input clock. This is done like this as in some cases 374 * (when DEC_RATE is 0) might give us the closest value to the one desired 375 * by the user... 376 */ 377 if (scaled_rate < min_sample_rate && !low_rate_allow) 378 scaled_rate = roundup(min_sample_rate, st->clk_freq); 379 380 sync_scale = scaled_rate / st->clk_freq; 381 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, sync_scale); 382 if (ret) 383 return ret; 384 385 sample_rate = scaled_rate; 386 } 387 388 dec = DIV_ROUND_CLOSEST(sample_rate, freq); 389 390 if (dec) 391 dec--; 392 393 if (dec > st->info->max_dec) 394 dec = st->info->max_dec; 395 396 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec); 397 if (ret) 398 return ret; 399 400 /* 401 * If decimation is used, then gyro and accel data will have meaningful 402 * bits on the LSB registers. This info is used on the trigger handler. 403 */ 404 assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec); 405 406 return 0; 407 } 408 409 /* The values are approximated. */ 410 static const u32 adis16475_3db_freqs[] = { 411 [0] = 720, /* Filter disabled, full BW (~720Hz) */ 412 [1] = 360, 413 [2] = 164, 414 [3] = 80, 415 [4] = 40, 416 [5] = 20, 417 [6] = 10, 418 }; 419 420 static int adis16475_get_filter(struct adis16475 *st, u32 *filter) 421 { 422 u16 filter_sz; 423 int ret; 424 const int mask = ADIS16475_FILT_CTRL_MASK; 425 426 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz); 427 if (ret) 428 return ret; 429 430 *filter = adis16475_3db_freqs[filter_sz & mask]; 431 432 return 0; 433 } 434 435 static int adis16475_set_filter(struct adis16475 *st, const u32 filter) 436 { 437 int i = ARRAY_SIZE(adis16475_3db_freqs); 438 int ret; 439 440 while (--i) { 441 if (adis16475_3db_freqs[i] >= filter) 442 break; 443 } 444 445 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, 446 ADIS16475_FILT_CTRL(i)); 447 if (ret) 448 return ret; 449 450 /* 451 * If FIR is used, then gyro and accel data will have meaningful 452 * bits on the LSB registers. This info is used on the trigger handler. 453 */ 454 assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i); 455 456 return 0; 457 } 458 459 static ssize_t adis16475_get_fifo_enabled(struct device *dev, 460 struct device_attribute *attr, 461 char *buf) 462 { 463 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 464 struct adis16475 *st = iio_priv(indio_dev); 465 int ret; 466 u16 val; 467 468 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val); 469 if (ret) 470 return ret; 471 472 return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_FIFO_EN_MASK, val)); 473 } 474 475 static ssize_t adis16475_get_fifo_watermark(struct device *dev, 476 struct device_attribute *attr, 477 char *buf) 478 { 479 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 480 struct adis16475 *st = iio_priv(indio_dev); 481 int ret; 482 u16 val; 483 484 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val); 485 if (ret) 486 return ret; 487 488 return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_WM_LVL_MASK, val) + 1); 489 } 490 491 static ssize_t hwfifo_watermark_min_show(struct device *dev, 492 struct device_attribute *attr, 493 char *buf) 494 { 495 return sysfs_emit(buf, "1\n"); 496 } 497 498 static ssize_t hwfifo_watermark_max_show(struct device *dev, 499 struct device_attribute *attr, 500 char *buf) 501 { 502 return sysfs_emit(buf, "%lu\n", ADIS16575_MAX_FIFO_WM); 503 } 504 505 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); 506 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); 507 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 508 adis16475_get_fifo_watermark, NULL, 0); 509 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 510 adis16475_get_fifo_enabled, NULL, 0); 511 512 static const struct iio_dev_attr *adis16475_fifo_attributes[] = { 513 &iio_dev_attr_hwfifo_watermark_min, 514 &iio_dev_attr_hwfifo_watermark_max, 515 &iio_dev_attr_hwfifo_watermark, 516 &iio_dev_attr_hwfifo_enabled, 517 NULL 518 }; 519 520 static int adis16475_buffer_postenable(struct iio_dev *indio_dev) 521 { 522 struct adis16475 *st = iio_priv(indio_dev); 523 struct adis *adis = &st->adis; 524 525 return adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL, 526 ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(1)); 527 } 528 529 static int adis16475_buffer_postdisable(struct iio_dev *indio_dev) 530 { 531 struct adis16475 *st = iio_priv(indio_dev); 532 struct adis *adis = &st->adis; 533 int ret; 534 535 adis_dev_auto_lock(&st->adis); 536 537 ret = __adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL, 538 ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(0)); 539 if (ret) 540 return ret; 541 542 return __adis_write_reg_16(adis, ADIS16475_REG_GLOB_CMD, 543 ADIS16575_FIFO_FLUSH_CMD); 544 } 545 546 static const struct iio_buffer_setup_ops adis16475_buffer_ops = { 547 .postenable = adis16475_buffer_postenable, 548 .postdisable = adis16475_buffer_postdisable, 549 }; 550 551 static int adis16475_set_watermark(struct iio_dev *indio_dev, unsigned int val) 552 { 553 struct adis16475 *st = iio_priv(indio_dev); 554 int ret; 555 u16 wm_lvl; 556 557 adis_dev_auto_lock(&st->adis); 558 559 val = min_t(unsigned int, val, ADIS16575_MAX_FIFO_WM); 560 561 wm_lvl = ADIS16575_WM_LVL(val - 1); 562 ret = __adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, ADIS16575_WM_LVL_MASK, wm_lvl); 563 if (ret) 564 return ret; 565 566 st->fifo_watermark = val; 567 568 return 0; 569 } 570 571 static const u32 adis16475_calib_regs[] = { 572 [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L, 573 [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L, 574 [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L, 575 [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L, 576 [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L, 577 [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L, 578 }; 579 580 static int adis16475_read_raw(struct iio_dev *indio_dev, 581 const struct iio_chan_spec *chan, 582 int *val, int *val2, long info) 583 { 584 struct adis16475 *st = iio_priv(indio_dev); 585 int ret; 586 u32 tmp; 587 588 switch (info) { 589 case IIO_CHAN_INFO_RAW: 590 return adis_single_conversion(indio_dev, chan, 0, val); 591 case IIO_CHAN_INFO_SCALE: 592 switch (chan->type) { 593 case IIO_ANGL_VEL: 594 *val = st->info->gyro_max_val; 595 *val2 = st->info->gyro_max_scale; 596 return IIO_VAL_FRACTIONAL; 597 case IIO_ACCEL: 598 *val = st->info->accel_max_val; 599 *val2 = st->info->accel_max_scale; 600 return IIO_VAL_FRACTIONAL; 601 case IIO_TEMP: 602 *val = st->info->temp_scale; 603 return IIO_VAL_INT; 604 case IIO_DELTA_ANGL: 605 *val = st->info->deltang_max_val; 606 *val2 = 31; 607 return IIO_VAL_FRACTIONAL_LOG2; 608 case IIO_DELTA_VELOCITY: 609 *val = st->info->deltvel_max_val; 610 *val2 = 31; 611 return IIO_VAL_FRACTIONAL_LOG2; 612 default: 613 return -EINVAL; 614 } 615 case IIO_CHAN_INFO_CALIBBIAS: 616 ret = adis_read_reg_32(&st->adis, 617 adis16475_calib_regs[chan->scan_index], 618 val); 619 if (ret) 620 return ret; 621 622 return IIO_VAL_INT; 623 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 624 ret = adis16475_get_filter(st, val); 625 if (ret) 626 return ret; 627 628 return IIO_VAL_INT; 629 case IIO_CHAN_INFO_SAMP_FREQ: 630 ret = adis16475_get_freq(st, &tmp); 631 if (ret) 632 return ret; 633 634 *val = tmp / 1000; 635 *val2 = (tmp % 1000) * 1000; 636 return IIO_VAL_INT_PLUS_MICRO; 637 default: 638 return -EINVAL; 639 } 640 } 641 642 static int adis16475_write_raw(struct iio_dev *indio_dev, 643 const struct iio_chan_spec *chan, 644 int val, int val2, long info) 645 { 646 struct adis16475 *st = iio_priv(indio_dev); 647 u32 tmp; 648 649 switch (info) { 650 case IIO_CHAN_INFO_SAMP_FREQ: 651 tmp = val * 1000 + val2 / 1000; 652 return adis16475_set_freq(st, tmp); 653 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 654 return adis16475_set_filter(st, val); 655 case IIO_CHAN_INFO_CALIBBIAS: 656 return adis_write_reg_32(&st->adis, 657 adis16475_calib_regs[chan->scan_index], 658 val); 659 default: 660 return -EINVAL; 661 } 662 } 663 664 #define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \ 665 { \ 666 .type = (_type), \ 667 .modified = 1, \ 668 .channel2 = (_mod), \ 669 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 670 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 671 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 672 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 673 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 674 .address = (_address), \ 675 .scan_index = (_si), \ 676 .scan_type = { \ 677 .sign = 's', \ 678 .realbits = (_r_bits), \ 679 .storagebits = (_s_bits), \ 680 .endianness = IIO_BE, \ 681 }, \ 682 } 683 684 #define ADIS16475_GYRO_CHANNEL(_mod) \ 685 ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 686 ADIS16475_REG_ ## _mod ## _GYRO_L, \ 687 ADIS16475_SCAN_GYRO_ ## _mod, 32, 32) 688 689 #define ADIS16475_ACCEL_CHANNEL(_mod) \ 690 ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \ 691 ADIS16475_REG_ ## _mod ## _ACCEL_L, \ 692 ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32) 693 694 #define ADIS16475_TEMP_CHANNEL() { \ 695 .type = IIO_TEMP, \ 696 .indexed = 1, \ 697 .channel = 0, \ 698 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 699 BIT(IIO_CHAN_INFO_SCALE), \ 700 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 701 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 702 .address = ADIS16475_REG_TEMP_OUT, \ 703 .scan_index = ADIS16475_SCAN_TEMP, \ 704 .scan_type = { \ 705 .sign = 's', \ 706 .realbits = 16, \ 707 .storagebits = 16, \ 708 .endianness = IIO_BE, \ 709 }, \ 710 } 711 712 #define ADIS16475_MOD_CHAN_DELTA(_type, _mod, _address, _si, _r_bits, _s_bits) { \ 713 .type = (_type), \ 714 .modified = 1, \ 715 .channel2 = (_mod), \ 716 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 717 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 718 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 719 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 720 .address = (_address), \ 721 .scan_index = _si, \ 722 .scan_type = { \ 723 .sign = 's', \ 724 .realbits = (_r_bits), \ 725 .storagebits = (_s_bits), \ 726 .endianness = IIO_BE, \ 727 }, \ 728 } 729 730 #define ADIS16475_DELTANG_CHAN(_mod) \ 731 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 732 ADIS16475_REG_ ## _mod ## _DELTANG_L, ADIS16475_SCAN_DELTANG_ ## _mod, 32, 32) 733 734 #define ADIS16475_DELTVEL_CHAN(_mod) \ 735 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 736 ADIS16475_REG_ ## _mod ## _DELTVEL_L, ADIS16475_SCAN_DELTVEL_ ## _mod, 32, 32) 737 738 #define ADIS16475_DELTANG_CHAN_NO_SCAN(_mod) \ 739 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 740 ADIS16475_REG_ ## _mod ## _DELTANG_L, -1, 32, 32) 741 742 #define ADIS16475_DELTVEL_CHAN_NO_SCAN(_mod) \ 743 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 744 ADIS16475_REG_ ## _mod ## _DELTVEL_L, -1, 32, 32) 745 746 static const struct iio_chan_spec adis16477_channels[] = { 747 ADIS16475_GYRO_CHANNEL(X), 748 ADIS16475_GYRO_CHANNEL(Y), 749 ADIS16475_GYRO_CHANNEL(Z), 750 ADIS16475_ACCEL_CHANNEL(X), 751 ADIS16475_ACCEL_CHANNEL(Y), 752 ADIS16475_ACCEL_CHANNEL(Z), 753 ADIS16475_TEMP_CHANNEL(), 754 ADIS16475_DELTANG_CHAN(X), 755 ADIS16475_DELTANG_CHAN(Y), 756 ADIS16475_DELTANG_CHAN(Z), 757 ADIS16475_DELTVEL_CHAN(X), 758 ADIS16475_DELTVEL_CHAN(Y), 759 ADIS16475_DELTVEL_CHAN(Z), 760 IIO_CHAN_SOFT_TIMESTAMP(13) 761 }; 762 763 static const struct iio_chan_spec adis16475_channels[] = { 764 ADIS16475_GYRO_CHANNEL(X), 765 ADIS16475_GYRO_CHANNEL(Y), 766 ADIS16475_GYRO_CHANNEL(Z), 767 ADIS16475_ACCEL_CHANNEL(X), 768 ADIS16475_ACCEL_CHANNEL(Y), 769 ADIS16475_ACCEL_CHANNEL(Z), 770 ADIS16475_TEMP_CHANNEL(), 771 ADIS16475_DELTANG_CHAN_NO_SCAN(X), 772 ADIS16475_DELTANG_CHAN_NO_SCAN(Y), 773 ADIS16475_DELTANG_CHAN_NO_SCAN(Z), 774 ADIS16475_DELTVEL_CHAN_NO_SCAN(X), 775 ADIS16475_DELTVEL_CHAN_NO_SCAN(Y), 776 ADIS16475_DELTVEL_CHAN_NO_SCAN(Z), 777 IIO_CHAN_SOFT_TIMESTAMP(7) 778 }; 779 780 static const struct iio_chan_spec adis16575_channels[] = { 781 ADIS16475_GYRO_CHANNEL(X), 782 ADIS16475_GYRO_CHANNEL(Y), 783 ADIS16475_GYRO_CHANNEL(Z), 784 ADIS16475_ACCEL_CHANNEL(X), 785 ADIS16475_ACCEL_CHANNEL(Y), 786 ADIS16475_ACCEL_CHANNEL(Z), 787 ADIS16475_TEMP_CHANNEL(), 788 ADIS16475_DELTANG_CHAN(X), 789 ADIS16475_DELTANG_CHAN(Y), 790 ADIS16475_DELTANG_CHAN(Z), 791 ADIS16475_DELTVEL_CHAN(X), 792 ADIS16475_DELTVEL_CHAN(Y), 793 ADIS16475_DELTVEL_CHAN(Z), 794 }; 795 796 enum adis16475_variant { 797 ADIS16470, 798 ADIS16475_1, 799 ADIS16475_2, 800 ADIS16475_3, 801 ADIS16477_1, 802 ADIS16477_2, 803 ADIS16477_3, 804 ADIS16465_1, 805 ADIS16465_2, 806 ADIS16465_3, 807 ADIS16467_1, 808 ADIS16467_2, 809 ADIS16467_3, 810 ADIS16500, 811 ADIS16501, 812 ADIS16505_1, 813 ADIS16505_2, 814 ADIS16505_3, 815 ADIS16507_1, 816 ADIS16507_2, 817 ADIS16507_3, 818 ADIS16575_2, 819 ADIS16575_3, 820 ADIS16576_2, 821 ADIS16576_3, 822 ADIS16577_2, 823 ADIS16577_3, 824 }; 825 826 enum { 827 ADIS16475_DIAG_STAT_DATA_PATH = 1, 828 ADIS16475_DIAG_STAT_FLASH_MEM, 829 ADIS16475_DIAG_STAT_SPI, 830 ADIS16475_DIAG_STAT_STANDBY, 831 ADIS16475_DIAG_STAT_SENSOR, 832 ADIS16475_DIAG_STAT_MEMORY, 833 ADIS16475_DIAG_STAT_CLK, 834 }; 835 836 static const char * const adis16475_status_error_msgs[] = { 837 [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun", 838 [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure", 839 [ADIS16475_DIAG_STAT_SPI] = "SPI communication error", 840 [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode", 841 [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure", 842 [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure", 843 [ADIS16475_DIAG_STAT_CLK] = "Clock error", 844 }; 845 846 #define ADIS16475_DATA(_prod_id, _timeouts, _burst_max_len, _burst_max_speed_hz, _has_fifo) \ 847 { \ 848 .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \ 849 .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \ 850 .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \ 851 .prod_id_reg = ADIS16475_REG_PROD_ID, \ 852 .prod_id = (_prod_id), \ 853 .self_test_mask = BIT(2), \ 854 .self_test_reg = ADIS16475_REG_GLOB_CMD, \ 855 .cs_change_delay = 16, \ 856 .read_delay = 5, \ 857 .write_delay = 5, \ 858 .status_error_msgs = adis16475_status_error_msgs, \ 859 .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ 860 BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ 861 BIT(ADIS16475_DIAG_STAT_SPI) | \ 862 BIT(ADIS16475_DIAG_STAT_STANDBY) | \ 863 BIT(ADIS16475_DIAG_STAT_SENSOR) | \ 864 BIT(ADIS16475_DIAG_STAT_MEMORY) | \ 865 BIT(ADIS16475_DIAG_STAT_CLK), \ 866 .unmasked_drdy = true, \ 867 .has_fifo = _has_fifo, \ 868 .timeouts = (_timeouts), \ 869 .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \ 870 .burst_len = ADIS16475_BURST_MAX_DATA, \ 871 .burst_max_len = _burst_max_len, \ 872 .burst_max_speed_hz = _burst_max_speed_hz \ 873 } 874 875 static const struct adis16475_sync adis16475_sync_mode[] = { 876 { ADIS16475_SYNC_OUTPUT }, 877 { ADIS16475_SYNC_DIRECT, 1900, 2100 }, 878 { ADIS16475_SYNC_SCALED, 1, 128 }, 879 { ADIS16475_SYNC_PULSE, 1000, 2100 }, 880 }; 881 882 static const struct adis16475_sync adis16575_sync_mode[] = { 883 { ADIS16475_SYNC_OUTPUT }, 884 { ADIS16475_SYNC_DIRECT, 1900, 4100 }, 885 { ADIS16475_SYNC_SCALED, 1, 400 }, 886 }; 887 888 static const struct adis_timeout adis16475_timeouts = { 889 .reset_ms = 200, 890 .sw_reset_ms = 200, 891 .self_test_ms = 20, 892 }; 893 894 static const struct adis_timeout adis1650x_timeouts = { 895 .reset_ms = 260, 896 .sw_reset_ms = 260, 897 .self_test_ms = 30, 898 }; 899 900 static const struct adis16475_chip_info adis16475_chip_info[] = { 901 [ADIS16470] = { 902 .name = "adis16470", 903 .num_channels = ARRAY_SIZE(adis16475_channels), 904 .channels = adis16475_channels, 905 .gyro_max_val = 1, 906 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 907 .accel_max_val = 1, 908 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 909 .temp_scale = 100, 910 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 911 .deltvel_max_val = 400, 912 .int_clk = 2000, 913 .max_dec = 1999, 914 .sync = adis16475_sync_mode, 915 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 916 .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts, 917 ADIS16475_BURST32_MAX_DATA_NO_TS32, 918 ADIS16475_BURST_MAX_SPEED, false), 919 }, 920 [ADIS16475_1] = { 921 .name = "adis16475-1", 922 .num_channels = ARRAY_SIZE(adis16475_channels), 923 .channels = adis16475_channels, 924 .gyro_max_val = 1, 925 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 926 .accel_max_val = 1, 927 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 928 .temp_scale = 100, 929 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 930 .deltvel_max_val = 100, 931 .int_clk = 2000, 932 .max_dec = 1999, 933 .sync = adis16475_sync_mode, 934 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 935 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts, 936 ADIS16475_BURST32_MAX_DATA_NO_TS32, 937 ADIS16475_BURST_MAX_SPEED, false), 938 }, 939 [ADIS16475_2] = { 940 .name = "adis16475-2", 941 .num_channels = ARRAY_SIZE(adis16475_channels), 942 .channels = adis16475_channels, 943 .gyro_max_val = 1, 944 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 945 .accel_max_val = 1, 946 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 947 .temp_scale = 100, 948 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 949 .deltvel_max_val = 100, 950 .int_clk = 2000, 951 .max_dec = 1999, 952 .sync = adis16475_sync_mode, 953 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 954 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts, 955 ADIS16475_BURST32_MAX_DATA_NO_TS32, 956 ADIS16475_BURST_MAX_SPEED, false), 957 }, 958 [ADIS16475_3] = { 959 .name = "adis16475-3", 960 .num_channels = ARRAY_SIZE(adis16475_channels), 961 .channels = adis16475_channels, 962 .gyro_max_val = 1, 963 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 964 .accel_max_val = 1, 965 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 966 .temp_scale = 100, 967 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 968 .deltvel_max_val = 100, 969 .int_clk = 2000, 970 .max_dec = 1999, 971 .sync = adis16475_sync_mode, 972 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 973 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts, 974 ADIS16475_BURST32_MAX_DATA_NO_TS32, 975 ADIS16475_BURST_MAX_SPEED, false), 976 }, 977 [ADIS16477_1] = { 978 .name = "adis16477-1", 979 .num_channels = ARRAY_SIZE(adis16477_channels), 980 .channels = adis16477_channels, 981 .gyro_max_val = 1, 982 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 983 .accel_max_val = 1, 984 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 985 .temp_scale = 100, 986 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 987 .deltvel_max_val = 400, 988 .int_clk = 2000, 989 .max_dec = 1999, 990 .sync = adis16475_sync_mode, 991 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 992 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 993 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts, 994 ADIS16475_BURST32_MAX_DATA_NO_TS32, 995 ADIS16475_BURST_MAX_SPEED, false), 996 }, 997 [ADIS16477_2] = { 998 .name = "adis16477-2", 999 .num_channels = ARRAY_SIZE(adis16477_channels), 1000 .channels = adis16477_channels, 1001 .gyro_max_val = 1, 1002 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1003 .accel_max_val = 1, 1004 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1005 .temp_scale = 100, 1006 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1007 .deltvel_max_val = 400, 1008 .int_clk = 2000, 1009 .max_dec = 1999, 1010 .sync = adis16475_sync_mode, 1011 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1012 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1013 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts, 1014 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1015 ADIS16475_BURST_MAX_SPEED, false), 1016 }, 1017 [ADIS16477_3] = { 1018 .name = "adis16477-3", 1019 .num_channels = ARRAY_SIZE(adis16477_channels), 1020 .channels = adis16477_channels, 1021 .gyro_max_val = 1, 1022 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1023 .accel_max_val = 1, 1024 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1025 .temp_scale = 100, 1026 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1027 .deltvel_max_val = 400, 1028 .int_clk = 2000, 1029 .max_dec = 1999, 1030 .sync = adis16475_sync_mode, 1031 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1032 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1033 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts, 1034 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1035 ADIS16475_BURST_MAX_SPEED, false), 1036 }, 1037 [ADIS16465_1] = { 1038 .name = "adis16465-1", 1039 .num_channels = ARRAY_SIZE(adis16475_channels), 1040 .channels = adis16475_channels, 1041 .gyro_max_val = 1, 1042 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 1043 .accel_max_val = 1, 1044 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 1045 .temp_scale = 100, 1046 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1047 .deltvel_max_val = 100, 1048 .int_clk = 2000, 1049 .max_dec = 1999, 1050 .sync = adis16475_sync_mode, 1051 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1052 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts, 1053 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1054 ADIS16475_BURST_MAX_SPEED, false), 1055 }, 1056 [ADIS16465_2] = { 1057 .name = "adis16465-2", 1058 .num_channels = ARRAY_SIZE(adis16475_channels), 1059 .channels = adis16475_channels, 1060 .gyro_max_val = 1, 1061 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1062 .accel_max_val = 1, 1063 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 1064 .temp_scale = 100, 1065 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1066 .deltvel_max_val = 100, 1067 .int_clk = 2000, 1068 .max_dec = 1999, 1069 .sync = adis16475_sync_mode, 1070 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1071 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts, 1072 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1073 ADIS16475_BURST_MAX_SPEED, false), 1074 }, 1075 [ADIS16465_3] = { 1076 .name = "adis16465-3", 1077 .num_channels = ARRAY_SIZE(adis16475_channels), 1078 .channels = adis16475_channels, 1079 .gyro_max_val = 1, 1080 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1081 .accel_max_val = 1, 1082 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 1083 .temp_scale = 100, 1084 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1085 .deltvel_max_val = 100, 1086 .int_clk = 2000, 1087 .max_dec = 1999, 1088 .sync = adis16475_sync_mode, 1089 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1090 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts, 1091 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1092 ADIS16475_BURST_MAX_SPEED, false), 1093 }, 1094 [ADIS16467_1] = { 1095 .name = "adis16467-1", 1096 .num_channels = ARRAY_SIZE(adis16475_channels), 1097 .channels = adis16475_channels, 1098 .gyro_max_val = 1, 1099 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 1100 .accel_max_val = 1, 1101 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1102 .temp_scale = 100, 1103 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1104 .deltvel_max_val = 400, 1105 .int_clk = 2000, 1106 .max_dec = 1999, 1107 .sync = adis16475_sync_mode, 1108 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1109 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts, 1110 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1111 ADIS16475_BURST_MAX_SPEED, false), 1112 }, 1113 [ADIS16467_2] = { 1114 .name = "adis16467-2", 1115 .num_channels = ARRAY_SIZE(adis16475_channels), 1116 .channels = adis16475_channels, 1117 .gyro_max_val = 1, 1118 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1119 .accel_max_val = 1, 1120 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1121 .temp_scale = 100, 1122 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1123 .deltvel_max_val = 400, 1124 .int_clk = 2000, 1125 .max_dec = 1999, 1126 .sync = adis16475_sync_mode, 1127 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1128 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts, 1129 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1130 ADIS16475_BURST_MAX_SPEED, false), 1131 }, 1132 [ADIS16467_3] = { 1133 .name = "adis16467-3", 1134 .num_channels = ARRAY_SIZE(adis16475_channels), 1135 .channels = adis16475_channels, 1136 .gyro_max_val = 1, 1137 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1138 .accel_max_val = 1, 1139 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1140 .temp_scale = 100, 1141 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1142 .deltvel_max_val = 400, 1143 .int_clk = 2000, 1144 .max_dec = 1999, 1145 .sync = adis16475_sync_mode, 1146 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1147 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts, 1148 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1149 ADIS16475_BURST_MAX_SPEED, false), 1150 }, 1151 [ADIS16500] = { 1152 .name = "adis16500", 1153 .num_channels = ARRAY_SIZE(adis16477_channels), 1154 .channels = adis16477_channels, 1155 .gyro_max_val = 1, 1156 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1157 .accel_max_val = 392, 1158 .accel_max_scale = 32000 << 16, 1159 .temp_scale = 100, 1160 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1161 .deltvel_max_val = 400, 1162 .int_clk = 2000, 1163 .max_dec = 1999, 1164 .sync = adis16475_sync_mode, 1165 /* pulse sync not supported */ 1166 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1167 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1168 .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts, 1169 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1170 ADIS16475_BURST_MAX_SPEED, false), 1171 }, 1172 [ADIS16501] = { 1173 .name = "adis16501", 1174 .num_channels = ARRAY_SIZE(adis16477_channels), 1175 .channels = adis16477_channels, 1176 .gyro_max_val = 1, 1177 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1178 .accel_max_val = 1, 1179 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1180 .temp_scale = 100, 1181 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1182 .deltvel_max_val = 125, 1183 .int_clk = 2000, 1184 .max_dec = 1999, 1185 .sync = adis16475_sync_mode, 1186 /* pulse sync not supported */ 1187 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1188 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1189 .adis_data = ADIS16475_DATA(16501, &adis1650x_timeouts, 1190 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1191 ADIS16475_BURST_MAX_SPEED, false), 1192 }, 1193 [ADIS16505_1] = { 1194 .name = "adis16505-1", 1195 .num_channels = ARRAY_SIZE(adis16477_channels), 1196 .channels = adis16477_channels, 1197 .gyro_max_val = 1, 1198 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 1199 .accel_max_val = 78, 1200 .accel_max_scale = 32000 << 16, 1201 .temp_scale = 100, 1202 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1203 .deltvel_max_val = 100, 1204 .int_clk = 2000, 1205 .max_dec = 1999, 1206 .sync = adis16475_sync_mode, 1207 /* pulse sync not supported */ 1208 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1209 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1210 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts, 1211 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1212 ADIS16475_BURST_MAX_SPEED, false), 1213 }, 1214 [ADIS16505_2] = { 1215 .name = "adis16505-2", 1216 .num_channels = ARRAY_SIZE(adis16477_channels), 1217 .channels = adis16477_channels, 1218 .gyro_max_val = 1, 1219 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1220 .accel_max_val = 78, 1221 .accel_max_scale = 32000 << 16, 1222 .temp_scale = 100, 1223 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1224 .deltvel_max_val = 100, 1225 .int_clk = 2000, 1226 .max_dec = 1999, 1227 .sync = adis16475_sync_mode, 1228 /* pulse sync not supported */ 1229 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1230 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1231 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts, 1232 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1233 ADIS16475_BURST_MAX_SPEED, false), 1234 }, 1235 [ADIS16505_3] = { 1236 .name = "adis16505-3", 1237 .num_channels = ARRAY_SIZE(adis16477_channels), 1238 .channels = adis16477_channels, 1239 .gyro_max_val = 1, 1240 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1241 .accel_max_val = 78, 1242 .accel_max_scale = 32000 << 16, 1243 .temp_scale = 100, 1244 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1245 .deltvel_max_val = 100, 1246 .int_clk = 2000, 1247 .max_dec = 1999, 1248 .sync = adis16475_sync_mode, 1249 /* pulse sync not supported */ 1250 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1251 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1252 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts, 1253 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1254 ADIS16475_BURST_MAX_SPEED, false), 1255 }, 1256 [ADIS16507_1] = { 1257 .name = "adis16507-1", 1258 .num_channels = ARRAY_SIZE(adis16477_channels), 1259 .channels = adis16477_channels, 1260 .gyro_max_val = 1, 1261 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 1262 .accel_max_val = 392, 1263 .accel_max_scale = 32000 << 16, 1264 .temp_scale = 100, 1265 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1266 .deltvel_max_val = 400, 1267 .int_clk = 2000, 1268 .max_dec = 1999, 1269 .sync = adis16475_sync_mode, 1270 /* pulse sync not supported */ 1271 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1272 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1273 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts, 1274 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1275 ADIS16475_BURST_MAX_SPEED, false), 1276 }, 1277 [ADIS16507_2] = { 1278 .name = "adis16507-2", 1279 .num_channels = ARRAY_SIZE(adis16477_channels), 1280 .channels = adis16477_channels, 1281 .gyro_max_val = 1, 1282 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1283 .accel_max_val = 392, 1284 .accel_max_scale = 32000 << 16, 1285 .temp_scale = 100, 1286 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1287 .deltvel_max_val = 400, 1288 .int_clk = 2000, 1289 .max_dec = 1999, 1290 .sync = adis16475_sync_mode, 1291 /* pulse sync not supported */ 1292 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1293 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1294 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts, 1295 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1296 ADIS16475_BURST_MAX_SPEED, false), 1297 }, 1298 [ADIS16507_3] = { 1299 .name = "adis16507-3", 1300 .num_channels = ARRAY_SIZE(adis16477_channels), 1301 .channels = adis16477_channels, 1302 .gyro_max_val = 1, 1303 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1304 .accel_max_val = 392, 1305 .accel_max_scale = 32000 << 16, 1306 .temp_scale = 100, 1307 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1308 .deltvel_max_val = 400, 1309 .int_clk = 2000, 1310 .max_dec = 1999, 1311 .sync = adis16475_sync_mode, 1312 /* pulse sync not supported */ 1313 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1314 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1315 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts, 1316 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1317 ADIS16475_BURST_MAX_SPEED, false), 1318 }, 1319 [ADIS16575_2] = { 1320 .name = "adis16575-2", 1321 .num_channels = ARRAY_SIZE(adis16575_channels), 1322 .channels = adis16575_channels, 1323 .gyro_max_val = 1, 1324 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1325 .accel_max_val = 8, 1326 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1327 .temp_scale = 100, 1328 .deltang_max_val = IIO_DEGREE_TO_RAD(450), 1329 .deltvel_max_val = 100, 1330 .int_clk = 4000, 1331 .max_dec = 3999, 1332 .sync = adis16575_sync_mode, 1333 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1334 .flags = ADIS16475_HAS_BURST32 | 1335 ADIS16475_HAS_BURST_DELTA_DATA | 1336 ADIS16475_NEEDS_BURST_REQUEST | 1337 ADIS16475_HAS_TIMESTAMP32, 1338 .adis_data = ADIS16475_DATA(16575, &adis16475_timeouts, 1339 ADIS16575_BURST32_DATA_TS32, 1340 ADIS16575_BURST_MAX_SPEED, true), 1341 }, 1342 [ADIS16575_3] = { 1343 .name = "adis16575-3", 1344 .num_channels = ARRAY_SIZE(adis16575_channels), 1345 .channels = adis16575_channels, 1346 .gyro_max_val = 1, 1347 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1348 .accel_max_val = 8, 1349 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1350 .temp_scale = 100, 1351 .deltang_max_val = IIO_DEGREE_TO_RAD(2000), 1352 .deltvel_max_val = 100, 1353 .int_clk = 4000, 1354 .max_dec = 3999, 1355 .sync = adis16575_sync_mode, 1356 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1357 .flags = ADIS16475_HAS_BURST32 | 1358 ADIS16475_HAS_BURST_DELTA_DATA | 1359 ADIS16475_NEEDS_BURST_REQUEST | 1360 ADIS16475_HAS_TIMESTAMP32, 1361 .adis_data = ADIS16475_DATA(16575, &adis16475_timeouts, 1362 ADIS16575_BURST32_DATA_TS32, 1363 ADIS16575_BURST_MAX_SPEED, true), 1364 }, 1365 [ADIS16576_2] = { 1366 .name = "adis16576-2", 1367 .num_channels = ARRAY_SIZE(adis16575_channels), 1368 .channels = adis16575_channels, 1369 .gyro_max_val = 1, 1370 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1371 .accel_max_val = 40, 1372 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1373 .temp_scale = 100, 1374 .deltang_max_val = IIO_DEGREE_TO_RAD(450), 1375 .deltvel_max_val = 125, 1376 .int_clk = 4000, 1377 .max_dec = 3999, 1378 .sync = adis16575_sync_mode, 1379 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1380 .flags = ADIS16475_HAS_BURST32 | 1381 ADIS16475_HAS_BURST_DELTA_DATA | 1382 ADIS16475_NEEDS_BURST_REQUEST | 1383 ADIS16475_HAS_TIMESTAMP32, 1384 .adis_data = ADIS16475_DATA(16576, &adis16475_timeouts, 1385 ADIS16575_BURST32_DATA_TS32, 1386 ADIS16575_BURST_MAX_SPEED, true), 1387 }, 1388 [ADIS16576_3] = { 1389 .name = "adis16576-3", 1390 .num_channels = ARRAY_SIZE(adis16575_channels), 1391 .channels = adis16575_channels, 1392 .gyro_max_val = 1, 1393 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1394 .accel_max_val = 40, 1395 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1396 .temp_scale = 100, 1397 .deltang_max_val = IIO_DEGREE_TO_RAD(2000), 1398 .deltvel_max_val = 125, 1399 .int_clk = 4000, 1400 .max_dec = 3999, 1401 .sync = adis16575_sync_mode, 1402 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1403 .flags = ADIS16475_HAS_BURST32 | 1404 ADIS16475_HAS_BURST_DELTA_DATA | 1405 ADIS16475_NEEDS_BURST_REQUEST | 1406 ADIS16475_HAS_TIMESTAMP32, 1407 .adis_data = ADIS16475_DATA(16576, &adis16475_timeouts, 1408 ADIS16575_BURST32_DATA_TS32, 1409 ADIS16575_BURST_MAX_SPEED, true), 1410 }, 1411 [ADIS16577_2] = { 1412 .name = "adis16577-2", 1413 .num_channels = ARRAY_SIZE(adis16575_channels), 1414 .channels = adis16575_channels, 1415 .gyro_max_val = 1, 1416 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1417 .accel_max_val = 40, 1418 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1419 .temp_scale = 100, 1420 .deltang_max_val = IIO_DEGREE_TO_RAD(450), 1421 .deltvel_max_val = 400, 1422 .int_clk = 4000, 1423 .max_dec = 3999, 1424 .sync = adis16575_sync_mode, 1425 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1426 .flags = ADIS16475_HAS_BURST32 | 1427 ADIS16475_HAS_BURST_DELTA_DATA | 1428 ADIS16475_NEEDS_BURST_REQUEST | 1429 ADIS16475_HAS_TIMESTAMP32, 1430 .adis_data = ADIS16475_DATA(16577, &adis16475_timeouts, 1431 ADIS16575_BURST32_DATA_TS32, 1432 ADIS16575_BURST_MAX_SPEED, true), 1433 }, 1434 [ADIS16577_3] = { 1435 .name = "adis16577-3", 1436 .num_channels = ARRAY_SIZE(adis16575_channels), 1437 .channels = adis16575_channels, 1438 .gyro_max_val = 1, 1439 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1440 .accel_max_val = 40, 1441 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1442 .temp_scale = 100, 1443 .deltang_max_val = IIO_DEGREE_TO_RAD(2000), 1444 .deltvel_max_val = 400, 1445 .int_clk = 4000, 1446 .max_dec = 3999, 1447 .sync = adis16575_sync_mode, 1448 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1449 .flags = ADIS16475_HAS_BURST32 | 1450 ADIS16475_HAS_BURST_DELTA_DATA | 1451 ADIS16475_NEEDS_BURST_REQUEST | 1452 ADIS16475_HAS_TIMESTAMP32, 1453 .adis_data = ADIS16475_DATA(16577, &adis16475_timeouts, 1454 ADIS16575_BURST32_DATA_TS32, 1455 ADIS16575_BURST_MAX_SPEED, true), 1456 }, 1457 }; 1458 1459 static int adis16475_update_scan_mode(struct iio_dev *indio_dev, 1460 const unsigned long *scan_mask) 1461 { 1462 u16 en; 1463 int ret; 1464 struct adis16475 *st = iio_priv(indio_dev); 1465 1466 if (st->info->flags & ADIS16475_HAS_BURST_DELTA_DATA) { 1467 if ((*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK) && 1468 (*scan_mask & ADIS16500_BURST_DATA_SEL_1_CHN_MASK)) 1469 return -EINVAL; 1470 if (*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK) 1471 en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 0); 1472 else 1473 en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 1); 1474 1475 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1476 ADIS16500_BURST_DATA_SEL_MASK, en); 1477 if (ret) 1478 return ret; 1479 } 1480 1481 return adis_update_scan_mode(indio_dev, scan_mask); 1482 } 1483 1484 static const struct iio_info adis16475_info = { 1485 .read_raw = &adis16475_read_raw, 1486 .write_raw = &adis16475_write_raw, 1487 .update_scan_mode = adis16475_update_scan_mode, 1488 .debugfs_reg_access = adis_debugfs_reg_access, 1489 }; 1490 1491 static const struct iio_info adis16575_info = { 1492 .read_raw = &adis16475_read_raw, 1493 .write_raw = &adis16475_write_raw, 1494 .update_scan_mode = adis16475_update_scan_mode, 1495 .debugfs_reg_access = adis_debugfs_reg_access, 1496 .hwfifo_set_watermark = adis16475_set_watermark, 1497 }; 1498 1499 static bool adis16475_validate_crc(const u8 *buffer, u16 crc, 1500 u16 burst_size, u16 start_idx) 1501 { 1502 int i; 1503 1504 for (i = start_idx; i < burst_size - 2; i++) 1505 crc -= buffer[i]; 1506 1507 return crc == 0; 1508 } 1509 1510 static void adis16475_burst32_check(struct adis16475 *st) 1511 { 1512 int ret; 1513 struct adis *adis = &st->adis; 1514 u8 timestamp32 = 0; 1515 1516 if (!(st->info->flags & ADIS16475_HAS_BURST32)) 1517 return; 1518 1519 if (st->info->flags & ADIS16475_HAS_TIMESTAMP32) 1520 timestamp32 = 1; 1521 1522 if (st->lsb_flag && !st->burst32) { 1523 const u16 en = ADIS16500_BURST32(1); 1524 1525 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1526 ADIS16500_BURST32_MASK, en); 1527 if (ret) 1528 return; 1529 1530 st->burst32 = true; 1531 1532 /* 1533 * In 32-bit mode we need extra 2 bytes for all gyro 1534 * and accel channels. 1535 * If the device has 32-bit timestamp value we need 2 extra 1536 * bytes for it. 1537 */ 1538 adis->burst_extra_len = (6 + timestamp32) * sizeof(u16); 1539 adis->xfer[1].len += (6 + timestamp32) * sizeof(u16); 1540 1541 dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d", 1542 adis->xfer[1].len); 1543 1544 } else if (!st->lsb_flag && st->burst32) { 1545 const u16 en = ADIS16500_BURST32(0); 1546 1547 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1548 ADIS16500_BURST32_MASK, en); 1549 if (ret) 1550 return; 1551 1552 st->burst32 = false; 1553 1554 /* Remove the extra bits */ 1555 adis->burst_extra_len = 0; 1556 adis->xfer[1].len -= (6 + timestamp32) * sizeof(u16); 1557 dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n", 1558 adis->xfer[1].len); 1559 } 1560 } 1561 1562 static int adis16475_push_single_sample(struct iio_poll_func *pf) 1563 { 1564 struct iio_dev *indio_dev = pf->indio_dev; 1565 struct adis16475 *st = iio_priv(indio_dev); 1566 struct adis *adis = &st->adis; 1567 int ret, bit, buff_offset = 0, i = 0; 1568 __be16 *buffer; 1569 u16 crc; 1570 bool valid; 1571 u8 crc_offset = 9; 1572 u16 burst_size = ADIS16475_BURST_MAX_DATA; 1573 u16 start_idx = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 2 : 0; 1574 1575 /* offset until the first element after gyro and accel */ 1576 const u8 offset = st->burst32 ? 13 : 7; 1577 1578 if (st->burst32) { 1579 crc_offset = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 16 : 15; 1580 burst_size = adis->data->burst_max_len; 1581 } 1582 1583 ret = spi_sync(adis->spi, &adis->msg); 1584 if (ret) 1585 return ret; 1586 1587 buffer = adis->buffer; 1588 1589 crc = be16_to_cpu(buffer[crc_offset]); 1590 valid = adis16475_validate_crc(adis->buffer, crc, burst_size, start_idx); 1591 if (!valid) { 1592 dev_err(&adis->spi->dev, "Invalid crc\n"); 1593 return -EINVAL; 1594 } 1595 1596 for_each_set_bit(bit, indio_dev->active_scan_mask, 1597 indio_dev->masklength) { 1598 /* 1599 * When burst mode is used, system flags is the first data 1600 * channel in the sequence, but the scan index is 7. 1601 */ 1602 switch (bit) { 1603 case ADIS16475_SCAN_TEMP: 1604 st->data[i++] = buffer[offset]; 1605 /* 1606 * The temperature channel has 16-bit storage size. 1607 * We need to perform the padding to have the buffer 1608 * elements naturally aligned in case there are any 1609 * 32-bit storage size channels enabled which have a 1610 * scan index higher than the temperature channel scan 1611 * index. 1612 */ 1613 if (*indio_dev->active_scan_mask & GENMASK(ADIS16475_SCAN_DELTVEL_Z, ADIS16475_SCAN_DELTANG_X)) 1614 st->data[i++] = 0; 1615 break; 1616 case ADIS16475_SCAN_DELTANG_X ... ADIS16475_SCAN_DELTVEL_Z: 1617 buff_offset = ADIS16475_SCAN_DELTANG_X; 1618 fallthrough; 1619 case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z: 1620 /* 1621 * The first 2 bytes on the received data are the 1622 * DIAG_STAT reg, hence the +1 offset here... 1623 */ 1624 if (st->burst32) { 1625 /* upper 16 */ 1626 st->data[i++] = buffer[(bit - buff_offset) * 2 + 2]; 1627 /* lower 16 */ 1628 st->data[i++] = buffer[(bit - buff_offset) * 2 + 1]; 1629 } else { 1630 st->data[i++] = buffer[(bit - buff_offset) + 1]; 1631 /* 1632 * Don't bother in doing the manual read if the 1633 * device supports burst32. burst32 will be 1634 * enabled in the next call to 1635 * adis16475_burst32_check()... 1636 */ 1637 if (st->lsb_flag && !(st->info->flags & ADIS16475_HAS_BURST32)) { 1638 u16 val = 0; 1639 const u32 reg = ADIS16475_REG_X_GYRO_L + 1640 bit * 4; 1641 1642 adis_read_reg_16(adis, reg, &val); 1643 st->data[i++] = cpu_to_be16(val); 1644 } else { 1645 /* lower not used */ 1646 st->data[i++] = 0; 1647 } 1648 } 1649 break; 1650 } 1651 } 1652 1653 /* There might not be a timestamp option for some devices. */ 1654 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); 1655 1656 return 0; 1657 } 1658 1659 static irqreturn_t adis16475_trigger_handler(int irq, void *p) 1660 { 1661 struct iio_poll_func *pf = p; 1662 struct iio_dev *indio_dev = pf->indio_dev; 1663 struct adis16475 *st = iio_priv(indio_dev); 1664 1665 adis16475_push_single_sample(pf); 1666 /* 1667 * We only check the burst mode at the end of the current capture since 1668 * it takes a full data ready cycle for the device to update the burst 1669 * array. 1670 */ 1671 adis16475_burst32_check(st); 1672 1673 iio_trigger_notify_done(indio_dev->trig); 1674 1675 return IRQ_HANDLED; 1676 } 1677 1678 /* 1679 * This function updates the first tx byte from the adis message based on the 1680 * given burst request. 1681 */ 1682 static void adis16575_update_msg_for_burst(struct adis *adis, u8 burst_req) 1683 { 1684 unsigned int burst_max_length; 1685 u8 *tx; 1686 1687 if (adis->data->burst_max_len) 1688 burst_max_length = adis->data->burst_max_len; 1689 else 1690 burst_max_length = adis->data->burst_len + adis->burst_extra_len; 1691 1692 tx = adis->buffer + burst_max_length; 1693 tx[0] = ADIS_READ_REG(burst_req); 1694 } 1695 1696 static int adis16575_custom_burst_read(struct iio_poll_func *pf, u8 burst_req) 1697 { 1698 struct iio_dev *indio_dev = pf->indio_dev; 1699 struct adis16475 *st = iio_priv(indio_dev); 1700 struct adis *adis = &st->adis; 1701 1702 adis16575_update_msg_for_burst(adis, burst_req); 1703 1704 if (burst_req) 1705 return spi_sync(adis->spi, &adis->msg); 1706 1707 return adis16475_push_single_sample(pf); 1708 } 1709 1710 /* 1711 * This handler is meant to be used for devices which support burst readings 1712 * from FIFO (namely devices from adis1657x family). 1713 * In order to pop the FIFO the 0x68 0x00 FIFO pop burst request has to be sent. 1714 * If the previous device command was not a FIFO pop burst request, the FIFO pop 1715 * burst request will simply pop the FIFO without returning valid data. 1716 * For the nth consecutive burst request, thedevice will send the data popped 1717 * with the (n-1)th consecutive burst request. 1718 * In order to read the data which was popped previously, without popping the 1719 * FIFO, the 0x00 0x00 burst request has to be sent. 1720 * If after a 0x68 0x00 FIFO pop burst request, there is any other device access 1721 * different from a 0x68 0x00 or a 0x00 0x00 burst request, the FIFO data popped 1722 * previously will be lost. 1723 */ 1724 static irqreturn_t adis16475_trigger_handler_with_fifo(int irq, void *p) 1725 { 1726 struct iio_poll_func *pf = p; 1727 struct iio_dev *indio_dev = pf->indio_dev; 1728 struct adis16475 *st = iio_priv(indio_dev); 1729 struct adis *adis = &st->adis; 1730 int ret; 1731 u16 fifo_cnt, i; 1732 1733 adis_dev_auto_lock(&st->adis); 1734 1735 ret = __adis_read_reg_16(adis, ADIS16575_REG_FIFO_CNT, &fifo_cnt); 1736 if (ret) 1737 goto unlock; 1738 1739 /* 1740 * If no sample is available, nothing can be read. This can happen if 1741 * a the used trigger has a higher frequency than the selected sample rate. 1742 */ 1743 if (!fifo_cnt) 1744 goto unlock; 1745 1746 /* 1747 * First burst request - FIFO pop: popped data will be returned in the 1748 * next burst request. 1749 */ 1750 ret = adis16575_custom_burst_read(pf, adis->data->burst_reg_cmd); 1751 if (ret) 1752 goto unlock; 1753 1754 for (i = 0; i < fifo_cnt - 1; i++) { 1755 ret = adis16475_push_single_sample(pf); 1756 if (ret) 1757 goto unlock; 1758 } 1759 1760 /* FIFO read without popping */ 1761 ret = adis16575_custom_burst_read(pf, 0); 1762 1763 unlock: 1764 /* 1765 * We only check the burst mode at the end of the current capture since 1766 * reading data from registers will impact the FIFO reading. 1767 */ 1768 adis16475_burst32_check(st); 1769 iio_trigger_notify_done(indio_dev->trig); 1770 1771 return IRQ_HANDLED; 1772 } 1773 1774 static int adis16475_config_sync_mode(struct adis16475 *st) 1775 { 1776 int ret; 1777 struct device *dev = &st->adis.spi->dev; 1778 const struct adis16475_sync *sync; 1779 u32 sync_mode; 1780 u16 max_sample_rate = st->info->int_clk + 100; 1781 u16 val; 1782 1783 /* if available, enable 4khz internal clock */ 1784 if (st->info->int_clk == 4000) { 1785 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1786 ADIS16575_SYNC_4KHZ_MASK, 1787 (u16)ADIS16575_SYNC_4KHZ(1)); 1788 if (ret) 1789 return ret; 1790 } 1791 1792 /* default to internal clk */ 1793 st->clk_freq = st->info->int_clk * 1000; 1794 1795 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode); 1796 if (ret) 1797 return 0; 1798 1799 if (sync_mode >= st->info->num_sync) { 1800 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode, 1801 st->info->name); 1802 return -EINVAL; 1803 } 1804 1805 sync = &st->info->sync[sync_mode]; 1806 st->sync_mode = sync->sync_mode; 1807 1808 /* All the other modes require external input signal */ 1809 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) { 1810 struct clk *clk = devm_clk_get_enabled(dev, NULL); 1811 1812 if (IS_ERR(clk)) 1813 return PTR_ERR(clk); 1814 1815 st->clk_freq = clk_get_rate(clk); 1816 if (st->clk_freq < sync->min_rate || 1817 st->clk_freq > sync->max_rate) { 1818 dev_err(dev, 1819 "Clk rate:%u not in a valid range:[%u %u]\n", 1820 st->clk_freq, sync->min_rate, sync->max_rate); 1821 return -EINVAL; 1822 } 1823 1824 if (sync->sync_mode == ADIS16475_SYNC_SCALED) { 1825 u16 up_scale; 1826 1827 /* 1828 * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale. 1829 * Hence, default the IMU sample rate to the highest multiple of the input 1830 * clock lower than the IMU max sample rate. 1831 */ 1832 up_scale = max_sample_rate / st->clk_freq; 1833 1834 ret = __adis_write_reg_16(&st->adis, 1835 ADIS16475_REG_UP_SCALE, 1836 up_scale); 1837 if (ret) 1838 return ret; 1839 } 1840 1841 st->clk_freq *= 1000; 1842 } 1843 /* 1844 * Keep in mind that the mask for the clk modes in adis1650* 1845 * chips is different (1100 instead of 11100). However, we 1846 * are not configuring BIT(4) in these chips and the default 1847 * value is 0, so we are fine in doing the below operations. 1848 * I'm keeping this for simplicity and avoiding extra variables 1849 * in chip_info. 1850 */ 1851 val = ADIS16475_SYNC_MODE(sync->sync_mode); 1852 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1853 ADIS16475_SYNC_MODE_MASK, val); 1854 if (ret) 1855 return ret; 1856 1857 usleep_range(250, 260); 1858 1859 return 0; 1860 } 1861 1862 static int adis16475_config_irq_pin(struct adis16475 *st) 1863 { 1864 int ret; 1865 u32 irq_type; 1866 u16 val = 0; 1867 u8 polarity; 1868 struct spi_device *spi = st->adis.spi; 1869 1870 irq_type = irq_get_trigger_type(spi->irq); 1871 1872 if (st->adis.data->has_fifo) { 1873 /* 1874 * It is possible to configure the fifo watermark pin polarity. 1875 * Furthermore, we need to update the adis struct if we want the 1876 * watermark pin active low. 1877 */ 1878 if (irq_type == IRQ_TYPE_LEVEL_HIGH) { 1879 polarity = 1; 1880 st->adis.irq_flag = IRQF_TRIGGER_HIGH; 1881 } else if (irq_type == IRQ_TYPE_LEVEL_LOW) { 1882 polarity = 0; 1883 st->adis.irq_flag = IRQF_TRIGGER_LOW; 1884 } else { 1885 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", 1886 irq_type); 1887 return -EINVAL; 1888 } 1889 1890 /* Configure the watermark pin polarity. */ 1891 val = ADIS16575_WM_POL(polarity); 1892 ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, 1893 ADIS16575_WM_POL_MASK, val); 1894 if (ret) 1895 return ret; 1896 1897 /* Enable watermark interrupt pin. */ 1898 ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, 1899 ADIS16575_WM_EN_MASK, 1900 (u16)ADIS16575_WM_EN(1)); 1901 if (ret) 1902 return ret; 1903 1904 } else { 1905 /* 1906 * It is possible to configure the data ready polarity. Furthermore, we 1907 * need to update the adis struct if we want data ready as active low. 1908 */ 1909 if (irq_type == IRQ_TYPE_EDGE_RISING) { 1910 polarity = 1; 1911 st->adis.irq_flag = IRQF_TRIGGER_RISING; 1912 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1913 polarity = 0; 1914 st->adis.irq_flag = IRQF_TRIGGER_FALLING; 1915 } else { 1916 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", 1917 irq_type); 1918 return -EINVAL; 1919 } 1920 1921 val = ADIS16475_MSG_CTRL_DR_POL(polarity); 1922 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1923 ADIS16475_MSG_CTRL_DR_POL_MASK, val); 1924 if (ret) 1925 return ret; 1926 /* 1927 * There is a delay writing to any bits written to the MSC_CTRL 1928 * register. It should not be bigger than 200us, so 250 should be more 1929 * than enough! 1930 */ 1931 usleep_range(250, 260); 1932 } 1933 1934 return 0; 1935 } 1936 1937 1938 static int adis16475_probe(struct spi_device *spi) 1939 { 1940 struct iio_dev *indio_dev; 1941 struct adis16475 *st; 1942 int ret; 1943 u16 val; 1944 1945 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1946 if (!indio_dev) 1947 return -ENOMEM; 1948 1949 st = iio_priv(indio_dev); 1950 1951 st->info = spi_get_device_match_data(spi); 1952 if (!st->info) 1953 return -EINVAL; 1954 1955 ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data); 1956 if (ret) 1957 return ret; 1958 1959 indio_dev->name = st->info->name; 1960 indio_dev->channels = st->info->channels; 1961 indio_dev->num_channels = st->info->num_channels; 1962 if (st->adis.data->has_fifo) 1963 indio_dev->info = &adis16575_info; 1964 else 1965 indio_dev->info = &adis16475_info; 1966 indio_dev->modes = INDIO_DIRECT_MODE; 1967 1968 ret = __adis_initial_startup(&st->adis); 1969 if (ret) 1970 return ret; 1971 1972 ret = adis16475_config_irq_pin(st); 1973 if (ret) 1974 return ret; 1975 1976 ret = adis16475_config_sync_mode(st); 1977 if (ret) 1978 return ret; 1979 1980 if (st->adis.data->has_fifo) { 1981 ret = devm_adis_setup_buffer_and_trigger_with_attrs(&st->adis, indio_dev, 1982 adis16475_trigger_handler_with_fifo, 1983 &adis16475_buffer_ops, 1984 adis16475_fifo_attributes); 1985 if (ret) 1986 return ret; 1987 1988 /* Update overflow behavior to always overwrite the oldest sample. */ 1989 val = ADIS16575_OVERWRITE_OLDEST; 1990 ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, 1991 ADIS16575_OVERFLOW_MASK, val); 1992 if (ret) 1993 return ret; 1994 } else { 1995 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, 1996 adis16475_trigger_handler); 1997 if (ret) 1998 return ret; 1999 } 2000 2001 ret = devm_iio_device_register(&spi->dev, indio_dev); 2002 if (ret) 2003 return ret; 2004 2005 adis16475_debugfs_init(indio_dev); 2006 2007 return 0; 2008 } 2009 2010 static const struct of_device_id adis16475_of_match[] = { 2011 { .compatible = "adi,adis16470", 2012 .data = &adis16475_chip_info[ADIS16470] }, 2013 { .compatible = "adi,adis16475-1", 2014 .data = &adis16475_chip_info[ADIS16475_1] }, 2015 { .compatible = "adi,adis16475-2", 2016 .data = &adis16475_chip_info[ADIS16475_2] }, 2017 { .compatible = "adi,adis16475-3", 2018 .data = &adis16475_chip_info[ADIS16475_3] }, 2019 { .compatible = "adi,adis16477-1", 2020 .data = &adis16475_chip_info[ADIS16477_1] }, 2021 { .compatible = "adi,adis16477-2", 2022 .data = &adis16475_chip_info[ADIS16477_2] }, 2023 { .compatible = "adi,adis16477-3", 2024 .data = &adis16475_chip_info[ADIS16477_3] }, 2025 { .compatible = "adi,adis16465-1", 2026 .data = &adis16475_chip_info[ADIS16465_1] }, 2027 { .compatible = "adi,adis16465-2", 2028 .data = &adis16475_chip_info[ADIS16465_2] }, 2029 { .compatible = "adi,adis16465-3", 2030 .data = &adis16475_chip_info[ADIS16465_3] }, 2031 { .compatible = "adi,adis16467-1", 2032 .data = &adis16475_chip_info[ADIS16467_1] }, 2033 { .compatible = "adi,adis16467-2", 2034 .data = &adis16475_chip_info[ADIS16467_2] }, 2035 { .compatible = "adi,adis16467-3", 2036 .data = &adis16475_chip_info[ADIS16467_3] }, 2037 { .compatible = "adi,adis16500", 2038 .data = &adis16475_chip_info[ADIS16500] }, 2039 { .compatible = "adi,adis16501", 2040 .data = &adis16475_chip_info[ADIS16501] }, 2041 { .compatible = "adi,adis16505-1", 2042 .data = &adis16475_chip_info[ADIS16505_1] }, 2043 { .compatible = "adi,adis16505-2", 2044 .data = &adis16475_chip_info[ADIS16505_2] }, 2045 { .compatible = "adi,adis16505-3", 2046 .data = &adis16475_chip_info[ADIS16505_3] }, 2047 { .compatible = "adi,adis16507-1", 2048 .data = &adis16475_chip_info[ADIS16507_1] }, 2049 { .compatible = "adi,adis16507-2", 2050 .data = &adis16475_chip_info[ADIS16507_2] }, 2051 { .compatible = "adi,adis16507-3", 2052 .data = &adis16475_chip_info[ADIS16507_3] }, 2053 { .compatible = "adi,adis16575-2", 2054 .data = &adis16475_chip_info[ADIS16575_2] }, 2055 { .compatible = "adi,adis16575-3", 2056 .data = &adis16475_chip_info[ADIS16575_3] }, 2057 { .compatible = "adi,adis16576-2", 2058 .data = &adis16475_chip_info[ADIS16576_2] }, 2059 { .compatible = "adi,adis16576-3", 2060 .data = &adis16475_chip_info[ADIS16576_3] }, 2061 { .compatible = "adi,adis16577-2", 2062 .data = &adis16475_chip_info[ADIS16577_2] }, 2063 { .compatible = "adi,adis16577-3", 2064 .data = &adis16475_chip_info[ADIS16577_3] }, 2065 { }, 2066 }; 2067 MODULE_DEVICE_TABLE(of, adis16475_of_match); 2068 2069 static const struct spi_device_id adis16475_ids[] = { 2070 { "adis16470", (kernel_ulong_t)&adis16475_chip_info[ADIS16470] }, 2071 { "adis16475-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16475_1] }, 2072 { "adis16475-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16475_2] }, 2073 { "adis16475-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16475_3] }, 2074 { "adis16477-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16477_1] }, 2075 { "adis16477-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16477_2] }, 2076 { "adis16477-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16477_3] }, 2077 { "adis16465-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16465_1] }, 2078 { "adis16465-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16465_2] }, 2079 { "adis16465-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16465_3] }, 2080 { "adis16467-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16467_1] }, 2081 { "adis16467-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16467_2] }, 2082 { "adis16467-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16467_3] }, 2083 { "adis16500", (kernel_ulong_t)&adis16475_chip_info[ADIS16500] }, 2084 { "adis16501", (kernel_ulong_t)&adis16475_chip_info[ADIS16501] }, 2085 { "adis16505-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16505_1] }, 2086 { "adis16505-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16505_2] }, 2087 { "adis16505-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16505_3] }, 2088 { "adis16507-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_1] }, 2089 { "adis16507-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_2] }, 2090 { "adis16507-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_3] }, 2091 { "adis16575-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16575_2] }, 2092 { "adis16575-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16575_3] }, 2093 { "adis16576-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16576_2] }, 2094 { "adis16576-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16576_3] }, 2095 { "adis16577-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16577_2] }, 2096 { "adis16577-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16577_3] }, 2097 { } 2098 }; 2099 MODULE_DEVICE_TABLE(spi, adis16475_ids); 2100 2101 static struct spi_driver adis16475_driver = { 2102 .driver = { 2103 .name = "adis16475", 2104 .of_match_table = adis16475_of_match, 2105 }, 2106 .probe = adis16475_probe, 2107 .id_table = adis16475_ids, 2108 }; 2109 module_spi_driver(adis16475_driver); 2110 2111 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 2112 MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver"); 2113 MODULE_LICENSE("GPL"); 2114 MODULE_IMPORT_NS(IIO_ADISLIB); 2115