1d6ad8058SMatt Ranostay // SPDX-License-Identifier: GPL-2.0+
24d33615dSMatt Ranostay /*
34d33615dSMatt Ranostay * max30100.c - Support for MAX30100 heart rate and pulse oximeter sensor
44d33615dSMatt Ranostay *
5d6ad8058SMatt Ranostay * Copyright (C) 2015, 2018
6d6ad8058SMatt Ranostay * Author: Matt Ranostay <matt.ranostay@konsulko.com>
74d33615dSMatt Ranostay *
8b11a3460SMatt Ranostay * TODO: enable pulse length controls via device tree properties
94d33615dSMatt Ranostay */
104d33615dSMatt Ranostay
114d33615dSMatt Ranostay #include <linux/module.h>
124d33615dSMatt Ranostay #include <linux/init.h>
134d33615dSMatt Ranostay #include <linux/interrupt.h>
144d33615dSMatt Ranostay #include <linux/delay.h>
154d33615dSMatt Ranostay #include <linux/err.h>
164d33615dSMatt Ranostay #include <linux/irq.h>
174d33615dSMatt Ranostay #include <linux/i2c.h>
184d33615dSMatt Ranostay #include <linux/mutex.h>
19bb8759f2SRohit Sarkar #include <linux/property.h>
204d33615dSMatt Ranostay #include <linux/regmap.h>
214d33615dSMatt Ranostay #include <linux/iio/iio.h>
224d33615dSMatt Ranostay #include <linux/iio/buffer.h>
234d33615dSMatt Ranostay #include <linux/iio/kfifo_buf.h>
244d33615dSMatt Ranostay
254d33615dSMatt Ranostay #define MAX30100_REGMAP_NAME "max30100_regmap"
264d33615dSMatt Ranostay #define MAX30100_DRV_NAME "max30100"
274d33615dSMatt Ranostay
284d33615dSMatt Ranostay #define MAX30100_REG_INT_STATUS 0x00
294d33615dSMatt Ranostay #define MAX30100_REG_INT_STATUS_PWR_RDY BIT(0)
304d33615dSMatt Ranostay #define MAX30100_REG_INT_STATUS_SPO2_RDY BIT(4)
314d33615dSMatt Ranostay #define MAX30100_REG_INT_STATUS_HR_RDY BIT(5)
324d33615dSMatt Ranostay #define MAX30100_REG_INT_STATUS_FIFO_RDY BIT(7)
334d33615dSMatt Ranostay
344d33615dSMatt Ranostay #define MAX30100_REG_INT_ENABLE 0x01
354d33615dSMatt Ranostay #define MAX30100_REG_INT_ENABLE_SPO2_EN BIT(0)
364d33615dSMatt Ranostay #define MAX30100_REG_INT_ENABLE_HR_EN BIT(1)
374d33615dSMatt Ranostay #define MAX30100_REG_INT_ENABLE_FIFO_EN BIT(3)
384d33615dSMatt Ranostay #define MAX30100_REG_INT_ENABLE_MASK 0xf0
394d33615dSMatt Ranostay #define MAX30100_REG_INT_ENABLE_MASK_SHIFT 4
404d33615dSMatt Ranostay
414d33615dSMatt Ranostay #define MAX30100_REG_FIFO_WR_PTR 0x02
424d33615dSMatt Ranostay #define MAX30100_REG_FIFO_OVR_CTR 0x03
434d33615dSMatt Ranostay #define MAX30100_REG_FIFO_RD_PTR 0x04
444d33615dSMatt Ranostay #define MAX30100_REG_FIFO_DATA 0x05
454d33615dSMatt Ranostay #define MAX30100_REG_FIFO_DATA_ENTRY_COUNT 16
464d33615dSMatt Ranostay #define MAX30100_REG_FIFO_DATA_ENTRY_LEN 4
474d33615dSMatt Ranostay
484d33615dSMatt Ranostay #define MAX30100_REG_MODE_CONFIG 0x06
494d33615dSMatt Ranostay #define MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN BIT(0)
504d33615dSMatt Ranostay #define MAX30100_REG_MODE_CONFIG_MODE_HR_EN BIT(1)
514d33615dSMatt Ranostay #define MAX30100_REG_MODE_CONFIG_MODE_MASK 0x03
524d33615dSMatt Ranostay #define MAX30100_REG_MODE_CONFIG_TEMP_EN BIT(3)
534d33615dSMatt Ranostay #define MAX30100_REG_MODE_CONFIG_PWR BIT(7)
544d33615dSMatt Ranostay
554d33615dSMatt Ranostay #define MAX30100_REG_SPO2_CONFIG 0x07
564d33615dSMatt Ranostay #define MAX30100_REG_SPO2_CONFIG_100HZ BIT(2)
574d33615dSMatt Ranostay #define MAX30100_REG_SPO2_CONFIG_HI_RES_EN BIT(6)
584d33615dSMatt Ranostay #define MAX30100_REG_SPO2_CONFIG_1600US 0x3
594d33615dSMatt Ranostay
604d33615dSMatt Ranostay #define MAX30100_REG_LED_CONFIG 0x09
61b11a3460SMatt Ranostay #define MAX30100_REG_LED_CONFIG_LED_MASK 0x0f
624d33615dSMatt Ranostay #define MAX30100_REG_LED_CONFIG_RED_LED_SHIFT 4
634d33615dSMatt Ranostay
644d33615dSMatt Ranostay #define MAX30100_REG_LED_CONFIG_24MA 0x07
654d33615dSMatt Ranostay #define MAX30100_REG_LED_CONFIG_50MA 0x0f
664d33615dSMatt Ranostay
674d33615dSMatt Ranostay #define MAX30100_REG_TEMP_INTEGER 0x16
684d33615dSMatt Ranostay #define MAX30100_REG_TEMP_FRACTION 0x17
694d33615dSMatt Ranostay
704d33615dSMatt Ranostay struct max30100_data {
714d33615dSMatt Ranostay struct i2c_client *client;
724d33615dSMatt Ranostay struct iio_dev *indio_dev;
734d33615dSMatt Ranostay struct mutex lock;
744d33615dSMatt Ranostay struct regmap *regmap;
754d33615dSMatt Ranostay
764d33615dSMatt Ranostay __be16 buffer[2]; /* 2 16-bit channels */
774d33615dSMatt Ranostay };
784d33615dSMatt Ranostay
max30100_is_volatile_reg(struct device * dev,unsigned int reg)794d33615dSMatt Ranostay static bool max30100_is_volatile_reg(struct device *dev, unsigned int reg)
804d33615dSMatt Ranostay {
814d33615dSMatt Ranostay switch (reg) {
824d33615dSMatt Ranostay case MAX30100_REG_INT_STATUS:
834d33615dSMatt Ranostay case MAX30100_REG_MODE_CONFIG:
844d33615dSMatt Ranostay case MAX30100_REG_FIFO_WR_PTR:
854d33615dSMatt Ranostay case MAX30100_REG_FIFO_OVR_CTR:
864d33615dSMatt Ranostay case MAX30100_REG_FIFO_RD_PTR:
874d33615dSMatt Ranostay case MAX30100_REG_FIFO_DATA:
884d33615dSMatt Ranostay case MAX30100_REG_TEMP_INTEGER:
894d33615dSMatt Ranostay case MAX30100_REG_TEMP_FRACTION:
904d33615dSMatt Ranostay return true;
914d33615dSMatt Ranostay default:
924d33615dSMatt Ranostay return false;
934d33615dSMatt Ranostay }
944d33615dSMatt Ranostay }
954d33615dSMatt Ranostay
964d33615dSMatt Ranostay static const struct regmap_config max30100_regmap_config = {
974d33615dSMatt Ranostay .name = MAX30100_REGMAP_NAME,
984d33615dSMatt Ranostay
994d33615dSMatt Ranostay .reg_bits = 8,
1004d33615dSMatt Ranostay .val_bits = 8,
1014d33615dSMatt Ranostay
1024d33615dSMatt Ranostay .max_register = MAX30100_REG_TEMP_FRACTION,
1034d33615dSMatt Ranostay .cache_type = REGCACHE_FLAT,
1044d33615dSMatt Ranostay
1054d33615dSMatt Ranostay .volatile_reg = max30100_is_volatile_reg,
1064d33615dSMatt Ranostay };
1074d33615dSMatt Ranostay
108b11a3460SMatt Ranostay static const unsigned int max30100_led_current_mapping[] = {
109b11a3460SMatt Ranostay 4400, 7600, 11000, 14200, 17400,
110b11a3460SMatt Ranostay 20800, 24000, 27100, 30600, 33800,
111b11a3460SMatt Ranostay 37000, 40200, 43600, 46800, 50000
112b11a3460SMatt Ranostay };
113b11a3460SMatt Ranostay
1144d33615dSMatt Ranostay static const unsigned long max30100_scan_masks[] = {0x3, 0};
1154d33615dSMatt Ranostay
1164d33615dSMatt Ranostay static const struct iio_chan_spec max30100_channels[] = {
1174d33615dSMatt Ranostay {
1184d33615dSMatt Ranostay .type = IIO_INTENSITY,
1194d33615dSMatt Ranostay .channel2 = IIO_MOD_LIGHT_IR,
1204d33615dSMatt Ranostay .modified = 1,
1214d33615dSMatt Ranostay
1224d33615dSMatt Ranostay .scan_index = 0,
1234d33615dSMatt Ranostay .scan_type = {
1244d33615dSMatt Ranostay .sign = 'u',
1254d33615dSMatt Ranostay .realbits = 16,
1264d33615dSMatt Ranostay .storagebits = 16,
1274d33615dSMatt Ranostay .endianness = IIO_BE,
1284d33615dSMatt Ranostay },
1294d33615dSMatt Ranostay },
1304d33615dSMatt Ranostay {
1314d33615dSMatt Ranostay .type = IIO_INTENSITY,
1324d33615dSMatt Ranostay .channel2 = IIO_MOD_LIGHT_RED,
1334d33615dSMatt Ranostay .modified = 1,
1344d33615dSMatt Ranostay
1354d33615dSMatt Ranostay .scan_index = 1,
1364d33615dSMatt Ranostay .scan_type = {
1374d33615dSMatt Ranostay .sign = 'u',
1384d33615dSMatt Ranostay .realbits = 16,
1394d33615dSMatt Ranostay .storagebits = 16,
1404d33615dSMatt Ranostay .endianness = IIO_BE,
1414d33615dSMatt Ranostay },
1424d33615dSMatt Ranostay },
1434d33615dSMatt Ranostay {
1444d33615dSMatt Ranostay .type = IIO_TEMP,
1454d33615dSMatt Ranostay .info_mask_separate =
1464d33615dSMatt Ranostay BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
1474d33615dSMatt Ranostay .scan_index = -1,
1484d33615dSMatt Ranostay },
1494d33615dSMatt Ranostay };
1504d33615dSMatt Ranostay
max30100_set_powermode(struct max30100_data * data,bool state)1514d33615dSMatt Ranostay static int max30100_set_powermode(struct max30100_data *data, bool state)
1524d33615dSMatt Ranostay {
1534d33615dSMatt Ranostay return regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
1544d33615dSMatt Ranostay MAX30100_REG_MODE_CONFIG_PWR,
1554d33615dSMatt Ranostay state ? 0 : MAX30100_REG_MODE_CONFIG_PWR);
1564d33615dSMatt Ranostay }
1574d33615dSMatt Ranostay
max30100_clear_fifo(struct max30100_data * data)1584d33615dSMatt Ranostay static int max30100_clear_fifo(struct max30100_data *data)
1594d33615dSMatt Ranostay {
1604d33615dSMatt Ranostay int ret;
1614d33615dSMatt Ranostay
1624d33615dSMatt Ranostay ret = regmap_write(data->regmap, MAX30100_REG_FIFO_WR_PTR, 0);
1634d33615dSMatt Ranostay if (ret)
1644d33615dSMatt Ranostay return ret;
1654d33615dSMatt Ranostay
1664d33615dSMatt Ranostay ret = regmap_write(data->regmap, MAX30100_REG_FIFO_OVR_CTR, 0);
1674d33615dSMatt Ranostay if (ret)
1684d33615dSMatt Ranostay return ret;
1694d33615dSMatt Ranostay
1704d33615dSMatt Ranostay return regmap_write(data->regmap, MAX30100_REG_FIFO_RD_PTR, 0);
1714d33615dSMatt Ranostay }
1724d33615dSMatt Ranostay
max30100_buffer_postenable(struct iio_dev * indio_dev)1734d33615dSMatt Ranostay static int max30100_buffer_postenable(struct iio_dev *indio_dev)
1744d33615dSMatt Ranostay {
1754d33615dSMatt Ranostay struct max30100_data *data = iio_priv(indio_dev);
1764d33615dSMatt Ranostay int ret;
1774d33615dSMatt Ranostay
1784d33615dSMatt Ranostay ret = max30100_set_powermode(data, true);
1794d33615dSMatt Ranostay if (ret)
1804d33615dSMatt Ranostay return ret;
1814d33615dSMatt Ranostay
1824d33615dSMatt Ranostay return max30100_clear_fifo(data);
1834d33615dSMatt Ranostay }
1844d33615dSMatt Ranostay
max30100_buffer_predisable(struct iio_dev * indio_dev)1854d33615dSMatt Ranostay static int max30100_buffer_predisable(struct iio_dev *indio_dev)
1864d33615dSMatt Ranostay {
1874d33615dSMatt Ranostay struct max30100_data *data = iio_priv(indio_dev);
1884d33615dSMatt Ranostay
1894d33615dSMatt Ranostay return max30100_set_powermode(data, false);
1904d33615dSMatt Ranostay }
1914d33615dSMatt Ranostay
1924d33615dSMatt Ranostay static const struct iio_buffer_setup_ops max30100_buffer_setup_ops = {
1934d33615dSMatt Ranostay .postenable = max30100_buffer_postenable,
1944d33615dSMatt Ranostay .predisable = max30100_buffer_predisable,
1954d33615dSMatt Ranostay };
1964d33615dSMatt Ranostay
max30100_fifo_count(struct max30100_data * data)1974d33615dSMatt Ranostay static inline int max30100_fifo_count(struct max30100_data *data)
1984d33615dSMatt Ranostay {
1994d33615dSMatt Ranostay unsigned int val;
2004d33615dSMatt Ranostay int ret;
2014d33615dSMatt Ranostay
2024d33615dSMatt Ranostay ret = regmap_read(data->regmap, MAX30100_REG_INT_STATUS, &val);
2034d33615dSMatt Ranostay if (ret)
2044d33615dSMatt Ranostay return ret;
2054d33615dSMatt Ranostay
2064d33615dSMatt Ranostay /* FIFO is almost full */
2074d33615dSMatt Ranostay if (val & MAX30100_REG_INT_STATUS_FIFO_RDY)
2084d33615dSMatt Ranostay return MAX30100_REG_FIFO_DATA_ENTRY_COUNT - 1;
2094d33615dSMatt Ranostay
2104d33615dSMatt Ranostay return 0;
2114d33615dSMatt Ranostay }
2124d33615dSMatt Ranostay
max30100_read_measurement(struct max30100_data * data)2134d33615dSMatt Ranostay static int max30100_read_measurement(struct max30100_data *data)
2144d33615dSMatt Ranostay {
2154d33615dSMatt Ranostay int ret;
2164d33615dSMatt Ranostay
2174d33615dSMatt Ranostay ret = i2c_smbus_read_i2c_block_data(data->client,
2184d33615dSMatt Ranostay MAX30100_REG_FIFO_DATA,
2194d33615dSMatt Ranostay MAX30100_REG_FIFO_DATA_ENTRY_LEN,
2204d33615dSMatt Ranostay (u8 *) &data->buffer);
2214d33615dSMatt Ranostay
2224d33615dSMatt Ranostay return (ret == MAX30100_REG_FIFO_DATA_ENTRY_LEN) ? 0 : ret;
2234d33615dSMatt Ranostay }
2244d33615dSMatt Ranostay
max30100_interrupt_handler(int irq,void * private)2254d33615dSMatt Ranostay static irqreturn_t max30100_interrupt_handler(int irq, void *private)
2264d33615dSMatt Ranostay {
2274d33615dSMatt Ranostay struct iio_dev *indio_dev = private;
2284d33615dSMatt Ranostay struct max30100_data *data = iio_priv(indio_dev);
2294d33615dSMatt Ranostay int ret, cnt = 0;
2304d33615dSMatt Ranostay
2314d33615dSMatt Ranostay mutex_lock(&data->lock);
2324d33615dSMatt Ranostay
233828f84eeSMatt Ranostay while (cnt || (cnt = max30100_fifo_count(data)) > 0) {
2344d33615dSMatt Ranostay ret = max30100_read_measurement(data);
2354d33615dSMatt Ranostay if (ret)
2364d33615dSMatt Ranostay break;
2374d33615dSMatt Ranostay
2384d33615dSMatt Ranostay iio_push_to_buffers(data->indio_dev, data->buffer);
239b74fccadSMatt Ranostay cnt--;
2404d33615dSMatt Ranostay }
2414d33615dSMatt Ranostay
2424d33615dSMatt Ranostay mutex_unlock(&data->lock);
2434d33615dSMatt Ranostay
2444d33615dSMatt Ranostay return IRQ_HANDLED;
2454d33615dSMatt Ranostay }
2464d33615dSMatt Ranostay
max30100_get_current_idx(unsigned int val,int * reg)247b11a3460SMatt Ranostay static int max30100_get_current_idx(unsigned int val, int *reg)
248b11a3460SMatt Ranostay {
249b11a3460SMatt Ranostay int idx;
250b11a3460SMatt Ranostay
251b11a3460SMatt Ranostay /* LED turned off */
252b11a3460SMatt Ranostay if (val == 0) {
253b11a3460SMatt Ranostay *reg = 0;
254b11a3460SMatt Ranostay return 0;
255b11a3460SMatt Ranostay }
256b11a3460SMatt Ranostay
257b11a3460SMatt Ranostay for (idx = 0; idx < ARRAY_SIZE(max30100_led_current_mapping); idx++) {
258b11a3460SMatt Ranostay if (max30100_led_current_mapping[idx] == val) {
259b11a3460SMatt Ranostay *reg = idx + 1;
260b11a3460SMatt Ranostay return 0;
261b11a3460SMatt Ranostay }
262b11a3460SMatt Ranostay }
263b11a3460SMatt Ranostay
264b11a3460SMatt Ranostay return -EINVAL;
265b11a3460SMatt Ranostay }
266b11a3460SMatt Ranostay
max30100_led_init(struct max30100_data * data)267b11a3460SMatt Ranostay static int max30100_led_init(struct max30100_data *data)
268b11a3460SMatt Ranostay {
269b11a3460SMatt Ranostay struct device *dev = &data->client->dev;
270b11a3460SMatt Ranostay unsigned int val[2];
271b11a3460SMatt Ranostay int reg, ret;
272b11a3460SMatt Ranostay
273bb8759f2SRohit Sarkar ret = device_property_read_u32_array(dev, "maxim,led-current-microamp",
274b11a3460SMatt Ranostay (unsigned int *) &val, 2);
275b11a3460SMatt Ranostay if (ret) {
276b11a3460SMatt Ranostay /* Default to 24 mA RED LED, 50 mA IR LED */
277b11a3460SMatt Ranostay reg = (MAX30100_REG_LED_CONFIG_24MA <<
278b11a3460SMatt Ranostay MAX30100_REG_LED_CONFIG_RED_LED_SHIFT) |
279b11a3460SMatt Ranostay MAX30100_REG_LED_CONFIG_50MA;
280b11a3460SMatt Ranostay dev_warn(dev, "no led-current-microamp set");
281b11a3460SMatt Ranostay
282b11a3460SMatt Ranostay return regmap_write(data->regmap, MAX30100_REG_LED_CONFIG, reg);
283b11a3460SMatt Ranostay }
284b11a3460SMatt Ranostay
285b11a3460SMatt Ranostay /* RED LED current */
286b11a3460SMatt Ranostay ret = max30100_get_current_idx(val[0], ®);
287b11a3460SMatt Ranostay if (ret) {
288b11a3460SMatt Ranostay dev_err(dev, "invalid RED current setting %d", val[0]);
289b11a3460SMatt Ranostay return ret;
290b11a3460SMatt Ranostay }
291b11a3460SMatt Ranostay
292b11a3460SMatt Ranostay ret = regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
293b11a3460SMatt Ranostay MAX30100_REG_LED_CONFIG_LED_MASK <<
294b11a3460SMatt Ranostay MAX30100_REG_LED_CONFIG_RED_LED_SHIFT,
295b11a3460SMatt Ranostay reg << MAX30100_REG_LED_CONFIG_RED_LED_SHIFT);
296b11a3460SMatt Ranostay if (ret)
297b11a3460SMatt Ranostay return ret;
298b11a3460SMatt Ranostay
299b11a3460SMatt Ranostay /* IR LED current */
300b11a3460SMatt Ranostay ret = max30100_get_current_idx(val[1], ®);
301b11a3460SMatt Ranostay if (ret) {
302b11a3460SMatt Ranostay dev_err(dev, "invalid IR current setting %d", val[1]);
303b11a3460SMatt Ranostay return ret;
304b11a3460SMatt Ranostay }
305b11a3460SMatt Ranostay
306b11a3460SMatt Ranostay return regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
307b11a3460SMatt Ranostay MAX30100_REG_LED_CONFIG_LED_MASK, reg);
308b11a3460SMatt Ranostay }
309b11a3460SMatt Ranostay
max30100_chip_init(struct max30100_data * data)3104d33615dSMatt Ranostay static int max30100_chip_init(struct max30100_data *data)
3114d33615dSMatt Ranostay {
3124d33615dSMatt Ranostay int ret;
3134d33615dSMatt Ranostay
314b11a3460SMatt Ranostay /* setup LED current settings */
315b11a3460SMatt Ranostay ret = max30100_led_init(data);
3164d33615dSMatt Ranostay if (ret)
3174d33615dSMatt Ranostay return ret;
3184d33615dSMatt Ranostay
3194d33615dSMatt Ranostay /* enable hi-res SPO2 readings at 100Hz */
3204d33615dSMatt Ranostay ret = regmap_write(data->regmap, MAX30100_REG_SPO2_CONFIG,
3214d33615dSMatt Ranostay MAX30100_REG_SPO2_CONFIG_HI_RES_EN |
3224d33615dSMatt Ranostay MAX30100_REG_SPO2_CONFIG_100HZ);
3234d33615dSMatt Ranostay if (ret)
3244d33615dSMatt Ranostay return ret;
3254d33615dSMatt Ranostay
3264d33615dSMatt Ranostay /* enable SPO2 mode */
3274d33615dSMatt Ranostay ret = regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
3284d33615dSMatt Ranostay MAX30100_REG_MODE_CONFIG_MODE_MASK,
3294d33615dSMatt Ranostay MAX30100_REG_MODE_CONFIG_MODE_HR_EN |
3304d33615dSMatt Ranostay MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN);
3314d33615dSMatt Ranostay if (ret)
3324d33615dSMatt Ranostay return ret;
3334d33615dSMatt Ranostay
3344d33615dSMatt Ranostay /* enable FIFO interrupt */
3354d33615dSMatt Ranostay return regmap_update_bits(data->regmap, MAX30100_REG_INT_ENABLE,
3364d33615dSMatt Ranostay MAX30100_REG_INT_ENABLE_MASK,
3374d33615dSMatt Ranostay MAX30100_REG_INT_ENABLE_FIFO_EN
3384d33615dSMatt Ranostay << MAX30100_REG_INT_ENABLE_MASK_SHIFT);
3394d33615dSMatt Ranostay }
3404d33615dSMatt Ranostay
max30100_read_temp(struct max30100_data * data,int * val)3414d33615dSMatt Ranostay static int max30100_read_temp(struct max30100_data *data, int *val)
3424d33615dSMatt Ranostay {
3434d33615dSMatt Ranostay int ret;
3444d33615dSMatt Ranostay unsigned int reg;
3454d33615dSMatt Ranostay
3464d33615dSMatt Ranostay ret = regmap_read(data->regmap, MAX30100_REG_TEMP_INTEGER, ®);
3474d33615dSMatt Ranostay if (ret < 0)
3484d33615dSMatt Ranostay return ret;
3494d33615dSMatt Ranostay *val = reg << 4;
3504d33615dSMatt Ranostay
3514d33615dSMatt Ranostay ret = regmap_read(data->regmap, MAX30100_REG_TEMP_FRACTION, ®);
3524d33615dSMatt Ranostay if (ret < 0)
3534d33615dSMatt Ranostay return ret;
3544d33615dSMatt Ranostay
3554d33615dSMatt Ranostay *val |= reg & 0xf;
3564d33615dSMatt Ranostay *val = sign_extend32(*val, 11);
3574d33615dSMatt Ranostay
3584d33615dSMatt Ranostay return 0;
3594d33615dSMatt Ranostay }
3604d33615dSMatt Ranostay
max30100_get_temp(struct max30100_data * data,int * val)3614d33615dSMatt Ranostay static int max30100_get_temp(struct max30100_data *data, int *val)
3624d33615dSMatt Ranostay {
3634d33615dSMatt Ranostay int ret;
3644d33615dSMatt Ranostay
3654d33615dSMatt Ranostay /* start acquisition */
366*04f16857STrevor Gamblin ret = regmap_set_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
3674d33615dSMatt Ranostay MAX30100_REG_MODE_CONFIG_TEMP_EN);
3684d33615dSMatt Ranostay if (ret)
3694d33615dSMatt Ranostay return ret;
3704d33615dSMatt Ranostay
37118e2452aSNicholas Mc Guire msleep(35);
3724d33615dSMatt Ranostay
3734d33615dSMatt Ranostay return max30100_read_temp(data, val);
3744d33615dSMatt Ranostay }
3754d33615dSMatt Ranostay
max30100_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)3764d33615dSMatt Ranostay static int max30100_read_raw(struct iio_dev *indio_dev,
3774d33615dSMatt Ranostay struct iio_chan_spec const *chan,
3784d33615dSMatt Ranostay int *val, int *val2, long mask)
3794d33615dSMatt Ranostay {
3804d33615dSMatt Ranostay struct max30100_data *data = iio_priv(indio_dev);
3814d33615dSMatt Ranostay int ret = -EINVAL;
3824d33615dSMatt Ranostay
3834d33615dSMatt Ranostay switch (mask) {
3844d33615dSMatt Ranostay case IIO_CHAN_INFO_RAW:
3854d33615dSMatt Ranostay /*
3864d33615dSMatt Ranostay * Temperature reading can only be acquired while engine
3874d33615dSMatt Ranostay * is running
3884d33615dSMatt Ranostay */
3891555790cSNuno Sá if (iio_device_claim_buffer_mode(indio_dev)) {
3901555790cSNuno Sá /*
3911555790cSNuno Sá * Replacing -EBUSY or other error code
3921555790cSNuno Sá * returned by iio_device_claim_buffer_mode()
3931555790cSNuno Sá * because user space may rely on the current
3941555790cSNuno Sá * one.
3951555790cSNuno Sá */
3964d33615dSMatt Ranostay ret = -EAGAIN;
3971555790cSNuno Sá } else {
3984d33615dSMatt Ranostay ret = max30100_get_temp(data, val);
3994d33615dSMatt Ranostay if (!ret)
4004d33615dSMatt Ranostay ret = IIO_VAL_INT;
4014d33615dSMatt Ranostay
4021555790cSNuno Sá iio_device_release_buffer_mode(indio_dev);
4034d33615dSMatt Ranostay }
4044d33615dSMatt Ranostay break;
4054d33615dSMatt Ranostay case IIO_CHAN_INFO_SCALE:
4064d33615dSMatt Ranostay *val = 1; /* 0.0625 */
4074d33615dSMatt Ranostay *val2 = 16;
4084d33615dSMatt Ranostay ret = IIO_VAL_FRACTIONAL;
4094d33615dSMatt Ranostay break;
4104d33615dSMatt Ranostay }
4114d33615dSMatt Ranostay
4124d33615dSMatt Ranostay return ret;
4134d33615dSMatt Ranostay }
4144d33615dSMatt Ranostay
4154d33615dSMatt Ranostay static const struct iio_info max30100_info = {
4164d33615dSMatt Ranostay .read_raw = max30100_read_raw,
4174d33615dSMatt Ranostay };
4184d33615dSMatt Ranostay
max30100_probe(struct i2c_client * client)4193ef7e6e0SUwe Kleine-König static int max30100_probe(struct i2c_client *client)
4204d33615dSMatt Ranostay {
4214d33615dSMatt Ranostay struct max30100_data *data;
4224d33615dSMatt Ranostay struct iio_dev *indio_dev;
4234d33615dSMatt Ranostay int ret;
4244d33615dSMatt Ranostay
4254d33615dSMatt Ranostay indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
4264d33615dSMatt Ranostay if (!indio_dev)
4274d33615dSMatt Ranostay return -ENOMEM;
4284d33615dSMatt Ranostay
4294d33615dSMatt Ranostay indio_dev->name = MAX30100_DRV_NAME;
4304d33615dSMatt Ranostay indio_dev->channels = max30100_channels;
4314d33615dSMatt Ranostay indio_dev->info = &max30100_info;
4324d33615dSMatt Ranostay indio_dev->num_channels = ARRAY_SIZE(max30100_channels);
4334d33615dSMatt Ranostay indio_dev->available_scan_masks = max30100_scan_masks;
43417395ce2SAlexandru Ardelean indio_dev->modes = INDIO_DIRECT_MODE;
43517395ce2SAlexandru Ardelean
43617395ce2SAlexandru Ardelean ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev,
43717395ce2SAlexandru Ardelean &max30100_buffer_setup_ops);
43817395ce2SAlexandru Ardelean if (ret)
43917395ce2SAlexandru Ardelean return ret;
4404d33615dSMatt Ranostay
4414d33615dSMatt Ranostay data = iio_priv(indio_dev);
4424d33615dSMatt Ranostay data->indio_dev = indio_dev;
4434d33615dSMatt Ranostay data->client = client;
4444d33615dSMatt Ranostay
4454d33615dSMatt Ranostay mutex_init(&data->lock);
4464d33615dSMatt Ranostay i2c_set_clientdata(client, indio_dev);
4474d33615dSMatt Ranostay
4484d33615dSMatt Ranostay data->regmap = devm_regmap_init_i2c(client, &max30100_regmap_config);
4494d33615dSMatt Ranostay if (IS_ERR(data->regmap)) {
4504d33615dSMatt Ranostay dev_err(&client->dev, "regmap initialization failed.\n");
4514d33615dSMatt Ranostay return PTR_ERR(data->regmap);
4524d33615dSMatt Ranostay }
4534d33615dSMatt Ranostay max30100_set_powermode(data, false);
4544d33615dSMatt Ranostay
4554d33615dSMatt Ranostay ret = max30100_chip_init(data);
4564d33615dSMatt Ranostay if (ret)
4574d33615dSMatt Ranostay return ret;
4584d33615dSMatt Ranostay
4594d33615dSMatt Ranostay if (client->irq <= 0) {
4604d33615dSMatt Ranostay dev_err(&client->dev, "no valid irq defined\n");
4614d33615dSMatt Ranostay return -EINVAL;
4624d33615dSMatt Ranostay }
4634d33615dSMatt Ranostay ret = devm_request_threaded_irq(&client->dev, client->irq,
4644d33615dSMatt Ranostay NULL, max30100_interrupt_handler,
4654d33615dSMatt Ranostay IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
4664d33615dSMatt Ranostay "max30100_irq", indio_dev);
4674d33615dSMatt Ranostay if (ret) {
4684d33615dSMatt Ranostay dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
4694d33615dSMatt Ranostay return ret;
4704d33615dSMatt Ranostay }
4714d33615dSMatt Ranostay
4724d33615dSMatt Ranostay return iio_device_register(indio_dev);
4734d33615dSMatt Ranostay }
4744d33615dSMatt Ranostay
max30100_remove(struct i2c_client * client)475ed5c2f5fSUwe Kleine-König static void max30100_remove(struct i2c_client *client)
4764d33615dSMatt Ranostay {
4774d33615dSMatt Ranostay struct iio_dev *indio_dev = i2c_get_clientdata(client);
4784d33615dSMatt Ranostay struct max30100_data *data = iio_priv(indio_dev);
4794d33615dSMatt Ranostay
4804d33615dSMatt Ranostay iio_device_unregister(indio_dev);
4814d33615dSMatt Ranostay max30100_set_powermode(data, false);
4824d33615dSMatt Ranostay }
4834d33615dSMatt Ranostay
4844d33615dSMatt Ranostay static const struct i2c_device_id max30100_id[] = {
4854391affaSUwe Kleine-König { "max30100" },
4864d33615dSMatt Ranostay {}
4874d33615dSMatt Ranostay };
4884d33615dSMatt Ranostay MODULE_DEVICE_TABLE(i2c, max30100_id);
4894d33615dSMatt Ranostay
4904d33615dSMatt Ranostay static const struct of_device_id max30100_dt_ids[] = {
4914d33615dSMatt Ranostay { .compatible = "maxim,max30100" },
4924d33615dSMatt Ranostay { }
4934d33615dSMatt Ranostay };
4944d33615dSMatt Ranostay MODULE_DEVICE_TABLE(of, max30100_dt_ids);
4954d33615dSMatt Ranostay
4964d33615dSMatt Ranostay static struct i2c_driver max30100_driver = {
4974d33615dSMatt Ranostay .driver = {
4984d33615dSMatt Ranostay .name = MAX30100_DRV_NAME,
499bb8759f2SRohit Sarkar .of_match_table = max30100_dt_ids,
5004d33615dSMatt Ranostay },
5017cf15f42SUwe Kleine-König .probe = max30100_probe,
5024d33615dSMatt Ranostay .remove = max30100_remove,
5034d33615dSMatt Ranostay .id_table = max30100_id,
5044d33615dSMatt Ranostay };
5054d33615dSMatt Ranostay module_i2c_driver(max30100_driver);
5064d33615dSMatt Ranostay
507d6ad8058SMatt Ranostay MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
5084d33615dSMatt Ranostay MODULE_DESCRIPTION("MAX30100 heart rate and pulse oximeter sensor");
5094d33615dSMatt Ranostay MODULE_LICENSE("GPL");
510