1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MPU3050 gyroscope driver 4 * 5 * Copyright (C) 2016 Linaro Ltd. 6 * Author: Linus Walleij <linus.walleij@linaro.org> 7 * 8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd 9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by 10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c. 11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011. 12 * 13 * TODO: add support for setting up the low pass 3dB frequency. 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/bitops.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/property.h> 30 #include <linux/random.h> 31 #include <linux/slab.h> 32 33 #include "mpu3050.h" 34 35 #define MPU3050_CHIP_ID 0x68 36 #define MPU3050_CHIP_ID_MASK 0x7E 37 38 /* 39 * Register map: anything suffixed *_H is a big-endian high byte and always 40 * followed by the corresponding low byte (*_L) even though these are not 41 * explicitly included in the register definitions. 42 */ 43 #define MPU3050_CHIP_ID_REG 0x00 44 #define MPU3050_PRODUCT_ID_REG 0x01 45 #define MPU3050_XG_OFFS_TC 0x05 46 #define MPU3050_YG_OFFS_TC 0x08 47 #define MPU3050_ZG_OFFS_TC 0x0B 48 #define MPU3050_X_OFFS_USR_H 0x0C 49 #define MPU3050_Y_OFFS_USR_H 0x0E 50 #define MPU3050_Z_OFFS_USR_H 0x10 51 #define MPU3050_FIFO_EN 0x12 52 #define MPU3050_AUX_VDDIO 0x13 53 #define MPU3050_SLV_ADDR 0x14 54 #define MPU3050_SMPLRT_DIV 0x15 55 #define MPU3050_DLPF_FS_SYNC 0x16 56 #define MPU3050_INT_CFG 0x17 57 #define MPU3050_AUX_ADDR 0x18 58 #define MPU3050_INT_STATUS 0x1A 59 #define MPU3050_TEMP_H 0x1B 60 #define MPU3050_XOUT_H 0x1D 61 #define MPU3050_YOUT_H 0x1F 62 #define MPU3050_ZOUT_H 0x21 63 #define MPU3050_DMP_CFG1 0x35 64 #define MPU3050_DMP_CFG2 0x36 65 #define MPU3050_BANK_SEL 0x37 66 #define MPU3050_MEM_START_ADDR 0x38 67 #define MPU3050_MEM_R_W 0x39 68 #define MPU3050_FIFO_COUNT_H 0x3A 69 #define MPU3050_FIFO_R 0x3C 70 #define MPU3050_USR_CTRL 0x3D 71 #define MPU3050_PWR_MGM 0x3E 72 73 /* MPU memory bank read options */ 74 #define MPU3050_MEM_PRFTCH BIT(5) 75 #define MPU3050_MEM_USER_BANK BIT(4) 76 /* Bits 8-11 select memory bank */ 77 #define MPU3050_MEM_RAM_BANK_0 0 78 #define MPU3050_MEM_RAM_BANK_1 1 79 #define MPU3050_MEM_RAM_BANK_2 2 80 #define MPU3050_MEM_RAM_BANK_3 3 81 #define MPU3050_MEM_OTP_BANK_0 4 82 83 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2)) 84 85 /* Register bits */ 86 87 /* FIFO Enable */ 88 #define MPU3050_FIFO_EN_FOOTER BIT(0) 89 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1) 90 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2) 91 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3) 92 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4) 93 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5) 94 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6) 95 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7) 96 97 /* 98 * Digital Low Pass filter (DLPF) 99 * Full Scale (FS) 100 * and Synchronization 101 */ 102 #define MPU3050_EXT_SYNC_NONE 0x00 103 #define MPU3050_EXT_SYNC_TEMP 0x20 104 #define MPU3050_EXT_SYNC_GYROX 0x40 105 #define MPU3050_EXT_SYNC_GYROY 0x60 106 #define MPU3050_EXT_SYNC_GYROZ 0x80 107 #define MPU3050_EXT_SYNC_ACCELX 0xA0 108 #define MPU3050_EXT_SYNC_ACCELY 0xC0 109 #define MPU3050_EXT_SYNC_ACCELZ 0xE0 110 #define MPU3050_EXT_SYNC_MASK 0xE0 111 #define MPU3050_EXT_SYNC_SHIFT 5 112 113 #define MPU3050_FS_250DPS 0x00 114 #define MPU3050_FS_500DPS 0x08 115 #define MPU3050_FS_1000DPS 0x10 116 #define MPU3050_FS_2000DPS 0x18 117 #define MPU3050_FS_MASK 0x18 118 #define MPU3050_FS_SHIFT 3 119 120 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00 121 #define MPU3050_DLPF_CFG_188HZ 0x01 122 #define MPU3050_DLPF_CFG_98HZ 0x02 123 #define MPU3050_DLPF_CFG_42HZ 0x03 124 #define MPU3050_DLPF_CFG_20HZ 0x04 125 #define MPU3050_DLPF_CFG_10HZ 0x05 126 #define MPU3050_DLPF_CFG_5HZ 0x06 127 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07 128 #define MPU3050_DLPF_CFG_MASK 0x07 129 #define MPU3050_DLPF_CFG_SHIFT 0 130 131 /* Interrupt config */ 132 #define MPU3050_INT_RAW_RDY_EN BIT(0) 133 #define MPU3050_INT_DMP_DONE_EN BIT(1) 134 #define MPU3050_INT_MPU_RDY_EN BIT(2) 135 #define MPU3050_INT_ANYRD_2CLEAR BIT(4) 136 #define MPU3050_INT_LATCH_EN BIT(5) 137 #define MPU3050_INT_OPEN BIT(6) 138 #define MPU3050_INT_ACTL BIT(7) 139 /* Interrupt status */ 140 #define MPU3050_INT_STATUS_RAW_RDY BIT(0) 141 #define MPU3050_INT_STATUS_DMP_DONE BIT(1) 142 #define MPU3050_INT_STATUS_MPU_RDY BIT(2) 143 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7) 144 /* USR_CTRL */ 145 #define MPU3050_USR_CTRL_FIFO_EN BIT(6) 146 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5) 147 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3) 148 #define MPU3050_USR_CTRL_FIFO_RST BIT(1) 149 #define MPU3050_USR_CTRL_GYRO_RST BIT(0) 150 /* PWR_MGM */ 151 #define MPU3050_PWR_MGM_PLL_X 0x01 152 #define MPU3050_PWR_MGM_PLL_Y 0x02 153 #define MPU3050_PWR_MGM_PLL_Z 0x03 154 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07 155 #define MPU3050_PWR_MGM_STBY_ZG BIT(3) 156 #define MPU3050_PWR_MGM_STBY_YG BIT(4) 157 #define MPU3050_PWR_MGM_STBY_XG BIT(5) 158 #define MPU3050_PWR_MGM_SLEEP BIT(6) 159 #define MPU3050_PWR_MGM_RESET BIT(7) 160 #define MPU3050_PWR_MGM_MASK 0xff 161 162 /* 163 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full 164 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale, 165 * in two's complement. 166 */ 167 static unsigned int mpu3050_fs_precision[] = { 168 IIO_DEGREE_TO_RAD(250), 169 IIO_DEGREE_TO_RAD(500), 170 IIO_DEGREE_TO_RAD(1000), 171 IIO_DEGREE_TO_RAD(2000) 172 }; 173 174 /* 175 * Regulator names 176 */ 177 static const char mpu3050_reg_vdd[] = "vdd"; 178 static const char mpu3050_reg_vlogic[] = "vlogic"; 179 180 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050) 181 { 182 unsigned int freq; 183 184 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) 185 freq = 8000; 186 else 187 freq = 1000; 188 freq /= (mpu3050->divisor + 1); 189 190 return freq; 191 } 192 193 static int mpu3050_start_sampling(struct mpu3050 *mpu3050) 194 { 195 __be16 raw_val[3]; 196 int ret; 197 int i; 198 199 /* Reset */ 200 ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM, 201 MPU3050_PWR_MGM_RESET); 202 if (ret) 203 return ret; 204 205 /* Turn on the Z-axis PLL */ 206 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 207 MPU3050_PWR_MGM_CLKSEL_MASK, 208 MPU3050_PWR_MGM_PLL_Z); 209 if (ret) 210 return ret; 211 212 /* Write calibration offset registers */ 213 for (i = 0; i < 3; i++) 214 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); 215 216 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val, 217 sizeof(raw_val)); 218 if (ret) 219 return ret; 220 221 /* Set low pass filter (sample rate), sync and full scale */ 222 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC, 223 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT | 224 mpu3050->fullscale << MPU3050_FS_SHIFT | 225 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT); 226 if (ret) 227 return ret; 228 229 /* Set up sampling frequency */ 230 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor); 231 if (ret) 232 return ret; 233 234 /* 235 * Max 50 ms start-up time after setting DLPF_FS_SYNC 236 * according to the data sheet, then wait for the next sample 237 * at this frequency T = 1000/f ms. 238 */ 239 msleep(50 + 1000 / mpu3050_get_freq(mpu3050)); 240 241 return 0; 242 } 243 244 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050) 245 { 246 int ret; 247 u8 divisor; 248 enum mpu3050_lpf lpf; 249 250 lpf = mpu3050->lpf; 251 divisor = mpu3050->divisor; 252 253 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */ 254 mpu3050->divisor = 0; /* Divide by 1 */ 255 ret = mpu3050_start_sampling(mpu3050); 256 257 mpu3050->lpf = lpf; 258 mpu3050->divisor = divisor; 259 260 return ret; 261 } 262 263 static int mpu3050_read_raw(struct iio_dev *indio_dev, 264 struct iio_chan_spec const *chan, 265 int *val, int *val2, 266 long mask) 267 { 268 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 269 int ret; 270 __be16 raw_val; 271 272 switch (mask) { 273 case IIO_CHAN_INFO_OFFSET: 274 switch (chan->type) { 275 case IIO_TEMP: 276 /* 277 * The temperature scaling is (x+23000)/280 Celsius 278 * for the "best fit straight line" temperature range 279 * of -30C..85C. The 23000 includes room temperature 280 * offset of +35C, 280 is the precision scale and x is 281 * the 16-bit signed integer reported by hardware. 282 * 283 * Temperature value itself represents temperature of 284 * the sensor die. 285 */ 286 *val = 23000; 287 return IIO_VAL_INT; 288 default: 289 return -EINVAL; 290 } 291 case IIO_CHAN_INFO_CALIBBIAS: 292 switch (chan->type) { 293 case IIO_ANGL_VEL: 294 *val = mpu3050->calibration[chan->scan_index-1]; 295 return IIO_VAL_INT; 296 default: 297 return -EINVAL; 298 } 299 case IIO_CHAN_INFO_SAMP_FREQ: 300 *val = mpu3050_get_freq(mpu3050); 301 return IIO_VAL_INT; 302 case IIO_CHAN_INFO_SCALE: 303 switch (chan->type) { 304 case IIO_TEMP: 305 /* Millidegrees, see about temperature scaling above */ 306 *val = 1000; 307 *val2 = 280; 308 return IIO_VAL_FRACTIONAL; 309 case IIO_ANGL_VEL: 310 /* 311 * Convert to the corresponding full scale in 312 * radians. All 16 bits are used with sign to 313 * span the available scale: to account for the one 314 * missing value if we multiply by 1/S16_MAX, instead 315 * multiply with 2/U16_MAX. 316 */ 317 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; 318 *val2 = U16_MAX; 319 return IIO_VAL_FRACTIONAL; 320 default: 321 return -EINVAL; 322 } 323 case IIO_CHAN_INFO_RAW: 324 /* Resume device */ 325 pm_runtime_get_sync(mpu3050->dev); 326 mutex_lock(&mpu3050->lock); 327 328 ret = mpu3050_set_8khz_samplerate(mpu3050); 329 if (ret) 330 goto out_read_raw_unlock; 331 332 switch (chan->type) { 333 case IIO_TEMP: 334 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, 335 &raw_val, sizeof(raw_val)); 336 if (ret) { 337 dev_err(mpu3050->dev, 338 "error reading temperature\n"); 339 goto out_read_raw_unlock; 340 } 341 342 *val = (s16)be16_to_cpu(raw_val); 343 ret = IIO_VAL_INT; 344 345 goto out_read_raw_unlock; 346 case IIO_ANGL_VEL: 347 ret = regmap_bulk_read(mpu3050->map, 348 MPU3050_AXIS_REGS(chan->scan_index-1), 349 &raw_val, 350 sizeof(raw_val)); 351 if (ret) { 352 dev_err(mpu3050->dev, 353 "error reading axis data\n"); 354 goto out_read_raw_unlock; 355 } 356 357 *val = be16_to_cpu(raw_val); 358 ret = IIO_VAL_INT; 359 360 goto out_read_raw_unlock; 361 default: 362 ret = -EINVAL; 363 goto out_read_raw_unlock; 364 } 365 default: 366 break; 367 } 368 369 return -EINVAL; 370 371 out_read_raw_unlock: 372 mutex_unlock(&mpu3050->lock); 373 pm_runtime_put_autosuspend(mpu3050->dev); 374 375 return ret; 376 } 377 378 static int mpu3050_write_raw(struct iio_dev *indio_dev, 379 const struct iio_chan_spec *chan, 380 int val, int val2, long mask) 381 { 382 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 383 /* 384 * Couldn't figure out a way to precalculate these at compile time. 385 */ 386 unsigned int fs250 = 387 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2, 388 U16_MAX); 389 unsigned int fs500 = 390 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2, 391 U16_MAX); 392 unsigned int fs1000 = 393 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2, 394 U16_MAX); 395 unsigned int fs2000 = 396 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2, 397 U16_MAX); 398 399 switch (mask) { 400 case IIO_CHAN_INFO_CALIBBIAS: 401 if (chan->type != IIO_ANGL_VEL) 402 return -EINVAL; 403 mpu3050->calibration[chan->scan_index-1] = val; 404 return 0; 405 case IIO_CHAN_INFO_SAMP_FREQ: 406 /* 407 * The max samplerate is 8000 Hz, the minimum 408 * 1000 / 256 ~= 4 Hz 409 */ 410 if (val < 4 || val > 8000) 411 return -EINVAL; 412 413 /* 414 * Above 1000 Hz we must turn off the digital low pass filter 415 * so we get a base frequency of 8kHz to the divider 416 */ 417 if (val > 1000) { 418 mpu3050->lpf = LPF_256_HZ_NOLPF; 419 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; 420 return 0; 421 } 422 423 mpu3050->lpf = LPF_188_HZ; 424 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; 425 return 0; 426 case IIO_CHAN_INFO_SCALE: 427 if (chan->type != IIO_ANGL_VEL) 428 return -EINVAL; 429 /* 430 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s 431 * which means we need to round to the closest radians 432 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35 433 * rad/s. The scale is then for the 16 bits used to cover 434 * it 2/(2^16) of that. 435 */ 436 437 /* Just too large, set the max range */ 438 if (val != 0) { 439 mpu3050->fullscale = FS_2000_DPS; 440 return 0; 441 } 442 443 /* 444 * Now we're dealing with fractions below zero in millirad/s 445 * do some integer interpolation and match with the closest 446 * fullscale in the table. 447 */ 448 if (val2 <= fs250 || 449 val2 < ((fs500 + fs250) / 2)) 450 mpu3050->fullscale = FS_250_DPS; 451 else if (val2 <= fs500 || 452 val2 < ((fs1000 + fs500) / 2)) 453 mpu3050->fullscale = FS_500_DPS; 454 else if (val2 <= fs1000 || 455 val2 < ((fs2000 + fs1000) / 2)) 456 mpu3050->fullscale = FS_1000_DPS; 457 else 458 /* Catch-all */ 459 mpu3050->fullscale = FS_2000_DPS; 460 return 0; 461 default: 462 break; 463 } 464 465 return -EINVAL; 466 } 467 468 static irqreturn_t mpu3050_trigger_handler(int irq, void *p) 469 { 470 const struct iio_poll_func *pf = p; 471 struct iio_dev *indio_dev = pf->indio_dev; 472 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 473 int ret; 474 struct { 475 __be16 chans[4]; 476 aligned_s64 timestamp; 477 } scan; 478 s64 timestamp; 479 unsigned int datums_from_fifo = 0; 480 481 /* 482 * If we're using the hardware trigger, get the precise timestamp from 483 * the top half of the threaded IRQ handler. Otherwise get the 484 * timestamp here so it will be close in time to the actual values 485 * read from the registers. 486 */ 487 if (iio_trigger_using_own(indio_dev)) 488 timestamp = mpu3050->hw_timestamp; 489 else 490 timestamp = iio_get_time_ns(indio_dev); 491 492 mutex_lock(&mpu3050->lock); 493 494 /* Using the hardware IRQ trigger? Check the buffer then. */ 495 if (mpu3050->hw_irq_trigger) { 496 __be16 raw_fifocnt; 497 u16 fifocnt; 498 /* X, Y, Z + temperature */ 499 unsigned int bytes_per_datum = 8; 500 bool fifo_overflow = false; 501 502 ret = regmap_bulk_read(mpu3050->map, 503 MPU3050_FIFO_COUNT_H, 504 &raw_fifocnt, 505 sizeof(raw_fifocnt)); 506 if (ret) 507 goto out_trigger_unlock; 508 fifocnt = be16_to_cpu(raw_fifocnt); 509 510 if (fifocnt == 512) { 511 dev_info(mpu3050->dev, 512 "FIFO overflow! Emptying and resetting FIFO\n"); 513 fifo_overflow = true; 514 /* Reset and enable the FIFO */ 515 ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL, 516 MPU3050_USR_CTRL_FIFO_EN | 517 MPU3050_USR_CTRL_FIFO_RST); 518 if (ret) { 519 dev_info(mpu3050->dev, "error resetting FIFO\n"); 520 goto out_trigger_unlock; 521 } 522 mpu3050->pending_fifo_footer = false; 523 } 524 525 if (fifocnt) 526 dev_dbg(mpu3050->dev, 527 "%d bytes in the FIFO\n", 528 fifocnt); 529 530 while (!fifo_overflow && fifocnt > bytes_per_datum) { 531 unsigned int toread; 532 unsigned int offset; 533 __be16 fifo_values[5]; 534 535 /* 536 * If there is a FIFO footer in the pipe, first clear 537 * that out. This follows the complex algorithm in the 538 * datasheet that states that you may never leave the 539 * FIFO empty after the first reading: you have to 540 * always leave two footer bytes in it. The footer is 541 * in practice just two zero bytes. 542 */ 543 if (mpu3050->pending_fifo_footer) { 544 toread = bytes_per_datum + 2; 545 offset = 0; 546 } else { 547 toread = bytes_per_datum; 548 offset = 1; 549 /* Put in some dummy value */ 550 fifo_values[0] = cpu_to_be16(0xAAAA); 551 } 552 553 ret = regmap_bulk_read(mpu3050->map, 554 MPU3050_FIFO_R, 555 &fifo_values[offset], 556 toread); 557 if (ret) 558 goto out_trigger_unlock; 559 560 dev_dbg(mpu3050->dev, 561 "%04x %04x %04x %04x %04x\n", 562 fifo_values[0], 563 fifo_values[1], 564 fifo_values[2], 565 fifo_values[3], 566 fifo_values[4]); 567 568 /* Index past the footer (fifo_values[0]) and push */ 569 iio_push_to_buffers_with_ts_unaligned(indio_dev, 570 &fifo_values[1], 571 sizeof(__be16) * 4, 572 timestamp); 573 574 fifocnt -= toread; 575 datums_from_fifo++; 576 mpu3050->pending_fifo_footer = true; 577 578 /* 579 * If we're emptying the FIFO, just make sure to 580 * check if something new appeared. 581 */ 582 if (fifocnt < bytes_per_datum) { 583 ret = regmap_bulk_read(mpu3050->map, 584 MPU3050_FIFO_COUNT_H, 585 &raw_fifocnt, 586 sizeof(raw_fifocnt)); 587 if (ret) 588 goto out_trigger_unlock; 589 fifocnt = be16_to_cpu(raw_fifocnt); 590 } 591 592 if (fifocnt < bytes_per_datum) 593 dev_dbg(mpu3050->dev, 594 "%d bytes left in the FIFO\n", 595 fifocnt); 596 597 /* 598 * At this point, the timestamp that triggered the 599 * hardware interrupt is no longer valid for what 600 * we are reading (the interrupt likely fired for 601 * the value on the top of the FIFO), so set the 602 * timestamp to zero and let userspace deal with it. 603 */ 604 timestamp = 0; 605 } 606 } 607 608 /* 609 * If we picked some datums from the FIFO that's enough, else 610 * fall through and just read from the current value registers. 611 * This happens in two cases: 612 * 613 * - We are using some other trigger (external, like an HRTimer) 614 * than the sensor's own sample generator. In this case the 615 * sensor is just set to the max sampling frequency and we give 616 * the trigger a copy of the latest value every time we get here. 617 * 618 * - The hardware trigger is active but unused and we actually use 619 * another trigger which calls here with a frequency higher 620 * than what the device provides data. We will then just read 621 * duplicate values directly from the hardware registers. 622 */ 623 if (datums_from_fifo) { 624 dev_dbg(mpu3050->dev, 625 "read %d datums from the FIFO\n", 626 datums_from_fifo); 627 goto out_trigger_unlock; 628 } 629 630 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, scan.chans, 631 sizeof(scan.chans)); 632 if (ret) { 633 dev_err(mpu3050->dev, 634 "error reading axis data\n"); 635 goto out_trigger_unlock; 636 } 637 638 iio_push_to_buffers_with_timestamp(indio_dev, &scan, timestamp); 639 640 out_trigger_unlock: 641 mutex_unlock(&mpu3050->lock); 642 iio_trigger_notify_done(indio_dev->trig); 643 644 return IRQ_HANDLED; 645 } 646 647 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev) 648 { 649 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 650 651 pm_runtime_get_sync(mpu3050->dev); 652 653 /* Unless we have OUR trigger active, run at full speed */ 654 if (!mpu3050->hw_irq_trigger) 655 return mpu3050_set_8khz_samplerate(mpu3050); 656 657 return 0; 658 } 659 660 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev) 661 { 662 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 663 664 pm_runtime_put_autosuspend(mpu3050->dev); 665 666 return 0; 667 } 668 669 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = { 670 .preenable = mpu3050_buffer_preenable, 671 .postdisable = mpu3050_buffer_postdisable, 672 }; 673 674 static const struct iio_mount_matrix * 675 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev, 676 const struct iio_chan_spec *chan) 677 { 678 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 679 680 return &mpu3050->orientation; 681 } 682 683 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = { 684 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix), 685 { } 686 }; 687 688 #define MPU3050_AXIS_CHANNEL(axis, index) \ 689 { \ 690 .type = IIO_ANGL_VEL, \ 691 .modified = 1, \ 692 .channel2 = IIO_MOD_##axis, \ 693 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 694 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 695 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 696 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 697 .ext_info = mpu3050_ext_info, \ 698 .scan_index = index, \ 699 .scan_type = { \ 700 .sign = 's', \ 701 .realbits = 16, \ 702 .storagebits = 16, \ 703 .endianness = IIO_BE, \ 704 }, \ 705 } 706 707 static const struct iio_chan_spec mpu3050_channels[] = { 708 { 709 .type = IIO_TEMP, 710 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 711 BIT(IIO_CHAN_INFO_SCALE) | 712 BIT(IIO_CHAN_INFO_OFFSET), 713 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 714 .scan_index = 0, 715 .scan_type = { 716 .sign = 's', 717 .realbits = 16, 718 .storagebits = 16, 719 .endianness = IIO_BE, 720 }, 721 }, 722 MPU3050_AXIS_CHANNEL(X, 1), 723 MPU3050_AXIS_CHANNEL(Y, 2), 724 MPU3050_AXIS_CHANNEL(Z, 3), 725 IIO_CHAN_SOFT_TIMESTAMP(4), 726 }; 727 728 /* Four channels apart from timestamp, scan mask = 0x0f */ 729 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 }; 730 731 /* 732 * These are just the hardcoded factors resulting from the more elaborate 733 * calculations done with fractions in the scale raw get/set functions. 734 */ 735 static IIO_CONST_ATTR(anglevel_scale_available, 736 "0.000122070 " 737 "0.000274658 " 738 "0.000518798 " 739 "0.001068115"); 740 741 static struct attribute *mpu3050_attributes[] = { 742 &iio_const_attr_anglevel_scale_available.dev_attr.attr, 743 NULL, 744 }; 745 746 static const struct attribute_group mpu3050_attribute_group = { 747 .attrs = mpu3050_attributes, 748 }; 749 750 static const struct iio_info mpu3050_info = { 751 .read_raw = mpu3050_read_raw, 752 .write_raw = mpu3050_write_raw, 753 .attrs = &mpu3050_attribute_group, 754 }; 755 756 /** 757 * mpu3050_read_mem() - read MPU-3050 internal memory 758 * @mpu3050: device to read from 759 * @bank: target bank 760 * @addr: target address 761 * @len: number of bytes 762 * @buf: the buffer to store the read bytes in 763 */ 764 static int mpu3050_read_mem(struct mpu3050 *mpu3050, 765 u8 bank, 766 u8 addr, 767 u8 len, 768 u8 *buf) 769 { 770 int ret; 771 772 ret = regmap_write(mpu3050->map, 773 MPU3050_BANK_SEL, 774 bank); 775 if (ret) 776 return ret; 777 778 ret = regmap_write(mpu3050->map, 779 MPU3050_MEM_START_ADDR, 780 addr); 781 if (ret) 782 return ret; 783 784 return regmap_bulk_read(mpu3050->map, 785 MPU3050_MEM_R_W, 786 buf, 787 len); 788 } 789 790 static int mpu3050_hw_init(struct mpu3050 *mpu3050) 791 { 792 int ret; 793 __le64 otp_le; 794 u64 otp; 795 796 /* Reset */ 797 ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM, 798 MPU3050_PWR_MGM_RESET); 799 if (ret) 800 return ret; 801 802 /* Turn on the PLL */ 803 ret = regmap_update_bits(mpu3050->map, 804 MPU3050_PWR_MGM, 805 MPU3050_PWR_MGM_CLKSEL_MASK, 806 MPU3050_PWR_MGM_PLL_Z); 807 if (ret) 808 return ret; 809 810 /* Disable IRQs */ 811 ret = regmap_write(mpu3050->map, 812 MPU3050_INT_CFG, 813 0); 814 if (ret) 815 return ret; 816 817 /* Read out the 8 bytes of OTP (one-time-programmable) memory */ 818 ret = mpu3050_read_mem(mpu3050, 819 (MPU3050_MEM_PRFTCH | 820 MPU3050_MEM_USER_BANK | 821 MPU3050_MEM_OTP_BANK_0), 822 0, 823 sizeof(otp_le), 824 (u8 *)&otp_le); 825 if (ret) 826 return ret; 827 828 /* This is device-unique data so it goes into the entropy pool */ 829 add_device_randomness(&otp_le, sizeof(otp_le)); 830 831 otp = le64_to_cpu(otp_le); 832 833 dev_info(mpu3050->dev, 834 "die ID: %04llX, wafer ID: %02llX, A lot ID: %04llX, " 835 "W lot ID: %03llX, WP ID: %01llX, rev ID: %02llX\n", 836 /* Die ID, bits 0-12 */ 837 FIELD_GET(GENMASK_ULL(12, 0), otp), 838 /* Wafer ID, bits 13-17 */ 839 FIELD_GET(GENMASK_ULL(17, 13), otp), 840 /* A lot ID, bits 18-33 */ 841 FIELD_GET(GENMASK_ULL(33, 18), otp), 842 /* W lot ID, bits 34-45 */ 843 FIELD_GET(GENMASK_ULL(45, 34), otp), 844 /* WP ID, bits 47-49 */ 845 FIELD_GET(GENMASK_ULL(49, 47), otp), 846 /* rev ID, bits 50-55 */ 847 FIELD_GET(GENMASK_ULL(55, 50), otp)); 848 849 return 0; 850 } 851 852 static int mpu3050_power_up(struct mpu3050 *mpu3050) 853 { 854 int ret; 855 856 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 857 if (ret) { 858 dev_err(mpu3050->dev, "cannot enable regulators\n"); 859 return ret; 860 } 861 /* 862 * 20-100 ms start-up time for register read/write according to 863 * the datasheet, be on the safe side and wait 200 ms. 864 */ 865 msleep(200); 866 867 /* Take device out of sleep mode */ 868 ret = regmap_clear_bits(mpu3050->map, MPU3050_PWR_MGM, 869 MPU3050_PWR_MGM_SLEEP); 870 if (ret) { 871 regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 872 dev_err(mpu3050->dev, "error setting power mode\n"); 873 return ret; 874 } 875 usleep_range(10000, 20000); 876 877 return 0; 878 } 879 880 static int mpu3050_power_down(struct mpu3050 *mpu3050) 881 { 882 int ret; 883 884 /* 885 * Put MPU-3050 into sleep mode before cutting regulators. 886 * This is important, because we may not be the sole user 887 * of the regulator so the power may stay on after this, and 888 * then we would be wasting power unless we go to sleep mode 889 * first. 890 */ 891 ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM, 892 MPU3050_PWR_MGM_SLEEP); 893 if (ret) 894 dev_err(mpu3050->dev, "error putting to sleep\n"); 895 896 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 897 if (ret) 898 dev_err(mpu3050->dev, "error disabling regulators\n"); 899 900 return 0; 901 } 902 903 static irqreturn_t mpu3050_irq_handler(int irq, void *p) 904 { 905 struct iio_trigger *trig = p; 906 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 907 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 908 909 if (!mpu3050->hw_irq_trigger) 910 return IRQ_NONE; 911 912 /* Get the time stamp as close in time as possible */ 913 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev); 914 915 return IRQ_WAKE_THREAD; 916 } 917 918 static irqreturn_t mpu3050_irq_thread(int irq, void *p) 919 { 920 struct iio_trigger *trig = p; 921 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 922 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 923 unsigned int val; 924 int ret; 925 926 /* ACK IRQ and check if it was from us */ 927 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 928 if (ret) { 929 dev_err(mpu3050->dev, "error reading IRQ status\n"); 930 return IRQ_HANDLED; 931 } 932 if (!(val & MPU3050_INT_STATUS_RAW_RDY)) 933 return IRQ_NONE; 934 935 iio_trigger_poll_nested(p); 936 937 return IRQ_HANDLED; 938 } 939 940 /** 941 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state 942 * @trig: trigger instance 943 * @enable: true if trigger should be enabled, false to disable 944 */ 945 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig, 946 bool enable) 947 { 948 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 949 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 950 unsigned int val; 951 int ret; 952 953 /* Disabling trigger: disable interrupt and return */ 954 if (!enable) { 955 /* Disable all interrupts */ 956 ret = regmap_write(mpu3050->map, 957 MPU3050_INT_CFG, 958 0); 959 if (ret) 960 dev_err(mpu3050->dev, "error disabling IRQ\n"); 961 962 /* Clear IRQ flag */ 963 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 964 if (ret) 965 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 966 967 /* Disable all things in the FIFO and reset it */ 968 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 969 if (ret) 970 dev_err(mpu3050->dev, "error disabling FIFO\n"); 971 972 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL, 973 MPU3050_USR_CTRL_FIFO_RST); 974 if (ret) 975 dev_err(mpu3050->dev, "error resetting FIFO\n"); 976 977 pm_runtime_put_autosuspend(mpu3050->dev); 978 mpu3050->hw_irq_trigger = false; 979 980 return 0; 981 } else { 982 /* Else we're enabling the trigger from this point */ 983 pm_runtime_get_sync(mpu3050->dev); 984 mpu3050->hw_irq_trigger = true; 985 986 /* Disable all things in the FIFO */ 987 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 988 if (ret) 989 return ret; 990 991 /* Reset and enable the FIFO */ 992 ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL, 993 MPU3050_USR_CTRL_FIFO_EN | 994 MPU3050_USR_CTRL_FIFO_RST); 995 if (ret) 996 return ret; 997 998 mpu3050->pending_fifo_footer = false; 999 1000 /* Turn on the FIFO for temp+X+Y+Z */ 1001 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 1002 MPU3050_FIFO_EN_TEMP_OUT | 1003 MPU3050_FIFO_EN_GYRO_XOUT | 1004 MPU3050_FIFO_EN_GYRO_YOUT | 1005 MPU3050_FIFO_EN_GYRO_ZOUT | 1006 MPU3050_FIFO_EN_FOOTER); 1007 if (ret) 1008 return ret; 1009 1010 /* Configure the sample engine */ 1011 ret = mpu3050_start_sampling(mpu3050); 1012 if (ret) 1013 return ret; 1014 1015 /* Clear IRQ flag */ 1016 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 1017 if (ret) 1018 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 1019 1020 /* Give us interrupts whenever there is new data ready */ 1021 val = MPU3050_INT_RAW_RDY_EN; 1022 1023 if (mpu3050->irq_actl) 1024 val |= MPU3050_INT_ACTL; 1025 if (mpu3050->irq_latch) 1026 val |= MPU3050_INT_LATCH_EN; 1027 if (mpu3050->irq_opendrain) 1028 val |= MPU3050_INT_OPEN; 1029 1030 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); 1031 if (ret) 1032 return ret; 1033 } 1034 1035 return 0; 1036 } 1037 1038 static const struct iio_trigger_ops mpu3050_trigger_ops = { 1039 .set_trigger_state = mpu3050_drdy_trigger_set_state, 1040 }; 1041 1042 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq) 1043 { 1044 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1045 struct device *dev = mpu3050->dev; 1046 unsigned long irq_trig; 1047 int ret; 1048 1049 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev, 1050 "%s-dev%d", 1051 indio_dev->name, 1052 iio_device_id(indio_dev)); 1053 if (!mpu3050->trig) 1054 return -ENOMEM; 1055 1056 /* Check if IRQ is open drain */ 1057 mpu3050->irq_opendrain = device_property_read_bool(dev, "drive-open-drain"); 1058 1059 /* 1060 * Configure the interrupt generator hardware to supply whatever 1061 * the interrupt is configured for, edges low/high level low/high, 1062 * we can provide it all. 1063 */ 1064 irq_trig = irq_get_trigger_type(irq); 1065 switch (irq_trig) { 1066 case IRQF_TRIGGER_RISING: 1067 dev_info(&indio_dev->dev, 1068 "pulse interrupts on the rising edge\n"); 1069 break; 1070 case IRQF_TRIGGER_FALLING: 1071 mpu3050->irq_actl = true; 1072 dev_info(&indio_dev->dev, 1073 "pulse interrupts on the falling edge\n"); 1074 break; 1075 case IRQF_TRIGGER_HIGH: 1076 mpu3050->irq_latch = true; 1077 dev_info(&indio_dev->dev, 1078 "interrupts active high level\n"); 1079 /* 1080 * With level IRQs, we mask the IRQ until it is processed, 1081 * but with edge IRQs (pulses) we can queue several interrupts 1082 * in the top half. 1083 */ 1084 irq_trig |= IRQF_ONESHOT; 1085 break; 1086 case IRQF_TRIGGER_LOW: 1087 mpu3050->irq_latch = true; 1088 mpu3050->irq_actl = true; 1089 irq_trig |= IRQF_ONESHOT; 1090 dev_info(&indio_dev->dev, 1091 "interrupts active low level\n"); 1092 break; 1093 default: 1094 /* This is the most preferred mode, if possible */ 1095 dev_err(&indio_dev->dev, 1096 "unsupported IRQ trigger specified (%lx), enforce " 1097 "rising edge\n", irq_trig); 1098 irq_trig = IRQF_TRIGGER_RISING; 1099 break; 1100 } 1101 1102 /* An open drain line can be shared with several devices */ 1103 if (mpu3050->irq_opendrain) 1104 irq_trig |= IRQF_SHARED; 1105 1106 ret = request_threaded_irq(irq, 1107 mpu3050_irq_handler, 1108 mpu3050_irq_thread, 1109 irq_trig, 1110 mpu3050->trig->name, 1111 mpu3050->trig); 1112 if (ret) { 1113 dev_err(dev, "can't get IRQ %d, error %d\n", irq, ret); 1114 return ret; 1115 } 1116 1117 mpu3050->irq = irq; 1118 mpu3050->trig->dev.parent = dev; 1119 mpu3050->trig->ops = &mpu3050_trigger_ops; 1120 iio_trigger_set_drvdata(mpu3050->trig, indio_dev); 1121 1122 ret = iio_trigger_register(mpu3050->trig); 1123 if (ret) 1124 return ret; 1125 1126 indio_dev->trig = iio_trigger_get(mpu3050->trig); 1127 1128 return 0; 1129 } 1130 1131 int mpu3050_common_probe(struct device *dev, 1132 struct regmap *map, 1133 int irq, 1134 const char *name) 1135 { 1136 struct iio_dev *indio_dev; 1137 struct mpu3050 *mpu3050; 1138 unsigned int val; 1139 int ret; 1140 1141 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050)); 1142 if (!indio_dev) 1143 return -ENOMEM; 1144 mpu3050 = iio_priv(indio_dev); 1145 1146 mpu3050->dev = dev; 1147 mpu3050->map = map; 1148 mutex_init(&mpu3050->lock); 1149 /* Default fullscale: 2000 degrees per second */ 1150 mpu3050->fullscale = FS_2000_DPS; 1151 /* 1 kHz, divide by 100, default frequency = 10 Hz */ 1152 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ; 1153 mpu3050->divisor = 99; 1154 1155 /* Read the mounting matrix, if present */ 1156 ret = iio_read_mount_matrix(dev, &mpu3050->orientation); 1157 if (ret) 1158 return ret; 1159 1160 /* Fetch and turn on regulators */ 1161 mpu3050->regs[0].supply = mpu3050_reg_vdd; 1162 mpu3050->regs[1].supply = mpu3050_reg_vlogic; 1163 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs), 1164 mpu3050->regs); 1165 if (ret) { 1166 dev_err(dev, "Cannot get regulators\n"); 1167 return ret; 1168 } 1169 1170 ret = mpu3050_power_up(mpu3050); 1171 if (ret) 1172 return ret; 1173 1174 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val); 1175 if (ret) { 1176 dev_err(dev, "could not read device ID\n"); 1177 ret = -ENODEV; 1178 1179 goto err_power_down; 1180 } 1181 1182 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) { 1183 dev_err(dev, "unsupported chip id %02x\n", 1184 (u8)(val & MPU3050_CHIP_ID_MASK)); 1185 ret = -ENODEV; 1186 goto err_power_down; 1187 } 1188 1189 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val); 1190 if (ret) { 1191 dev_err(dev, "could not read device ID\n"); 1192 ret = -ENODEV; 1193 1194 goto err_power_down; 1195 } 1196 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n", 1197 ((val >> 4) & 0xf), (val & 0xf)); 1198 1199 ret = mpu3050_hw_init(mpu3050); 1200 if (ret) 1201 goto err_power_down; 1202 1203 indio_dev->channels = mpu3050_channels; 1204 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels); 1205 indio_dev->info = &mpu3050_info; 1206 indio_dev->available_scan_masks = mpu3050_scan_masks; 1207 indio_dev->modes = INDIO_DIRECT_MODE; 1208 indio_dev->name = name; 1209 1210 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time, 1211 mpu3050_trigger_handler, 1212 &mpu3050_buffer_setup_ops); 1213 if (ret) { 1214 dev_err(dev, "triggered buffer setup failed\n"); 1215 goto err_power_down; 1216 } 1217 1218 ret = iio_device_register(indio_dev); 1219 if (ret) { 1220 dev_err(dev, "device register failed\n"); 1221 goto err_cleanup_buffer; 1222 } 1223 1224 dev_set_drvdata(dev, indio_dev); 1225 1226 /* Check if we have an assigned IRQ to use as trigger */ 1227 if (irq) { 1228 ret = mpu3050_trigger_probe(indio_dev, irq); 1229 if (ret) 1230 dev_err(dev, "failed to register trigger\n"); 1231 } 1232 1233 /* Enable runtime PM */ 1234 pm_runtime_get_noresume(dev); 1235 pm_runtime_set_active(dev); 1236 pm_runtime_enable(dev); 1237 /* 1238 * Set autosuspend to two orders of magnitude larger than the 1239 * start-up time. 100ms start-up time means 10000ms autosuspend, 1240 * i.e. 10 seconds. 1241 */ 1242 pm_runtime_set_autosuspend_delay(dev, 10000); 1243 pm_runtime_use_autosuspend(dev); 1244 pm_runtime_put(dev); 1245 1246 return 0; 1247 1248 err_cleanup_buffer: 1249 iio_triggered_buffer_cleanup(indio_dev); 1250 err_power_down: 1251 mpu3050_power_down(mpu3050); 1252 1253 return ret; 1254 } 1255 1256 void mpu3050_common_remove(struct device *dev) 1257 { 1258 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1259 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1260 1261 pm_runtime_get_sync(dev); 1262 pm_runtime_put_noidle(dev); 1263 pm_runtime_disable(dev); 1264 iio_triggered_buffer_cleanup(indio_dev); 1265 if (mpu3050->irq) 1266 free_irq(mpu3050->irq, mpu3050); 1267 iio_device_unregister(indio_dev); 1268 mpu3050_power_down(mpu3050); 1269 } 1270 1271 static int mpu3050_runtime_suspend(struct device *dev) 1272 { 1273 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev))); 1274 } 1275 1276 static int mpu3050_runtime_resume(struct device *dev) 1277 { 1278 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev))); 1279 } 1280 1281 DEFINE_RUNTIME_DEV_PM_OPS(mpu3050_dev_pm_ops, mpu3050_runtime_suspend, 1282 mpu3050_runtime_resume, NULL); 1283 MODULE_AUTHOR("Linus Walleij"); 1284 MODULE_DESCRIPTION("MPU3050 gyroscope driver"); 1285 MODULE_LICENSE("GPL"); 1286