1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MPU3050 gyroscope driver 4 * 5 * Copyright (C) 2016 Linaro Ltd. 6 * Author: Linus Walleij <linus.walleij@linaro.org> 7 * 8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd 9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by 10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c. 11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011. 12 * 13 * TODO: add support for setting up the low pass 3dB frequency. 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/bitops.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/property.h> 30 #include <linux/random.h> 31 #include <linux/slab.h> 32 33 #include "mpu3050.h" 34 35 #define MPU3050_CHIP_ID 0x68 36 #define MPU3050_CHIP_ID_MASK 0x7E 37 38 /* 39 * Register map: anything suffixed *_H is a big-endian high byte and always 40 * followed by the corresponding low byte (*_L) even though these are not 41 * explicitly included in the register definitions. 42 */ 43 #define MPU3050_CHIP_ID_REG 0x00 44 #define MPU3050_PRODUCT_ID_REG 0x01 45 #define MPU3050_XG_OFFS_TC 0x05 46 #define MPU3050_YG_OFFS_TC 0x08 47 #define MPU3050_ZG_OFFS_TC 0x0B 48 #define MPU3050_X_OFFS_USR_H 0x0C 49 #define MPU3050_Y_OFFS_USR_H 0x0E 50 #define MPU3050_Z_OFFS_USR_H 0x10 51 #define MPU3050_FIFO_EN 0x12 52 #define MPU3050_AUX_VDDIO 0x13 53 #define MPU3050_SLV_ADDR 0x14 54 #define MPU3050_SMPLRT_DIV 0x15 55 #define MPU3050_DLPF_FS_SYNC 0x16 56 #define MPU3050_INT_CFG 0x17 57 #define MPU3050_AUX_ADDR 0x18 58 #define MPU3050_INT_STATUS 0x1A 59 #define MPU3050_TEMP_H 0x1B 60 #define MPU3050_XOUT_H 0x1D 61 #define MPU3050_YOUT_H 0x1F 62 #define MPU3050_ZOUT_H 0x21 63 #define MPU3050_DMP_CFG1 0x35 64 #define MPU3050_DMP_CFG2 0x36 65 #define MPU3050_BANK_SEL 0x37 66 #define MPU3050_MEM_START_ADDR 0x38 67 #define MPU3050_MEM_R_W 0x39 68 #define MPU3050_FIFO_COUNT_H 0x3A 69 #define MPU3050_FIFO_R 0x3C 70 #define MPU3050_USR_CTRL 0x3D 71 #define MPU3050_PWR_MGM 0x3E 72 73 /* MPU memory bank read options */ 74 #define MPU3050_MEM_PRFTCH BIT(5) 75 #define MPU3050_MEM_USER_BANK BIT(4) 76 /* Bits 8-11 select memory bank */ 77 #define MPU3050_MEM_RAM_BANK_0 0 78 #define MPU3050_MEM_RAM_BANK_1 1 79 #define MPU3050_MEM_RAM_BANK_2 2 80 #define MPU3050_MEM_RAM_BANK_3 3 81 #define MPU3050_MEM_OTP_BANK_0 4 82 83 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2)) 84 85 /* Register bits */ 86 87 /* FIFO Enable */ 88 #define MPU3050_FIFO_EN_FOOTER BIT(0) 89 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1) 90 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2) 91 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3) 92 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4) 93 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5) 94 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6) 95 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7) 96 97 /* 98 * Digital Low Pass filter (DLPF) 99 * Full Scale (FS) 100 * and Synchronization 101 */ 102 #define MPU3050_EXT_SYNC_NONE 0x00 103 #define MPU3050_EXT_SYNC_TEMP 0x20 104 #define MPU3050_EXT_SYNC_GYROX 0x40 105 #define MPU3050_EXT_SYNC_GYROY 0x60 106 #define MPU3050_EXT_SYNC_GYROZ 0x80 107 #define MPU3050_EXT_SYNC_ACCELX 0xA0 108 #define MPU3050_EXT_SYNC_ACCELY 0xC0 109 #define MPU3050_EXT_SYNC_ACCELZ 0xE0 110 #define MPU3050_EXT_SYNC_MASK 0xE0 111 #define MPU3050_EXT_SYNC_SHIFT 5 112 113 #define MPU3050_FS_250DPS 0x00 114 #define MPU3050_FS_500DPS 0x08 115 #define MPU3050_FS_1000DPS 0x10 116 #define MPU3050_FS_2000DPS 0x18 117 #define MPU3050_FS_MASK 0x18 118 #define MPU3050_FS_SHIFT 3 119 120 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00 121 #define MPU3050_DLPF_CFG_188HZ 0x01 122 #define MPU3050_DLPF_CFG_98HZ 0x02 123 #define MPU3050_DLPF_CFG_42HZ 0x03 124 #define MPU3050_DLPF_CFG_20HZ 0x04 125 #define MPU3050_DLPF_CFG_10HZ 0x05 126 #define MPU3050_DLPF_CFG_5HZ 0x06 127 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07 128 #define MPU3050_DLPF_CFG_MASK 0x07 129 #define MPU3050_DLPF_CFG_SHIFT 0 130 131 /* Interrupt config */ 132 #define MPU3050_INT_RAW_RDY_EN BIT(0) 133 #define MPU3050_INT_DMP_DONE_EN BIT(1) 134 #define MPU3050_INT_MPU_RDY_EN BIT(2) 135 #define MPU3050_INT_ANYRD_2CLEAR BIT(4) 136 #define MPU3050_INT_LATCH_EN BIT(5) 137 #define MPU3050_INT_OPEN BIT(6) 138 #define MPU3050_INT_ACTL BIT(7) 139 /* Interrupt status */ 140 #define MPU3050_INT_STATUS_RAW_RDY BIT(0) 141 #define MPU3050_INT_STATUS_DMP_DONE BIT(1) 142 #define MPU3050_INT_STATUS_MPU_RDY BIT(2) 143 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7) 144 /* USR_CTRL */ 145 #define MPU3050_USR_CTRL_FIFO_EN BIT(6) 146 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5) 147 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3) 148 #define MPU3050_USR_CTRL_FIFO_RST BIT(1) 149 #define MPU3050_USR_CTRL_GYRO_RST BIT(0) 150 /* PWR_MGM */ 151 #define MPU3050_PWR_MGM_PLL_X 0x01 152 #define MPU3050_PWR_MGM_PLL_Y 0x02 153 #define MPU3050_PWR_MGM_PLL_Z 0x03 154 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07 155 #define MPU3050_PWR_MGM_STBY_ZG BIT(3) 156 #define MPU3050_PWR_MGM_STBY_YG BIT(4) 157 #define MPU3050_PWR_MGM_STBY_XG BIT(5) 158 #define MPU3050_PWR_MGM_SLEEP BIT(6) 159 #define MPU3050_PWR_MGM_RESET BIT(7) 160 #define MPU3050_PWR_MGM_MASK 0xff 161 162 /* 163 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full 164 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale, 165 * in two's complement. 166 */ 167 static unsigned int mpu3050_fs_precision[] = { 168 IIO_DEGREE_TO_RAD(250), 169 IIO_DEGREE_TO_RAD(500), 170 IIO_DEGREE_TO_RAD(1000), 171 IIO_DEGREE_TO_RAD(2000) 172 }; 173 174 /* 175 * Regulator names 176 */ 177 static const char mpu3050_reg_vdd[] = "vdd"; 178 static const char mpu3050_reg_vlogic[] = "vlogic"; 179 180 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050) 181 { 182 unsigned int freq; 183 184 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) 185 freq = 8000; 186 else 187 freq = 1000; 188 freq /= (mpu3050->divisor + 1); 189 190 return freq; 191 } 192 193 static int mpu3050_start_sampling(struct mpu3050 *mpu3050) 194 { 195 __be16 raw_val[3]; 196 int ret; 197 int i; 198 199 /* Reset */ 200 ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM, 201 MPU3050_PWR_MGM_RESET); 202 if (ret) 203 return ret; 204 205 /* Turn on the Z-axis PLL */ 206 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 207 MPU3050_PWR_MGM_CLKSEL_MASK, 208 MPU3050_PWR_MGM_PLL_Z); 209 if (ret) 210 return ret; 211 212 /* Write calibration offset registers */ 213 for (i = 0; i < 3; i++) 214 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); 215 216 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val, 217 sizeof(raw_val)); 218 if (ret) 219 return ret; 220 221 /* Set low pass filter (sample rate), sync and full scale */ 222 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC, 223 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT | 224 mpu3050->fullscale << MPU3050_FS_SHIFT | 225 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT); 226 if (ret) 227 return ret; 228 229 /* Set up sampling frequency */ 230 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor); 231 if (ret) 232 return ret; 233 234 /* 235 * Max 50 ms start-up time after setting DLPF_FS_SYNC 236 * according to the data sheet, then wait for the next sample 237 * at this frequency T = 1000/f ms. 238 */ 239 msleep(50 + 1000 / mpu3050_get_freq(mpu3050)); 240 241 return 0; 242 } 243 244 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050) 245 { 246 int ret; 247 u8 divisor; 248 enum mpu3050_lpf lpf; 249 250 lpf = mpu3050->lpf; 251 divisor = mpu3050->divisor; 252 253 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */ 254 mpu3050->divisor = 0; /* Divide by 1 */ 255 ret = mpu3050_start_sampling(mpu3050); 256 257 mpu3050->lpf = lpf; 258 mpu3050->divisor = divisor; 259 260 return ret; 261 } 262 263 static int mpu3050_read_raw(struct iio_dev *indio_dev, 264 struct iio_chan_spec const *chan, 265 int *val, int *val2, 266 long mask) 267 { 268 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 269 int ret; 270 __be16 raw_val; 271 272 switch (mask) { 273 case IIO_CHAN_INFO_OFFSET: 274 switch (chan->type) { 275 case IIO_TEMP: 276 /* 277 * The temperature scaling is (x+23000)/280 Celsius 278 * for the "best fit straight line" temperature range 279 * of -30C..85C. The 23000 includes room temperature 280 * offset of +35C, 280 is the precision scale and x is 281 * the 16-bit signed integer reported by hardware. 282 * 283 * Temperature value itself represents temperature of 284 * the sensor die. 285 */ 286 *val = 23000; 287 return IIO_VAL_INT; 288 default: 289 return -EINVAL; 290 } 291 case IIO_CHAN_INFO_CALIBBIAS: 292 switch (chan->type) { 293 case IIO_ANGL_VEL: 294 *val = mpu3050->calibration[chan->scan_index-1]; 295 return IIO_VAL_INT; 296 default: 297 return -EINVAL; 298 } 299 case IIO_CHAN_INFO_SAMP_FREQ: 300 *val = mpu3050_get_freq(mpu3050); 301 return IIO_VAL_INT; 302 case IIO_CHAN_INFO_SCALE: 303 switch (chan->type) { 304 case IIO_TEMP: 305 /* Millidegrees, see about temperature scaling above */ 306 *val = 1000; 307 *val2 = 280; 308 return IIO_VAL_FRACTIONAL; 309 case IIO_ANGL_VEL: 310 /* 311 * Convert to the corresponding full scale in 312 * radians. All 16 bits are used with sign to 313 * span the available scale: to account for the one 314 * missing value if we multiply by 1/S16_MAX, instead 315 * multiply with 2/U16_MAX. 316 */ 317 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; 318 *val2 = U16_MAX; 319 return IIO_VAL_FRACTIONAL; 320 default: 321 return -EINVAL; 322 } 323 case IIO_CHAN_INFO_RAW: 324 /* Resume device */ 325 pm_runtime_get_sync(mpu3050->dev); 326 mutex_lock(&mpu3050->lock); 327 328 ret = mpu3050_set_8khz_samplerate(mpu3050); 329 if (ret) 330 goto out_read_raw_unlock; 331 332 switch (chan->type) { 333 case IIO_TEMP: 334 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, 335 &raw_val, sizeof(raw_val)); 336 if (ret) { 337 dev_err(mpu3050->dev, 338 "error reading temperature\n"); 339 goto out_read_raw_unlock; 340 } 341 342 *val = (s16)be16_to_cpu(raw_val); 343 ret = IIO_VAL_INT; 344 345 goto out_read_raw_unlock; 346 case IIO_ANGL_VEL: 347 ret = regmap_bulk_read(mpu3050->map, 348 MPU3050_AXIS_REGS(chan->scan_index-1), 349 &raw_val, 350 sizeof(raw_val)); 351 if (ret) { 352 dev_err(mpu3050->dev, 353 "error reading axis data\n"); 354 goto out_read_raw_unlock; 355 } 356 357 *val = be16_to_cpu(raw_val); 358 ret = IIO_VAL_INT; 359 360 goto out_read_raw_unlock; 361 default: 362 ret = -EINVAL; 363 goto out_read_raw_unlock; 364 } 365 default: 366 break; 367 } 368 369 return -EINVAL; 370 371 out_read_raw_unlock: 372 mutex_unlock(&mpu3050->lock); 373 pm_runtime_mark_last_busy(mpu3050->dev); 374 pm_runtime_put_autosuspend(mpu3050->dev); 375 376 return ret; 377 } 378 379 static int mpu3050_write_raw(struct iio_dev *indio_dev, 380 const struct iio_chan_spec *chan, 381 int val, int val2, long mask) 382 { 383 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 384 /* 385 * Couldn't figure out a way to precalculate these at compile time. 386 */ 387 unsigned int fs250 = 388 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2, 389 U16_MAX); 390 unsigned int fs500 = 391 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2, 392 U16_MAX); 393 unsigned int fs1000 = 394 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2, 395 U16_MAX); 396 unsigned int fs2000 = 397 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2, 398 U16_MAX); 399 400 switch (mask) { 401 case IIO_CHAN_INFO_CALIBBIAS: 402 if (chan->type != IIO_ANGL_VEL) 403 return -EINVAL; 404 mpu3050->calibration[chan->scan_index-1] = val; 405 return 0; 406 case IIO_CHAN_INFO_SAMP_FREQ: 407 /* 408 * The max samplerate is 8000 Hz, the minimum 409 * 1000 / 256 ~= 4 Hz 410 */ 411 if (val < 4 || val > 8000) 412 return -EINVAL; 413 414 /* 415 * Above 1000 Hz we must turn off the digital low pass filter 416 * so we get a base frequency of 8kHz to the divider 417 */ 418 if (val > 1000) { 419 mpu3050->lpf = LPF_256_HZ_NOLPF; 420 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; 421 return 0; 422 } 423 424 mpu3050->lpf = LPF_188_HZ; 425 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; 426 return 0; 427 case IIO_CHAN_INFO_SCALE: 428 if (chan->type != IIO_ANGL_VEL) 429 return -EINVAL; 430 /* 431 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s 432 * which means we need to round to the closest radians 433 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35 434 * rad/s. The scale is then for the 16 bits used to cover 435 * it 2/(2^16) of that. 436 */ 437 438 /* Just too large, set the max range */ 439 if (val != 0) { 440 mpu3050->fullscale = FS_2000_DPS; 441 return 0; 442 } 443 444 /* 445 * Now we're dealing with fractions below zero in millirad/s 446 * do some integer interpolation and match with the closest 447 * fullscale in the table. 448 */ 449 if (val2 <= fs250 || 450 val2 < ((fs500 + fs250) / 2)) 451 mpu3050->fullscale = FS_250_DPS; 452 else if (val2 <= fs500 || 453 val2 < ((fs1000 + fs500) / 2)) 454 mpu3050->fullscale = FS_500_DPS; 455 else if (val2 <= fs1000 || 456 val2 < ((fs2000 + fs1000) / 2)) 457 mpu3050->fullscale = FS_1000_DPS; 458 else 459 /* Catch-all */ 460 mpu3050->fullscale = FS_2000_DPS; 461 return 0; 462 default: 463 break; 464 } 465 466 return -EINVAL; 467 } 468 469 static irqreturn_t mpu3050_trigger_handler(int irq, void *p) 470 { 471 const struct iio_poll_func *pf = p; 472 struct iio_dev *indio_dev = pf->indio_dev; 473 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 474 int ret; 475 struct { 476 __be16 chans[4]; 477 s64 timestamp __aligned(8); 478 } scan; 479 s64 timestamp; 480 unsigned int datums_from_fifo = 0; 481 482 /* 483 * If we're using the hardware trigger, get the precise timestamp from 484 * the top half of the threaded IRQ handler. Otherwise get the 485 * timestamp here so it will be close in time to the actual values 486 * read from the registers. 487 */ 488 if (iio_trigger_using_own(indio_dev)) 489 timestamp = mpu3050->hw_timestamp; 490 else 491 timestamp = iio_get_time_ns(indio_dev); 492 493 mutex_lock(&mpu3050->lock); 494 495 /* Using the hardware IRQ trigger? Check the buffer then. */ 496 if (mpu3050->hw_irq_trigger) { 497 __be16 raw_fifocnt; 498 u16 fifocnt; 499 /* X, Y, Z + temperature */ 500 unsigned int bytes_per_datum = 8; 501 bool fifo_overflow = false; 502 503 ret = regmap_bulk_read(mpu3050->map, 504 MPU3050_FIFO_COUNT_H, 505 &raw_fifocnt, 506 sizeof(raw_fifocnt)); 507 if (ret) 508 goto out_trigger_unlock; 509 fifocnt = be16_to_cpu(raw_fifocnt); 510 511 if (fifocnt == 512) { 512 dev_info(mpu3050->dev, 513 "FIFO overflow! Emptying and resetting FIFO\n"); 514 fifo_overflow = true; 515 /* Reset and enable the FIFO */ 516 ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL, 517 MPU3050_USR_CTRL_FIFO_EN | 518 MPU3050_USR_CTRL_FIFO_RST); 519 if (ret) { 520 dev_info(mpu3050->dev, "error resetting FIFO\n"); 521 goto out_trigger_unlock; 522 } 523 mpu3050->pending_fifo_footer = false; 524 } 525 526 if (fifocnt) 527 dev_dbg(mpu3050->dev, 528 "%d bytes in the FIFO\n", 529 fifocnt); 530 531 while (!fifo_overflow && fifocnt > bytes_per_datum) { 532 unsigned int toread; 533 unsigned int offset; 534 __be16 fifo_values[5]; 535 536 /* 537 * If there is a FIFO footer in the pipe, first clear 538 * that out. This follows the complex algorithm in the 539 * datasheet that states that you may never leave the 540 * FIFO empty after the first reading: you have to 541 * always leave two footer bytes in it. The footer is 542 * in practice just two zero bytes. 543 */ 544 if (mpu3050->pending_fifo_footer) { 545 toread = bytes_per_datum + 2; 546 offset = 0; 547 } else { 548 toread = bytes_per_datum; 549 offset = 1; 550 /* Put in some dummy value */ 551 fifo_values[0] = cpu_to_be16(0xAAAA); 552 } 553 554 ret = regmap_bulk_read(mpu3050->map, 555 MPU3050_FIFO_R, 556 &fifo_values[offset], 557 toread); 558 if (ret) 559 goto out_trigger_unlock; 560 561 dev_dbg(mpu3050->dev, 562 "%04x %04x %04x %04x %04x\n", 563 fifo_values[0], 564 fifo_values[1], 565 fifo_values[2], 566 fifo_values[3], 567 fifo_values[4]); 568 569 /* Index past the footer (fifo_values[0]) and push */ 570 iio_push_to_buffers_with_ts_unaligned(indio_dev, 571 &fifo_values[1], 572 sizeof(__be16) * 4, 573 timestamp); 574 575 fifocnt -= toread; 576 datums_from_fifo++; 577 mpu3050->pending_fifo_footer = true; 578 579 /* 580 * If we're emptying the FIFO, just make sure to 581 * check if something new appeared. 582 */ 583 if (fifocnt < bytes_per_datum) { 584 ret = regmap_bulk_read(mpu3050->map, 585 MPU3050_FIFO_COUNT_H, 586 &raw_fifocnt, 587 sizeof(raw_fifocnt)); 588 if (ret) 589 goto out_trigger_unlock; 590 fifocnt = be16_to_cpu(raw_fifocnt); 591 } 592 593 if (fifocnt < bytes_per_datum) 594 dev_dbg(mpu3050->dev, 595 "%d bytes left in the FIFO\n", 596 fifocnt); 597 598 /* 599 * At this point, the timestamp that triggered the 600 * hardware interrupt is no longer valid for what 601 * we are reading (the interrupt likely fired for 602 * the value on the top of the FIFO), so set the 603 * timestamp to zero and let userspace deal with it. 604 */ 605 timestamp = 0; 606 } 607 } 608 609 /* 610 * If we picked some datums from the FIFO that's enough, else 611 * fall through and just read from the current value registers. 612 * This happens in two cases: 613 * 614 * - We are using some other trigger (external, like an HRTimer) 615 * than the sensor's own sample generator. In this case the 616 * sensor is just set to the max sampling frequency and we give 617 * the trigger a copy of the latest value every time we get here. 618 * 619 * - The hardware trigger is active but unused and we actually use 620 * another trigger which calls here with a frequency higher 621 * than what the device provides data. We will then just read 622 * duplicate values directly from the hardware registers. 623 */ 624 if (datums_from_fifo) { 625 dev_dbg(mpu3050->dev, 626 "read %d datums from the FIFO\n", 627 datums_from_fifo); 628 goto out_trigger_unlock; 629 } 630 631 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, scan.chans, 632 sizeof(scan.chans)); 633 if (ret) { 634 dev_err(mpu3050->dev, 635 "error reading axis data\n"); 636 goto out_trigger_unlock; 637 } 638 639 iio_push_to_buffers_with_timestamp(indio_dev, &scan, timestamp); 640 641 out_trigger_unlock: 642 mutex_unlock(&mpu3050->lock); 643 iio_trigger_notify_done(indio_dev->trig); 644 645 return IRQ_HANDLED; 646 } 647 648 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev) 649 { 650 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 651 652 pm_runtime_get_sync(mpu3050->dev); 653 654 /* Unless we have OUR trigger active, run at full speed */ 655 if (!mpu3050->hw_irq_trigger) 656 return mpu3050_set_8khz_samplerate(mpu3050); 657 658 return 0; 659 } 660 661 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev) 662 { 663 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 664 665 pm_runtime_mark_last_busy(mpu3050->dev); 666 pm_runtime_put_autosuspend(mpu3050->dev); 667 668 return 0; 669 } 670 671 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = { 672 .preenable = mpu3050_buffer_preenable, 673 .postdisable = mpu3050_buffer_postdisable, 674 }; 675 676 static const struct iio_mount_matrix * 677 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev, 678 const struct iio_chan_spec *chan) 679 { 680 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 681 682 return &mpu3050->orientation; 683 } 684 685 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = { 686 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix), 687 { }, 688 }; 689 690 #define MPU3050_AXIS_CHANNEL(axis, index) \ 691 { \ 692 .type = IIO_ANGL_VEL, \ 693 .modified = 1, \ 694 .channel2 = IIO_MOD_##axis, \ 695 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 696 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 697 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 698 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 699 .ext_info = mpu3050_ext_info, \ 700 .scan_index = index, \ 701 .scan_type = { \ 702 .sign = 's', \ 703 .realbits = 16, \ 704 .storagebits = 16, \ 705 .endianness = IIO_BE, \ 706 }, \ 707 } 708 709 static const struct iio_chan_spec mpu3050_channels[] = { 710 { 711 .type = IIO_TEMP, 712 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 713 BIT(IIO_CHAN_INFO_SCALE) | 714 BIT(IIO_CHAN_INFO_OFFSET), 715 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 716 .scan_index = 0, 717 .scan_type = { 718 .sign = 's', 719 .realbits = 16, 720 .storagebits = 16, 721 .endianness = IIO_BE, 722 }, 723 }, 724 MPU3050_AXIS_CHANNEL(X, 1), 725 MPU3050_AXIS_CHANNEL(Y, 2), 726 MPU3050_AXIS_CHANNEL(Z, 3), 727 IIO_CHAN_SOFT_TIMESTAMP(4), 728 }; 729 730 /* Four channels apart from timestamp, scan mask = 0x0f */ 731 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 }; 732 733 /* 734 * These are just the hardcoded factors resulting from the more elaborate 735 * calculations done with fractions in the scale raw get/set functions. 736 */ 737 static IIO_CONST_ATTR(anglevel_scale_available, 738 "0.000122070 " 739 "0.000274658 " 740 "0.000518798 " 741 "0.001068115"); 742 743 static struct attribute *mpu3050_attributes[] = { 744 &iio_const_attr_anglevel_scale_available.dev_attr.attr, 745 NULL, 746 }; 747 748 static const struct attribute_group mpu3050_attribute_group = { 749 .attrs = mpu3050_attributes, 750 }; 751 752 static const struct iio_info mpu3050_info = { 753 .read_raw = mpu3050_read_raw, 754 .write_raw = mpu3050_write_raw, 755 .attrs = &mpu3050_attribute_group, 756 }; 757 758 /** 759 * mpu3050_read_mem() - read MPU-3050 internal memory 760 * @mpu3050: device to read from 761 * @bank: target bank 762 * @addr: target address 763 * @len: number of bytes 764 * @buf: the buffer to store the read bytes in 765 */ 766 static int mpu3050_read_mem(struct mpu3050 *mpu3050, 767 u8 bank, 768 u8 addr, 769 u8 len, 770 u8 *buf) 771 { 772 int ret; 773 774 ret = regmap_write(mpu3050->map, 775 MPU3050_BANK_SEL, 776 bank); 777 if (ret) 778 return ret; 779 780 ret = regmap_write(mpu3050->map, 781 MPU3050_MEM_START_ADDR, 782 addr); 783 if (ret) 784 return ret; 785 786 return regmap_bulk_read(mpu3050->map, 787 MPU3050_MEM_R_W, 788 buf, 789 len); 790 } 791 792 static int mpu3050_hw_init(struct mpu3050 *mpu3050) 793 { 794 int ret; 795 __le64 otp_le; 796 u64 otp; 797 798 /* Reset */ 799 ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM, 800 MPU3050_PWR_MGM_RESET); 801 if (ret) 802 return ret; 803 804 /* Turn on the PLL */ 805 ret = regmap_update_bits(mpu3050->map, 806 MPU3050_PWR_MGM, 807 MPU3050_PWR_MGM_CLKSEL_MASK, 808 MPU3050_PWR_MGM_PLL_Z); 809 if (ret) 810 return ret; 811 812 /* Disable IRQs */ 813 ret = regmap_write(mpu3050->map, 814 MPU3050_INT_CFG, 815 0); 816 if (ret) 817 return ret; 818 819 /* Read out the 8 bytes of OTP (one-time-programmable) memory */ 820 ret = mpu3050_read_mem(mpu3050, 821 (MPU3050_MEM_PRFTCH | 822 MPU3050_MEM_USER_BANK | 823 MPU3050_MEM_OTP_BANK_0), 824 0, 825 sizeof(otp_le), 826 (u8 *)&otp_le); 827 if (ret) 828 return ret; 829 830 /* This is device-unique data so it goes into the entropy pool */ 831 add_device_randomness(&otp_le, sizeof(otp_le)); 832 833 otp = le64_to_cpu(otp_le); 834 835 dev_info(mpu3050->dev, 836 "die ID: %04llX, wafer ID: %02llX, A lot ID: %04llX, " 837 "W lot ID: %03llX, WP ID: %01llX, rev ID: %02llX\n", 838 /* Die ID, bits 0-12 */ 839 FIELD_GET(GENMASK_ULL(12, 0), otp), 840 /* Wafer ID, bits 13-17 */ 841 FIELD_GET(GENMASK_ULL(17, 13), otp), 842 /* A lot ID, bits 18-33 */ 843 FIELD_GET(GENMASK_ULL(33, 18), otp), 844 /* W lot ID, bits 34-45 */ 845 FIELD_GET(GENMASK_ULL(45, 34), otp), 846 /* WP ID, bits 47-49 */ 847 FIELD_GET(GENMASK_ULL(49, 47), otp), 848 /* rev ID, bits 50-55 */ 849 FIELD_GET(GENMASK_ULL(55, 50), otp)); 850 851 return 0; 852 } 853 854 static int mpu3050_power_up(struct mpu3050 *mpu3050) 855 { 856 int ret; 857 858 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 859 if (ret) { 860 dev_err(mpu3050->dev, "cannot enable regulators\n"); 861 return ret; 862 } 863 /* 864 * 20-100 ms start-up time for register read/write according to 865 * the datasheet, be on the safe side and wait 200 ms. 866 */ 867 msleep(200); 868 869 /* Take device out of sleep mode */ 870 ret = regmap_clear_bits(mpu3050->map, MPU3050_PWR_MGM, 871 MPU3050_PWR_MGM_SLEEP); 872 if (ret) { 873 regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 874 dev_err(mpu3050->dev, "error setting power mode\n"); 875 return ret; 876 } 877 usleep_range(10000, 20000); 878 879 return 0; 880 } 881 882 static int mpu3050_power_down(struct mpu3050 *mpu3050) 883 { 884 int ret; 885 886 /* 887 * Put MPU-3050 into sleep mode before cutting regulators. 888 * This is important, because we may not be the sole user 889 * of the regulator so the power may stay on after this, and 890 * then we would be wasting power unless we go to sleep mode 891 * first. 892 */ 893 ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM, 894 MPU3050_PWR_MGM_SLEEP); 895 if (ret) 896 dev_err(mpu3050->dev, "error putting to sleep\n"); 897 898 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 899 if (ret) 900 dev_err(mpu3050->dev, "error disabling regulators\n"); 901 902 return 0; 903 } 904 905 static irqreturn_t mpu3050_irq_handler(int irq, void *p) 906 { 907 struct iio_trigger *trig = p; 908 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 909 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 910 911 if (!mpu3050->hw_irq_trigger) 912 return IRQ_NONE; 913 914 /* Get the time stamp as close in time as possible */ 915 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev); 916 917 return IRQ_WAKE_THREAD; 918 } 919 920 static irqreturn_t mpu3050_irq_thread(int irq, void *p) 921 { 922 struct iio_trigger *trig = p; 923 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 924 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 925 unsigned int val; 926 int ret; 927 928 /* ACK IRQ and check if it was from us */ 929 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 930 if (ret) { 931 dev_err(mpu3050->dev, "error reading IRQ status\n"); 932 return IRQ_HANDLED; 933 } 934 if (!(val & MPU3050_INT_STATUS_RAW_RDY)) 935 return IRQ_NONE; 936 937 iio_trigger_poll_nested(p); 938 939 return IRQ_HANDLED; 940 } 941 942 /** 943 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state 944 * @trig: trigger instance 945 * @enable: true if trigger should be enabled, false to disable 946 */ 947 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig, 948 bool enable) 949 { 950 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 951 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 952 unsigned int val; 953 int ret; 954 955 /* Disabling trigger: disable interrupt and return */ 956 if (!enable) { 957 /* Disable all interrupts */ 958 ret = regmap_write(mpu3050->map, 959 MPU3050_INT_CFG, 960 0); 961 if (ret) 962 dev_err(mpu3050->dev, "error disabling IRQ\n"); 963 964 /* Clear IRQ flag */ 965 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 966 if (ret) 967 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 968 969 /* Disable all things in the FIFO and reset it */ 970 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 971 if (ret) 972 dev_err(mpu3050->dev, "error disabling FIFO\n"); 973 974 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL, 975 MPU3050_USR_CTRL_FIFO_RST); 976 if (ret) 977 dev_err(mpu3050->dev, "error resetting FIFO\n"); 978 979 pm_runtime_mark_last_busy(mpu3050->dev); 980 pm_runtime_put_autosuspend(mpu3050->dev); 981 mpu3050->hw_irq_trigger = false; 982 983 return 0; 984 } else { 985 /* Else we're enabling the trigger from this point */ 986 pm_runtime_get_sync(mpu3050->dev); 987 mpu3050->hw_irq_trigger = true; 988 989 /* Disable all things in the FIFO */ 990 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 991 if (ret) 992 return ret; 993 994 /* Reset and enable the FIFO */ 995 ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL, 996 MPU3050_USR_CTRL_FIFO_EN | 997 MPU3050_USR_CTRL_FIFO_RST); 998 if (ret) 999 return ret; 1000 1001 mpu3050->pending_fifo_footer = false; 1002 1003 /* Turn on the FIFO for temp+X+Y+Z */ 1004 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 1005 MPU3050_FIFO_EN_TEMP_OUT | 1006 MPU3050_FIFO_EN_GYRO_XOUT | 1007 MPU3050_FIFO_EN_GYRO_YOUT | 1008 MPU3050_FIFO_EN_GYRO_ZOUT | 1009 MPU3050_FIFO_EN_FOOTER); 1010 if (ret) 1011 return ret; 1012 1013 /* Configure the sample engine */ 1014 ret = mpu3050_start_sampling(mpu3050); 1015 if (ret) 1016 return ret; 1017 1018 /* Clear IRQ flag */ 1019 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 1020 if (ret) 1021 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 1022 1023 /* Give us interrupts whenever there is new data ready */ 1024 val = MPU3050_INT_RAW_RDY_EN; 1025 1026 if (mpu3050->irq_actl) 1027 val |= MPU3050_INT_ACTL; 1028 if (mpu3050->irq_latch) 1029 val |= MPU3050_INT_LATCH_EN; 1030 if (mpu3050->irq_opendrain) 1031 val |= MPU3050_INT_OPEN; 1032 1033 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); 1034 if (ret) 1035 return ret; 1036 } 1037 1038 return 0; 1039 } 1040 1041 static const struct iio_trigger_ops mpu3050_trigger_ops = { 1042 .set_trigger_state = mpu3050_drdy_trigger_set_state, 1043 }; 1044 1045 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq) 1046 { 1047 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1048 struct device *dev = mpu3050->dev; 1049 unsigned long irq_trig; 1050 int ret; 1051 1052 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev, 1053 "%s-dev%d", 1054 indio_dev->name, 1055 iio_device_id(indio_dev)); 1056 if (!mpu3050->trig) 1057 return -ENOMEM; 1058 1059 /* Check if IRQ is open drain */ 1060 mpu3050->irq_opendrain = device_property_read_bool(dev, "drive-open-drain"); 1061 1062 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1063 /* 1064 * Configure the interrupt generator hardware to supply whatever 1065 * the interrupt is configured for, edges low/high level low/high, 1066 * we can provide it all. 1067 */ 1068 switch (irq_trig) { 1069 case IRQF_TRIGGER_RISING: 1070 dev_info(&indio_dev->dev, 1071 "pulse interrupts on the rising edge\n"); 1072 break; 1073 case IRQF_TRIGGER_FALLING: 1074 mpu3050->irq_actl = true; 1075 dev_info(&indio_dev->dev, 1076 "pulse interrupts on the falling edge\n"); 1077 break; 1078 case IRQF_TRIGGER_HIGH: 1079 mpu3050->irq_latch = true; 1080 dev_info(&indio_dev->dev, 1081 "interrupts active high level\n"); 1082 /* 1083 * With level IRQs, we mask the IRQ until it is processed, 1084 * but with edge IRQs (pulses) we can queue several interrupts 1085 * in the top half. 1086 */ 1087 irq_trig |= IRQF_ONESHOT; 1088 break; 1089 case IRQF_TRIGGER_LOW: 1090 mpu3050->irq_latch = true; 1091 mpu3050->irq_actl = true; 1092 irq_trig |= IRQF_ONESHOT; 1093 dev_info(&indio_dev->dev, 1094 "interrupts active low level\n"); 1095 break; 1096 default: 1097 /* This is the most preferred mode, if possible */ 1098 dev_err(&indio_dev->dev, 1099 "unsupported IRQ trigger specified (%lx), enforce " 1100 "rising edge\n", irq_trig); 1101 irq_trig = IRQF_TRIGGER_RISING; 1102 break; 1103 } 1104 1105 /* An open drain line can be shared with several devices */ 1106 if (mpu3050->irq_opendrain) 1107 irq_trig |= IRQF_SHARED; 1108 1109 ret = request_threaded_irq(irq, 1110 mpu3050_irq_handler, 1111 mpu3050_irq_thread, 1112 irq_trig, 1113 mpu3050->trig->name, 1114 mpu3050->trig); 1115 if (ret) { 1116 dev_err(dev, "can't get IRQ %d, error %d\n", irq, ret); 1117 return ret; 1118 } 1119 1120 mpu3050->irq = irq; 1121 mpu3050->trig->dev.parent = dev; 1122 mpu3050->trig->ops = &mpu3050_trigger_ops; 1123 iio_trigger_set_drvdata(mpu3050->trig, indio_dev); 1124 1125 ret = iio_trigger_register(mpu3050->trig); 1126 if (ret) 1127 return ret; 1128 1129 indio_dev->trig = iio_trigger_get(mpu3050->trig); 1130 1131 return 0; 1132 } 1133 1134 int mpu3050_common_probe(struct device *dev, 1135 struct regmap *map, 1136 int irq, 1137 const char *name) 1138 { 1139 struct iio_dev *indio_dev; 1140 struct mpu3050 *mpu3050; 1141 unsigned int val; 1142 int ret; 1143 1144 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050)); 1145 if (!indio_dev) 1146 return -ENOMEM; 1147 mpu3050 = iio_priv(indio_dev); 1148 1149 mpu3050->dev = dev; 1150 mpu3050->map = map; 1151 mutex_init(&mpu3050->lock); 1152 /* Default fullscale: 2000 degrees per second */ 1153 mpu3050->fullscale = FS_2000_DPS; 1154 /* 1 kHz, divide by 100, default frequency = 10 Hz */ 1155 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ; 1156 mpu3050->divisor = 99; 1157 1158 /* Read the mounting matrix, if present */ 1159 ret = iio_read_mount_matrix(dev, &mpu3050->orientation); 1160 if (ret) 1161 return ret; 1162 1163 /* Fetch and turn on regulators */ 1164 mpu3050->regs[0].supply = mpu3050_reg_vdd; 1165 mpu3050->regs[1].supply = mpu3050_reg_vlogic; 1166 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs), 1167 mpu3050->regs); 1168 if (ret) { 1169 dev_err(dev, "Cannot get regulators\n"); 1170 return ret; 1171 } 1172 1173 ret = mpu3050_power_up(mpu3050); 1174 if (ret) 1175 return ret; 1176 1177 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val); 1178 if (ret) { 1179 dev_err(dev, "could not read device ID\n"); 1180 ret = -ENODEV; 1181 1182 goto err_power_down; 1183 } 1184 1185 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) { 1186 dev_err(dev, "unsupported chip id %02x\n", 1187 (u8)(val & MPU3050_CHIP_ID_MASK)); 1188 ret = -ENODEV; 1189 goto err_power_down; 1190 } 1191 1192 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val); 1193 if (ret) { 1194 dev_err(dev, "could not read device ID\n"); 1195 ret = -ENODEV; 1196 1197 goto err_power_down; 1198 } 1199 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n", 1200 ((val >> 4) & 0xf), (val & 0xf)); 1201 1202 ret = mpu3050_hw_init(mpu3050); 1203 if (ret) 1204 goto err_power_down; 1205 1206 indio_dev->channels = mpu3050_channels; 1207 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels); 1208 indio_dev->info = &mpu3050_info; 1209 indio_dev->available_scan_masks = mpu3050_scan_masks; 1210 indio_dev->modes = INDIO_DIRECT_MODE; 1211 indio_dev->name = name; 1212 1213 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time, 1214 mpu3050_trigger_handler, 1215 &mpu3050_buffer_setup_ops); 1216 if (ret) { 1217 dev_err(dev, "triggered buffer setup failed\n"); 1218 goto err_power_down; 1219 } 1220 1221 ret = iio_device_register(indio_dev); 1222 if (ret) { 1223 dev_err(dev, "device register failed\n"); 1224 goto err_cleanup_buffer; 1225 } 1226 1227 dev_set_drvdata(dev, indio_dev); 1228 1229 /* Check if we have an assigned IRQ to use as trigger */ 1230 if (irq) { 1231 ret = mpu3050_trigger_probe(indio_dev, irq); 1232 if (ret) 1233 dev_err(dev, "failed to register trigger\n"); 1234 } 1235 1236 /* Enable runtime PM */ 1237 pm_runtime_get_noresume(dev); 1238 pm_runtime_set_active(dev); 1239 pm_runtime_enable(dev); 1240 /* 1241 * Set autosuspend to two orders of magnitude larger than the 1242 * start-up time. 100ms start-up time means 10000ms autosuspend, 1243 * i.e. 10 seconds. 1244 */ 1245 pm_runtime_set_autosuspend_delay(dev, 10000); 1246 pm_runtime_use_autosuspend(dev); 1247 pm_runtime_put(dev); 1248 1249 return 0; 1250 1251 err_cleanup_buffer: 1252 iio_triggered_buffer_cleanup(indio_dev); 1253 err_power_down: 1254 mpu3050_power_down(mpu3050); 1255 1256 return ret; 1257 } 1258 1259 void mpu3050_common_remove(struct device *dev) 1260 { 1261 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1262 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1263 1264 pm_runtime_get_sync(dev); 1265 pm_runtime_put_noidle(dev); 1266 pm_runtime_disable(dev); 1267 iio_triggered_buffer_cleanup(indio_dev); 1268 if (mpu3050->irq) 1269 free_irq(mpu3050->irq, mpu3050); 1270 iio_device_unregister(indio_dev); 1271 mpu3050_power_down(mpu3050); 1272 } 1273 1274 static int mpu3050_runtime_suspend(struct device *dev) 1275 { 1276 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev))); 1277 } 1278 1279 static int mpu3050_runtime_resume(struct device *dev) 1280 { 1281 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev))); 1282 } 1283 1284 DEFINE_RUNTIME_DEV_PM_OPS(mpu3050_dev_pm_ops, mpu3050_runtime_suspend, 1285 mpu3050_runtime_resume, NULL); 1286 MODULE_AUTHOR("Linus Walleij"); 1287 MODULE_DESCRIPTION("MPU3050 gyroscope driver"); 1288 MODULE_LICENSE("GPL"); 1289