1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MPU3050 gyroscope driver 4 * 5 * Copyright (C) 2016 Linaro Ltd. 6 * Author: Linus Walleij <linus.walleij@linaro.org> 7 * 8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd 9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by 10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c. 11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011. 12 * 13 * TODO: add support for setting up the low pass 3dB frequency. 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/bitops.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/random.h> 30 #include <linux/slab.h> 31 32 #include "mpu3050.h" 33 34 #define MPU3050_CHIP_ID 0x68 35 #define MPU3050_CHIP_ID_MASK 0x7E 36 37 /* 38 * Register map: anything suffixed *_H is a big-endian high byte and always 39 * followed by the corresponding low byte (*_L) even though these are not 40 * explicitly included in the register definitions. 41 */ 42 #define MPU3050_CHIP_ID_REG 0x00 43 #define MPU3050_PRODUCT_ID_REG 0x01 44 #define MPU3050_XG_OFFS_TC 0x05 45 #define MPU3050_YG_OFFS_TC 0x08 46 #define MPU3050_ZG_OFFS_TC 0x0B 47 #define MPU3050_X_OFFS_USR_H 0x0C 48 #define MPU3050_Y_OFFS_USR_H 0x0E 49 #define MPU3050_Z_OFFS_USR_H 0x10 50 #define MPU3050_FIFO_EN 0x12 51 #define MPU3050_AUX_VDDIO 0x13 52 #define MPU3050_SLV_ADDR 0x14 53 #define MPU3050_SMPLRT_DIV 0x15 54 #define MPU3050_DLPF_FS_SYNC 0x16 55 #define MPU3050_INT_CFG 0x17 56 #define MPU3050_AUX_ADDR 0x18 57 #define MPU3050_INT_STATUS 0x1A 58 #define MPU3050_TEMP_H 0x1B 59 #define MPU3050_XOUT_H 0x1D 60 #define MPU3050_YOUT_H 0x1F 61 #define MPU3050_ZOUT_H 0x21 62 #define MPU3050_DMP_CFG1 0x35 63 #define MPU3050_DMP_CFG2 0x36 64 #define MPU3050_BANK_SEL 0x37 65 #define MPU3050_MEM_START_ADDR 0x38 66 #define MPU3050_MEM_R_W 0x39 67 #define MPU3050_FIFO_COUNT_H 0x3A 68 #define MPU3050_FIFO_R 0x3C 69 #define MPU3050_USR_CTRL 0x3D 70 #define MPU3050_PWR_MGM 0x3E 71 72 /* MPU memory bank read options */ 73 #define MPU3050_MEM_PRFTCH BIT(5) 74 #define MPU3050_MEM_USER_BANK BIT(4) 75 /* Bits 8-11 select memory bank */ 76 #define MPU3050_MEM_RAM_BANK_0 0 77 #define MPU3050_MEM_RAM_BANK_1 1 78 #define MPU3050_MEM_RAM_BANK_2 2 79 #define MPU3050_MEM_RAM_BANK_3 3 80 #define MPU3050_MEM_OTP_BANK_0 4 81 82 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2)) 83 84 /* Register bits */ 85 86 /* FIFO Enable */ 87 #define MPU3050_FIFO_EN_FOOTER BIT(0) 88 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1) 89 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2) 90 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3) 91 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4) 92 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5) 93 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6) 94 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7) 95 96 /* 97 * Digital Low Pass filter (DLPF) 98 * Full Scale (FS) 99 * and Synchronization 100 */ 101 #define MPU3050_EXT_SYNC_NONE 0x00 102 #define MPU3050_EXT_SYNC_TEMP 0x20 103 #define MPU3050_EXT_SYNC_GYROX 0x40 104 #define MPU3050_EXT_SYNC_GYROY 0x60 105 #define MPU3050_EXT_SYNC_GYROZ 0x80 106 #define MPU3050_EXT_SYNC_ACCELX 0xA0 107 #define MPU3050_EXT_SYNC_ACCELY 0xC0 108 #define MPU3050_EXT_SYNC_ACCELZ 0xE0 109 #define MPU3050_EXT_SYNC_MASK 0xE0 110 #define MPU3050_EXT_SYNC_SHIFT 5 111 112 #define MPU3050_FS_250DPS 0x00 113 #define MPU3050_FS_500DPS 0x08 114 #define MPU3050_FS_1000DPS 0x10 115 #define MPU3050_FS_2000DPS 0x18 116 #define MPU3050_FS_MASK 0x18 117 #define MPU3050_FS_SHIFT 3 118 119 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00 120 #define MPU3050_DLPF_CFG_188HZ 0x01 121 #define MPU3050_DLPF_CFG_98HZ 0x02 122 #define MPU3050_DLPF_CFG_42HZ 0x03 123 #define MPU3050_DLPF_CFG_20HZ 0x04 124 #define MPU3050_DLPF_CFG_10HZ 0x05 125 #define MPU3050_DLPF_CFG_5HZ 0x06 126 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07 127 #define MPU3050_DLPF_CFG_MASK 0x07 128 #define MPU3050_DLPF_CFG_SHIFT 0 129 130 /* Interrupt config */ 131 #define MPU3050_INT_RAW_RDY_EN BIT(0) 132 #define MPU3050_INT_DMP_DONE_EN BIT(1) 133 #define MPU3050_INT_MPU_RDY_EN BIT(2) 134 #define MPU3050_INT_ANYRD_2CLEAR BIT(4) 135 #define MPU3050_INT_LATCH_EN BIT(5) 136 #define MPU3050_INT_OPEN BIT(6) 137 #define MPU3050_INT_ACTL BIT(7) 138 /* Interrupt status */ 139 #define MPU3050_INT_STATUS_RAW_RDY BIT(0) 140 #define MPU3050_INT_STATUS_DMP_DONE BIT(1) 141 #define MPU3050_INT_STATUS_MPU_RDY BIT(2) 142 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7) 143 /* USR_CTRL */ 144 #define MPU3050_USR_CTRL_FIFO_EN BIT(6) 145 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5) 146 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3) 147 #define MPU3050_USR_CTRL_FIFO_RST BIT(1) 148 #define MPU3050_USR_CTRL_GYRO_RST BIT(0) 149 /* PWR_MGM */ 150 #define MPU3050_PWR_MGM_PLL_X 0x01 151 #define MPU3050_PWR_MGM_PLL_Y 0x02 152 #define MPU3050_PWR_MGM_PLL_Z 0x03 153 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07 154 #define MPU3050_PWR_MGM_STBY_ZG BIT(3) 155 #define MPU3050_PWR_MGM_STBY_YG BIT(4) 156 #define MPU3050_PWR_MGM_STBY_XG BIT(5) 157 #define MPU3050_PWR_MGM_SLEEP BIT(6) 158 #define MPU3050_PWR_MGM_RESET BIT(7) 159 #define MPU3050_PWR_MGM_MASK 0xff 160 161 /* 162 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full 163 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale, 164 * in two's complement. 165 */ 166 static unsigned int mpu3050_fs_precision[] = { 167 IIO_DEGREE_TO_RAD(250), 168 IIO_DEGREE_TO_RAD(500), 169 IIO_DEGREE_TO_RAD(1000), 170 IIO_DEGREE_TO_RAD(2000) 171 }; 172 173 /* 174 * Regulator names 175 */ 176 static const char mpu3050_reg_vdd[] = "vdd"; 177 static const char mpu3050_reg_vlogic[] = "vlogic"; 178 179 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050) 180 { 181 unsigned int freq; 182 183 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) 184 freq = 8000; 185 else 186 freq = 1000; 187 freq /= (mpu3050->divisor + 1); 188 189 return freq; 190 } 191 192 static int mpu3050_start_sampling(struct mpu3050 *mpu3050) 193 { 194 __be16 raw_val[3]; 195 int ret; 196 int i; 197 198 /* Reset */ 199 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 200 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET); 201 if (ret) 202 return ret; 203 204 /* Turn on the Z-axis PLL */ 205 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 206 MPU3050_PWR_MGM_CLKSEL_MASK, 207 MPU3050_PWR_MGM_PLL_Z); 208 if (ret) 209 return ret; 210 211 /* Write calibration offset registers */ 212 for (i = 0; i < 3; i++) 213 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); 214 215 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val, 216 sizeof(raw_val)); 217 if (ret) 218 return ret; 219 220 /* Set low pass filter (sample rate), sync and full scale */ 221 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC, 222 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT | 223 mpu3050->fullscale << MPU3050_FS_SHIFT | 224 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT); 225 if (ret) 226 return ret; 227 228 /* Set up sampling frequency */ 229 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor); 230 if (ret) 231 return ret; 232 233 /* 234 * Max 50 ms start-up time after setting DLPF_FS_SYNC 235 * according to the data sheet, then wait for the next sample 236 * at this frequency T = 1000/f ms. 237 */ 238 msleep(50 + 1000 / mpu3050_get_freq(mpu3050)); 239 240 return 0; 241 } 242 243 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050) 244 { 245 int ret; 246 u8 divisor; 247 enum mpu3050_lpf lpf; 248 249 lpf = mpu3050->lpf; 250 divisor = mpu3050->divisor; 251 252 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */ 253 mpu3050->divisor = 0; /* Divide by 1 */ 254 ret = mpu3050_start_sampling(mpu3050); 255 256 mpu3050->lpf = lpf; 257 mpu3050->divisor = divisor; 258 259 return ret; 260 } 261 262 static int mpu3050_read_raw(struct iio_dev *indio_dev, 263 struct iio_chan_spec const *chan, 264 int *val, int *val2, 265 long mask) 266 { 267 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 268 int ret; 269 __be16 raw_val; 270 271 switch (mask) { 272 case IIO_CHAN_INFO_OFFSET: 273 switch (chan->type) { 274 case IIO_TEMP: 275 /* The temperature scaling is (x+23000)/280 Celsius */ 276 *val = 23000; 277 return IIO_VAL_INT; 278 default: 279 return -EINVAL; 280 } 281 case IIO_CHAN_INFO_CALIBBIAS: 282 switch (chan->type) { 283 case IIO_ANGL_VEL: 284 *val = mpu3050->calibration[chan->scan_index-1]; 285 return IIO_VAL_INT; 286 default: 287 return -EINVAL; 288 } 289 case IIO_CHAN_INFO_SAMP_FREQ: 290 *val = mpu3050_get_freq(mpu3050); 291 return IIO_VAL_INT; 292 case IIO_CHAN_INFO_SCALE: 293 switch (chan->type) { 294 case IIO_TEMP: 295 /* Millidegrees, see about temperature scaling above */ 296 *val = 1000; 297 *val2 = 280; 298 return IIO_VAL_FRACTIONAL; 299 case IIO_ANGL_VEL: 300 /* 301 * Convert to the corresponding full scale in 302 * radians. All 16 bits are used with sign to 303 * span the available scale: to account for the one 304 * missing value if we multiply by 1/S16_MAX, instead 305 * multiply with 2/U16_MAX. 306 */ 307 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; 308 *val2 = U16_MAX; 309 return IIO_VAL_FRACTIONAL; 310 default: 311 return -EINVAL; 312 } 313 case IIO_CHAN_INFO_RAW: 314 /* Resume device */ 315 pm_runtime_get_sync(mpu3050->dev); 316 mutex_lock(&mpu3050->lock); 317 318 ret = mpu3050_set_8khz_samplerate(mpu3050); 319 if (ret) 320 goto out_read_raw_unlock; 321 322 switch (chan->type) { 323 case IIO_TEMP: 324 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, 325 &raw_val, sizeof(raw_val)); 326 if (ret) { 327 dev_err(mpu3050->dev, 328 "error reading temperature\n"); 329 goto out_read_raw_unlock; 330 } 331 332 *val = be16_to_cpu(raw_val); 333 ret = IIO_VAL_INT; 334 335 goto out_read_raw_unlock; 336 case IIO_ANGL_VEL: 337 ret = regmap_bulk_read(mpu3050->map, 338 MPU3050_AXIS_REGS(chan->scan_index-1), 339 &raw_val, 340 sizeof(raw_val)); 341 if (ret) { 342 dev_err(mpu3050->dev, 343 "error reading axis data\n"); 344 goto out_read_raw_unlock; 345 } 346 347 *val = be16_to_cpu(raw_val); 348 ret = IIO_VAL_INT; 349 350 goto out_read_raw_unlock; 351 default: 352 ret = -EINVAL; 353 goto out_read_raw_unlock; 354 } 355 default: 356 break; 357 } 358 359 return -EINVAL; 360 361 out_read_raw_unlock: 362 mutex_unlock(&mpu3050->lock); 363 pm_runtime_mark_last_busy(mpu3050->dev); 364 pm_runtime_put_autosuspend(mpu3050->dev); 365 366 return ret; 367 } 368 369 static int mpu3050_write_raw(struct iio_dev *indio_dev, 370 const struct iio_chan_spec *chan, 371 int val, int val2, long mask) 372 { 373 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 374 /* 375 * Couldn't figure out a way to precalculate these at compile time. 376 */ 377 unsigned int fs250 = 378 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2, 379 U16_MAX); 380 unsigned int fs500 = 381 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2, 382 U16_MAX); 383 unsigned int fs1000 = 384 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2, 385 U16_MAX); 386 unsigned int fs2000 = 387 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2, 388 U16_MAX); 389 390 switch (mask) { 391 case IIO_CHAN_INFO_CALIBBIAS: 392 if (chan->type != IIO_ANGL_VEL) 393 return -EINVAL; 394 mpu3050->calibration[chan->scan_index-1] = val; 395 return 0; 396 case IIO_CHAN_INFO_SAMP_FREQ: 397 /* 398 * The max samplerate is 8000 Hz, the minimum 399 * 1000 / 256 ~= 4 Hz 400 */ 401 if (val < 4 || val > 8000) 402 return -EINVAL; 403 404 /* 405 * Above 1000 Hz we must turn off the digital low pass filter 406 * so we get a base frequency of 8kHz to the divider 407 */ 408 if (val > 1000) { 409 mpu3050->lpf = LPF_256_HZ_NOLPF; 410 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; 411 return 0; 412 } 413 414 mpu3050->lpf = LPF_188_HZ; 415 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; 416 return 0; 417 case IIO_CHAN_INFO_SCALE: 418 if (chan->type != IIO_ANGL_VEL) 419 return -EINVAL; 420 /* 421 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s 422 * which means we need to round to the closest radians 423 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35 424 * rad/s. The scale is then for the 16 bits used to cover 425 * it 2/(2^16) of that. 426 */ 427 428 /* Just too large, set the max range */ 429 if (val != 0) { 430 mpu3050->fullscale = FS_2000_DPS; 431 return 0; 432 } 433 434 /* 435 * Now we're dealing with fractions below zero in millirad/s 436 * do some integer interpolation and match with the closest 437 * fullscale in the table. 438 */ 439 if (val2 <= fs250 || 440 val2 < ((fs500 + fs250) / 2)) 441 mpu3050->fullscale = FS_250_DPS; 442 else if (val2 <= fs500 || 443 val2 < ((fs1000 + fs500) / 2)) 444 mpu3050->fullscale = FS_500_DPS; 445 else if (val2 <= fs1000 || 446 val2 < ((fs2000 + fs1000) / 2)) 447 mpu3050->fullscale = FS_1000_DPS; 448 else 449 /* Catch-all */ 450 mpu3050->fullscale = FS_2000_DPS; 451 return 0; 452 default: 453 break; 454 } 455 456 return -EINVAL; 457 } 458 459 static irqreturn_t mpu3050_trigger_handler(int irq, void *p) 460 { 461 const struct iio_poll_func *pf = p; 462 struct iio_dev *indio_dev = pf->indio_dev; 463 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 464 int ret; 465 /* 466 * Temperature 1*16 bits 467 * Three axes 3*16 bits 468 * Timestamp 64 bits (4*16 bits) 469 * Sum total 8*16 bits 470 */ 471 __be16 hw_values[8]; 472 s64 timestamp; 473 unsigned int datums_from_fifo = 0; 474 475 /* 476 * If we're using the hardware trigger, get the precise timestamp from 477 * the top half of the threaded IRQ handler. Otherwise get the 478 * timestamp here so it will be close in time to the actual values 479 * read from the registers. 480 */ 481 if (iio_trigger_using_own(indio_dev)) 482 timestamp = mpu3050->hw_timestamp; 483 else 484 timestamp = iio_get_time_ns(indio_dev); 485 486 mutex_lock(&mpu3050->lock); 487 488 /* Using the hardware IRQ trigger? Check the buffer then. */ 489 if (mpu3050->hw_irq_trigger) { 490 __be16 raw_fifocnt; 491 u16 fifocnt; 492 /* X, Y, Z + temperature */ 493 unsigned int bytes_per_datum = 8; 494 bool fifo_overflow = false; 495 496 ret = regmap_bulk_read(mpu3050->map, 497 MPU3050_FIFO_COUNT_H, 498 &raw_fifocnt, 499 sizeof(raw_fifocnt)); 500 if (ret) 501 goto out_trigger_unlock; 502 fifocnt = be16_to_cpu(raw_fifocnt); 503 504 if (fifocnt == 512) { 505 dev_info(mpu3050->dev, 506 "FIFO overflow! Emptying and resetting FIFO\n"); 507 fifo_overflow = true; 508 /* Reset and enable the FIFO */ 509 ret = regmap_update_bits(mpu3050->map, 510 MPU3050_USR_CTRL, 511 MPU3050_USR_CTRL_FIFO_EN | 512 MPU3050_USR_CTRL_FIFO_RST, 513 MPU3050_USR_CTRL_FIFO_EN | 514 MPU3050_USR_CTRL_FIFO_RST); 515 if (ret) { 516 dev_info(mpu3050->dev, "error resetting FIFO\n"); 517 goto out_trigger_unlock; 518 } 519 mpu3050->pending_fifo_footer = false; 520 } 521 522 if (fifocnt) 523 dev_dbg(mpu3050->dev, 524 "%d bytes in the FIFO\n", 525 fifocnt); 526 527 while (!fifo_overflow && fifocnt > bytes_per_datum) { 528 unsigned int toread; 529 unsigned int offset; 530 __be16 fifo_values[5]; 531 532 /* 533 * If there is a FIFO footer in the pipe, first clear 534 * that out. This follows the complex algorithm in the 535 * datasheet that states that you may never leave the 536 * FIFO empty after the first reading: you have to 537 * always leave two footer bytes in it. The footer is 538 * in practice just two zero bytes. 539 */ 540 if (mpu3050->pending_fifo_footer) { 541 toread = bytes_per_datum + 2; 542 offset = 0; 543 } else { 544 toread = bytes_per_datum; 545 offset = 1; 546 /* Put in some dummy value */ 547 fifo_values[0] = cpu_to_be16(0xAAAA); 548 } 549 550 ret = regmap_bulk_read(mpu3050->map, 551 MPU3050_FIFO_R, 552 &fifo_values[offset], 553 toread); 554 555 dev_dbg(mpu3050->dev, 556 "%04x %04x %04x %04x %04x\n", 557 fifo_values[0], 558 fifo_values[1], 559 fifo_values[2], 560 fifo_values[3], 561 fifo_values[4]); 562 563 /* Index past the footer (fifo_values[0]) and push */ 564 iio_push_to_buffers_with_timestamp(indio_dev, 565 &fifo_values[1], 566 timestamp); 567 568 fifocnt -= toread; 569 datums_from_fifo++; 570 mpu3050->pending_fifo_footer = true; 571 572 /* 573 * If we're emptying the FIFO, just make sure to 574 * check if something new appeared. 575 */ 576 if (fifocnt < bytes_per_datum) { 577 ret = regmap_bulk_read(mpu3050->map, 578 MPU3050_FIFO_COUNT_H, 579 &raw_fifocnt, 580 sizeof(raw_fifocnt)); 581 if (ret) 582 goto out_trigger_unlock; 583 fifocnt = be16_to_cpu(raw_fifocnt); 584 } 585 586 if (fifocnt < bytes_per_datum) 587 dev_dbg(mpu3050->dev, 588 "%d bytes left in the FIFO\n", 589 fifocnt); 590 591 /* 592 * At this point, the timestamp that triggered the 593 * hardware interrupt is no longer valid for what 594 * we are reading (the interrupt likely fired for 595 * the value on the top of the FIFO), so set the 596 * timestamp to zero and let userspace deal with it. 597 */ 598 timestamp = 0; 599 } 600 } 601 602 /* 603 * If we picked some datums from the FIFO that's enough, else 604 * fall through and just read from the current value registers. 605 * This happens in two cases: 606 * 607 * - We are using some other trigger (external, like an HRTimer) 608 * than the sensor's own sample generator. In this case the 609 * sensor is just set to the max sampling frequency and we give 610 * the trigger a copy of the latest value every time we get here. 611 * 612 * - The hardware trigger is active but unused and we actually use 613 * another trigger which calls here with a frequency higher 614 * than what the device provides data. We will then just read 615 * duplicate values directly from the hardware registers. 616 */ 617 if (datums_from_fifo) { 618 dev_dbg(mpu3050->dev, 619 "read %d datums from the FIFO\n", 620 datums_from_fifo); 621 goto out_trigger_unlock; 622 } 623 624 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values, 625 sizeof(hw_values)); 626 if (ret) { 627 dev_err(mpu3050->dev, 628 "error reading axis data\n"); 629 goto out_trigger_unlock; 630 } 631 632 iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp); 633 634 out_trigger_unlock: 635 mutex_unlock(&mpu3050->lock); 636 iio_trigger_notify_done(indio_dev->trig); 637 638 return IRQ_HANDLED; 639 } 640 641 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev) 642 { 643 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 644 645 pm_runtime_get_sync(mpu3050->dev); 646 647 /* Unless we have OUR trigger active, run at full speed */ 648 if (!mpu3050->hw_irq_trigger) 649 return mpu3050_set_8khz_samplerate(mpu3050); 650 651 return 0; 652 } 653 654 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev) 655 { 656 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 657 658 pm_runtime_mark_last_busy(mpu3050->dev); 659 pm_runtime_put_autosuspend(mpu3050->dev); 660 661 return 0; 662 } 663 664 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = { 665 .preenable = mpu3050_buffer_preenable, 666 .postdisable = mpu3050_buffer_postdisable, 667 }; 668 669 static const struct iio_mount_matrix * 670 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev, 671 const struct iio_chan_spec *chan) 672 { 673 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 674 675 return &mpu3050->orientation; 676 } 677 678 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = { 679 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix), 680 { }, 681 }; 682 683 #define MPU3050_AXIS_CHANNEL(axis, index) \ 684 { \ 685 .type = IIO_ANGL_VEL, \ 686 .modified = 1, \ 687 .channel2 = IIO_MOD_##axis, \ 688 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 689 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 690 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 691 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 692 .ext_info = mpu3050_ext_info, \ 693 .scan_index = index, \ 694 .scan_type = { \ 695 .sign = 's', \ 696 .realbits = 16, \ 697 .storagebits = 16, \ 698 .endianness = IIO_BE, \ 699 }, \ 700 } 701 702 static const struct iio_chan_spec mpu3050_channels[] = { 703 { 704 .type = IIO_TEMP, 705 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 706 BIT(IIO_CHAN_INFO_SCALE) | 707 BIT(IIO_CHAN_INFO_OFFSET), 708 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 709 .scan_index = 0, 710 .scan_type = { 711 .sign = 's', 712 .realbits = 16, 713 .storagebits = 16, 714 .endianness = IIO_BE, 715 }, 716 }, 717 MPU3050_AXIS_CHANNEL(X, 1), 718 MPU3050_AXIS_CHANNEL(Y, 2), 719 MPU3050_AXIS_CHANNEL(Z, 3), 720 IIO_CHAN_SOFT_TIMESTAMP(4), 721 }; 722 723 /* Four channels apart from timestamp, scan mask = 0x0f */ 724 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 }; 725 726 /* 727 * These are just the hardcoded factors resulting from the more elaborate 728 * calculations done with fractions in the scale raw get/set functions. 729 */ 730 static IIO_CONST_ATTR(anglevel_scale_available, 731 "0.000122070 " 732 "0.000274658 " 733 "0.000518798 " 734 "0.001068115"); 735 736 static struct attribute *mpu3050_attributes[] = { 737 &iio_const_attr_anglevel_scale_available.dev_attr.attr, 738 NULL, 739 }; 740 741 static const struct attribute_group mpu3050_attribute_group = { 742 .attrs = mpu3050_attributes, 743 }; 744 745 static const struct iio_info mpu3050_info = { 746 .read_raw = mpu3050_read_raw, 747 .write_raw = mpu3050_write_raw, 748 .attrs = &mpu3050_attribute_group, 749 }; 750 751 /** 752 * mpu3050_read_mem() - read MPU-3050 internal memory 753 * @mpu3050: device to read from 754 * @bank: target bank 755 * @addr: target address 756 * @len: number of bytes 757 * @buf: the buffer to store the read bytes in 758 */ 759 static int mpu3050_read_mem(struct mpu3050 *mpu3050, 760 u8 bank, 761 u8 addr, 762 u8 len, 763 u8 *buf) 764 { 765 int ret; 766 767 ret = regmap_write(mpu3050->map, 768 MPU3050_BANK_SEL, 769 bank); 770 if (ret) 771 return ret; 772 773 ret = regmap_write(mpu3050->map, 774 MPU3050_MEM_START_ADDR, 775 addr); 776 if (ret) 777 return ret; 778 779 return regmap_bulk_read(mpu3050->map, 780 MPU3050_MEM_R_W, 781 buf, 782 len); 783 } 784 785 static int mpu3050_hw_init(struct mpu3050 *mpu3050) 786 { 787 int ret; 788 __le64 otp_le; 789 u64 otp; 790 791 /* Reset */ 792 ret = regmap_update_bits(mpu3050->map, 793 MPU3050_PWR_MGM, 794 MPU3050_PWR_MGM_RESET, 795 MPU3050_PWR_MGM_RESET); 796 if (ret) 797 return ret; 798 799 /* Turn on the PLL */ 800 ret = regmap_update_bits(mpu3050->map, 801 MPU3050_PWR_MGM, 802 MPU3050_PWR_MGM_CLKSEL_MASK, 803 MPU3050_PWR_MGM_PLL_Z); 804 if (ret) 805 return ret; 806 807 /* Disable IRQs */ 808 ret = regmap_write(mpu3050->map, 809 MPU3050_INT_CFG, 810 0); 811 if (ret) 812 return ret; 813 814 /* Read out the 8 bytes of OTP (one-time-programmable) memory */ 815 ret = mpu3050_read_mem(mpu3050, 816 (MPU3050_MEM_PRFTCH | 817 MPU3050_MEM_USER_BANK | 818 MPU3050_MEM_OTP_BANK_0), 819 0, 820 sizeof(otp_le), 821 (u8 *)&otp_le); 822 if (ret) 823 return ret; 824 825 /* This is device-unique data so it goes into the entropy pool */ 826 add_device_randomness(&otp_le, sizeof(otp_le)); 827 828 otp = le64_to_cpu(otp_le); 829 830 dev_info(mpu3050->dev, 831 "die ID: %04llX, wafer ID: %02llX, A lot ID: %04llX, " 832 "W lot ID: %03llX, WP ID: %01llX, rev ID: %02llX\n", 833 /* Die ID, bits 0-12 */ 834 FIELD_GET(GENMASK_ULL(12, 0), otp), 835 /* Wafer ID, bits 13-17 */ 836 FIELD_GET(GENMASK_ULL(17, 13), otp), 837 /* A lot ID, bits 18-33 */ 838 FIELD_GET(GENMASK_ULL(33, 18), otp), 839 /* W lot ID, bits 34-45 */ 840 FIELD_GET(GENMASK_ULL(45, 34), otp), 841 /* WP ID, bits 47-49 */ 842 FIELD_GET(GENMASK_ULL(49, 47), otp), 843 /* rev ID, bits 50-55 */ 844 FIELD_GET(GENMASK_ULL(55, 50), otp)); 845 846 return 0; 847 } 848 849 static int mpu3050_power_up(struct mpu3050 *mpu3050) 850 { 851 int ret; 852 853 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 854 if (ret) { 855 dev_err(mpu3050->dev, "cannot enable regulators\n"); 856 return ret; 857 } 858 /* 859 * 20-100 ms start-up time for register read/write according to 860 * the datasheet, be on the safe side and wait 200 ms. 861 */ 862 msleep(200); 863 864 /* Take device out of sleep mode */ 865 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 866 MPU3050_PWR_MGM_SLEEP, 0); 867 if (ret) { 868 dev_err(mpu3050->dev, "error setting power mode\n"); 869 return ret; 870 } 871 usleep_range(10000, 20000); 872 873 return 0; 874 } 875 876 static int mpu3050_power_down(struct mpu3050 *mpu3050) 877 { 878 int ret; 879 880 /* 881 * Put MPU-3050 into sleep mode before cutting regulators. 882 * This is important, because we may not be the sole user 883 * of the regulator so the power may stay on after this, and 884 * then we would be wasting power unless we go to sleep mode 885 * first. 886 */ 887 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 888 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP); 889 if (ret) 890 dev_err(mpu3050->dev, "error putting to sleep\n"); 891 892 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 893 if (ret) 894 dev_err(mpu3050->dev, "error disabling regulators\n"); 895 896 return 0; 897 } 898 899 static irqreturn_t mpu3050_irq_handler(int irq, void *p) 900 { 901 struct iio_trigger *trig = p; 902 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 903 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 904 905 if (!mpu3050->hw_irq_trigger) 906 return IRQ_NONE; 907 908 /* Get the time stamp as close in time as possible */ 909 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev); 910 911 return IRQ_WAKE_THREAD; 912 } 913 914 static irqreturn_t mpu3050_irq_thread(int irq, void *p) 915 { 916 struct iio_trigger *trig = p; 917 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 918 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 919 unsigned int val; 920 int ret; 921 922 /* ACK IRQ and check if it was from us */ 923 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 924 if (ret) { 925 dev_err(mpu3050->dev, "error reading IRQ status\n"); 926 return IRQ_HANDLED; 927 } 928 if (!(val & MPU3050_INT_STATUS_RAW_RDY)) 929 return IRQ_NONE; 930 931 iio_trigger_poll_chained(p); 932 933 return IRQ_HANDLED; 934 } 935 936 /** 937 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state 938 * @trig: trigger instance 939 * @enable: true if trigger should be enabled, false to disable 940 */ 941 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig, 942 bool enable) 943 { 944 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 945 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 946 unsigned int val; 947 int ret; 948 949 /* Disabling trigger: disable interrupt and return */ 950 if (!enable) { 951 /* Disable all interrupts */ 952 ret = regmap_write(mpu3050->map, 953 MPU3050_INT_CFG, 954 0); 955 if (ret) 956 dev_err(mpu3050->dev, "error disabling IRQ\n"); 957 958 /* Clear IRQ flag */ 959 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 960 if (ret) 961 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 962 963 /* Disable all things in the FIFO and reset it */ 964 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 965 if (ret) 966 dev_err(mpu3050->dev, "error disabling FIFO\n"); 967 968 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL, 969 MPU3050_USR_CTRL_FIFO_RST); 970 if (ret) 971 dev_err(mpu3050->dev, "error resetting FIFO\n"); 972 973 pm_runtime_mark_last_busy(mpu3050->dev); 974 pm_runtime_put_autosuspend(mpu3050->dev); 975 mpu3050->hw_irq_trigger = false; 976 977 return 0; 978 } else { 979 /* Else we're enabling the trigger from this point */ 980 pm_runtime_get_sync(mpu3050->dev); 981 mpu3050->hw_irq_trigger = true; 982 983 /* Disable all things in the FIFO */ 984 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 985 if (ret) 986 return ret; 987 988 /* Reset and enable the FIFO */ 989 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL, 990 MPU3050_USR_CTRL_FIFO_EN | 991 MPU3050_USR_CTRL_FIFO_RST, 992 MPU3050_USR_CTRL_FIFO_EN | 993 MPU3050_USR_CTRL_FIFO_RST); 994 if (ret) 995 return ret; 996 997 mpu3050->pending_fifo_footer = false; 998 999 /* Turn on the FIFO for temp+X+Y+Z */ 1000 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 1001 MPU3050_FIFO_EN_TEMP_OUT | 1002 MPU3050_FIFO_EN_GYRO_XOUT | 1003 MPU3050_FIFO_EN_GYRO_YOUT | 1004 MPU3050_FIFO_EN_GYRO_ZOUT | 1005 MPU3050_FIFO_EN_FOOTER); 1006 if (ret) 1007 return ret; 1008 1009 /* Configure the sample engine */ 1010 ret = mpu3050_start_sampling(mpu3050); 1011 if (ret) 1012 return ret; 1013 1014 /* Clear IRQ flag */ 1015 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 1016 if (ret) 1017 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 1018 1019 /* Give us interrupts whenever there is new data ready */ 1020 val = MPU3050_INT_RAW_RDY_EN; 1021 1022 if (mpu3050->irq_actl) 1023 val |= MPU3050_INT_ACTL; 1024 if (mpu3050->irq_latch) 1025 val |= MPU3050_INT_LATCH_EN; 1026 if (mpu3050->irq_opendrain) 1027 val |= MPU3050_INT_OPEN; 1028 1029 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); 1030 if (ret) 1031 return ret; 1032 } 1033 1034 return 0; 1035 } 1036 1037 static const struct iio_trigger_ops mpu3050_trigger_ops = { 1038 .set_trigger_state = mpu3050_drdy_trigger_set_state, 1039 }; 1040 1041 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq) 1042 { 1043 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1044 unsigned long irq_trig; 1045 int ret; 1046 1047 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev, 1048 "%s-dev%d", 1049 indio_dev->name, 1050 indio_dev->id); 1051 if (!mpu3050->trig) 1052 return -ENOMEM; 1053 1054 /* Check if IRQ is open drain */ 1055 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain")) 1056 mpu3050->irq_opendrain = true; 1057 1058 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1059 /* 1060 * Configure the interrupt generator hardware to supply whatever 1061 * the interrupt is configured for, edges low/high level low/high, 1062 * we can provide it all. 1063 */ 1064 switch (irq_trig) { 1065 case IRQF_TRIGGER_RISING: 1066 dev_info(&indio_dev->dev, 1067 "pulse interrupts on the rising edge\n"); 1068 break; 1069 case IRQF_TRIGGER_FALLING: 1070 mpu3050->irq_actl = true; 1071 dev_info(&indio_dev->dev, 1072 "pulse interrupts on the falling edge\n"); 1073 break; 1074 case IRQF_TRIGGER_HIGH: 1075 mpu3050->irq_latch = true; 1076 dev_info(&indio_dev->dev, 1077 "interrupts active high level\n"); 1078 /* 1079 * With level IRQs, we mask the IRQ until it is processed, 1080 * but with edge IRQs (pulses) we can queue several interrupts 1081 * in the top half. 1082 */ 1083 irq_trig |= IRQF_ONESHOT; 1084 break; 1085 case IRQF_TRIGGER_LOW: 1086 mpu3050->irq_latch = true; 1087 mpu3050->irq_actl = true; 1088 irq_trig |= IRQF_ONESHOT; 1089 dev_info(&indio_dev->dev, 1090 "interrupts active low level\n"); 1091 break; 1092 default: 1093 /* This is the most preferred mode, if possible */ 1094 dev_err(&indio_dev->dev, 1095 "unsupported IRQ trigger specified (%lx), enforce " 1096 "rising edge\n", irq_trig); 1097 irq_trig = IRQF_TRIGGER_RISING; 1098 break; 1099 } 1100 1101 /* An open drain line can be shared with several devices */ 1102 if (mpu3050->irq_opendrain) 1103 irq_trig |= IRQF_SHARED; 1104 1105 ret = request_threaded_irq(irq, 1106 mpu3050_irq_handler, 1107 mpu3050_irq_thread, 1108 irq_trig, 1109 mpu3050->trig->name, 1110 mpu3050->trig); 1111 if (ret) { 1112 dev_err(mpu3050->dev, 1113 "can't get IRQ %d, error %d\n", irq, ret); 1114 return ret; 1115 } 1116 1117 mpu3050->irq = irq; 1118 mpu3050->trig->dev.parent = mpu3050->dev; 1119 mpu3050->trig->ops = &mpu3050_trigger_ops; 1120 iio_trigger_set_drvdata(mpu3050->trig, indio_dev); 1121 1122 ret = iio_trigger_register(mpu3050->trig); 1123 if (ret) 1124 return ret; 1125 1126 indio_dev->trig = iio_trigger_get(mpu3050->trig); 1127 1128 return 0; 1129 } 1130 1131 int mpu3050_common_probe(struct device *dev, 1132 struct regmap *map, 1133 int irq, 1134 const char *name) 1135 { 1136 struct iio_dev *indio_dev; 1137 struct mpu3050 *mpu3050; 1138 unsigned int val; 1139 int ret; 1140 1141 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050)); 1142 if (!indio_dev) 1143 return -ENOMEM; 1144 mpu3050 = iio_priv(indio_dev); 1145 1146 mpu3050->dev = dev; 1147 mpu3050->map = map; 1148 mutex_init(&mpu3050->lock); 1149 /* Default fullscale: 2000 degrees per second */ 1150 mpu3050->fullscale = FS_2000_DPS; 1151 /* 1 kHz, divide by 100, default frequency = 10 Hz */ 1152 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ; 1153 mpu3050->divisor = 99; 1154 1155 /* Read the mounting matrix, if present */ 1156 ret = iio_read_mount_matrix(dev, "mount-matrix", &mpu3050->orientation); 1157 if (ret) 1158 return ret; 1159 1160 /* Fetch and turn on regulators */ 1161 mpu3050->regs[0].supply = mpu3050_reg_vdd; 1162 mpu3050->regs[1].supply = mpu3050_reg_vlogic; 1163 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs), 1164 mpu3050->regs); 1165 if (ret) { 1166 dev_err(dev, "Cannot get regulators\n"); 1167 return ret; 1168 } 1169 1170 ret = mpu3050_power_up(mpu3050); 1171 if (ret) 1172 return ret; 1173 1174 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val); 1175 if (ret) { 1176 dev_err(dev, "could not read device ID\n"); 1177 ret = -ENODEV; 1178 1179 goto err_power_down; 1180 } 1181 1182 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) { 1183 dev_err(dev, "unsupported chip id %02x\n", 1184 (u8)(val & MPU3050_CHIP_ID_MASK)); 1185 ret = -ENODEV; 1186 goto err_power_down; 1187 } 1188 1189 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val); 1190 if (ret) { 1191 dev_err(dev, "could not read device ID\n"); 1192 ret = -ENODEV; 1193 1194 goto err_power_down; 1195 } 1196 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n", 1197 ((val >> 4) & 0xf), (val & 0xf)); 1198 1199 ret = mpu3050_hw_init(mpu3050); 1200 if (ret) 1201 goto err_power_down; 1202 1203 indio_dev->channels = mpu3050_channels; 1204 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels); 1205 indio_dev->info = &mpu3050_info; 1206 indio_dev->available_scan_masks = mpu3050_scan_masks; 1207 indio_dev->modes = INDIO_DIRECT_MODE; 1208 indio_dev->name = name; 1209 1210 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time, 1211 mpu3050_trigger_handler, 1212 &mpu3050_buffer_setup_ops); 1213 if (ret) { 1214 dev_err(dev, "triggered buffer setup failed\n"); 1215 goto err_power_down; 1216 } 1217 1218 ret = iio_device_register(indio_dev); 1219 if (ret) { 1220 dev_err(dev, "device register failed\n"); 1221 goto err_cleanup_buffer; 1222 } 1223 1224 dev_set_drvdata(dev, indio_dev); 1225 1226 /* Check if we have an assigned IRQ to use as trigger */ 1227 if (irq) { 1228 ret = mpu3050_trigger_probe(indio_dev, irq); 1229 if (ret) 1230 dev_err(dev, "failed to register trigger\n"); 1231 } 1232 1233 /* Enable runtime PM */ 1234 pm_runtime_get_noresume(dev); 1235 pm_runtime_set_active(dev); 1236 pm_runtime_enable(dev); 1237 /* 1238 * Set autosuspend to two orders of magnitude larger than the 1239 * start-up time. 100ms start-up time means 10000ms autosuspend, 1240 * i.e. 10 seconds. 1241 */ 1242 pm_runtime_set_autosuspend_delay(dev, 10000); 1243 pm_runtime_use_autosuspend(dev); 1244 pm_runtime_put(dev); 1245 1246 return 0; 1247 1248 err_cleanup_buffer: 1249 iio_triggered_buffer_cleanup(indio_dev); 1250 err_power_down: 1251 mpu3050_power_down(mpu3050); 1252 1253 return ret; 1254 } 1255 EXPORT_SYMBOL(mpu3050_common_probe); 1256 1257 int mpu3050_common_remove(struct device *dev) 1258 { 1259 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1260 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1261 1262 pm_runtime_get_sync(dev); 1263 pm_runtime_put_noidle(dev); 1264 pm_runtime_disable(dev); 1265 iio_triggered_buffer_cleanup(indio_dev); 1266 if (mpu3050->irq) 1267 free_irq(mpu3050->irq, mpu3050); 1268 iio_device_unregister(indio_dev); 1269 mpu3050_power_down(mpu3050); 1270 1271 return 0; 1272 } 1273 EXPORT_SYMBOL(mpu3050_common_remove); 1274 1275 #ifdef CONFIG_PM 1276 static int mpu3050_runtime_suspend(struct device *dev) 1277 { 1278 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev))); 1279 } 1280 1281 static int mpu3050_runtime_resume(struct device *dev) 1282 { 1283 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev))); 1284 } 1285 #endif /* CONFIG_PM */ 1286 1287 const struct dev_pm_ops mpu3050_dev_pm_ops = { 1288 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1289 pm_runtime_force_resume) 1290 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend, 1291 mpu3050_runtime_resume, NULL) 1292 }; 1293 EXPORT_SYMBOL(mpu3050_dev_pm_ops); 1294 1295 MODULE_AUTHOR("Linus Walleij"); 1296 MODULE_DESCRIPTION("MPU3050 gyroscope driver"); 1297 MODULE_LICENSE("GPL"); 1298