1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BMG160 Gyro Sensor driver 4 * Copyright (c) 2014, Intel Corporation. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/pm.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/iio/iio.h> 14 #include <linux/iio/sysfs.h> 15 #include <linux/iio/buffer.h> 16 #include <linux/iio/trigger.h> 17 #include <linux/iio/events.h> 18 #include <linux/iio/trigger_consumer.h> 19 #include <linux/iio/triggered_buffer.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include "bmg160.h" 23 24 #define BMG160_IRQ_NAME "bmg160_event" 25 26 #define BMG160_REG_CHIP_ID 0x00 27 #define BMG160_CHIP_ID_VAL 0x0F 28 29 #define BMG160_REG_PMU_LPW 0x11 30 #define BMG160_MODE_NORMAL 0x00 31 #define BMG160_MODE_DEEP_SUSPEND 0x20 32 #define BMG160_MODE_SUSPEND 0x80 33 34 #define BMG160_REG_RANGE 0x0F 35 36 #define BMG160_RANGE_2000DPS 0 37 #define BMG160_RANGE_1000DPS 1 38 #define BMG160_RANGE_500DPS 2 39 #define BMG160_RANGE_250DPS 3 40 #define BMG160_RANGE_125DPS 4 41 42 #define BMG160_REG_PMU_BW 0x10 43 #define BMG160_NO_FILTER 0 44 #define BMG160_DEF_BW 100 45 #define BMG160_REG_PMU_BW_RES BIT(7) 46 47 #define BMG160_GYRO_REG_RESET 0x14 48 #define BMG160_GYRO_RESET_VAL 0xb6 49 50 #define BMG160_REG_INT_MAP_0 0x17 51 #define BMG160_INT_MAP_0_BIT_ANY BIT(1) 52 53 #define BMG160_REG_INT_MAP_1 0x18 54 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) 55 56 #define BMG160_REG_INT_RST_LATCH 0x21 57 #define BMG160_INT_MODE_LATCH_RESET 0x80 58 #define BMG160_INT_MODE_LATCH_INT 0x0F 59 #define BMG160_INT_MODE_NON_LATCH_INT 0x00 60 61 #define BMG160_REG_INT_EN_0 0x15 62 #define BMG160_DATA_ENABLE_INT BIT(7) 63 64 #define BMG160_REG_INT_EN_1 0x16 65 #define BMG160_INT1_BIT_OD BIT(1) 66 67 #define BMG160_REG_XOUT_L 0x02 68 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2)) 69 70 #define BMG160_REG_SLOPE_THRES 0x1B 71 #define BMG160_SLOPE_THRES_MASK 0x0F 72 73 #define BMG160_REG_MOTION_INTR 0x1C 74 #define BMG160_INT_MOTION_X BIT(0) 75 #define BMG160_INT_MOTION_Y BIT(1) 76 #define BMG160_INT_MOTION_Z BIT(2) 77 #define BMG160_ANY_DUR_MASK 0x30 78 #define BMG160_ANY_DUR_SHIFT 4 79 80 #define BMG160_REG_INT_STATUS_2 0x0B 81 #define BMG160_ANY_MOTION_MASK 0x07 82 #define BMG160_ANY_MOTION_BIT_X BIT(0) 83 #define BMG160_ANY_MOTION_BIT_Y BIT(1) 84 #define BMG160_ANY_MOTION_BIT_Z BIT(2) 85 86 #define BMG160_REG_TEMP 0x08 87 #define BMG160_TEMP_CENTER_VAL 23 88 89 #define BMG160_MAX_STARTUP_TIME_MS 80 90 91 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000 92 93 struct bmg160_data { 94 struct regmap *regmap; 95 struct iio_trigger *dready_trig; 96 struct iio_trigger *motion_trig; 97 struct iio_mount_matrix orientation; 98 struct mutex mutex; 99 /* Ensure naturally aligned timestamp */ 100 struct { 101 s16 chans[3]; 102 s64 timestamp __aligned(8); 103 } scan; 104 u32 dps_range; 105 int ev_enable_state; 106 int slope_thres; 107 bool dready_trigger_on; 108 bool motion_trigger_on; 109 int irq; 110 }; 111 112 enum bmg160_axis { 113 AXIS_X, 114 AXIS_Y, 115 AXIS_Z, 116 AXIS_MAX, 117 }; 118 119 static const struct { 120 int odr; 121 int filter; 122 int bw_bits; 123 } bmg160_samp_freq_table[] = { {100, 32, 0x07}, 124 {200, 64, 0x06}, 125 {100, 12, 0x05}, 126 {200, 23, 0x04}, 127 {400, 47, 0x03}, 128 {1000, 116, 0x02}, 129 {2000, 230, 0x01} }; 130 131 static const struct { 132 int scale; 133 int dps_range; 134 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS}, 135 { 532, BMG160_RANGE_1000DPS}, 136 { 266, BMG160_RANGE_500DPS}, 137 { 133, BMG160_RANGE_250DPS}, 138 { 66, BMG160_RANGE_125DPS} }; 139 140 static int bmg160_set_mode(struct bmg160_data *data, u8 mode) 141 { 142 struct device *dev = regmap_get_device(data->regmap); 143 int ret; 144 145 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode); 146 if (ret < 0) { 147 dev_err(dev, "Error writing reg_pmu_lpw\n"); 148 return ret; 149 } 150 151 return 0; 152 } 153 154 static int bmg160_convert_freq_to_bit(int val) 155 { 156 int i; 157 158 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 159 if (bmg160_samp_freq_table[i].odr == val) 160 return bmg160_samp_freq_table[i].bw_bits; 161 } 162 163 return -EINVAL; 164 } 165 166 static int bmg160_set_bw(struct bmg160_data *data, int val) 167 { 168 struct device *dev = regmap_get_device(data->regmap); 169 int ret; 170 int bw_bits; 171 172 bw_bits = bmg160_convert_freq_to_bit(val); 173 if (bw_bits < 0) 174 return bw_bits; 175 176 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits); 177 if (ret < 0) { 178 dev_err(dev, "Error writing reg_pmu_bw\n"); 179 return ret; 180 } 181 182 return 0; 183 } 184 185 static int bmg160_get_filter(struct bmg160_data *data, int *val) 186 { 187 struct device *dev = regmap_get_device(data->regmap); 188 int ret; 189 int i; 190 unsigned int bw_bits; 191 192 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 193 if (ret < 0) { 194 dev_err(dev, "Error reading reg_pmu_bw\n"); 195 return ret; 196 } 197 198 /* Ignore the readonly reserved bit. */ 199 bw_bits &= ~BMG160_REG_PMU_BW_RES; 200 201 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 202 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) 203 break; 204 } 205 206 *val = bmg160_samp_freq_table[i].filter; 207 208 return ret ? ret : IIO_VAL_INT; 209 } 210 211 212 static int bmg160_set_filter(struct bmg160_data *data, int val) 213 { 214 struct device *dev = regmap_get_device(data->regmap); 215 int ret; 216 int i; 217 218 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 219 if (bmg160_samp_freq_table[i].filter == val) 220 break; 221 } 222 223 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, 224 bmg160_samp_freq_table[i].bw_bits); 225 if (ret < 0) { 226 dev_err(dev, "Error writing reg_pmu_bw\n"); 227 return ret; 228 } 229 230 return 0; 231 } 232 233 static int bmg160_chip_init(struct bmg160_data *data) 234 { 235 struct device *dev = regmap_get_device(data->regmap); 236 int ret; 237 unsigned int val; 238 239 /* 240 * Reset chip to get it in a known good state. A delay of 30ms after 241 * reset is required according to the datasheet. 242 */ 243 regmap_write(data->regmap, BMG160_GYRO_REG_RESET, 244 BMG160_GYRO_RESET_VAL); 245 usleep_range(30000, 30700); 246 247 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); 248 if (ret < 0) { 249 dev_err(dev, "Error reading reg_chip_id\n"); 250 return ret; 251 } 252 253 dev_dbg(dev, "Chip Id %x\n", val); 254 if (val != BMG160_CHIP_ID_VAL) { 255 dev_err(dev, "invalid chip %x\n", val); 256 return -ENODEV; 257 } 258 259 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 260 if (ret < 0) 261 return ret; 262 263 /* Wait upto 500 ms to be ready after changing mode */ 264 usleep_range(500, 1000); 265 266 /* Set Bandwidth */ 267 ret = bmg160_set_bw(data, BMG160_DEF_BW); 268 if (ret < 0) 269 return ret; 270 271 /* Set Default Range */ 272 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS); 273 if (ret < 0) { 274 dev_err(dev, "Error writing reg_range\n"); 275 return ret; 276 } 277 data->dps_range = BMG160_RANGE_500DPS; 278 279 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); 280 if (ret < 0) { 281 dev_err(dev, "Error reading reg_slope_thres\n"); 282 return ret; 283 } 284 data->slope_thres = val; 285 286 /* Set default interrupt mode */ 287 ret = regmap_clear_bits(data->regmap, BMG160_REG_INT_EN_1, 288 BMG160_INT1_BIT_OD); 289 if (ret < 0) { 290 dev_err(dev, "Error updating bits in reg_int_en_1\n"); 291 return ret; 292 } 293 294 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 295 BMG160_INT_MODE_LATCH_INT | 296 BMG160_INT_MODE_LATCH_RESET); 297 if (ret < 0) { 298 dev_err(dev, 299 "Error writing reg_motion_intr\n"); 300 return ret; 301 } 302 303 return 0; 304 } 305 306 static int bmg160_set_power_state(struct bmg160_data *data, bool on) 307 { 308 #ifdef CONFIG_PM 309 struct device *dev = regmap_get_device(data->regmap); 310 int ret; 311 312 if (on) 313 ret = pm_runtime_get_sync(dev); 314 else { 315 pm_runtime_mark_last_busy(dev); 316 ret = pm_runtime_put_autosuspend(dev); 317 } 318 319 if (ret < 0) { 320 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on); 321 322 if (on) 323 pm_runtime_put_noidle(dev); 324 325 return ret; 326 } 327 #endif 328 329 return 0; 330 } 331 332 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data, 333 bool status) 334 { 335 struct device *dev = regmap_get_device(data->regmap); 336 int ret; 337 338 /* Enable/Disable INT_MAP0 mapping */ 339 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0, 340 BMG160_INT_MAP_0_BIT_ANY, 341 (status ? BMG160_INT_MAP_0_BIT_ANY : 0)); 342 if (ret < 0) { 343 dev_err(dev, "Error updating bits reg_int_map0\n"); 344 return ret; 345 } 346 347 /* Enable/Disable slope interrupts */ 348 if (status) { 349 /* Update slope thres */ 350 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES, 351 data->slope_thres); 352 if (ret < 0) { 353 dev_err(dev, "Error writing reg_slope_thres\n"); 354 return ret; 355 } 356 357 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR, 358 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y | 359 BMG160_INT_MOTION_Z); 360 if (ret < 0) { 361 dev_err(dev, "Error writing reg_motion_intr\n"); 362 return ret; 363 } 364 365 /* 366 * New data interrupt is always non-latched, 367 * which will have higher priority, so no need 368 * to set latched mode, we will be flooded anyway with INTR 369 */ 370 if (!data->dready_trigger_on) { 371 ret = regmap_write(data->regmap, 372 BMG160_REG_INT_RST_LATCH, 373 BMG160_INT_MODE_LATCH_INT | 374 BMG160_INT_MODE_LATCH_RESET); 375 if (ret < 0) { 376 dev_err(dev, "Error writing reg_rst_latch\n"); 377 return ret; 378 } 379 } 380 381 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 382 BMG160_DATA_ENABLE_INT); 383 384 } else { 385 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 386 } 387 388 if (ret < 0) { 389 dev_err(dev, "Error writing reg_int_en0\n"); 390 return ret; 391 } 392 393 return 0; 394 } 395 396 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data, 397 bool status) 398 { 399 struct device *dev = regmap_get_device(data->regmap); 400 int ret; 401 402 /* Enable/Disable INT_MAP1 mapping */ 403 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1, 404 BMG160_INT_MAP_1_BIT_NEW_DATA, 405 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0)); 406 if (ret < 0) { 407 dev_err(dev, "Error updating bits in reg_int_map1\n"); 408 return ret; 409 } 410 411 if (status) { 412 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 413 BMG160_INT_MODE_NON_LATCH_INT | 414 BMG160_INT_MODE_LATCH_RESET); 415 if (ret < 0) { 416 dev_err(dev, "Error writing reg_rst_latch\n"); 417 return ret; 418 } 419 420 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 421 BMG160_DATA_ENABLE_INT); 422 423 } else { 424 /* Restore interrupt mode */ 425 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 426 BMG160_INT_MODE_LATCH_INT | 427 BMG160_INT_MODE_LATCH_RESET); 428 if (ret < 0) { 429 dev_err(dev, "Error writing reg_rst_latch\n"); 430 return ret; 431 } 432 433 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 434 } 435 436 if (ret < 0) { 437 dev_err(dev, "Error writing reg_int_en0\n"); 438 return ret; 439 } 440 441 return 0; 442 } 443 444 static int bmg160_get_bw(struct bmg160_data *data, int *val) 445 { 446 struct device *dev = regmap_get_device(data->regmap); 447 int i; 448 unsigned int bw_bits; 449 int ret; 450 451 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); 452 if (ret < 0) { 453 dev_err(dev, "Error reading reg_pmu_bw\n"); 454 return ret; 455 } 456 457 /* Ignore the readonly reserved bit. */ 458 bw_bits &= ~BMG160_REG_PMU_BW_RES; 459 460 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 461 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) { 462 *val = bmg160_samp_freq_table[i].odr; 463 return IIO_VAL_INT; 464 } 465 } 466 467 return -EINVAL; 468 } 469 470 static int bmg160_set_scale(struct bmg160_data *data, int val) 471 { 472 struct device *dev = regmap_get_device(data->regmap); 473 int ret, i; 474 475 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 476 if (bmg160_scale_table[i].scale == val) { 477 ret = regmap_write(data->regmap, BMG160_REG_RANGE, 478 bmg160_scale_table[i].dps_range); 479 if (ret < 0) { 480 dev_err(dev, "Error writing reg_range\n"); 481 return ret; 482 } 483 data->dps_range = bmg160_scale_table[i].dps_range; 484 return 0; 485 } 486 } 487 488 return -EINVAL; 489 } 490 491 static int bmg160_get_temp(struct bmg160_data *data, int *val) 492 { 493 struct device *dev = regmap_get_device(data->regmap); 494 int ret; 495 unsigned int raw_val; 496 497 mutex_lock(&data->mutex); 498 ret = bmg160_set_power_state(data, true); 499 if (ret < 0) { 500 mutex_unlock(&data->mutex); 501 return ret; 502 } 503 504 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val); 505 if (ret < 0) { 506 dev_err(dev, "Error reading reg_temp\n"); 507 bmg160_set_power_state(data, false); 508 mutex_unlock(&data->mutex); 509 return ret; 510 } 511 512 *val = sign_extend32(raw_val, 7); 513 ret = bmg160_set_power_state(data, false); 514 mutex_unlock(&data->mutex); 515 if (ret < 0) 516 return ret; 517 518 return IIO_VAL_INT; 519 } 520 521 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) 522 { 523 struct device *dev = regmap_get_device(data->regmap); 524 int ret; 525 __le16 raw_val; 526 527 mutex_lock(&data->mutex); 528 ret = bmg160_set_power_state(data, true); 529 if (ret < 0) { 530 mutex_unlock(&data->mutex); 531 return ret; 532 } 533 534 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val, 535 sizeof(raw_val)); 536 if (ret < 0) { 537 dev_err(dev, "Error reading axis %d\n", axis); 538 bmg160_set_power_state(data, false); 539 mutex_unlock(&data->mutex); 540 return ret; 541 } 542 543 *val = sign_extend32(le16_to_cpu(raw_val), 15); 544 ret = bmg160_set_power_state(data, false); 545 mutex_unlock(&data->mutex); 546 if (ret < 0) 547 return ret; 548 549 return IIO_VAL_INT; 550 } 551 552 static int bmg160_read_raw(struct iio_dev *indio_dev, 553 struct iio_chan_spec const *chan, 554 int *val, int *val2, long mask) 555 { 556 struct bmg160_data *data = iio_priv(indio_dev); 557 int ret; 558 559 switch (mask) { 560 case IIO_CHAN_INFO_RAW: 561 switch (chan->type) { 562 case IIO_TEMP: 563 return bmg160_get_temp(data, val); 564 case IIO_ANGL_VEL: 565 if (iio_buffer_enabled(indio_dev)) 566 return -EBUSY; 567 else 568 return bmg160_get_axis(data, chan->scan_index, 569 val); 570 default: 571 return -EINVAL; 572 } 573 case IIO_CHAN_INFO_OFFSET: 574 if (chan->type == IIO_TEMP) { 575 *val = BMG160_TEMP_CENTER_VAL; 576 return IIO_VAL_INT; 577 } else 578 return -EINVAL; 579 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 580 return bmg160_get_filter(data, val); 581 case IIO_CHAN_INFO_SCALE: 582 switch (chan->type) { 583 case IIO_TEMP: 584 *val = 500; 585 return IIO_VAL_INT; 586 case IIO_ANGL_VEL: 587 { 588 int i; 589 590 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 591 if (bmg160_scale_table[i].dps_range == 592 data->dps_range) { 593 *val = 0; 594 *val2 = bmg160_scale_table[i].scale; 595 return IIO_VAL_INT_PLUS_MICRO; 596 } 597 } 598 return -EINVAL; 599 } 600 default: 601 return -EINVAL; 602 } 603 case IIO_CHAN_INFO_SAMP_FREQ: 604 *val2 = 0; 605 mutex_lock(&data->mutex); 606 ret = bmg160_get_bw(data, val); 607 mutex_unlock(&data->mutex); 608 return ret; 609 default: 610 return -EINVAL; 611 } 612 } 613 614 static int bmg160_write_raw(struct iio_dev *indio_dev, 615 struct iio_chan_spec const *chan, 616 int val, int val2, long mask) 617 { 618 struct bmg160_data *data = iio_priv(indio_dev); 619 int ret; 620 621 switch (mask) { 622 case IIO_CHAN_INFO_SAMP_FREQ: 623 mutex_lock(&data->mutex); 624 /* 625 * Section 4.2 of spec 626 * In suspend mode, the only supported operations are reading 627 * registers as well as writing to the (0x14) softreset 628 * register. Since we will be in suspend mode by default, change 629 * mode to power on for other writes. 630 */ 631 ret = bmg160_set_power_state(data, true); 632 if (ret < 0) { 633 mutex_unlock(&data->mutex); 634 return ret; 635 } 636 ret = bmg160_set_bw(data, val); 637 if (ret < 0) { 638 bmg160_set_power_state(data, false); 639 mutex_unlock(&data->mutex); 640 return ret; 641 } 642 ret = bmg160_set_power_state(data, false); 643 mutex_unlock(&data->mutex); 644 return ret; 645 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 646 if (val2) 647 return -EINVAL; 648 649 mutex_lock(&data->mutex); 650 ret = bmg160_set_power_state(data, true); 651 if (ret < 0) { 652 bmg160_set_power_state(data, false); 653 mutex_unlock(&data->mutex); 654 return ret; 655 } 656 ret = bmg160_set_filter(data, val); 657 if (ret < 0) { 658 bmg160_set_power_state(data, false); 659 mutex_unlock(&data->mutex); 660 return ret; 661 } 662 ret = bmg160_set_power_state(data, false); 663 mutex_unlock(&data->mutex); 664 return ret; 665 case IIO_CHAN_INFO_SCALE: 666 if (val) 667 return -EINVAL; 668 669 mutex_lock(&data->mutex); 670 /* Refer to comments above for the suspend mode ops */ 671 ret = bmg160_set_power_state(data, true); 672 if (ret < 0) { 673 mutex_unlock(&data->mutex); 674 return ret; 675 } 676 ret = bmg160_set_scale(data, val2); 677 if (ret < 0) { 678 bmg160_set_power_state(data, false); 679 mutex_unlock(&data->mutex); 680 return ret; 681 } 682 ret = bmg160_set_power_state(data, false); 683 mutex_unlock(&data->mutex); 684 return ret; 685 default: 686 return -EINVAL; 687 } 688 689 return -EINVAL; 690 } 691 692 static int bmg160_read_event(struct iio_dev *indio_dev, 693 const struct iio_chan_spec *chan, 694 enum iio_event_type type, 695 enum iio_event_direction dir, 696 enum iio_event_info info, 697 int *val, int *val2) 698 { 699 struct bmg160_data *data = iio_priv(indio_dev); 700 701 *val2 = 0; 702 switch (info) { 703 case IIO_EV_INFO_VALUE: 704 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; 705 break; 706 default: 707 return -EINVAL; 708 } 709 710 return IIO_VAL_INT; 711 } 712 713 static int bmg160_write_event(struct iio_dev *indio_dev, 714 const struct iio_chan_spec *chan, 715 enum iio_event_type type, 716 enum iio_event_direction dir, 717 enum iio_event_info info, 718 int val, int val2) 719 { 720 struct bmg160_data *data = iio_priv(indio_dev); 721 722 switch (info) { 723 case IIO_EV_INFO_VALUE: 724 if (data->ev_enable_state) 725 return -EBUSY; 726 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK; 727 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); 728 break; 729 default: 730 return -EINVAL; 731 } 732 733 return 0; 734 } 735 736 static int bmg160_read_event_config(struct iio_dev *indio_dev, 737 const struct iio_chan_spec *chan, 738 enum iio_event_type type, 739 enum iio_event_direction dir) 740 { 741 742 struct bmg160_data *data = iio_priv(indio_dev); 743 744 return data->ev_enable_state; 745 } 746 747 static int bmg160_write_event_config(struct iio_dev *indio_dev, 748 const struct iio_chan_spec *chan, 749 enum iio_event_type type, 750 enum iio_event_direction dir, 751 bool state) 752 { 753 struct bmg160_data *data = iio_priv(indio_dev); 754 int ret; 755 756 if (state && data->ev_enable_state) 757 return 0; 758 759 mutex_lock(&data->mutex); 760 761 if (!state && data->motion_trigger_on) { 762 data->ev_enable_state = 0; 763 mutex_unlock(&data->mutex); 764 return 0; 765 } 766 /* 767 * We will expect the enable and disable to do operation 768 * in reverse order. This will happen here anyway as our 769 * resume operation uses sync mode runtime pm calls, the 770 * suspend operation will be delayed by autosuspend delay 771 * So the disable operation will still happen in reverse of 772 * enable operation. When runtime pm is disabled the mode 773 * is always on so sequence doesn't matter 774 */ 775 ret = bmg160_set_power_state(data, state); 776 if (ret < 0) { 777 mutex_unlock(&data->mutex); 778 return ret; 779 } 780 781 ret = bmg160_setup_any_motion_interrupt(data, state); 782 if (ret < 0) { 783 bmg160_set_power_state(data, false); 784 mutex_unlock(&data->mutex); 785 return ret; 786 } 787 788 data->ev_enable_state = state; 789 mutex_unlock(&data->mutex); 790 791 return 0; 792 } 793 794 static const struct iio_mount_matrix * 795 bmg160_get_mount_matrix(const struct iio_dev *indio_dev, 796 const struct iio_chan_spec *chan) 797 { 798 struct bmg160_data *data = iio_priv(indio_dev); 799 800 return &data->orientation; 801 } 802 803 static const struct iio_chan_spec_ext_info bmg160_ext_info[] = { 804 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmg160_get_mount_matrix), 805 { } 806 }; 807 808 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000"); 809 810 static IIO_CONST_ATTR(in_anglvel_scale_available, 811 "0.001065 0.000532 0.000266 0.000133 0.000066"); 812 813 static struct attribute *bmg160_attributes[] = { 814 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 815 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 816 NULL, 817 }; 818 819 static const struct attribute_group bmg160_attrs_group = { 820 .attrs = bmg160_attributes, 821 }; 822 823 static const struct iio_event_spec bmg160_event = { 824 .type = IIO_EV_TYPE_ROC, 825 .dir = IIO_EV_DIR_EITHER, 826 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 827 BIT(IIO_EV_INFO_ENABLE) 828 }; 829 830 #define BMG160_CHANNEL(_axis) { \ 831 .type = IIO_ANGL_VEL, \ 832 .modified = 1, \ 833 .channel2 = IIO_MOD_##_axis, \ 834 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 835 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 836 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 837 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 838 .scan_index = AXIS_##_axis, \ 839 .scan_type = { \ 840 .sign = 's', \ 841 .realbits = 16, \ 842 .storagebits = 16, \ 843 .endianness = IIO_LE, \ 844 }, \ 845 .ext_info = bmg160_ext_info, \ 846 .event_spec = &bmg160_event, \ 847 .num_event_specs = 1 \ 848 } 849 850 static const struct iio_chan_spec bmg160_channels[] = { 851 { 852 .type = IIO_TEMP, 853 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 854 BIT(IIO_CHAN_INFO_SCALE) | 855 BIT(IIO_CHAN_INFO_OFFSET), 856 .scan_index = -1, 857 }, 858 BMG160_CHANNEL(X), 859 BMG160_CHANNEL(Y), 860 BMG160_CHANNEL(Z), 861 IIO_CHAN_SOFT_TIMESTAMP(3), 862 }; 863 864 static const struct iio_info bmg160_info = { 865 .attrs = &bmg160_attrs_group, 866 .read_raw = bmg160_read_raw, 867 .write_raw = bmg160_write_raw, 868 .read_event_value = bmg160_read_event, 869 .write_event_value = bmg160_write_event, 870 .write_event_config = bmg160_write_event_config, 871 .read_event_config = bmg160_read_event_config, 872 }; 873 874 static const unsigned long bmg160_accel_scan_masks[] = { 875 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 876 0}; 877 878 static irqreturn_t bmg160_trigger_handler(int irq, void *p) 879 { 880 struct iio_poll_func *pf = p; 881 struct iio_dev *indio_dev = pf->indio_dev; 882 struct bmg160_data *data = iio_priv(indio_dev); 883 int ret; 884 885 mutex_lock(&data->mutex); 886 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L, 887 data->scan.chans, AXIS_MAX * 2); 888 mutex_unlock(&data->mutex); 889 if (ret < 0) 890 goto err; 891 892 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 893 pf->timestamp); 894 err: 895 iio_trigger_notify_done(indio_dev->trig); 896 897 return IRQ_HANDLED; 898 } 899 900 static void bmg160_trig_reen(struct iio_trigger *trig) 901 { 902 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 903 struct bmg160_data *data = iio_priv(indio_dev); 904 struct device *dev = regmap_get_device(data->regmap); 905 int ret; 906 907 /* new data interrupts don't need ack */ 908 if (data->dready_trigger_on) 909 return; 910 911 /* Set latched mode interrupt and clear any latched interrupt */ 912 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 913 BMG160_INT_MODE_LATCH_INT | 914 BMG160_INT_MODE_LATCH_RESET); 915 if (ret < 0) 916 dev_err(dev, "Error writing reg_rst_latch\n"); 917 } 918 919 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, 920 bool state) 921 { 922 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 923 struct bmg160_data *data = iio_priv(indio_dev); 924 int ret; 925 926 mutex_lock(&data->mutex); 927 928 if (!state && data->ev_enable_state && data->motion_trigger_on) { 929 data->motion_trigger_on = false; 930 mutex_unlock(&data->mutex); 931 return 0; 932 } 933 934 /* 935 * Refer to comment in bmg160_write_event_config for 936 * enable/disable operation order 937 */ 938 ret = bmg160_set_power_state(data, state); 939 if (ret < 0) { 940 mutex_unlock(&data->mutex); 941 return ret; 942 } 943 if (data->motion_trig == trig) 944 ret = bmg160_setup_any_motion_interrupt(data, state); 945 else 946 ret = bmg160_setup_new_data_interrupt(data, state); 947 if (ret < 0) { 948 bmg160_set_power_state(data, false); 949 mutex_unlock(&data->mutex); 950 return ret; 951 } 952 if (data->motion_trig == trig) 953 data->motion_trigger_on = state; 954 else 955 data->dready_trigger_on = state; 956 957 mutex_unlock(&data->mutex); 958 959 return 0; 960 } 961 962 static const struct iio_trigger_ops bmg160_trigger_ops = { 963 .set_trigger_state = bmg160_data_rdy_trigger_set_state, 964 .reenable = bmg160_trig_reen, 965 }; 966 967 static irqreturn_t bmg160_event_handler(int irq, void *private) 968 { 969 struct iio_dev *indio_dev = private; 970 struct bmg160_data *data = iio_priv(indio_dev); 971 struct device *dev = regmap_get_device(data->regmap); 972 int ret; 973 int dir; 974 unsigned int val; 975 976 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); 977 if (ret < 0) { 978 dev_err(dev, "Error reading reg_int_status2\n"); 979 goto ack_intr_status; 980 } 981 982 if (val & 0x08) 983 dir = IIO_EV_DIR_RISING; 984 else 985 dir = IIO_EV_DIR_FALLING; 986 987 if (val & BMG160_ANY_MOTION_BIT_X) 988 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 989 0, 990 IIO_MOD_X, 991 IIO_EV_TYPE_ROC, 992 dir), 993 iio_get_time_ns(indio_dev)); 994 if (val & BMG160_ANY_MOTION_BIT_Y) 995 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 996 0, 997 IIO_MOD_Y, 998 IIO_EV_TYPE_ROC, 999 dir), 1000 iio_get_time_ns(indio_dev)); 1001 if (val & BMG160_ANY_MOTION_BIT_Z) 1002 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 1003 0, 1004 IIO_MOD_Z, 1005 IIO_EV_TYPE_ROC, 1006 dir), 1007 iio_get_time_ns(indio_dev)); 1008 1009 ack_intr_status: 1010 if (!data->dready_trigger_on) { 1011 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 1012 BMG160_INT_MODE_LATCH_INT | 1013 BMG160_INT_MODE_LATCH_RESET); 1014 if (ret < 0) 1015 dev_err(dev, "Error writing reg_rst_latch\n"); 1016 } 1017 1018 return IRQ_HANDLED; 1019 } 1020 1021 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private) 1022 { 1023 struct iio_dev *indio_dev = private; 1024 struct bmg160_data *data = iio_priv(indio_dev); 1025 1026 if (data->dready_trigger_on) 1027 iio_trigger_poll(data->dready_trig); 1028 else if (data->motion_trigger_on) 1029 iio_trigger_poll(data->motion_trig); 1030 1031 if (data->ev_enable_state) 1032 return IRQ_WAKE_THREAD; 1033 else 1034 return IRQ_HANDLED; 1035 1036 } 1037 1038 static int bmg160_buffer_preenable(struct iio_dev *indio_dev) 1039 { 1040 struct bmg160_data *data = iio_priv(indio_dev); 1041 1042 return bmg160_set_power_state(data, true); 1043 } 1044 1045 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev) 1046 { 1047 struct bmg160_data *data = iio_priv(indio_dev); 1048 1049 return bmg160_set_power_state(data, false); 1050 } 1051 1052 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = { 1053 .preenable = bmg160_buffer_preenable, 1054 .postdisable = bmg160_buffer_postdisable, 1055 }; 1056 1057 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq, 1058 const char *name) 1059 { 1060 static const char * const regulators[] = { "vdd", "vddio" }; 1061 struct bmg160_data *data; 1062 struct iio_dev *indio_dev; 1063 int ret; 1064 1065 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1066 if (!indio_dev) 1067 return -ENOMEM; 1068 1069 data = iio_priv(indio_dev); 1070 dev_set_drvdata(dev, indio_dev); 1071 data->irq = irq; 1072 data->regmap = regmap; 1073 1074 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators), 1075 regulators); 1076 if (ret) 1077 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1078 1079 ret = iio_read_mount_matrix(dev, &data->orientation); 1080 if (ret) 1081 return ret; 1082 1083 ret = bmg160_chip_init(data); 1084 if (ret < 0) 1085 return ret; 1086 1087 mutex_init(&data->mutex); 1088 1089 indio_dev->channels = bmg160_channels; 1090 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels); 1091 indio_dev->name = name; 1092 indio_dev->available_scan_masks = bmg160_accel_scan_masks; 1093 indio_dev->modes = INDIO_DIRECT_MODE; 1094 indio_dev->info = &bmg160_info; 1095 1096 if (data->irq > 0) { 1097 ret = devm_request_threaded_irq(dev, 1098 data->irq, 1099 bmg160_data_rdy_trig_poll, 1100 bmg160_event_handler, 1101 IRQF_TRIGGER_RISING, 1102 BMG160_IRQ_NAME, 1103 indio_dev); 1104 if (ret) 1105 return ret; 1106 1107 data->dready_trig = devm_iio_trigger_alloc(dev, 1108 "%s-dev%d", 1109 indio_dev->name, 1110 iio_device_id(indio_dev)); 1111 if (!data->dready_trig) 1112 return -ENOMEM; 1113 1114 data->motion_trig = devm_iio_trigger_alloc(dev, 1115 "%s-any-motion-dev%d", 1116 indio_dev->name, 1117 iio_device_id(indio_dev)); 1118 if (!data->motion_trig) 1119 return -ENOMEM; 1120 1121 data->dready_trig->ops = &bmg160_trigger_ops; 1122 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 1123 ret = iio_trigger_register(data->dready_trig); 1124 if (ret) 1125 return ret; 1126 1127 data->motion_trig->ops = &bmg160_trigger_ops; 1128 iio_trigger_set_drvdata(data->motion_trig, indio_dev); 1129 ret = iio_trigger_register(data->motion_trig); 1130 if (ret) { 1131 data->motion_trig = NULL; 1132 goto err_trigger_unregister; 1133 } 1134 } 1135 1136 ret = iio_triggered_buffer_setup(indio_dev, 1137 iio_pollfunc_store_time, 1138 bmg160_trigger_handler, 1139 &bmg160_buffer_setup_ops); 1140 if (ret < 0) { 1141 dev_err(dev, 1142 "iio triggered buffer setup failed\n"); 1143 goto err_trigger_unregister; 1144 } 1145 1146 ret = pm_runtime_set_active(dev); 1147 if (ret) 1148 goto err_buffer_cleanup; 1149 1150 pm_runtime_enable(dev); 1151 pm_runtime_set_autosuspend_delay(dev, 1152 BMG160_AUTO_SUSPEND_DELAY_MS); 1153 pm_runtime_use_autosuspend(dev); 1154 1155 ret = iio_device_register(indio_dev); 1156 if (ret < 0) { 1157 dev_err(dev, "unable to register iio device\n"); 1158 goto err_pm_cleanup; 1159 } 1160 1161 return 0; 1162 1163 err_pm_cleanup: 1164 pm_runtime_dont_use_autosuspend(dev); 1165 pm_runtime_disable(dev); 1166 err_buffer_cleanup: 1167 iio_triggered_buffer_cleanup(indio_dev); 1168 err_trigger_unregister: 1169 if (data->dready_trig) 1170 iio_trigger_unregister(data->dready_trig); 1171 if (data->motion_trig) 1172 iio_trigger_unregister(data->motion_trig); 1173 1174 return ret; 1175 } 1176 EXPORT_SYMBOL_GPL(bmg160_core_probe); 1177 1178 void bmg160_core_remove(struct device *dev) 1179 { 1180 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1181 struct bmg160_data *data = iio_priv(indio_dev); 1182 1183 iio_device_unregister(indio_dev); 1184 1185 pm_runtime_disable(dev); 1186 pm_runtime_set_suspended(dev); 1187 pm_runtime_put_noidle(dev); 1188 1189 iio_triggered_buffer_cleanup(indio_dev); 1190 1191 if (data->dready_trig) { 1192 iio_trigger_unregister(data->dready_trig); 1193 iio_trigger_unregister(data->motion_trig); 1194 } 1195 1196 mutex_lock(&data->mutex); 1197 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND); 1198 mutex_unlock(&data->mutex); 1199 } 1200 EXPORT_SYMBOL_GPL(bmg160_core_remove); 1201 1202 #ifdef CONFIG_PM_SLEEP 1203 static int bmg160_suspend(struct device *dev) 1204 { 1205 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1206 struct bmg160_data *data = iio_priv(indio_dev); 1207 1208 mutex_lock(&data->mutex); 1209 bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1210 mutex_unlock(&data->mutex); 1211 1212 return 0; 1213 } 1214 1215 static int bmg160_resume(struct device *dev) 1216 { 1217 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1218 struct bmg160_data *data = iio_priv(indio_dev); 1219 1220 mutex_lock(&data->mutex); 1221 if (data->dready_trigger_on || data->motion_trigger_on || 1222 data->ev_enable_state) 1223 bmg160_set_mode(data, BMG160_MODE_NORMAL); 1224 mutex_unlock(&data->mutex); 1225 1226 return 0; 1227 } 1228 #endif 1229 1230 #ifdef CONFIG_PM 1231 static int bmg160_runtime_suspend(struct device *dev) 1232 { 1233 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1234 struct bmg160_data *data = iio_priv(indio_dev); 1235 int ret; 1236 1237 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1238 if (ret < 0) { 1239 dev_err(dev, "set mode failed\n"); 1240 return -EAGAIN; 1241 } 1242 1243 return 0; 1244 } 1245 1246 static int bmg160_runtime_resume(struct device *dev) 1247 { 1248 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1249 struct bmg160_data *data = iio_priv(indio_dev); 1250 int ret; 1251 1252 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 1253 if (ret < 0) 1254 return ret; 1255 1256 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS); 1257 1258 return 0; 1259 } 1260 #endif 1261 1262 const struct dev_pm_ops bmg160_pm_ops = { 1263 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume) 1264 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend, 1265 bmg160_runtime_resume, NULL) 1266 }; 1267 EXPORT_SYMBOL_GPL(bmg160_pm_ops); 1268 1269 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1270 MODULE_LICENSE("GPL v2"); 1271 MODULE_DESCRIPTION("BMG160 Gyro driver"); 1272