1 /* 2 * BMG160 Gyro Sensor driver 3 * Copyright (c) 2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/slab.h> 19 #include <linux/acpi.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/iio/iio.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/trigger.h> 27 #include <linux/iio/events.h> 28 #include <linux/iio/trigger_consumer.h> 29 #include <linux/iio/triggered_buffer.h> 30 #include <linux/regmap.h> 31 #include "bmg160.h" 32 33 #define BMG160_IRQ_NAME "bmg160_event" 34 #define BMG160_GPIO_NAME "gpio_int" 35 36 #define BMG160_REG_CHIP_ID 0x00 37 #define BMG160_CHIP_ID_VAL 0x0F 38 39 #define BMG160_REG_PMU_LPW 0x11 40 #define BMG160_MODE_NORMAL 0x00 41 #define BMG160_MODE_DEEP_SUSPEND 0x20 42 #define BMG160_MODE_SUSPEND 0x80 43 44 #define BMG160_REG_RANGE 0x0F 45 46 #define BMG160_RANGE_2000DPS 0 47 #define BMG160_RANGE_1000DPS 1 48 #define BMG160_RANGE_500DPS 2 49 #define BMG160_RANGE_250DPS 3 50 #define BMG160_RANGE_125DPS 4 51 52 #define BMG160_REG_PMU_BW 0x10 53 #define BMG160_NO_FILTER 0 54 #define BMG160_DEF_BW 100 55 56 #define BMG160_REG_INT_MAP_0 0x17 57 #define BMG160_INT_MAP_0_BIT_ANY BIT(1) 58 59 #define BMG160_REG_INT_MAP_1 0x18 60 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) 61 62 #define BMG160_REG_INT_RST_LATCH 0x21 63 #define BMG160_INT_MODE_LATCH_RESET 0x80 64 #define BMG160_INT_MODE_LATCH_INT 0x0F 65 #define BMG160_INT_MODE_NON_LATCH_INT 0x00 66 67 #define BMG160_REG_INT_EN_0 0x15 68 #define BMG160_DATA_ENABLE_INT BIT(7) 69 70 #define BMG160_REG_INT_EN_1 0x16 71 #define BMG160_INT1_BIT_OD BIT(1) 72 73 #define BMG160_REG_XOUT_L 0x02 74 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2)) 75 76 #define BMG160_REG_SLOPE_THRES 0x1B 77 #define BMG160_SLOPE_THRES_MASK 0x0F 78 79 #define BMG160_REG_MOTION_INTR 0x1C 80 #define BMG160_INT_MOTION_X BIT(0) 81 #define BMG160_INT_MOTION_Y BIT(1) 82 #define BMG160_INT_MOTION_Z BIT(2) 83 #define BMG160_ANY_DUR_MASK 0x30 84 #define BMG160_ANY_DUR_SHIFT 4 85 86 #define BMG160_REG_INT_STATUS_2 0x0B 87 #define BMG160_ANY_MOTION_MASK 0x07 88 #define BMG160_ANY_MOTION_BIT_X BIT(0) 89 #define BMG160_ANY_MOTION_BIT_Y BIT(1) 90 #define BMG160_ANY_MOTION_BIT_Z BIT(2) 91 92 #define BMG160_REG_TEMP 0x08 93 #define BMG160_TEMP_CENTER_VAL 23 94 95 #define BMG160_MAX_STARTUP_TIME_MS 80 96 97 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000 98 99 struct bmg160_data { 100 struct device *dev; 101 struct regmap *regmap; 102 struct iio_trigger *dready_trig; 103 struct iio_trigger *motion_trig; 104 struct mutex mutex; 105 s16 buffer[8]; 106 u8 bw_bits; 107 u32 dps_range; 108 int ev_enable_state; 109 int slope_thres; 110 bool dready_trigger_on; 111 bool motion_trigger_on; 112 int irq; 113 }; 114 115 enum bmg160_axis { 116 AXIS_X, 117 AXIS_Y, 118 AXIS_Z, 119 }; 120 121 static const struct { 122 int val; 123 int bw_bits; 124 } bmg160_samp_freq_table[] = { {100, 0x07}, 125 {200, 0x06}, 126 {400, 0x03}, 127 {1000, 0x02}, 128 {2000, 0x01} }; 129 130 static const struct { 131 int scale; 132 int dps_range; 133 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS}, 134 { 532, BMG160_RANGE_1000DPS}, 135 { 266, BMG160_RANGE_500DPS}, 136 { 133, BMG160_RANGE_250DPS}, 137 { 66, BMG160_RANGE_125DPS} }; 138 139 static int bmg160_set_mode(struct bmg160_data *data, u8 mode) 140 { 141 int ret; 142 143 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode); 144 if (ret < 0) { 145 dev_err(data->dev, "Error writing reg_pmu_lpw\n"); 146 return ret; 147 } 148 149 return 0; 150 } 151 152 static int bmg160_convert_freq_to_bit(int val) 153 { 154 int i; 155 156 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 157 if (bmg160_samp_freq_table[i].val == val) 158 return bmg160_samp_freq_table[i].bw_bits; 159 } 160 161 return -EINVAL; 162 } 163 164 static int bmg160_set_bw(struct bmg160_data *data, int val) 165 { 166 int ret; 167 int bw_bits; 168 169 bw_bits = bmg160_convert_freq_to_bit(val); 170 if (bw_bits < 0) 171 return bw_bits; 172 173 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits); 174 if (ret < 0) { 175 dev_err(data->dev, "Error writing reg_pmu_bw\n"); 176 return ret; 177 } 178 179 data->bw_bits = bw_bits; 180 181 return 0; 182 } 183 184 static int bmg160_chip_init(struct bmg160_data *data) 185 { 186 int ret; 187 unsigned int val; 188 189 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); 190 if (ret < 0) { 191 dev_err(data->dev, "Error reading reg_chip_id\n"); 192 return ret; 193 } 194 195 dev_dbg(data->dev, "Chip Id %x\n", val); 196 if (val != BMG160_CHIP_ID_VAL) { 197 dev_err(data->dev, "invalid chip %x\n", val); 198 return -ENODEV; 199 } 200 201 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 202 if (ret < 0) 203 return ret; 204 205 /* Wait upto 500 ms to be ready after changing mode */ 206 usleep_range(500, 1000); 207 208 /* Set Bandwidth */ 209 ret = bmg160_set_bw(data, BMG160_DEF_BW); 210 if (ret < 0) 211 return ret; 212 213 /* Set Default Range */ 214 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS); 215 if (ret < 0) { 216 dev_err(data->dev, "Error writing reg_range\n"); 217 return ret; 218 } 219 data->dps_range = BMG160_RANGE_500DPS; 220 221 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); 222 if (ret < 0) { 223 dev_err(data->dev, "Error reading reg_slope_thres\n"); 224 return ret; 225 } 226 data->slope_thres = val; 227 228 /* Set default interrupt mode */ 229 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1, 230 BMG160_INT1_BIT_OD, 0); 231 if (ret < 0) { 232 dev_err(data->dev, "Error updating bits in reg_int_en_1\n"); 233 return ret; 234 } 235 236 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 237 BMG160_INT_MODE_LATCH_INT | 238 BMG160_INT_MODE_LATCH_RESET); 239 if (ret < 0) { 240 dev_err(data->dev, 241 "Error writing reg_motion_intr\n"); 242 return ret; 243 } 244 245 return 0; 246 } 247 248 static int bmg160_set_power_state(struct bmg160_data *data, bool on) 249 { 250 #ifdef CONFIG_PM 251 int ret; 252 253 if (on) 254 ret = pm_runtime_get_sync(data->dev); 255 else { 256 pm_runtime_mark_last_busy(data->dev); 257 ret = pm_runtime_put_autosuspend(data->dev); 258 } 259 260 if (ret < 0) { 261 dev_err(data->dev, 262 "Failed: bmg160_set_power_state for %d\n", on); 263 if (on) 264 pm_runtime_put_noidle(data->dev); 265 266 return ret; 267 } 268 #endif 269 270 return 0; 271 } 272 273 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data, 274 bool status) 275 { 276 int ret; 277 278 /* Enable/Disable INT_MAP0 mapping */ 279 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0, 280 BMG160_INT_MAP_0_BIT_ANY, 281 (status ? BMG160_INT_MAP_0_BIT_ANY : 0)); 282 if (ret < 0) { 283 dev_err(data->dev, "Error updating bits reg_int_map0\n"); 284 return ret; 285 } 286 287 /* Enable/Disable slope interrupts */ 288 if (status) { 289 /* Update slope thres */ 290 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES, 291 data->slope_thres); 292 if (ret < 0) { 293 dev_err(data->dev, 294 "Error writing reg_slope_thres\n"); 295 return ret; 296 } 297 298 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR, 299 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y | 300 BMG160_INT_MOTION_Z); 301 if (ret < 0) { 302 dev_err(data->dev, 303 "Error writing reg_motion_intr\n"); 304 return ret; 305 } 306 307 /* 308 * New data interrupt is always non-latched, 309 * which will have higher priority, so no need 310 * to set latched mode, we will be flooded anyway with INTR 311 */ 312 if (!data->dready_trigger_on) { 313 ret = regmap_write(data->regmap, 314 BMG160_REG_INT_RST_LATCH, 315 BMG160_INT_MODE_LATCH_INT | 316 BMG160_INT_MODE_LATCH_RESET); 317 if (ret < 0) { 318 dev_err(data->dev, 319 "Error writing reg_rst_latch\n"); 320 return ret; 321 } 322 } 323 324 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 325 BMG160_DATA_ENABLE_INT); 326 327 } else { 328 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 329 } 330 331 if (ret < 0) { 332 dev_err(data->dev, "Error writing reg_int_en0\n"); 333 return ret; 334 } 335 336 return 0; 337 } 338 339 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data, 340 bool status) 341 { 342 int ret; 343 344 /* Enable/Disable INT_MAP1 mapping */ 345 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1, 346 BMG160_INT_MAP_1_BIT_NEW_DATA, 347 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0)); 348 if (ret < 0) { 349 dev_err(data->dev, "Error updating bits in reg_int_map1\n"); 350 return ret; 351 } 352 353 if (status) { 354 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 355 BMG160_INT_MODE_NON_LATCH_INT | 356 BMG160_INT_MODE_LATCH_RESET); 357 if (ret < 0) { 358 dev_err(data->dev, 359 "Error writing reg_rst_latch\n"); 360 return ret; 361 } 362 363 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 364 BMG160_DATA_ENABLE_INT); 365 366 } else { 367 /* Restore interrupt mode */ 368 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 369 BMG160_INT_MODE_LATCH_INT | 370 BMG160_INT_MODE_LATCH_RESET); 371 if (ret < 0) { 372 dev_err(data->dev, 373 "Error writing reg_rst_latch\n"); 374 return ret; 375 } 376 377 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 378 } 379 380 if (ret < 0) { 381 dev_err(data->dev, "Error writing reg_int_en0\n"); 382 return ret; 383 } 384 385 return 0; 386 } 387 388 static int bmg160_get_bw(struct bmg160_data *data, int *val) 389 { 390 int i; 391 392 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 393 if (bmg160_samp_freq_table[i].bw_bits == data->bw_bits) { 394 *val = bmg160_samp_freq_table[i].val; 395 return IIO_VAL_INT; 396 } 397 } 398 399 return -EINVAL; 400 } 401 402 static int bmg160_set_scale(struct bmg160_data *data, int val) 403 { 404 int ret, i; 405 406 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 407 if (bmg160_scale_table[i].scale == val) { 408 ret = regmap_write(data->regmap, BMG160_REG_RANGE, 409 bmg160_scale_table[i].dps_range); 410 if (ret < 0) { 411 dev_err(data->dev, 412 "Error writing reg_range\n"); 413 return ret; 414 } 415 data->dps_range = bmg160_scale_table[i].dps_range; 416 return 0; 417 } 418 } 419 420 return -EINVAL; 421 } 422 423 static int bmg160_get_temp(struct bmg160_data *data, int *val) 424 { 425 int ret; 426 unsigned int raw_val; 427 428 mutex_lock(&data->mutex); 429 ret = bmg160_set_power_state(data, true); 430 if (ret < 0) { 431 mutex_unlock(&data->mutex); 432 return ret; 433 } 434 435 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val); 436 if (ret < 0) { 437 dev_err(data->dev, "Error reading reg_temp\n"); 438 bmg160_set_power_state(data, false); 439 mutex_unlock(&data->mutex); 440 return ret; 441 } 442 443 *val = sign_extend32(raw_val, 7); 444 ret = bmg160_set_power_state(data, false); 445 mutex_unlock(&data->mutex); 446 if (ret < 0) 447 return ret; 448 449 return IIO_VAL_INT; 450 } 451 452 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) 453 { 454 int ret; 455 __le16 raw_val; 456 457 mutex_lock(&data->mutex); 458 ret = bmg160_set_power_state(data, true); 459 if (ret < 0) { 460 mutex_unlock(&data->mutex); 461 return ret; 462 } 463 464 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val, 465 sizeof(raw_val)); 466 if (ret < 0) { 467 dev_err(data->dev, "Error reading axis %d\n", axis); 468 bmg160_set_power_state(data, false); 469 mutex_unlock(&data->mutex); 470 return ret; 471 } 472 473 *val = sign_extend32(le16_to_cpu(raw_val), 15); 474 ret = bmg160_set_power_state(data, false); 475 mutex_unlock(&data->mutex); 476 if (ret < 0) 477 return ret; 478 479 return IIO_VAL_INT; 480 } 481 482 static int bmg160_read_raw(struct iio_dev *indio_dev, 483 struct iio_chan_spec const *chan, 484 int *val, int *val2, long mask) 485 { 486 struct bmg160_data *data = iio_priv(indio_dev); 487 int ret; 488 489 switch (mask) { 490 case IIO_CHAN_INFO_RAW: 491 switch (chan->type) { 492 case IIO_TEMP: 493 return bmg160_get_temp(data, val); 494 case IIO_ANGL_VEL: 495 if (iio_buffer_enabled(indio_dev)) 496 return -EBUSY; 497 else 498 return bmg160_get_axis(data, chan->scan_index, 499 val); 500 default: 501 return -EINVAL; 502 } 503 case IIO_CHAN_INFO_OFFSET: 504 if (chan->type == IIO_TEMP) { 505 *val = BMG160_TEMP_CENTER_VAL; 506 return IIO_VAL_INT; 507 } else 508 return -EINVAL; 509 case IIO_CHAN_INFO_SCALE: 510 *val = 0; 511 switch (chan->type) { 512 case IIO_TEMP: 513 *val2 = 500000; 514 return IIO_VAL_INT_PLUS_MICRO; 515 case IIO_ANGL_VEL: 516 { 517 int i; 518 519 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 520 if (bmg160_scale_table[i].dps_range == 521 data->dps_range) { 522 *val2 = bmg160_scale_table[i].scale; 523 return IIO_VAL_INT_PLUS_MICRO; 524 } 525 } 526 return -EINVAL; 527 } 528 default: 529 return -EINVAL; 530 } 531 case IIO_CHAN_INFO_SAMP_FREQ: 532 *val2 = 0; 533 mutex_lock(&data->mutex); 534 ret = bmg160_get_bw(data, val); 535 mutex_unlock(&data->mutex); 536 return ret; 537 default: 538 return -EINVAL; 539 } 540 } 541 542 static int bmg160_write_raw(struct iio_dev *indio_dev, 543 struct iio_chan_spec const *chan, 544 int val, int val2, long mask) 545 { 546 struct bmg160_data *data = iio_priv(indio_dev); 547 int ret; 548 549 switch (mask) { 550 case IIO_CHAN_INFO_SAMP_FREQ: 551 mutex_lock(&data->mutex); 552 /* 553 * Section 4.2 of spec 554 * In suspend mode, the only supported operations are reading 555 * registers as well as writing to the (0x14) softreset 556 * register. Since we will be in suspend mode by default, change 557 * mode to power on for other writes. 558 */ 559 ret = bmg160_set_power_state(data, true); 560 if (ret < 0) { 561 mutex_unlock(&data->mutex); 562 return ret; 563 } 564 ret = bmg160_set_bw(data, val); 565 if (ret < 0) { 566 bmg160_set_power_state(data, false); 567 mutex_unlock(&data->mutex); 568 return ret; 569 } 570 ret = bmg160_set_power_state(data, false); 571 mutex_unlock(&data->mutex); 572 return ret; 573 case IIO_CHAN_INFO_SCALE: 574 if (val) 575 return -EINVAL; 576 577 mutex_lock(&data->mutex); 578 /* Refer to comments above for the suspend mode ops */ 579 ret = bmg160_set_power_state(data, true); 580 if (ret < 0) { 581 mutex_unlock(&data->mutex); 582 return ret; 583 } 584 ret = bmg160_set_scale(data, val2); 585 if (ret < 0) { 586 bmg160_set_power_state(data, false); 587 mutex_unlock(&data->mutex); 588 return ret; 589 } 590 ret = bmg160_set_power_state(data, false); 591 mutex_unlock(&data->mutex); 592 return ret; 593 default: 594 return -EINVAL; 595 } 596 597 return -EINVAL; 598 } 599 600 static int bmg160_read_event(struct iio_dev *indio_dev, 601 const struct iio_chan_spec *chan, 602 enum iio_event_type type, 603 enum iio_event_direction dir, 604 enum iio_event_info info, 605 int *val, int *val2) 606 { 607 struct bmg160_data *data = iio_priv(indio_dev); 608 609 *val2 = 0; 610 switch (info) { 611 case IIO_EV_INFO_VALUE: 612 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; 613 break; 614 default: 615 return -EINVAL; 616 } 617 618 return IIO_VAL_INT; 619 } 620 621 static int bmg160_write_event(struct iio_dev *indio_dev, 622 const struct iio_chan_spec *chan, 623 enum iio_event_type type, 624 enum iio_event_direction dir, 625 enum iio_event_info info, 626 int val, int val2) 627 { 628 struct bmg160_data *data = iio_priv(indio_dev); 629 630 switch (info) { 631 case IIO_EV_INFO_VALUE: 632 if (data->ev_enable_state) 633 return -EBUSY; 634 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK; 635 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); 636 break; 637 default: 638 return -EINVAL; 639 } 640 641 return 0; 642 } 643 644 static int bmg160_read_event_config(struct iio_dev *indio_dev, 645 const struct iio_chan_spec *chan, 646 enum iio_event_type type, 647 enum iio_event_direction dir) 648 { 649 650 struct bmg160_data *data = iio_priv(indio_dev); 651 652 return data->ev_enable_state; 653 } 654 655 static int bmg160_write_event_config(struct iio_dev *indio_dev, 656 const struct iio_chan_spec *chan, 657 enum iio_event_type type, 658 enum iio_event_direction dir, 659 int state) 660 { 661 struct bmg160_data *data = iio_priv(indio_dev); 662 int ret; 663 664 if (state && data->ev_enable_state) 665 return 0; 666 667 mutex_lock(&data->mutex); 668 669 if (!state && data->motion_trigger_on) { 670 data->ev_enable_state = 0; 671 mutex_unlock(&data->mutex); 672 return 0; 673 } 674 /* 675 * We will expect the enable and disable to do operation in 676 * in reverse order. This will happen here anyway as our 677 * resume operation uses sync mode runtime pm calls, the 678 * suspend operation will be delayed by autosuspend delay 679 * So the disable operation will still happen in reverse of 680 * enable operation. When runtime pm is disabled the mode 681 * is always on so sequence doesn't matter 682 */ 683 ret = bmg160_set_power_state(data, state); 684 if (ret < 0) { 685 mutex_unlock(&data->mutex); 686 return ret; 687 } 688 689 ret = bmg160_setup_any_motion_interrupt(data, state); 690 if (ret < 0) { 691 bmg160_set_power_state(data, false); 692 mutex_unlock(&data->mutex); 693 return ret; 694 } 695 696 data->ev_enable_state = state; 697 mutex_unlock(&data->mutex); 698 699 return 0; 700 } 701 702 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000"); 703 704 static IIO_CONST_ATTR(in_anglvel_scale_available, 705 "0.001065 0.000532 0.000266 0.000133 0.000066"); 706 707 static struct attribute *bmg160_attributes[] = { 708 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 709 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 710 NULL, 711 }; 712 713 static const struct attribute_group bmg160_attrs_group = { 714 .attrs = bmg160_attributes, 715 }; 716 717 static const struct iio_event_spec bmg160_event = { 718 .type = IIO_EV_TYPE_ROC, 719 .dir = IIO_EV_DIR_EITHER, 720 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 721 BIT(IIO_EV_INFO_ENABLE) 722 }; 723 724 #define BMG160_CHANNEL(_axis) { \ 725 .type = IIO_ANGL_VEL, \ 726 .modified = 1, \ 727 .channel2 = IIO_MOD_##_axis, \ 728 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 729 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 730 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 731 .scan_index = AXIS_##_axis, \ 732 .scan_type = { \ 733 .sign = 's', \ 734 .realbits = 16, \ 735 .storagebits = 16, \ 736 .endianness = IIO_LE, \ 737 }, \ 738 .event_spec = &bmg160_event, \ 739 .num_event_specs = 1 \ 740 } 741 742 static const struct iio_chan_spec bmg160_channels[] = { 743 { 744 .type = IIO_TEMP, 745 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 746 BIT(IIO_CHAN_INFO_SCALE) | 747 BIT(IIO_CHAN_INFO_OFFSET), 748 .scan_index = -1, 749 }, 750 BMG160_CHANNEL(X), 751 BMG160_CHANNEL(Y), 752 BMG160_CHANNEL(Z), 753 IIO_CHAN_SOFT_TIMESTAMP(3), 754 }; 755 756 static const struct iio_info bmg160_info = { 757 .attrs = &bmg160_attrs_group, 758 .read_raw = bmg160_read_raw, 759 .write_raw = bmg160_write_raw, 760 .read_event_value = bmg160_read_event, 761 .write_event_value = bmg160_write_event, 762 .write_event_config = bmg160_write_event_config, 763 .read_event_config = bmg160_read_event_config, 764 .driver_module = THIS_MODULE, 765 }; 766 767 static irqreturn_t bmg160_trigger_handler(int irq, void *p) 768 { 769 struct iio_poll_func *pf = p; 770 struct iio_dev *indio_dev = pf->indio_dev; 771 struct bmg160_data *data = iio_priv(indio_dev); 772 int bit, ret, i = 0; 773 unsigned int val; 774 775 mutex_lock(&data->mutex); 776 for_each_set_bit(bit, indio_dev->active_scan_mask, 777 indio_dev->masklength) { 778 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(bit), 779 &val, 2); 780 if (ret < 0) { 781 mutex_unlock(&data->mutex); 782 goto err; 783 } 784 data->buffer[i++] = val; 785 } 786 mutex_unlock(&data->mutex); 787 788 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 789 pf->timestamp); 790 err: 791 iio_trigger_notify_done(indio_dev->trig); 792 793 return IRQ_HANDLED; 794 } 795 796 static int bmg160_trig_try_reen(struct iio_trigger *trig) 797 { 798 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 799 struct bmg160_data *data = iio_priv(indio_dev); 800 int ret; 801 802 /* new data interrupts don't need ack */ 803 if (data->dready_trigger_on) 804 return 0; 805 806 /* Set latched mode interrupt and clear any latched interrupt */ 807 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 808 BMG160_INT_MODE_LATCH_INT | 809 BMG160_INT_MODE_LATCH_RESET); 810 if (ret < 0) { 811 dev_err(data->dev, "Error writing reg_rst_latch\n"); 812 return ret; 813 } 814 815 return 0; 816 } 817 818 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, 819 bool state) 820 { 821 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 822 struct bmg160_data *data = iio_priv(indio_dev); 823 int ret; 824 825 mutex_lock(&data->mutex); 826 827 if (!state && data->ev_enable_state && data->motion_trigger_on) { 828 data->motion_trigger_on = false; 829 mutex_unlock(&data->mutex); 830 return 0; 831 } 832 833 /* 834 * Refer to comment in bmg160_write_event_config for 835 * enable/disable operation order 836 */ 837 ret = bmg160_set_power_state(data, state); 838 if (ret < 0) { 839 mutex_unlock(&data->mutex); 840 return ret; 841 } 842 if (data->motion_trig == trig) 843 ret = bmg160_setup_any_motion_interrupt(data, state); 844 else 845 ret = bmg160_setup_new_data_interrupt(data, state); 846 if (ret < 0) { 847 bmg160_set_power_state(data, false); 848 mutex_unlock(&data->mutex); 849 return ret; 850 } 851 if (data->motion_trig == trig) 852 data->motion_trigger_on = state; 853 else 854 data->dready_trigger_on = state; 855 856 mutex_unlock(&data->mutex); 857 858 return 0; 859 } 860 861 static const struct iio_trigger_ops bmg160_trigger_ops = { 862 .set_trigger_state = bmg160_data_rdy_trigger_set_state, 863 .try_reenable = bmg160_trig_try_reen, 864 .owner = THIS_MODULE, 865 }; 866 867 static irqreturn_t bmg160_event_handler(int irq, void *private) 868 { 869 struct iio_dev *indio_dev = private; 870 struct bmg160_data *data = iio_priv(indio_dev); 871 int ret; 872 int dir; 873 unsigned int val; 874 875 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); 876 if (ret < 0) { 877 dev_err(data->dev, "Error reading reg_int_status2\n"); 878 goto ack_intr_status; 879 } 880 881 if (val & 0x08) 882 dir = IIO_EV_DIR_RISING; 883 else 884 dir = IIO_EV_DIR_FALLING; 885 886 if (val & BMG160_ANY_MOTION_BIT_X) 887 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 888 0, 889 IIO_MOD_X, 890 IIO_EV_TYPE_ROC, 891 dir), 892 iio_get_time_ns()); 893 if (val & BMG160_ANY_MOTION_BIT_Y) 894 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 895 0, 896 IIO_MOD_Y, 897 IIO_EV_TYPE_ROC, 898 dir), 899 iio_get_time_ns()); 900 if (val & BMG160_ANY_MOTION_BIT_Z) 901 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 902 0, 903 IIO_MOD_Z, 904 IIO_EV_TYPE_ROC, 905 dir), 906 iio_get_time_ns()); 907 908 ack_intr_status: 909 if (!data->dready_trigger_on) { 910 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 911 BMG160_INT_MODE_LATCH_INT | 912 BMG160_INT_MODE_LATCH_RESET); 913 if (ret < 0) 914 dev_err(data->dev, 915 "Error writing reg_rst_latch\n"); 916 } 917 918 return IRQ_HANDLED; 919 } 920 921 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private) 922 { 923 struct iio_dev *indio_dev = private; 924 struct bmg160_data *data = iio_priv(indio_dev); 925 926 if (data->dready_trigger_on) 927 iio_trigger_poll(data->dready_trig); 928 else if (data->motion_trigger_on) 929 iio_trigger_poll(data->motion_trig); 930 931 if (data->ev_enable_state) 932 return IRQ_WAKE_THREAD; 933 else 934 return IRQ_HANDLED; 935 936 } 937 938 static int bmg160_buffer_preenable(struct iio_dev *indio_dev) 939 { 940 struct bmg160_data *data = iio_priv(indio_dev); 941 942 return bmg160_set_power_state(data, true); 943 } 944 945 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev) 946 { 947 struct bmg160_data *data = iio_priv(indio_dev); 948 949 return bmg160_set_power_state(data, false); 950 } 951 952 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = { 953 .preenable = bmg160_buffer_preenable, 954 .postenable = iio_triggered_buffer_postenable, 955 .predisable = iio_triggered_buffer_predisable, 956 .postdisable = bmg160_buffer_postdisable, 957 }; 958 959 static int bmg160_gpio_probe(struct bmg160_data *data) 960 961 { 962 struct device *dev; 963 struct gpio_desc *gpio; 964 965 dev = data->dev; 966 967 /* data ready gpio interrupt pin */ 968 gpio = devm_gpiod_get_index(dev, BMG160_GPIO_NAME, 0, GPIOD_IN); 969 if (IS_ERR(gpio)) { 970 dev_err(dev, "acpi gpio get index failed\n"); 971 return PTR_ERR(gpio); 972 } 973 974 data->irq = gpiod_to_irq(gpio); 975 976 dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), 977 data->irq); 978 979 return 0; 980 } 981 982 static const char *bmg160_match_acpi_device(struct device *dev) 983 { 984 const struct acpi_device_id *id; 985 986 id = acpi_match_device(dev->driver->acpi_match_table, dev); 987 if (!id) 988 return NULL; 989 990 return dev_name(dev); 991 } 992 993 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq, 994 const char *name) 995 { 996 struct bmg160_data *data; 997 struct iio_dev *indio_dev; 998 int ret; 999 1000 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1001 if (!indio_dev) 1002 return -ENOMEM; 1003 1004 data = iio_priv(indio_dev); 1005 dev_set_drvdata(dev, indio_dev); 1006 data->dev = dev; 1007 data->irq = irq; 1008 data->regmap = regmap; 1009 1010 ret = bmg160_chip_init(data); 1011 if (ret < 0) 1012 return ret; 1013 1014 mutex_init(&data->mutex); 1015 1016 if (ACPI_HANDLE(dev)) 1017 name = bmg160_match_acpi_device(dev); 1018 1019 indio_dev->dev.parent = dev; 1020 indio_dev->channels = bmg160_channels; 1021 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels); 1022 indio_dev->name = name; 1023 indio_dev->modes = INDIO_DIRECT_MODE; 1024 indio_dev->info = &bmg160_info; 1025 1026 if (data->irq <= 0) 1027 bmg160_gpio_probe(data); 1028 1029 if (data->irq > 0) { 1030 ret = devm_request_threaded_irq(dev, 1031 data->irq, 1032 bmg160_data_rdy_trig_poll, 1033 bmg160_event_handler, 1034 IRQF_TRIGGER_RISING, 1035 BMG160_IRQ_NAME, 1036 indio_dev); 1037 if (ret) 1038 return ret; 1039 1040 data->dready_trig = devm_iio_trigger_alloc(dev, 1041 "%s-dev%d", 1042 indio_dev->name, 1043 indio_dev->id); 1044 if (!data->dready_trig) 1045 return -ENOMEM; 1046 1047 data->motion_trig = devm_iio_trigger_alloc(dev, 1048 "%s-any-motion-dev%d", 1049 indio_dev->name, 1050 indio_dev->id); 1051 if (!data->motion_trig) 1052 return -ENOMEM; 1053 1054 data->dready_trig->dev.parent = dev; 1055 data->dready_trig->ops = &bmg160_trigger_ops; 1056 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 1057 ret = iio_trigger_register(data->dready_trig); 1058 if (ret) 1059 return ret; 1060 1061 data->motion_trig->dev.parent = dev; 1062 data->motion_trig->ops = &bmg160_trigger_ops; 1063 iio_trigger_set_drvdata(data->motion_trig, indio_dev); 1064 ret = iio_trigger_register(data->motion_trig); 1065 if (ret) { 1066 data->motion_trig = NULL; 1067 goto err_trigger_unregister; 1068 } 1069 } 1070 1071 ret = iio_triggered_buffer_setup(indio_dev, 1072 iio_pollfunc_store_time, 1073 bmg160_trigger_handler, 1074 &bmg160_buffer_setup_ops); 1075 if (ret < 0) { 1076 dev_err(dev, 1077 "iio triggered buffer setup failed\n"); 1078 goto err_trigger_unregister; 1079 } 1080 1081 ret = pm_runtime_set_active(dev); 1082 if (ret) 1083 goto err_buffer_cleanup; 1084 1085 pm_runtime_enable(dev); 1086 pm_runtime_set_autosuspend_delay(dev, 1087 BMG160_AUTO_SUSPEND_DELAY_MS); 1088 pm_runtime_use_autosuspend(dev); 1089 1090 ret = iio_device_register(indio_dev); 1091 if (ret < 0) { 1092 dev_err(dev, "unable to register iio device\n"); 1093 goto err_buffer_cleanup; 1094 } 1095 1096 return 0; 1097 1098 err_buffer_cleanup: 1099 iio_triggered_buffer_cleanup(indio_dev); 1100 err_trigger_unregister: 1101 if (data->dready_trig) 1102 iio_trigger_unregister(data->dready_trig); 1103 if (data->motion_trig) 1104 iio_trigger_unregister(data->motion_trig); 1105 1106 return ret; 1107 } 1108 EXPORT_SYMBOL_GPL(bmg160_core_probe); 1109 1110 void bmg160_core_remove(struct device *dev) 1111 { 1112 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1113 struct bmg160_data *data = iio_priv(indio_dev); 1114 1115 iio_device_unregister(indio_dev); 1116 1117 pm_runtime_disable(dev); 1118 pm_runtime_set_suspended(dev); 1119 pm_runtime_put_noidle(dev); 1120 1121 iio_triggered_buffer_cleanup(indio_dev); 1122 1123 if (data->dready_trig) { 1124 iio_trigger_unregister(data->dready_trig); 1125 iio_trigger_unregister(data->motion_trig); 1126 } 1127 1128 mutex_lock(&data->mutex); 1129 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND); 1130 mutex_unlock(&data->mutex); 1131 } 1132 EXPORT_SYMBOL_GPL(bmg160_core_remove); 1133 1134 #ifdef CONFIG_PM_SLEEP 1135 static int bmg160_suspend(struct device *dev) 1136 { 1137 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1138 struct bmg160_data *data = iio_priv(indio_dev); 1139 1140 mutex_lock(&data->mutex); 1141 bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1142 mutex_unlock(&data->mutex); 1143 1144 return 0; 1145 } 1146 1147 static int bmg160_resume(struct device *dev) 1148 { 1149 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1150 struct bmg160_data *data = iio_priv(indio_dev); 1151 1152 mutex_lock(&data->mutex); 1153 if (data->dready_trigger_on || data->motion_trigger_on || 1154 data->ev_enable_state) 1155 bmg160_set_mode(data, BMG160_MODE_NORMAL); 1156 mutex_unlock(&data->mutex); 1157 1158 return 0; 1159 } 1160 #endif 1161 1162 #ifdef CONFIG_PM 1163 static int bmg160_runtime_suspend(struct device *dev) 1164 { 1165 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1166 struct bmg160_data *data = iio_priv(indio_dev); 1167 int ret; 1168 1169 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1170 if (ret < 0) { 1171 dev_err(data->dev, "set mode failed\n"); 1172 return -EAGAIN; 1173 } 1174 1175 return 0; 1176 } 1177 1178 static int bmg160_runtime_resume(struct device *dev) 1179 { 1180 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1181 struct bmg160_data *data = iio_priv(indio_dev); 1182 int ret; 1183 1184 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 1185 if (ret < 0) 1186 return ret; 1187 1188 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS); 1189 1190 return 0; 1191 } 1192 #endif 1193 1194 const struct dev_pm_ops bmg160_pm_ops = { 1195 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume) 1196 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend, 1197 bmg160_runtime_resume, NULL) 1198 }; 1199 EXPORT_SYMBOL_GPL(bmg160_pm_ops); 1200 1201 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1202 MODULE_LICENSE("GPL v2"); 1203 MODULE_DESCRIPTION("BMG160 Gyro driver"); 1204