1 /* 2 * BMG160 Gyro Sensor driver 3 * Copyright (c) 2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/slab.h> 19 #include <linux/acpi.h> 20 #include <linux/pm.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/iio/iio.h> 23 #include <linux/iio/sysfs.h> 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/trigger.h> 26 #include <linux/iio/events.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 #include <linux/regmap.h> 30 #include "bmg160.h" 31 32 #define BMG160_IRQ_NAME "bmg160_event" 33 34 #define BMG160_REG_CHIP_ID 0x00 35 #define BMG160_CHIP_ID_VAL 0x0F 36 37 #define BMG160_REG_PMU_LPW 0x11 38 #define BMG160_MODE_NORMAL 0x00 39 #define BMG160_MODE_DEEP_SUSPEND 0x20 40 #define BMG160_MODE_SUSPEND 0x80 41 42 #define BMG160_REG_RANGE 0x0F 43 44 #define BMG160_RANGE_2000DPS 0 45 #define BMG160_RANGE_1000DPS 1 46 #define BMG160_RANGE_500DPS 2 47 #define BMG160_RANGE_250DPS 3 48 #define BMG160_RANGE_125DPS 4 49 50 #define BMG160_REG_PMU_BW 0x10 51 #define BMG160_NO_FILTER 0 52 #define BMG160_DEF_BW 100 53 54 #define BMG160_REG_INT_MAP_0 0x17 55 #define BMG160_INT_MAP_0_BIT_ANY BIT(1) 56 57 #define BMG160_REG_INT_MAP_1 0x18 58 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) 59 60 #define BMG160_REG_INT_RST_LATCH 0x21 61 #define BMG160_INT_MODE_LATCH_RESET 0x80 62 #define BMG160_INT_MODE_LATCH_INT 0x0F 63 #define BMG160_INT_MODE_NON_LATCH_INT 0x00 64 65 #define BMG160_REG_INT_EN_0 0x15 66 #define BMG160_DATA_ENABLE_INT BIT(7) 67 68 #define BMG160_REG_INT_EN_1 0x16 69 #define BMG160_INT1_BIT_OD BIT(1) 70 71 #define BMG160_REG_XOUT_L 0x02 72 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2)) 73 74 #define BMG160_REG_SLOPE_THRES 0x1B 75 #define BMG160_SLOPE_THRES_MASK 0x0F 76 77 #define BMG160_REG_MOTION_INTR 0x1C 78 #define BMG160_INT_MOTION_X BIT(0) 79 #define BMG160_INT_MOTION_Y BIT(1) 80 #define BMG160_INT_MOTION_Z BIT(2) 81 #define BMG160_ANY_DUR_MASK 0x30 82 #define BMG160_ANY_DUR_SHIFT 4 83 84 #define BMG160_REG_INT_STATUS_2 0x0B 85 #define BMG160_ANY_MOTION_MASK 0x07 86 #define BMG160_ANY_MOTION_BIT_X BIT(0) 87 #define BMG160_ANY_MOTION_BIT_Y BIT(1) 88 #define BMG160_ANY_MOTION_BIT_Z BIT(2) 89 90 #define BMG160_REG_TEMP 0x08 91 #define BMG160_TEMP_CENTER_VAL 23 92 93 #define BMG160_MAX_STARTUP_TIME_MS 80 94 95 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000 96 97 struct bmg160_data { 98 struct regmap *regmap; 99 struct iio_trigger *dready_trig; 100 struct iio_trigger *motion_trig; 101 struct mutex mutex; 102 s16 buffer[8]; 103 u8 bw_bits; 104 u32 dps_range; 105 int ev_enable_state; 106 int slope_thres; 107 bool dready_trigger_on; 108 bool motion_trigger_on; 109 int irq; 110 }; 111 112 enum bmg160_axis { 113 AXIS_X, 114 AXIS_Y, 115 AXIS_Z, 116 AXIS_MAX, 117 }; 118 119 static const struct { 120 int val; 121 int bw_bits; 122 } bmg160_samp_freq_table[] = { {100, 0x07}, 123 {200, 0x06}, 124 {400, 0x03}, 125 {1000, 0x02}, 126 {2000, 0x01} }; 127 128 static const struct { 129 int scale; 130 int dps_range; 131 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS}, 132 { 532, BMG160_RANGE_1000DPS}, 133 { 266, BMG160_RANGE_500DPS}, 134 { 133, BMG160_RANGE_250DPS}, 135 { 66, BMG160_RANGE_125DPS} }; 136 137 static int bmg160_set_mode(struct bmg160_data *data, u8 mode) 138 { 139 struct device *dev = regmap_get_device(data->regmap); 140 int ret; 141 142 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode); 143 if (ret < 0) { 144 dev_err(dev, "Error writing reg_pmu_lpw\n"); 145 return ret; 146 } 147 148 return 0; 149 } 150 151 static int bmg160_convert_freq_to_bit(int val) 152 { 153 int i; 154 155 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 156 if (bmg160_samp_freq_table[i].val == val) 157 return bmg160_samp_freq_table[i].bw_bits; 158 } 159 160 return -EINVAL; 161 } 162 163 static int bmg160_set_bw(struct bmg160_data *data, int val) 164 { 165 struct device *dev = regmap_get_device(data->regmap); 166 int ret; 167 int bw_bits; 168 169 bw_bits = bmg160_convert_freq_to_bit(val); 170 if (bw_bits < 0) 171 return bw_bits; 172 173 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits); 174 if (ret < 0) { 175 dev_err(dev, "Error writing reg_pmu_bw\n"); 176 return ret; 177 } 178 179 data->bw_bits = bw_bits; 180 181 return 0; 182 } 183 184 static int bmg160_chip_init(struct bmg160_data *data) 185 { 186 struct device *dev = regmap_get_device(data->regmap); 187 int ret; 188 unsigned int val; 189 190 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); 191 if (ret < 0) { 192 dev_err(dev, "Error reading reg_chip_id\n"); 193 return ret; 194 } 195 196 dev_dbg(dev, "Chip Id %x\n", val); 197 if (val != BMG160_CHIP_ID_VAL) { 198 dev_err(dev, "invalid chip %x\n", val); 199 return -ENODEV; 200 } 201 202 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 203 if (ret < 0) 204 return ret; 205 206 /* Wait upto 500 ms to be ready after changing mode */ 207 usleep_range(500, 1000); 208 209 /* Set Bandwidth */ 210 ret = bmg160_set_bw(data, BMG160_DEF_BW); 211 if (ret < 0) 212 return ret; 213 214 /* Set Default Range */ 215 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS); 216 if (ret < 0) { 217 dev_err(dev, "Error writing reg_range\n"); 218 return ret; 219 } 220 data->dps_range = BMG160_RANGE_500DPS; 221 222 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); 223 if (ret < 0) { 224 dev_err(dev, "Error reading reg_slope_thres\n"); 225 return ret; 226 } 227 data->slope_thres = val; 228 229 /* Set default interrupt mode */ 230 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1, 231 BMG160_INT1_BIT_OD, 0); 232 if (ret < 0) { 233 dev_err(dev, "Error updating bits in reg_int_en_1\n"); 234 return ret; 235 } 236 237 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 238 BMG160_INT_MODE_LATCH_INT | 239 BMG160_INT_MODE_LATCH_RESET); 240 if (ret < 0) { 241 dev_err(dev, 242 "Error writing reg_motion_intr\n"); 243 return ret; 244 } 245 246 return 0; 247 } 248 249 static int bmg160_set_power_state(struct bmg160_data *data, bool on) 250 { 251 #ifdef CONFIG_PM 252 struct device *dev = regmap_get_device(data->regmap); 253 int ret; 254 255 if (on) 256 ret = pm_runtime_get_sync(dev); 257 else { 258 pm_runtime_mark_last_busy(dev); 259 ret = pm_runtime_put_autosuspend(dev); 260 } 261 262 if (ret < 0) { 263 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on); 264 265 if (on) 266 pm_runtime_put_noidle(dev); 267 268 return ret; 269 } 270 #endif 271 272 return 0; 273 } 274 275 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data, 276 bool status) 277 { 278 struct device *dev = regmap_get_device(data->regmap); 279 int ret; 280 281 /* Enable/Disable INT_MAP0 mapping */ 282 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0, 283 BMG160_INT_MAP_0_BIT_ANY, 284 (status ? BMG160_INT_MAP_0_BIT_ANY : 0)); 285 if (ret < 0) { 286 dev_err(dev, "Error updating bits reg_int_map0\n"); 287 return ret; 288 } 289 290 /* Enable/Disable slope interrupts */ 291 if (status) { 292 /* Update slope thres */ 293 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES, 294 data->slope_thres); 295 if (ret < 0) { 296 dev_err(dev, "Error writing reg_slope_thres\n"); 297 return ret; 298 } 299 300 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR, 301 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y | 302 BMG160_INT_MOTION_Z); 303 if (ret < 0) { 304 dev_err(dev, "Error writing reg_motion_intr\n"); 305 return ret; 306 } 307 308 /* 309 * New data interrupt is always non-latched, 310 * which will have higher priority, so no need 311 * to set latched mode, we will be flooded anyway with INTR 312 */ 313 if (!data->dready_trigger_on) { 314 ret = regmap_write(data->regmap, 315 BMG160_REG_INT_RST_LATCH, 316 BMG160_INT_MODE_LATCH_INT | 317 BMG160_INT_MODE_LATCH_RESET); 318 if (ret < 0) { 319 dev_err(dev, "Error writing reg_rst_latch\n"); 320 return ret; 321 } 322 } 323 324 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 325 BMG160_DATA_ENABLE_INT); 326 327 } else { 328 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 329 } 330 331 if (ret < 0) { 332 dev_err(dev, "Error writing reg_int_en0\n"); 333 return ret; 334 } 335 336 return 0; 337 } 338 339 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data, 340 bool status) 341 { 342 struct device *dev = regmap_get_device(data->regmap); 343 int ret; 344 345 /* Enable/Disable INT_MAP1 mapping */ 346 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1, 347 BMG160_INT_MAP_1_BIT_NEW_DATA, 348 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0)); 349 if (ret < 0) { 350 dev_err(dev, "Error updating bits in reg_int_map1\n"); 351 return ret; 352 } 353 354 if (status) { 355 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 356 BMG160_INT_MODE_NON_LATCH_INT | 357 BMG160_INT_MODE_LATCH_RESET); 358 if (ret < 0) { 359 dev_err(dev, "Error writing reg_rst_latch\n"); 360 return ret; 361 } 362 363 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 364 BMG160_DATA_ENABLE_INT); 365 366 } else { 367 /* Restore interrupt mode */ 368 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 369 BMG160_INT_MODE_LATCH_INT | 370 BMG160_INT_MODE_LATCH_RESET); 371 if (ret < 0) { 372 dev_err(dev, "Error writing reg_rst_latch\n"); 373 return ret; 374 } 375 376 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); 377 } 378 379 if (ret < 0) { 380 dev_err(dev, "Error writing reg_int_en0\n"); 381 return ret; 382 } 383 384 return 0; 385 } 386 387 static int bmg160_get_bw(struct bmg160_data *data, int *val) 388 { 389 int i; 390 391 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { 392 if (bmg160_samp_freq_table[i].bw_bits == data->bw_bits) { 393 *val = bmg160_samp_freq_table[i].val; 394 return IIO_VAL_INT; 395 } 396 } 397 398 return -EINVAL; 399 } 400 401 static int bmg160_set_scale(struct bmg160_data *data, int val) 402 { 403 struct device *dev = regmap_get_device(data->regmap); 404 int ret, i; 405 406 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 407 if (bmg160_scale_table[i].scale == val) { 408 ret = regmap_write(data->regmap, BMG160_REG_RANGE, 409 bmg160_scale_table[i].dps_range); 410 if (ret < 0) { 411 dev_err(dev, "Error writing reg_range\n"); 412 return ret; 413 } 414 data->dps_range = bmg160_scale_table[i].dps_range; 415 return 0; 416 } 417 } 418 419 return -EINVAL; 420 } 421 422 static int bmg160_get_temp(struct bmg160_data *data, int *val) 423 { 424 struct device *dev = regmap_get_device(data->regmap); 425 int ret; 426 unsigned int raw_val; 427 428 mutex_lock(&data->mutex); 429 ret = bmg160_set_power_state(data, true); 430 if (ret < 0) { 431 mutex_unlock(&data->mutex); 432 return ret; 433 } 434 435 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val); 436 if (ret < 0) { 437 dev_err(dev, "Error reading reg_temp\n"); 438 bmg160_set_power_state(data, false); 439 mutex_unlock(&data->mutex); 440 return ret; 441 } 442 443 *val = sign_extend32(raw_val, 7); 444 ret = bmg160_set_power_state(data, false); 445 mutex_unlock(&data->mutex); 446 if (ret < 0) 447 return ret; 448 449 return IIO_VAL_INT; 450 } 451 452 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) 453 { 454 struct device *dev = regmap_get_device(data->regmap); 455 int ret; 456 __le16 raw_val; 457 458 mutex_lock(&data->mutex); 459 ret = bmg160_set_power_state(data, true); 460 if (ret < 0) { 461 mutex_unlock(&data->mutex); 462 return ret; 463 } 464 465 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val, 466 sizeof(raw_val)); 467 if (ret < 0) { 468 dev_err(dev, "Error reading axis %d\n", axis); 469 bmg160_set_power_state(data, false); 470 mutex_unlock(&data->mutex); 471 return ret; 472 } 473 474 *val = sign_extend32(le16_to_cpu(raw_val), 15); 475 ret = bmg160_set_power_state(data, false); 476 mutex_unlock(&data->mutex); 477 if (ret < 0) 478 return ret; 479 480 return IIO_VAL_INT; 481 } 482 483 static int bmg160_read_raw(struct iio_dev *indio_dev, 484 struct iio_chan_spec const *chan, 485 int *val, int *val2, long mask) 486 { 487 struct bmg160_data *data = iio_priv(indio_dev); 488 int ret; 489 490 switch (mask) { 491 case IIO_CHAN_INFO_RAW: 492 switch (chan->type) { 493 case IIO_TEMP: 494 return bmg160_get_temp(data, val); 495 case IIO_ANGL_VEL: 496 if (iio_buffer_enabled(indio_dev)) 497 return -EBUSY; 498 else 499 return bmg160_get_axis(data, chan->scan_index, 500 val); 501 default: 502 return -EINVAL; 503 } 504 case IIO_CHAN_INFO_OFFSET: 505 if (chan->type == IIO_TEMP) { 506 *val = BMG160_TEMP_CENTER_VAL; 507 return IIO_VAL_INT; 508 } else 509 return -EINVAL; 510 case IIO_CHAN_INFO_SCALE: 511 *val = 0; 512 switch (chan->type) { 513 case IIO_TEMP: 514 *val2 = 500000; 515 return IIO_VAL_INT_PLUS_MICRO; 516 case IIO_ANGL_VEL: 517 { 518 int i; 519 520 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { 521 if (bmg160_scale_table[i].dps_range == 522 data->dps_range) { 523 *val2 = bmg160_scale_table[i].scale; 524 return IIO_VAL_INT_PLUS_MICRO; 525 } 526 } 527 return -EINVAL; 528 } 529 default: 530 return -EINVAL; 531 } 532 case IIO_CHAN_INFO_SAMP_FREQ: 533 *val2 = 0; 534 mutex_lock(&data->mutex); 535 ret = bmg160_get_bw(data, val); 536 mutex_unlock(&data->mutex); 537 return ret; 538 default: 539 return -EINVAL; 540 } 541 } 542 543 static int bmg160_write_raw(struct iio_dev *indio_dev, 544 struct iio_chan_spec const *chan, 545 int val, int val2, long mask) 546 { 547 struct bmg160_data *data = iio_priv(indio_dev); 548 int ret; 549 550 switch (mask) { 551 case IIO_CHAN_INFO_SAMP_FREQ: 552 mutex_lock(&data->mutex); 553 /* 554 * Section 4.2 of spec 555 * In suspend mode, the only supported operations are reading 556 * registers as well as writing to the (0x14) softreset 557 * register. Since we will be in suspend mode by default, change 558 * mode to power on for other writes. 559 */ 560 ret = bmg160_set_power_state(data, true); 561 if (ret < 0) { 562 mutex_unlock(&data->mutex); 563 return ret; 564 } 565 ret = bmg160_set_bw(data, val); 566 if (ret < 0) { 567 bmg160_set_power_state(data, false); 568 mutex_unlock(&data->mutex); 569 return ret; 570 } 571 ret = bmg160_set_power_state(data, false); 572 mutex_unlock(&data->mutex); 573 return ret; 574 case IIO_CHAN_INFO_SCALE: 575 if (val) 576 return -EINVAL; 577 578 mutex_lock(&data->mutex); 579 /* Refer to comments above for the suspend mode ops */ 580 ret = bmg160_set_power_state(data, true); 581 if (ret < 0) { 582 mutex_unlock(&data->mutex); 583 return ret; 584 } 585 ret = bmg160_set_scale(data, val2); 586 if (ret < 0) { 587 bmg160_set_power_state(data, false); 588 mutex_unlock(&data->mutex); 589 return ret; 590 } 591 ret = bmg160_set_power_state(data, false); 592 mutex_unlock(&data->mutex); 593 return ret; 594 default: 595 return -EINVAL; 596 } 597 598 return -EINVAL; 599 } 600 601 static int bmg160_read_event(struct iio_dev *indio_dev, 602 const struct iio_chan_spec *chan, 603 enum iio_event_type type, 604 enum iio_event_direction dir, 605 enum iio_event_info info, 606 int *val, int *val2) 607 { 608 struct bmg160_data *data = iio_priv(indio_dev); 609 610 *val2 = 0; 611 switch (info) { 612 case IIO_EV_INFO_VALUE: 613 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; 614 break; 615 default: 616 return -EINVAL; 617 } 618 619 return IIO_VAL_INT; 620 } 621 622 static int bmg160_write_event(struct iio_dev *indio_dev, 623 const struct iio_chan_spec *chan, 624 enum iio_event_type type, 625 enum iio_event_direction dir, 626 enum iio_event_info info, 627 int val, int val2) 628 { 629 struct bmg160_data *data = iio_priv(indio_dev); 630 631 switch (info) { 632 case IIO_EV_INFO_VALUE: 633 if (data->ev_enable_state) 634 return -EBUSY; 635 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK; 636 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); 637 break; 638 default: 639 return -EINVAL; 640 } 641 642 return 0; 643 } 644 645 static int bmg160_read_event_config(struct iio_dev *indio_dev, 646 const struct iio_chan_spec *chan, 647 enum iio_event_type type, 648 enum iio_event_direction dir) 649 { 650 651 struct bmg160_data *data = iio_priv(indio_dev); 652 653 return data->ev_enable_state; 654 } 655 656 static int bmg160_write_event_config(struct iio_dev *indio_dev, 657 const struct iio_chan_spec *chan, 658 enum iio_event_type type, 659 enum iio_event_direction dir, 660 int state) 661 { 662 struct bmg160_data *data = iio_priv(indio_dev); 663 int ret; 664 665 if (state && data->ev_enable_state) 666 return 0; 667 668 mutex_lock(&data->mutex); 669 670 if (!state && data->motion_trigger_on) { 671 data->ev_enable_state = 0; 672 mutex_unlock(&data->mutex); 673 return 0; 674 } 675 /* 676 * We will expect the enable and disable to do operation in 677 * in reverse order. This will happen here anyway as our 678 * resume operation uses sync mode runtime pm calls, the 679 * suspend operation will be delayed by autosuspend delay 680 * So the disable operation will still happen in reverse of 681 * enable operation. When runtime pm is disabled the mode 682 * is always on so sequence doesn't matter 683 */ 684 ret = bmg160_set_power_state(data, state); 685 if (ret < 0) { 686 mutex_unlock(&data->mutex); 687 return ret; 688 } 689 690 ret = bmg160_setup_any_motion_interrupt(data, state); 691 if (ret < 0) { 692 bmg160_set_power_state(data, false); 693 mutex_unlock(&data->mutex); 694 return ret; 695 } 696 697 data->ev_enable_state = state; 698 mutex_unlock(&data->mutex); 699 700 return 0; 701 } 702 703 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000"); 704 705 static IIO_CONST_ATTR(in_anglvel_scale_available, 706 "0.001065 0.000532 0.000266 0.000133 0.000066"); 707 708 static struct attribute *bmg160_attributes[] = { 709 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 710 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, 711 NULL, 712 }; 713 714 static const struct attribute_group bmg160_attrs_group = { 715 .attrs = bmg160_attributes, 716 }; 717 718 static const struct iio_event_spec bmg160_event = { 719 .type = IIO_EV_TYPE_ROC, 720 .dir = IIO_EV_DIR_EITHER, 721 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 722 BIT(IIO_EV_INFO_ENABLE) 723 }; 724 725 #define BMG160_CHANNEL(_axis) { \ 726 .type = IIO_ANGL_VEL, \ 727 .modified = 1, \ 728 .channel2 = IIO_MOD_##_axis, \ 729 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 730 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 731 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 732 .scan_index = AXIS_##_axis, \ 733 .scan_type = { \ 734 .sign = 's', \ 735 .realbits = 16, \ 736 .storagebits = 16, \ 737 .endianness = IIO_LE, \ 738 }, \ 739 .event_spec = &bmg160_event, \ 740 .num_event_specs = 1 \ 741 } 742 743 static const struct iio_chan_spec bmg160_channels[] = { 744 { 745 .type = IIO_TEMP, 746 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 747 BIT(IIO_CHAN_INFO_SCALE) | 748 BIT(IIO_CHAN_INFO_OFFSET), 749 .scan_index = -1, 750 }, 751 BMG160_CHANNEL(X), 752 BMG160_CHANNEL(Y), 753 BMG160_CHANNEL(Z), 754 IIO_CHAN_SOFT_TIMESTAMP(3), 755 }; 756 757 static const struct iio_info bmg160_info = { 758 .attrs = &bmg160_attrs_group, 759 .read_raw = bmg160_read_raw, 760 .write_raw = bmg160_write_raw, 761 .read_event_value = bmg160_read_event, 762 .write_event_value = bmg160_write_event, 763 .write_event_config = bmg160_write_event_config, 764 .read_event_config = bmg160_read_event_config, 765 .driver_module = THIS_MODULE, 766 }; 767 768 static const unsigned long bmg160_accel_scan_masks[] = { 769 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 770 0}; 771 772 static irqreturn_t bmg160_trigger_handler(int irq, void *p) 773 { 774 struct iio_poll_func *pf = p; 775 struct iio_dev *indio_dev = pf->indio_dev; 776 struct bmg160_data *data = iio_priv(indio_dev); 777 int ret; 778 779 mutex_lock(&data->mutex); 780 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L, 781 data->buffer, AXIS_MAX * 2); 782 mutex_unlock(&data->mutex); 783 if (ret < 0) 784 goto err; 785 786 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 787 pf->timestamp); 788 err: 789 iio_trigger_notify_done(indio_dev->trig); 790 791 return IRQ_HANDLED; 792 } 793 794 static int bmg160_trig_try_reen(struct iio_trigger *trig) 795 { 796 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 797 struct bmg160_data *data = iio_priv(indio_dev); 798 struct device *dev = regmap_get_device(data->regmap); 799 int ret; 800 801 /* new data interrupts don't need ack */ 802 if (data->dready_trigger_on) 803 return 0; 804 805 /* Set latched mode interrupt and clear any latched interrupt */ 806 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 807 BMG160_INT_MODE_LATCH_INT | 808 BMG160_INT_MODE_LATCH_RESET); 809 if (ret < 0) { 810 dev_err(dev, "Error writing reg_rst_latch\n"); 811 return ret; 812 } 813 814 return 0; 815 } 816 817 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, 818 bool state) 819 { 820 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 821 struct bmg160_data *data = iio_priv(indio_dev); 822 int ret; 823 824 mutex_lock(&data->mutex); 825 826 if (!state && data->ev_enable_state && data->motion_trigger_on) { 827 data->motion_trigger_on = false; 828 mutex_unlock(&data->mutex); 829 return 0; 830 } 831 832 /* 833 * Refer to comment in bmg160_write_event_config for 834 * enable/disable operation order 835 */ 836 ret = bmg160_set_power_state(data, state); 837 if (ret < 0) { 838 mutex_unlock(&data->mutex); 839 return ret; 840 } 841 if (data->motion_trig == trig) 842 ret = bmg160_setup_any_motion_interrupt(data, state); 843 else 844 ret = bmg160_setup_new_data_interrupt(data, state); 845 if (ret < 0) { 846 bmg160_set_power_state(data, false); 847 mutex_unlock(&data->mutex); 848 return ret; 849 } 850 if (data->motion_trig == trig) 851 data->motion_trigger_on = state; 852 else 853 data->dready_trigger_on = state; 854 855 mutex_unlock(&data->mutex); 856 857 return 0; 858 } 859 860 static const struct iio_trigger_ops bmg160_trigger_ops = { 861 .set_trigger_state = bmg160_data_rdy_trigger_set_state, 862 .try_reenable = bmg160_trig_try_reen, 863 .owner = THIS_MODULE, 864 }; 865 866 static irqreturn_t bmg160_event_handler(int irq, void *private) 867 { 868 struct iio_dev *indio_dev = private; 869 struct bmg160_data *data = iio_priv(indio_dev); 870 struct device *dev = regmap_get_device(data->regmap); 871 int ret; 872 int dir; 873 unsigned int val; 874 875 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); 876 if (ret < 0) { 877 dev_err(dev, "Error reading reg_int_status2\n"); 878 goto ack_intr_status; 879 } 880 881 if (val & 0x08) 882 dir = IIO_EV_DIR_RISING; 883 else 884 dir = IIO_EV_DIR_FALLING; 885 886 if (val & BMG160_ANY_MOTION_BIT_X) 887 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 888 0, 889 IIO_MOD_X, 890 IIO_EV_TYPE_ROC, 891 dir), 892 iio_get_time_ns()); 893 if (val & BMG160_ANY_MOTION_BIT_Y) 894 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 895 0, 896 IIO_MOD_Y, 897 IIO_EV_TYPE_ROC, 898 dir), 899 iio_get_time_ns()); 900 if (val & BMG160_ANY_MOTION_BIT_Z) 901 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, 902 0, 903 IIO_MOD_Z, 904 IIO_EV_TYPE_ROC, 905 dir), 906 iio_get_time_ns()); 907 908 ack_intr_status: 909 if (!data->dready_trigger_on) { 910 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, 911 BMG160_INT_MODE_LATCH_INT | 912 BMG160_INT_MODE_LATCH_RESET); 913 if (ret < 0) 914 dev_err(dev, "Error writing reg_rst_latch\n"); 915 } 916 917 return IRQ_HANDLED; 918 } 919 920 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private) 921 { 922 struct iio_dev *indio_dev = private; 923 struct bmg160_data *data = iio_priv(indio_dev); 924 925 if (data->dready_trigger_on) 926 iio_trigger_poll(data->dready_trig); 927 else if (data->motion_trigger_on) 928 iio_trigger_poll(data->motion_trig); 929 930 if (data->ev_enable_state) 931 return IRQ_WAKE_THREAD; 932 else 933 return IRQ_HANDLED; 934 935 } 936 937 static int bmg160_buffer_preenable(struct iio_dev *indio_dev) 938 { 939 struct bmg160_data *data = iio_priv(indio_dev); 940 941 return bmg160_set_power_state(data, true); 942 } 943 944 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev) 945 { 946 struct bmg160_data *data = iio_priv(indio_dev); 947 948 return bmg160_set_power_state(data, false); 949 } 950 951 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = { 952 .preenable = bmg160_buffer_preenable, 953 .postenable = iio_triggered_buffer_postenable, 954 .predisable = iio_triggered_buffer_predisable, 955 .postdisable = bmg160_buffer_postdisable, 956 }; 957 958 static const char *bmg160_match_acpi_device(struct device *dev) 959 { 960 const struct acpi_device_id *id; 961 962 id = acpi_match_device(dev->driver->acpi_match_table, dev); 963 if (!id) 964 return NULL; 965 966 return dev_name(dev); 967 } 968 969 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq, 970 const char *name) 971 { 972 struct bmg160_data *data; 973 struct iio_dev *indio_dev; 974 int ret; 975 976 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 977 if (!indio_dev) 978 return -ENOMEM; 979 980 data = iio_priv(indio_dev); 981 dev_set_drvdata(dev, indio_dev); 982 data->irq = irq; 983 data->regmap = regmap; 984 985 ret = bmg160_chip_init(data); 986 if (ret < 0) 987 return ret; 988 989 mutex_init(&data->mutex); 990 991 if (ACPI_HANDLE(dev)) 992 name = bmg160_match_acpi_device(dev); 993 994 indio_dev->dev.parent = dev; 995 indio_dev->channels = bmg160_channels; 996 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels); 997 indio_dev->name = name; 998 indio_dev->available_scan_masks = bmg160_accel_scan_masks; 999 indio_dev->modes = INDIO_DIRECT_MODE; 1000 indio_dev->info = &bmg160_info; 1001 1002 if (data->irq > 0) { 1003 ret = devm_request_threaded_irq(dev, 1004 data->irq, 1005 bmg160_data_rdy_trig_poll, 1006 bmg160_event_handler, 1007 IRQF_TRIGGER_RISING, 1008 BMG160_IRQ_NAME, 1009 indio_dev); 1010 if (ret) 1011 return ret; 1012 1013 data->dready_trig = devm_iio_trigger_alloc(dev, 1014 "%s-dev%d", 1015 indio_dev->name, 1016 indio_dev->id); 1017 if (!data->dready_trig) 1018 return -ENOMEM; 1019 1020 data->motion_trig = devm_iio_trigger_alloc(dev, 1021 "%s-any-motion-dev%d", 1022 indio_dev->name, 1023 indio_dev->id); 1024 if (!data->motion_trig) 1025 return -ENOMEM; 1026 1027 data->dready_trig->dev.parent = dev; 1028 data->dready_trig->ops = &bmg160_trigger_ops; 1029 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 1030 ret = iio_trigger_register(data->dready_trig); 1031 if (ret) 1032 return ret; 1033 1034 data->motion_trig->dev.parent = dev; 1035 data->motion_trig->ops = &bmg160_trigger_ops; 1036 iio_trigger_set_drvdata(data->motion_trig, indio_dev); 1037 ret = iio_trigger_register(data->motion_trig); 1038 if (ret) { 1039 data->motion_trig = NULL; 1040 goto err_trigger_unregister; 1041 } 1042 } 1043 1044 ret = iio_triggered_buffer_setup(indio_dev, 1045 iio_pollfunc_store_time, 1046 bmg160_trigger_handler, 1047 &bmg160_buffer_setup_ops); 1048 if (ret < 0) { 1049 dev_err(dev, 1050 "iio triggered buffer setup failed\n"); 1051 goto err_trigger_unregister; 1052 } 1053 1054 ret = pm_runtime_set_active(dev); 1055 if (ret) 1056 goto err_buffer_cleanup; 1057 1058 pm_runtime_enable(dev); 1059 pm_runtime_set_autosuspend_delay(dev, 1060 BMG160_AUTO_SUSPEND_DELAY_MS); 1061 pm_runtime_use_autosuspend(dev); 1062 1063 ret = iio_device_register(indio_dev); 1064 if (ret < 0) { 1065 dev_err(dev, "unable to register iio device\n"); 1066 goto err_buffer_cleanup; 1067 } 1068 1069 return 0; 1070 1071 err_buffer_cleanup: 1072 iio_triggered_buffer_cleanup(indio_dev); 1073 err_trigger_unregister: 1074 if (data->dready_trig) 1075 iio_trigger_unregister(data->dready_trig); 1076 if (data->motion_trig) 1077 iio_trigger_unregister(data->motion_trig); 1078 1079 return ret; 1080 } 1081 EXPORT_SYMBOL_GPL(bmg160_core_probe); 1082 1083 void bmg160_core_remove(struct device *dev) 1084 { 1085 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1086 struct bmg160_data *data = iio_priv(indio_dev); 1087 1088 iio_device_unregister(indio_dev); 1089 1090 pm_runtime_disable(dev); 1091 pm_runtime_set_suspended(dev); 1092 pm_runtime_put_noidle(dev); 1093 1094 iio_triggered_buffer_cleanup(indio_dev); 1095 1096 if (data->dready_trig) { 1097 iio_trigger_unregister(data->dready_trig); 1098 iio_trigger_unregister(data->motion_trig); 1099 } 1100 1101 mutex_lock(&data->mutex); 1102 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND); 1103 mutex_unlock(&data->mutex); 1104 } 1105 EXPORT_SYMBOL_GPL(bmg160_core_remove); 1106 1107 #ifdef CONFIG_PM_SLEEP 1108 static int bmg160_suspend(struct device *dev) 1109 { 1110 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1111 struct bmg160_data *data = iio_priv(indio_dev); 1112 1113 mutex_lock(&data->mutex); 1114 bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1115 mutex_unlock(&data->mutex); 1116 1117 return 0; 1118 } 1119 1120 static int bmg160_resume(struct device *dev) 1121 { 1122 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1123 struct bmg160_data *data = iio_priv(indio_dev); 1124 1125 mutex_lock(&data->mutex); 1126 if (data->dready_trigger_on || data->motion_trigger_on || 1127 data->ev_enable_state) 1128 bmg160_set_mode(data, BMG160_MODE_NORMAL); 1129 mutex_unlock(&data->mutex); 1130 1131 return 0; 1132 } 1133 #endif 1134 1135 #ifdef CONFIG_PM 1136 static int bmg160_runtime_suspend(struct device *dev) 1137 { 1138 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1139 struct bmg160_data *data = iio_priv(indio_dev); 1140 int ret; 1141 1142 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND); 1143 if (ret < 0) { 1144 dev_err(dev, "set mode failed\n"); 1145 return -EAGAIN; 1146 } 1147 1148 return 0; 1149 } 1150 1151 static int bmg160_runtime_resume(struct device *dev) 1152 { 1153 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1154 struct bmg160_data *data = iio_priv(indio_dev); 1155 int ret; 1156 1157 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); 1158 if (ret < 0) 1159 return ret; 1160 1161 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS); 1162 1163 return 0; 1164 } 1165 #endif 1166 1167 const struct dev_pm_ops bmg160_pm_ops = { 1168 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume) 1169 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend, 1170 bmg160_runtime_resume, NULL) 1171 }; 1172 EXPORT_SYMBOL_GPL(bmg160_pm_ops); 1173 1174 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1175 MODULE_LICENSE("GPL v2"); 1176 MODULE_DESCRIPTION("BMG160 Gyro driver"); 1177