1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADRF6780 driver 4 * 5 * Copyright 2021 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/clkdev.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/iio/iio.h> 15 #include <linux/module.h> 16 #include <linux/spi/spi.h> 17 18 #include <linux/unaligned.h> 19 20 /* ADRF6780 Register Map */ 21 #define ADRF6780_REG_CONTROL 0x00 22 #define ADRF6780_REG_ALARM_READBACK 0x01 23 #define ADRF6780_REG_ALARM_MASKS 0x02 24 #define ADRF6780_REG_ENABLE 0x03 25 #define ADRF6780_REG_LINEARIZE 0x04 26 #define ADRF6780_REG_LO_PATH 0x05 27 #define ADRF6780_REG_ADC_CONTROL 0x06 28 #define ADRF6780_REG_ADC_OUTPUT 0x0C 29 30 /* ADRF6780_REG_CONTROL Map */ 31 #define ADRF6780_PARITY_EN_MSK BIT(15) 32 #define ADRF6780_SOFT_RESET_MSK BIT(14) 33 #define ADRF6780_CHIP_ID_MSK GENMASK(11, 4) 34 #define ADRF6780_CHIP_ID 0xA 35 #define ADRF6780_CHIP_REVISION_MSK GENMASK(3, 0) 36 37 /* ADRF6780_REG_ALARM_READBACK Map */ 38 #define ADRF6780_PARITY_ERROR_MSK BIT(15) 39 #define ADRF6780_TOO_FEW_ERRORS_MSK BIT(14) 40 #define ADRF6780_TOO_MANY_ERRORS_MSK BIT(13) 41 #define ADRF6780_ADDRESS_RANGE_ERROR_MSK BIT(12) 42 43 /* ADRF6780_REG_ENABLE Map */ 44 #define ADRF6780_VGA_BUFFER_EN_MSK BIT(8) 45 #define ADRF6780_DETECTOR_EN_MSK BIT(7) 46 #define ADRF6780_LO_BUFFER_EN_MSK BIT(6) 47 #define ADRF6780_IF_MODE_EN_MSK BIT(5) 48 #define ADRF6780_IQ_MODE_EN_MSK BIT(4) 49 #define ADRF6780_LO_X2_EN_MSK BIT(3) 50 #define ADRF6780_LO_PPF_EN_MSK BIT(2) 51 #define ADRF6780_LO_EN_MSK BIT(1) 52 #define ADRF6780_UC_BIAS_EN_MSK BIT(0) 53 54 /* ADRF6780_REG_LINEARIZE Map */ 55 #define ADRF6780_RDAC_LINEARIZE_MSK GENMASK(7, 0) 56 57 /* ADRF6780_REG_LO_PATH Map */ 58 #define ADRF6780_LO_SIDEBAND_MSK BIT(10) 59 #define ADRF6780_Q_PATH_PHASE_ACCURACY_MSK GENMASK(7, 4) 60 #define ADRF6780_I_PATH_PHASE_ACCURACY_MSK GENMASK(3, 0) 61 62 /* ADRF6780_REG_ADC_CONTROL Map */ 63 #define ADRF6780_VDET_OUTPUT_SELECT_MSK BIT(3) 64 #define ADRF6780_ADC_START_MSK BIT(2) 65 #define ADRF6780_ADC_EN_MSK BIT(1) 66 #define ADRF6780_ADC_CLOCK_EN_MSK BIT(0) 67 68 /* ADRF6780_REG_ADC_OUTPUT Map */ 69 #define ADRF6780_ADC_STATUS_MSK BIT(8) 70 #define ADRF6780_ADC_VALUE_MSK GENMASK(7, 0) 71 72 struct adrf6780_state { 73 struct spi_device *spi; 74 struct clk *clkin; 75 /* Protect against concurrent accesses to the device */ 76 struct mutex lock; 77 bool vga_buff_en; 78 bool lo_buff_en; 79 bool if_mode_en; 80 bool iq_mode_en; 81 bool lo_x2_en; 82 bool lo_ppf_en; 83 bool lo_en; 84 bool uc_bias_en; 85 bool lo_sideband; 86 bool vdet_out_en; 87 u8 data[3] __aligned(IIO_DMA_MINALIGN); 88 }; 89 90 static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg, 91 unsigned int *val) 92 { 93 int ret; 94 struct spi_transfer t = {0}; 95 96 st->data[0] = 0x80 | (reg << 1); 97 st->data[1] = 0x0; 98 st->data[2] = 0x0; 99 100 t.rx_buf = &st->data[0]; 101 t.tx_buf = &st->data[0]; 102 t.len = 3; 103 104 ret = spi_sync_transfer(st->spi, &t, 1); 105 if (ret) 106 return ret; 107 108 *val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0); 109 110 return ret; 111 } 112 113 static int adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg, 114 unsigned int *val) 115 { 116 int ret; 117 118 mutex_lock(&st->lock); 119 ret = __adrf6780_spi_read(st, reg, val); 120 mutex_unlock(&st->lock); 121 122 return ret; 123 } 124 125 static int __adrf6780_spi_write(struct adrf6780_state *st, 126 unsigned int reg, 127 unsigned int val) 128 { 129 put_unaligned_be24((val << 1) | (reg << 17), &st->data[0]); 130 131 return spi_write(st->spi, &st->data[0], 3); 132 } 133 134 static int adrf6780_spi_write(struct adrf6780_state *st, unsigned int reg, 135 unsigned int val) 136 { 137 int ret; 138 139 mutex_lock(&st->lock); 140 ret = __adrf6780_spi_write(st, reg, val); 141 mutex_unlock(&st->lock); 142 143 return ret; 144 } 145 146 static int __adrf6780_spi_update_bits(struct adrf6780_state *st, 147 unsigned int reg, unsigned int mask, 148 unsigned int val) 149 { 150 int ret; 151 unsigned int data, temp; 152 153 ret = __adrf6780_spi_read(st, reg, &data); 154 if (ret) 155 return ret; 156 157 temp = (data & ~mask) | (val & mask); 158 159 return __adrf6780_spi_write(st, reg, temp); 160 } 161 162 static int adrf6780_spi_update_bits(struct adrf6780_state *st, unsigned int reg, 163 unsigned int mask, unsigned int val) 164 { 165 int ret; 166 167 mutex_lock(&st->lock); 168 ret = __adrf6780_spi_update_bits(st, reg, mask, val); 169 mutex_unlock(&st->lock); 170 171 return ret; 172 } 173 174 static int adrf6780_read_adc_raw(struct adrf6780_state *st, unsigned int *read_val) 175 { 176 int ret; 177 178 mutex_lock(&st->lock); 179 180 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL, 181 ADRF6780_ADC_EN_MSK | 182 ADRF6780_ADC_CLOCK_EN_MSK | 183 ADRF6780_ADC_START_MSK, 184 FIELD_PREP(ADRF6780_ADC_EN_MSK, 1) | 185 FIELD_PREP(ADRF6780_ADC_CLOCK_EN_MSK, 1) | 186 FIELD_PREP(ADRF6780_ADC_START_MSK, 1)); 187 if (ret) 188 goto exit; 189 190 /* 191 * Per ADRF6780 datasheet (Rev. D, page 23, ADC section), 192 * wait approximately 200 us for the ADC to be ready. 193 */ 194 fsleep(200); 195 196 ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val); 197 if (ret) 198 goto exit; 199 200 if (!(*read_val & ADRF6780_ADC_STATUS_MSK)) { 201 ret = -EINVAL; 202 goto exit; 203 } 204 205 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL, 206 ADRF6780_ADC_START_MSK, 207 FIELD_PREP(ADRF6780_ADC_START_MSK, 0)); 208 if (ret) 209 goto exit; 210 211 ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val); 212 213 exit: 214 mutex_unlock(&st->lock); 215 return ret; 216 } 217 218 static int adrf6780_read_raw(struct iio_dev *indio_dev, 219 struct iio_chan_spec const *chan, 220 int *val, int *val2, long info) 221 { 222 struct adrf6780_state *dev = iio_priv(indio_dev); 223 unsigned int data; 224 int ret; 225 226 switch (info) { 227 case IIO_CHAN_INFO_RAW: 228 ret = adrf6780_read_adc_raw(dev, &data); 229 if (ret) 230 return ret; 231 232 *val = data & ADRF6780_ADC_VALUE_MSK; 233 234 return IIO_VAL_INT; 235 236 case IIO_CHAN_INFO_SCALE: 237 ret = adrf6780_spi_read(dev, ADRF6780_REG_LINEARIZE, &data); 238 if (ret) 239 return ret; 240 241 *val = data & ADRF6780_RDAC_LINEARIZE_MSK; 242 243 return IIO_VAL_INT; 244 case IIO_CHAN_INFO_PHASE: 245 ret = adrf6780_spi_read(dev, ADRF6780_REG_LO_PATH, &data); 246 if (ret) 247 return ret; 248 249 switch (chan->channel2) { 250 case IIO_MOD_I: 251 *val = data & ADRF6780_I_PATH_PHASE_ACCURACY_MSK; 252 253 return IIO_VAL_INT; 254 case IIO_MOD_Q: 255 *val = FIELD_GET(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, 256 data); 257 258 return IIO_VAL_INT; 259 default: 260 return -EINVAL; 261 } 262 default: 263 return -EINVAL; 264 } 265 } 266 267 static int adrf6780_write_raw(struct iio_dev *indio_dev, 268 struct iio_chan_spec const *chan, 269 int val, int val2, long info) 270 { 271 struct adrf6780_state *st = iio_priv(indio_dev); 272 273 switch (info) { 274 case IIO_CHAN_INFO_SCALE: 275 return adrf6780_spi_write(st, ADRF6780_REG_LINEARIZE, val); 276 case IIO_CHAN_INFO_PHASE: 277 switch (chan->channel2) { 278 case IIO_MOD_I: 279 return adrf6780_spi_update_bits(st, 280 ADRF6780_REG_LO_PATH, 281 ADRF6780_I_PATH_PHASE_ACCURACY_MSK, 282 FIELD_PREP(ADRF6780_I_PATH_PHASE_ACCURACY_MSK, val)); 283 case IIO_MOD_Q: 284 return adrf6780_spi_update_bits(st, 285 ADRF6780_REG_LO_PATH, 286 ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, 287 FIELD_PREP(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, val)); 288 default: 289 return -EINVAL; 290 } 291 default: 292 return -EINVAL; 293 } 294 } 295 296 static int adrf6780_reg_access(struct iio_dev *indio_dev, 297 unsigned int reg, 298 unsigned int write_val, 299 unsigned int *read_val) 300 { 301 struct adrf6780_state *st = iio_priv(indio_dev); 302 303 if (read_val) 304 return adrf6780_spi_read(st, reg, read_val); 305 else 306 return adrf6780_spi_write(st, reg, write_val); 307 } 308 309 static const struct iio_info adrf6780_info = { 310 .read_raw = adrf6780_read_raw, 311 .write_raw = adrf6780_write_raw, 312 .debugfs_reg_access = &adrf6780_reg_access, 313 }; 314 315 #define ADRF6780_CHAN_ADC(_channel) { \ 316 .type = IIO_ALTVOLTAGE, \ 317 .output = 0, \ 318 .indexed = 1, \ 319 .channel = _channel, \ 320 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 321 } 322 323 #define ADRF6780_CHAN_RDAC(_channel) { \ 324 .type = IIO_ALTVOLTAGE, \ 325 .output = 1, \ 326 .indexed = 1, \ 327 .channel = _channel, \ 328 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) \ 329 } 330 331 #define ADRF6780_CHAN_IQ_PHASE(_channel, rf_comp) { \ 332 .type = IIO_ALTVOLTAGE, \ 333 .modified = 1, \ 334 .output = 1, \ 335 .indexed = 1, \ 336 .channel2 = IIO_MOD_##rf_comp, \ 337 .channel = _channel, \ 338 .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) \ 339 } 340 341 static const struct iio_chan_spec adrf6780_channels[] = { 342 ADRF6780_CHAN_ADC(0), 343 ADRF6780_CHAN_RDAC(0), 344 ADRF6780_CHAN_IQ_PHASE(0, I), 345 ADRF6780_CHAN_IQ_PHASE(0, Q), 346 }; 347 348 static int adrf6780_reset(struct adrf6780_state *st) 349 { 350 int ret; 351 struct device *dev = &st->spi->dev; 352 353 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL, 354 ADRF6780_SOFT_RESET_MSK, 355 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 1)); 356 if (ret) 357 return dev_err_probe(dev, ret, 358 "ADRF6780 SPI software reset failed.\n"); 359 360 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL, 361 ADRF6780_SOFT_RESET_MSK, 362 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 0)); 363 if (ret) 364 return dev_err_probe(dev, ret, 365 "ADRF6780 SPI software reset disable failed.\n"); 366 367 return 0; 368 } 369 370 static int adrf6780_init(struct adrf6780_state *st) 371 { 372 int ret; 373 unsigned int chip_id, enable_reg, enable_reg_msk; 374 struct device *dev = &st->spi->dev; 375 376 /* Perform a software reset */ 377 ret = adrf6780_reset(st); 378 if (ret) 379 return ret; 380 381 ret = __adrf6780_spi_read(st, ADRF6780_REG_CONTROL, &chip_id); 382 if (ret) 383 return ret; 384 385 chip_id = FIELD_GET(ADRF6780_CHIP_ID_MSK, chip_id); 386 if (chip_id != ADRF6780_CHIP_ID) 387 return dev_err_probe(dev, -EINVAL, 388 "ADRF6780 Invalid Chip ID.\n"); 389 390 enable_reg_msk = ADRF6780_VGA_BUFFER_EN_MSK | 391 ADRF6780_DETECTOR_EN_MSK | 392 ADRF6780_LO_BUFFER_EN_MSK | 393 ADRF6780_IF_MODE_EN_MSK | 394 ADRF6780_IQ_MODE_EN_MSK | 395 ADRF6780_LO_X2_EN_MSK | 396 ADRF6780_LO_PPF_EN_MSK | 397 ADRF6780_LO_EN_MSK | 398 ADRF6780_UC_BIAS_EN_MSK; 399 400 enable_reg = FIELD_PREP(ADRF6780_VGA_BUFFER_EN_MSK, st->vga_buff_en) | 401 FIELD_PREP(ADRF6780_DETECTOR_EN_MSK, 1) | 402 FIELD_PREP(ADRF6780_LO_BUFFER_EN_MSK, st->lo_buff_en) | 403 FIELD_PREP(ADRF6780_IF_MODE_EN_MSK, st->if_mode_en) | 404 FIELD_PREP(ADRF6780_IQ_MODE_EN_MSK, st->iq_mode_en) | 405 FIELD_PREP(ADRF6780_LO_X2_EN_MSK, st->lo_x2_en) | 406 FIELD_PREP(ADRF6780_LO_PPF_EN_MSK, st->lo_ppf_en) | 407 FIELD_PREP(ADRF6780_LO_EN_MSK, st->lo_en) | 408 FIELD_PREP(ADRF6780_UC_BIAS_EN_MSK, st->uc_bias_en); 409 410 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ENABLE, 411 enable_reg_msk, enable_reg); 412 if (ret) 413 return ret; 414 415 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_LO_PATH, 416 ADRF6780_LO_SIDEBAND_MSK, 417 FIELD_PREP(ADRF6780_LO_SIDEBAND_MSK, st->lo_sideband)); 418 if (ret) 419 return ret; 420 421 return __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL, 422 ADRF6780_VDET_OUTPUT_SELECT_MSK, 423 FIELD_PREP(ADRF6780_VDET_OUTPUT_SELECT_MSK, st->vdet_out_en)); 424 } 425 426 static void adrf6780_properties_parse(struct adrf6780_state *st) 427 { 428 struct device *dev = &st->spi->dev; 429 430 st->vga_buff_en = device_property_read_bool(dev, "adi,vga-buff-en"); 431 st->lo_buff_en = device_property_read_bool(dev, "adi,lo-buff-en"); 432 st->if_mode_en = device_property_read_bool(dev, "adi,if-mode-en"); 433 st->iq_mode_en = device_property_read_bool(dev, "adi,iq-mode-en"); 434 st->lo_x2_en = device_property_read_bool(dev, "adi,lo-x2-en"); 435 st->lo_ppf_en = device_property_read_bool(dev, "adi,lo-ppf-en"); 436 st->lo_en = device_property_read_bool(dev, "adi,lo-en"); 437 st->uc_bias_en = device_property_read_bool(dev, "adi,uc-bias-en"); 438 st->lo_sideband = device_property_read_bool(dev, "adi,lo-sideband"); 439 st->vdet_out_en = device_property_read_bool(dev, "adi,vdet-out-en"); 440 } 441 442 static void adrf6780_powerdown(void *data) 443 { 444 /* Disable all components in the Enable Register */ 445 adrf6780_spi_write(data, ADRF6780_REG_ENABLE, 0x0); 446 } 447 448 static int adrf6780_probe(struct spi_device *spi) 449 { 450 struct iio_dev *indio_dev; 451 struct adrf6780_state *st; 452 struct device *dev = &spi->dev; 453 int ret; 454 455 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 456 if (!indio_dev) 457 return -ENOMEM; 458 459 st = iio_priv(indio_dev); 460 461 indio_dev->info = &adrf6780_info; 462 indio_dev->name = "adrf6780"; 463 indio_dev->channels = adrf6780_channels; 464 indio_dev->num_channels = ARRAY_SIZE(adrf6780_channels); 465 466 st->spi = spi; 467 468 adrf6780_properties_parse(st); 469 470 st->clkin = devm_clk_get_enabled(dev, "lo_in"); 471 if (IS_ERR(st->clkin)) 472 return dev_err_probe(dev, PTR_ERR(st->clkin), 473 "failed to get the LO input clock\n"); 474 475 mutex_init(&st->lock); 476 477 ret = adrf6780_init(st); 478 if (ret) 479 return ret; 480 481 ret = devm_add_action_or_reset(dev, adrf6780_powerdown, st); 482 if (ret) 483 return ret; 484 485 return devm_iio_device_register(dev, indio_dev); 486 } 487 488 static const struct spi_device_id adrf6780_id[] = { 489 { .name = "adrf6780" }, 490 { } 491 }; 492 MODULE_DEVICE_TABLE(spi, adrf6780_id); 493 494 static const struct of_device_id adrf6780_of_match[] = { 495 { .compatible = "adi,adrf6780" }, 496 { } 497 }; 498 MODULE_DEVICE_TABLE(of, adrf6780_of_match); 499 500 static struct spi_driver adrf6780_driver = { 501 .driver = { 502 .name = "adrf6780", 503 .of_match_table = adrf6780_of_match, 504 }, 505 .probe = adrf6780_probe, 506 .id_table = adrf6780_id, 507 }; 508 module_spi_driver(adrf6780_driver); 509 510 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); 511 MODULE_DESCRIPTION("Analog Devices ADRF6780"); 512 MODULE_LICENSE("GPL v2"); 513