1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADMV1014 driver 4 * 5 * Copyright 2022 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/clkdev.h> 12 #include <linux/device.h> 13 #include <linux/iio/iio.h> 14 #include <linux/module.h> 15 #include <linux/notifier.h> 16 #include <linux/property.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/spi/spi.h> 19 #include <linux/units.h> 20 21 #include <linux/unaligned.h> 22 23 /* ADMV1014 Register Map */ 24 #define ADMV1014_REG_SPI_CONTROL 0x00 25 #define ADMV1014_REG_ALARM 0x01 26 #define ADMV1014_REG_ALARM_MASKS 0x02 27 #define ADMV1014_REG_ENABLE 0x03 28 #define ADMV1014_REG_QUAD 0x04 29 #define ADMV1014_REG_LO_AMP_PHASE_ADJUST1 0x05 30 #define ADMV1014_REG_MIXER 0x07 31 #define ADMV1014_REG_IF_AMP 0x08 32 #define ADMV1014_REG_IF_AMP_BB_AMP 0x09 33 #define ADMV1014_REG_BB_AMP_AGC 0x0A 34 #define ADMV1014_REG_VVA_TEMP_COMP 0x0B 35 36 /* ADMV1014_REG_SPI_CONTROL Map */ 37 #define ADMV1014_PARITY_EN_MSK BIT(15) 38 #define ADMV1014_SPI_SOFT_RESET_MSK BIT(14) 39 #define ADMV1014_CHIP_ID_MSK GENMASK(11, 4) 40 #define ADMV1014_CHIP_ID 0x9 41 #define ADMV1014_REVISION_ID_MSK GENMASK(3, 0) 42 43 /* ADMV1014_REG_ALARM Map */ 44 #define ADMV1014_PARITY_ERROR_MSK BIT(15) 45 #define ADMV1014_TOO_FEW_ERRORS_MSK BIT(14) 46 #define ADMV1014_TOO_MANY_ERRORS_MSK BIT(13) 47 #define ADMV1014_ADDRESS_RANGE_ERROR_MSK BIT(12) 48 49 /* ADMV1014_REG_ENABLE Map */ 50 #define ADMV1014_IBIAS_PD_MSK BIT(14) 51 #define ADMV1014_P1DB_COMPENSATION_MSK GENMASK(13, 12) 52 #define ADMV1014_IF_AMP_PD_MSK BIT(11) 53 #define ADMV1014_QUAD_BG_PD_MSK BIT(9) 54 #define ADMV1014_BB_AMP_PD_MSK BIT(8) 55 #define ADMV1014_QUAD_IBIAS_PD_MSK BIT(7) 56 #define ADMV1014_DET_EN_MSK BIT(6) 57 #define ADMV1014_BG_PD_MSK BIT(5) 58 59 /* ADMV1014_REG_QUAD Map */ 60 #define ADMV1014_QUAD_SE_MODE_MSK GENMASK(9, 6) 61 #define ADMV1014_QUAD_FILTERS_MSK GENMASK(3, 0) 62 63 /* ADMV1014_REG_LO_AMP_PHASE_ADJUST1 Map */ 64 #define ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK GENMASK(15, 9) 65 #define ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK GENMASK(8, 2) 66 67 /* ADMV1014_REG_MIXER Map */ 68 #define ADMV1014_MIXER_VGATE_MSK GENMASK(15, 9) 69 #define ADMV1014_DET_PROG_MSK GENMASK(6, 0) 70 71 /* ADMV1014_REG_IF_AMP Map */ 72 #define ADMV1014_IF_AMP_COARSE_GAIN_I_MSK GENMASK(11, 8) 73 #define ADMV1014_IF_AMP_FINE_GAIN_Q_MSK GENMASK(7, 4) 74 #define ADMV1014_IF_AMP_FINE_GAIN_I_MSK GENMASK(3, 0) 75 76 /* ADMV1014_REG_IF_AMP_BB_AMP Map */ 77 #define ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK GENMASK(15, 12) 78 #define ADMV1014_BB_AMP_OFFSET_Q_MSK GENMASK(9, 5) 79 #define ADMV1014_BB_AMP_OFFSET_I_MSK GENMASK(4, 0) 80 81 /* ADMV1014_REG_BB_AMP_AGC Map */ 82 #define ADMV1014_BB_AMP_REF_GEN_MSK GENMASK(6, 3) 83 #define ADMV1014_BB_AMP_GAIN_CTRL_MSK GENMASK(2, 1) 84 #define ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK BIT(0) 85 86 /* ADMV1014_REG_VVA_TEMP_COMP Map */ 87 #define ADMV1014_VVA_TEMP_COMP_MSK GENMASK(15, 0) 88 89 /* ADMV1014 Miscellaneous Defines */ 90 #define ADMV1014_READ BIT(7) 91 #define ADMV1014_REG_ADDR_READ_MSK GENMASK(6, 1) 92 #define ADMV1014_REG_ADDR_WRITE_MSK GENMASK(22, 17) 93 #define ADMV1014_REG_DATA_MSK GENMASK(16, 1) 94 #define ADMV1014_NUM_REGULATORS 9 95 96 enum { 97 ADMV1014_IQ_MODE, 98 ADMV1014_IF_MODE, 99 }; 100 101 enum { 102 ADMV1014_SE_MODE_POS = 6, 103 ADMV1014_SE_MODE_NEG = 9, 104 ADMV1014_SE_MODE_DIFF = 12, 105 }; 106 107 enum { 108 ADMV1014_CALIBSCALE_COARSE, 109 ADMV1014_CALIBSCALE_FINE, 110 }; 111 112 static const int detector_table[] = {0, 1, 2, 4, 8, 16, 32, 64}; 113 114 static const char * const input_mode_names[] = { "iq", "if" }; 115 116 static const char * const quad_se_mode_names[] = { "se-pos", "se-neg", "diff" }; 117 118 struct admv1014_state { 119 struct spi_device *spi; 120 struct clk *clkin; 121 struct notifier_block nb; 122 /* Protect against concurrent accesses to the device and to data*/ 123 struct mutex lock; 124 struct regulator_bulk_data regulators[ADMV1014_NUM_REGULATORS]; 125 unsigned int input_mode; 126 unsigned int quad_se_mode; 127 unsigned int p1db_comp; 128 bool det_en; 129 u8 data[3] __aligned(IIO_DMA_MINALIGN); 130 }; 131 132 static const int mixer_vgate_table[] = {106, 107, 108, 110, 111, 112, 113, 114, 133 117, 118, 119, 120, 122, 123, 44, 45}; 134 135 static int __admv1014_spi_read(struct admv1014_state *st, unsigned int reg, 136 unsigned int *val) 137 { 138 struct spi_transfer t = {}; 139 int ret; 140 141 st->data[0] = ADMV1014_READ | FIELD_PREP(ADMV1014_REG_ADDR_READ_MSK, reg); 142 st->data[1] = 0; 143 st->data[2] = 0; 144 145 t.rx_buf = &st->data[0]; 146 t.tx_buf = &st->data[0]; 147 t.len = sizeof(st->data); 148 149 ret = spi_sync_transfer(st->spi, &t, 1); 150 if (ret) 151 return ret; 152 153 *val = FIELD_GET(ADMV1014_REG_DATA_MSK, get_unaligned_be24(&st->data[0])); 154 155 return ret; 156 } 157 158 static int admv1014_spi_read(struct admv1014_state *st, unsigned int reg, 159 unsigned int *val) 160 { 161 int ret; 162 163 mutex_lock(&st->lock); 164 ret = __admv1014_spi_read(st, reg, val); 165 mutex_unlock(&st->lock); 166 167 return ret; 168 } 169 170 static int __admv1014_spi_write(struct admv1014_state *st, 171 unsigned int reg, 172 unsigned int val) 173 { 174 put_unaligned_be24(FIELD_PREP(ADMV1014_REG_DATA_MSK, val) | 175 FIELD_PREP(ADMV1014_REG_ADDR_WRITE_MSK, reg), &st->data[0]); 176 177 return spi_write(st->spi, &st->data[0], 3); 178 } 179 180 static int admv1014_spi_write(struct admv1014_state *st, unsigned int reg, 181 unsigned int val) 182 { 183 int ret; 184 185 mutex_lock(&st->lock); 186 ret = __admv1014_spi_write(st, reg, val); 187 mutex_unlock(&st->lock); 188 189 return ret; 190 } 191 192 static int __admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg, 193 unsigned int mask, unsigned int val) 194 { 195 unsigned int data, temp; 196 int ret; 197 198 ret = __admv1014_spi_read(st, reg, &data); 199 if (ret) 200 return ret; 201 202 temp = (data & ~mask) | (val & mask); 203 204 return __admv1014_spi_write(st, reg, temp); 205 } 206 207 static int admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg, 208 unsigned int mask, unsigned int val) 209 { 210 int ret; 211 212 mutex_lock(&st->lock); 213 ret = __admv1014_spi_update_bits(st, reg, mask, val); 214 mutex_unlock(&st->lock); 215 216 return ret; 217 } 218 219 static int admv1014_update_quad_filters(struct admv1014_state *st) 220 { 221 unsigned int filt_raw; 222 u64 rate = clk_get_rate(st->clkin); 223 224 if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ)) 225 filt_raw = 15; 226 else if (rate > (7000 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ)) 227 filt_raw = 10; 228 else if (rate > (8000 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ)) 229 filt_raw = 5; 230 else 231 filt_raw = 0; 232 233 return __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD, 234 ADMV1014_QUAD_FILTERS_MSK, 235 FIELD_PREP(ADMV1014_QUAD_FILTERS_MSK, filt_raw)); 236 } 237 238 static int admv1014_update_vcm_settings(struct admv1014_state *st) 239 { 240 unsigned int i, vcm_mv, vcm_comp, bb_sw_hl_cm; 241 int ret; 242 243 vcm_mv = regulator_get_voltage(st->regulators[0].consumer) / 1000; 244 for (i = 0; i < ARRAY_SIZE(mixer_vgate_table); i++) { 245 vcm_comp = 1050 + mult_frac(i, 450, 8); 246 if (vcm_mv != vcm_comp) 247 continue; 248 249 ret = __admv1014_spi_update_bits(st, ADMV1014_REG_MIXER, 250 ADMV1014_MIXER_VGATE_MSK, 251 FIELD_PREP(ADMV1014_MIXER_VGATE_MSK, 252 mixer_vgate_table[i])); 253 if (ret) 254 return ret; 255 256 bb_sw_hl_cm = ~(i / 8); 257 bb_sw_hl_cm = FIELD_PREP(ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK, bb_sw_hl_cm); 258 259 return __admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC, 260 ADMV1014_BB_AMP_REF_GEN_MSK | 261 ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK, 262 FIELD_PREP(ADMV1014_BB_AMP_REF_GEN_MSK, i) | 263 bb_sw_hl_cm); 264 } 265 266 return -EINVAL; 267 } 268 269 static int admv1014_read_raw(struct iio_dev *indio_dev, 270 struct iio_chan_spec const *chan, 271 int *val, int *val2, long info) 272 { 273 struct admv1014_state *st = iio_priv(indio_dev); 274 unsigned int data; 275 int ret; 276 277 switch (info) { 278 case IIO_CHAN_INFO_OFFSET: 279 ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data); 280 if (ret) 281 return ret; 282 283 if (chan->channel2 == IIO_MOD_I) 284 *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_I_MSK, data); 285 else 286 *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_Q_MSK, data); 287 288 return IIO_VAL_INT; 289 case IIO_CHAN_INFO_PHASE: 290 ret = admv1014_spi_read(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, &data); 291 if (ret) 292 return ret; 293 294 if (chan->channel2 == IIO_MOD_I) 295 *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, data); 296 else 297 *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, data); 298 299 return IIO_VAL_INT; 300 case IIO_CHAN_INFO_SCALE: 301 ret = admv1014_spi_read(st, ADMV1014_REG_MIXER, &data); 302 if (ret) 303 return ret; 304 305 *val = FIELD_GET(ADMV1014_DET_PROG_MSK, data); 306 return IIO_VAL_INT; 307 case IIO_CHAN_INFO_CALIBSCALE: 308 ret = admv1014_spi_read(st, ADMV1014_REG_BB_AMP_AGC, &data); 309 if (ret) 310 return ret; 311 312 *val = FIELD_GET(ADMV1014_BB_AMP_GAIN_CTRL_MSK, data); 313 return IIO_VAL_INT; 314 default: 315 return -EINVAL; 316 } 317 } 318 319 static int admv1014_write_raw(struct iio_dev *indio_dev, 320 struct iio_chan_spec const *chan, 321 int val, int val2, long info) 322 { 323 int data; 324 unsigned int msk; 325 struct admv1014_state *st = iio_priv(indio_dev); 326 327 switch (info) { 328 case IIO_CHAN_INFO_OFFSET: 329 if (chan->channel2 == IIO_MOD_I) { 330 msk = ADMV1014_BB_AMP_OFFSET_I_MSK; 331 data = FIELD_PREP(ADMV1014_BB_AMP_OFFSET_I_MSK, val); 332 } else { 333 msk = ADMV1014_BB_AMP_OFFSET_Q_MSK; 334 data = FIELD_PREP(ADMV1014_BB_AMP_OFFSET_Q_MSK, val); 335 } 336 337 return admv1014_spi_update_bits(st, ADMV1014_REG_IF_AMP_BB_AMP, msk, data); 338 case IIO_CHAN_INFO_PHASE: 339 if (chan->channel2 == IIO_MOD_I) { 340 msk = ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK; 341 data = FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, val); 342 } else { 343 msk = ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK; 344 data = FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, val); 345 } 346 347 return admv1014_spi_update_bits(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, msk, data); 348 case IIO_CHAN_INFO_SCALE: 349 return admv1014_spi_update_bits(st, ADMV1014_REG_MIXER, 350 ADMV1014_DET_PROG_MSK, 351 FIELD_PREP(ADMV1014_DET_PROG_MSK, val)); 352 case IIO_CHAN_INFO_CALIBSCALE: 353 return admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC, 354 ADMV1014_BB_AMP_GAIN_CTRL_MSK, 355 FIELD_PREP(ADMV1014_BB_AMP_GAIN_CTRL_MSK, val)); 356 default: 357 return -EINVAL; 358 } 359 } 360 361 static ssize_t admv1014_read(struct iio_dev *indio_dev, 362 uintptr_t private, 363 const struct iio_chan_spec *chan, 364 char *buf) 365 { 366 struct admv1014_state *st = iio_priv(indio_dev); 367 unsigned int data; 368 int ret; 369 370 switch (private) { 371 case ADMV1014_CALIBSCALE_COARSE: 372 if (chan->channel2 == IIO_MOD_I) { 373 ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data); 374 if (ret) 375 return ret; 376 377 data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data); 378 } else { 379 ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data); 380 if (ret) 381 return ret; 382 383 data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data); 384 } 385 break; 386 case ADMV1014_CALIBSCALE_FINE: 387 ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data); 388 if (ret) 389 return ret; 390 391 if (chan->channel2 == IIO_MOD_I) 392 data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data); 393 else 394 data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data); 395 break; 396 default: 397 return -EINVAL; 398 } 399 400 return sysfs_emit(buf, "%u\n", data); 401 } 402 403 static ssize_t admv1014_write(struct iio_dev *indio_dev, 404 uintptr_t private, 405 const struct iio_chan_spec *chan, 406 const char *buf, size_t len) 407 { 408 struct admv1014_state *st = iio_priv(indio_dev); 409 unsigned int data, addr, msk; 410 int ret; 411 412 ret = kstrtouint(buf, 10, &data); 413 if (ret) 414 return ret; 415 416 switch (private) { 417 case ADMV1014_CALIBSCALE_COARSE: 418 if (chan->channel2 == IIO_MOD_I) { 419 addr = ADMV1014_REG_IF_AMP; 420 msk = ADMV1014_IF_AMP_COARSE_GAIN_I_MSK; 421 data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data); 422 } else { 423 addr = ADMV1014_REG_IF_AMP_BB_AMP; 424 msk = ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK; 425 data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data); 426 } 427 break; 428 case ADMV1014_CALIBSCALE_FINE: 429 addr = ADMV1014_REG_IF_AMP; 430 431 if (chan->channel2 == IIO_MOD_I) { 432 msk = ADMV1014_IF_AMP_FINE_GAIN_I_MSK; 433 data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data); 434 } else { 435 msk = ADMV1014_IF_AMP_FINE_GAIN_Q_MSK; 436 data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data); 437 } 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 ret = admv1014_spi_update_bits(st, addr, msk, data); 444 445 return ret ? ret : len; 446 } 447 448 static int admv1014_read_avail(struct iio_dev *indio_dev, 449 struct iio_chan_spec const *chan, 450 const int **vals, int *type, int *length, 451 long info) 452 { 453 switch (info) { 454 case IIO_CHAN_INFO_SCALE: 455 *vals = detector_table; 456 *type = IIO_VAL_INT; 457 *length = ARRAY_SIZE(detector_table); 458 459 return IIO_AVAIL_LIST; 460 default: 461 return -EINVAL; 462 } 463 } 464 465 static int admv1014_reg_access(struct iio_dev *indio_dev, 466 unsigned int reg, 467 unsigned int write_val, 468 unsigned int *read_val) 469 { 470 struct admv1014_state *st = iio_priv(indio_dev); 471 472 if (read_val) 473 return admv1014_spi_read(st, reg, read_val); 474 else 475 return admv1014_spi_write(st, reg, write_val); 476 } 477 478 static const struct iio_info admv1014_info = { 479 .read_raw = admv1014_read_raw, 480 .write_raw = admv1014_write_raw, 481 .read_avail = &admv1014_read_avail, 482 .debugfs_reg_access = &admv1014_reg_access, 483 }; 484 485 static const char * const admv1014_reg_name[] = { 486 "vcm", "vcc-if-bb", "vcc-vga", "vcc-vva", "vcc-lna-3p3", 487 "vcc-lna-1p5", "vcc-bg", "vcc-quad", "vcc-mixer" 488 }; 489 490 static int admv1014_freq_change(struct notifier_block *nb, unsigned long action, void *data) 491 { 492 struct admv1014_state *st = container_of(nb, struct admv1014_state, nb); 493 int ret; 494 495 if (action == POST_RATE_CHANGE) { 496 mutex_lock(&st->lock); 497 ret = notifier_from_errno(admv1014_update_quad_filters(st)); 498 mutex_unlock(&st->lock); 499 return ret; 500 } 501 502 return NOTIFY_OK; 503 } 504 505 #define _ADMV1014_EXT_INFO(_name, _shared, _ident) { \ 506 .name = _name, \ 507 .read = admv1014_read, \ 508 .write = admv1014_write, \ 509 .private = _ident, \ 510 .shared = _shared, \ 511 } 512 513 static const struct iio_chan_spec_ext_info admv1014_ext_info[] = { 514 _ADMV1014_EXT_INFO("calibscale_coarse", IIO_SEPARATE, ADMV1014_CALIBSCALE_COARSE), 515 _ADMV1014_EXT_INFO("calibscale_fine", IIO_SEPARATE, ADMV1014_CALIBSCALE_FINE), 516 { } 517 }; 518 519 #define ADMV1014_CHAN_IQ(_channel, rf_comp) { \ 520 .type = IIO_ALTVOLTAGE, \ 521 .modified = 1, \ 522 .output = 0, \ 523 .indexed = 1, \ 524 .channel2 = IIO_MOD_##rf_comp, \ 525 .channel = _channel, \ 526 .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | \ 527 BIT(IIO_CHAN_INFO_OFFSET), \ 528 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBSCALE), \ 529 } 530 531 #define ADMV1014_CHAN_IF(_channel, rf_comp) { \ 532 .type = IIO_ALTVOLTAGE, \ 533 .modified = 1, \ 534 .output = 0, \ 535 .indexed = 1, \ 536 .channel2 = IIO_MOD_##rf_comp, \ 537 .channel = _channel, \ 538 .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | \ 539 BIT(IIO_CHAN_INFO_OFFSET), \ 540 } 541 542 #define ADMV1014_CHAN_POWER(_channel) { \ 543 .type = IIO_POWER, \ 544 .output = 0, \ 545 .indexed = 1, \ 546 .channel = _channel, \ 547 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \ 548 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 549 } 550 551 #define ADMV1014_CHAN_CALIBSCALE(_channel, rf_comp, _admv1014_ext_info) { \ 552 .type = IIO_ALTVOLTAGE, \ 553 .modified = 1, \ 554 .output = 0, \ 555 .indexed = 1, \ 556 .channel2 = IIO_MOD_##rf_comp, \ 557 .channel = _channel, \ 558 .ext_info = _admv1014_ext_info, \ 559 } 560 561 static const struct iio_chan_spec admv1014_channels_iq[] = { 562 ADMV1014_CHAN_IQ(0, I), 563 ADMV1014_CHAN_IQ(0, Q), 564 ADMV1014_CHAN_POWER(0), 565 }; 566 567 static const struct iio_chan_spec admv1014_channels_if[] = { 568 ADMV1014_CHAN_IF(0, I), 569 ADMV1014_CHAN_IF(0, Q), 570 ADMV1014_CHAN_CALIBSCALE(0, I, admv1014_ext_info), 571 ADMV1014_CHAN_CALIBSCALE(0, Q, admv1014_ext_info), 572 ADMV1014_CHAN_POWER(0), 573 }; 574 575 static void admv1014_clk_disable(void *data) 576 { 577 clk_disable_unprepare(data); 578 } 579 580 static void admv1014_reg_disable(void *data) 581 { 582 regulator_bulk_disable(ADMV1014_NUM_REGULATORS, data); 583 } 584 585 static void admv1014_powerdown(void *data) 586 { 587 unsigned int enable_reg, enable_reg_msk; 588 589 /* Disable all components in the Enable Register */ 590 enable_reg_msk = ADMV1014_IBIAS_PD_MSK | 591 ADMV1014_IF_AMP_PD_MSK | 592 ADMV1014_QUAD_BG_PD_MSK | 593 ADMV1014_BB_AMP_PD_MSK | 594 ADMV1014_QUAD_IBIAS_PD_MSK | 595 ADMV1014_BG_PD_MSK; 596 597 enable_reg = FIELD_PREP(ADMV1014_IBIAS_PD_MSK, 1) | 598 FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, 1) | 599 FIELD_PREP(ADMV1014_QUAD_BG_PD_MSK, 1) | 600 FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, 1) | 601 FIELD_PREP(ADMV1014_QUAD_IBIAS_PD_MSK, 1) | 602 FIELD_PREP(ADMV1014_BG_PD_MSK, 1); 603 604 admv1014_spi_update_bits(data, ADMV1014_REG_ENABLE, 605 enable_reg_msk, enable_reg); 606 } 607 608 static int admv1014_init(struct admv1014_state *st) 609 { 610 unsigned int chip_id, enable_reg, enable_reg_msk; 611 struct spi_device *spi = st->spi; 612 struct device *dev = &spi->dev; 613 int ret; 614 615 ret = regulator_bulk_enable(ADMV1014_NUM_REGULATORS, st->regulators); 616 if (ret) 617 return dev_err_probe(dev, ret, "Failed to enable regulators"); 618 619 ret = devm_add_action_or_reset(dev, admv1014_reg_disable, st->regulators); 620 if (ret) 621 return ret; 622 623 ret = clk_prepare_enable(st->clkin); 624 if (ret) 625 return ret; 626 627 ret = devm_add_action_or_reset(dev, admv1014_clk_disable, st->clkin); 628 if (ret) 629 return ret; 630 631 st->nb.notifier_call = admv1014_freq_change; 632 ret = devm_clk_notifier_register(dev, st->clkin, &st->nb); 633 if (ret) 634 return ret; 635 636 ret = devm_add_action_or_reset(dev, admv1014_powerdown, st); 637 if (ret) 638 return ret; 639 640 /* Perform a software reset */ 641 ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, 642 ADMV1014_SPI_SOFT_RESET_MSK, 643 FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 1)); 644 if (ret) 645 return dev_err_probe(dev, ret, 646 "ADMV1014 SPI software reset failed.\n"); 647 648 ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, 649 ADMV1014_SPI_SOFT_RESET_MSK, 650 FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 0)); 651 if (ret) 652 return dev_err_probe(dev, ret, 653 "ADMV1014 SPI software reset disable failed.\n"); 654 655 ret = __admv1014_spi_write(st, ADMV1014_REG_VVA_TEMP_COMP, 0x727C); 656 if (ret) 657 return dev_err_probe(dev, ret, 658 "Writing default Temperature Compensation value failed.\n"); 659 660 ret = __admv1014_spi_read(st, ADMV1014_REG_SPI_CONTROL, &chip_id); 661 if (ret) 662 return ret; 663 664 chip_id = FIELD_GET(ADMV1014_CHIP_ID_MSK, chip_id); 665 if (chip_id != ADMV1014_CHIP_ID) 666 return dev_err_probe(dev, -EINVAL, "Invalid Chip ID.\n"); 667 668 ret = __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD, 669 ADMV1014_QUAD_SE_MODE_MSK, 670 FIELD_PREP(ADMV1014_QUAD_SE_MODE_MSK, 671 st->quad_se_mode)); 672 if (ret) 673 return dev_err_probe(dev, ret, 674 "Writing Quad SE Mode failed.\n"); 675 676 ret = admv1014_update_quad_filters(st); 677 if (ret) 678 return dev_err_probe(dev, ret, 679 "Update Quad Filters failed.\n"); 680 681 ret = admv1014_update_vcm_settings(st); 682 if (ret) 683 return dev_err_probe(dev, ret, 684 "Update VCM Settings failed.\n"); 685 686 enable_reg_msk = ADMV1014_P1DB_COMPENSATION_MSK | 687 ADMV1014_IF_AMP_PD_MSK | 688 ADMV1014_BB_AMP_PD_MSK | 689 ADMV1014_DET_EN_MSK; 690 691 enable_reg = FIELD_PREP(ADMV1014_P1DB_COMPENSATION_MSK, st->p1db_comp ? 3 : 0) | 692 FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, 693 (st->input_mode == ADMV1014_IF_MODE) ? 0 : 1) | 694 FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, 695 (st->input_mode == ADMV1014_IF_MODE) ? 1 : 0) | 696 FIELD_PREP(ADMV1014_DET_EN_MSK, st->det_en); 697 698 return __admv1014_spi_update_bits(st, ADMV1014_REG_ENABLE, enable_reg_msk, enable_reg); 699 } 700 701 static int admv1014_properties_parse(struct admv1014_state *st) 702 { 703 unsigned int i; 704 struct spi_device *spi = st->spi; 705 struct device *dev = &spi->dev; 706 int ret; 707 708 st->det_en = device_property_read_bool(dev, "adi,detector-enable"); 709 710 st->p1db_comp = device_property_read_bool(dev, "adi,p1db-compensation-enable"); 711 712 ret = device_property_match_property_string(dev, "adi,input-mode", 713 input_mode_names, 714 ARRAY_SIZE(input_mode_names)); 715 if (ret >= 0) 716 st->input_mode = ret; 717 else 718 st->input_mode = ADMV1014_IQ_MODE; 719 720 ret = device_property_match_property_string(dev, "adi,quad-se-mode", 721 quad_se_mode_names, 722 ARRAY_SIZE(quad_se_mode_names)); 723 if (ret >= 0) 724 st->quad_se_mode = ADMV1014_SE_MODE_POS + (ret * 3); 725 else 726 st->quad_se_mode = ADMV1014_SE_MODE_POS; 727 728 for (i = 0; i < ADMV1014_NUM_REGULATORS; ++i) 729 st->regulators[i].supply = admv1014_reg_name[i]; 730 731 ret = devm_regulator_bulk_get(dev, ADMV1014_NUM_REGULATORS, 732 st->regulators); 733 if (ret) 734 return dev_err_probe(dev, ret, "Failed to request regulators"); 735 736 st->clkin = devm_clk_get(dev, "lo_in"); 737 if (IS_ERR(st->clkin)) 738 return dev_err_probe(dev, PTR_ERR(st->clkin), 739 "failed to get the LO input clock\n"); 740 741 return 0; 742 } 743 744 static int admv1014_probe(struct spi_device *spi) 745 { 746 struct iio_dev *indio_dev; 747 struct admv1014_state *st; 748 struct device *dev = &spi->dev; 749 int ret; 750 751 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 752 if (!indio_dev) 753 return -ENOMEM; 754 755 st = iio_priv(indio_dev); 756 757 ret = admv1014_properties_parse(st); 758 if (ret) 759 return ret; 760 761 indio_dev->info = &admv1014_info; 762 indio_dev->name = "admv1014"; 763 764 if (st->input_mode == ADMV1014_IQ_MODE) { 765 indio_dev->channels = admv1014_channels_iq; 766 indio_dev->num_channels = ARRAY_SIZE(admv1014_channels_iq); 767 } else { 768 indio_dev->channels = admv1014_channels_if; 769 indio_dev->num_channels = ARRAY_SIZE(admv1014_channels_if); 770 } 771 772 st->spi = spi; 773 774 mutex_init(&st->lock); 775 776 ret = admv1014_init(st); 777 if (ret) 778 return ret; 779 780 return devm_iio_device_register(dev, indio_dev); 781 } 782 783 static const struct spi_device_id admv1014_id[] = { 784 { .name = "admv1014" }, 785 { } 786 }; 787 MODULE_DEVICE_TABLE(spi, admv1014_id); 788 789 static const struct of_device_id admv1014_of_match[] = { 790 { .compatible = "adi,admv1014" }, 791 { } 792 }; 793 MODULE_DEVICE_TABLE(of, admv1014_of_match); 794 795 static struct spi_driver admv1014_driver = { 796 .driver = { 797 .name = "admv1014", 798 .of_match_table = admv1014_of_match, 799 }, 800 .probe = admv1014_probe, 801 .id_table = admv1014_id, 802 }; 803 module_spi_driver(admv1014_driver); 804 805 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); 806 MODULE_DESCRIPTION("Analog Devices ADMV1014"); 807 MODULE_LICENSE("GPL v2"); 808