1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADMV1013 driver 4 * 5 * Copyright 2021 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/iio/iio.h> 13 #include <linux/module.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/notifier.h> 16 #include <linux/property.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/spi/spi.h> 19 #include <linux/units.h> 20 21 #include <asm/unaligned.h> 22 23 /* ADMV1013 Register Map */ 24 #define ADMV1013_REG_SPI_CONTROL 0x00 25 #define ADMV1013_REG_ALARM 0x01 26 #define ADMV1013_REG_ALARM_MASKS 0x02 27 #define ADMV1013_REG_ENABLE 0x03 28 #define ADMV1013_REG_LO_AMP_I 0x05 29 #define ADMV1013_REG_LO_AMP_Q 0x06 30 #define ADMV1013_REG_OFFSET_ADJUST_I 0x07 31 #define ADMV1013_REG_OFFSET_ADJUST_Q 0x08 32 #define ADMV1013_REG_QUAD 0x09 33 #define ADMV1013_REG_VVA_TEMP_COMP 0x0A 34 35 /* ADMV1013_REG_SPI_CONTROL Map */ 36 #define ADMV1013_PARITY_EN_MSK BIT(15) 37 #define ADMV1013_SPI_SOFT_RESET_MSK BIT(14) 38 #define ADMV1013_CHIP_ID_MSK GENMASK(11, 4) 39 #define ADMV1013_CHIP_ID 0xA 40 #define ADMV1013_REVISION_ID_MSK GENMASK(3, 0) 41 42 /* ADMV1013_REG_ALARM Map */ 43 #define ADMV1013_PARITY_ERROR_MSK BIT(15) 44 #define ADMV1013_TOO_FEW_ERRORS_MSK BIT(14) 45 #define ADMV1013_TOO_MANY_ERRORS_MSK BIT(13) 46 #define ADMV1013_ADDRESS_RANGE_ERROR_MSK BIT(12) 47 48 /* ADMV1013_REG_ENABLE Map */ 49 #define ADMV1013_VGA_PD_MSK BIT(15) 50 #define ADMV1013_MIXER_PD_MSK BIT(14) 51 #define ADMV1013_QUAD_PD_MSK GENMASK(13, 11) 52 #define ADMV1013_BG_PD_MSK BIT(10) 53 #define ADMV1013_MIXER_IF_EN_MSK BIT(7) 54 #define ADMV1013_DET_EN_MSK BIT(5) 55 56 /* ADMV1013_REG_LO_AMP Map */ 57 #define ADMV1013_LOAMP_PH_ADJ_FINE_MSK GENMASK(13, 7) 58 #define ADMV1013_MIXER_VGATE_MSK GENMASK(6, 0) 59 60 /* ADMV1013_REG_OFFSET_ADJUST Map */ 61 #define ADMV1013_MIXER_OFF_ADJ_P_MSK GENMASK(15, 9) 62 #define ADMV1013_MIXER_OFF_ADJ_N_MSK GENMASK(8, 2) 63 64 /* ADMV1013_REG_QUAD Map */ 65 #define ADMV1013_QUAD_SE_MODE_MSK GENMASK(9, 6) 66 #define ADMV1013_QUAD_FILTERS_MSK GENMASK(3, 0) 67 68 /* ADMV1013_REG_VVA_TEMP_COMP Map */ 69 #define ADMV1013_VVA_TEMP_COMP_MSK GENMASK(15, 0) 70 71 /* ADMV1013 Miscellaneous Defines */ 72 #define ADMV1013_READ BIT(7) 73 #define ADMV1013_REG_ADDR_READ_MSK GENMASK(6, 1) 74 #define ADMV1013_REG_ADDR_WRITE_MSK GENMASK(22, 17) 75 #define ADMV1013_REG_DATA_MSK GENMASK(16, 1) 76 77 enum { 78 ADMV1013_IQ_MODE, 79 ADMV1013_IF_MODE 80 }; 81 82 enum { 83 ADMV1013_RFMOD_I_CALIBPHASE, 84 ADMV1013_RFMOD_Q_CALIBPHASE, 85 }; 86 87 enum { 88 ADMV1013_SE_MODE_POS = 6, 89 ADMV1013_SE_MODE_NEG = 9, 90 ADMV1013_SE_MODE_DIFF = 12 91 }; 92 93 struct admv1013_state { 94 struct spi_device *spi; 95 struct clk *clkin; 96 /* Protect against concurrent accesses to the device and to data */ 97 struct mutex lock; 98 struct regulator *reg; 99 struct notifier_block nb; 100 unsigned int input_mode; 101 unsigned int quad_se_mode; 102 bool det_en; 103 u8 data[3] __aligned(IIO_DMA_MINALIGN); 104 }; 105 106 static int __admv1013_spi_read(struct admv1013_state *st, unsigned int reg, 107 unsigned int *val) 108 { 109 int ret; 110 struct spi_transfer t = {0}; 111 112 st->data[0] = ADMV1013_READ | FIELD_PREP(ADMV1013_REG_ADDR_READ_MSK, reg); 113 st->data[1] = 0x0; 114 st->data[2] = 0x0; 115 116 t.rx_buf = &st->data[0]; 117 t.tx_buf = &st->data[0]; 118 t.len = 3; 119 120 ret = spi_sync_transfer(st->spi, &t, 1); 121 if (ret) 122 return ret; 123 124 *val = FIELD_GET(ADMV1013_REG_DATA_MSK, get_unaligned_be24(&st->data[0])); 125 126 return ret; 127 } 128 129 static int admv1013_spi_read(struct admv1013_state *st, unsigned int reg, 130 unsigned int *val) 131 { 132 int ret; 133 134 mutex_lock(&st->lock); 135 ret = __admv1013_spi_read(st, reg, val); 136 mutex_unlock(&st->lock); 137 138 return ret; 139 } 140 141 static int __admv1013_spi_write(struct admv1013_state *st, 142 unsigned int reg, 143 unsigned int val) 144 { 145 put_unaligned_be24(FIELD_PREP(ADMV1013_REG_DATA_MSK, val) | 146 FIELD_PREP(ADMV1013_REG_ADDR_WRITE_MSK, reg), &st->data[0]); 147 148 return spi_write(st->spi, &st->data[0], 3); 149 } 150 151 static int admv1013_spi_write(struct admv1013_state *st, unsigned int reg, 152 unsigned int val) 153 { 154 int ret; 155 156 mutex_lock(&st->lock); 157 ret = __admv1013_spi_write(st, reg, val); 158 mutex_unlock(&st->lock); 159 160 return ret; 161 } 162 163 static int __admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg, 164 unsigned int mask, unsigned int val) 165 { 166 int ret; 167 unsigned int data, temp; 168 169 ret = __admv1013_spi_read(st, reg, &data); 170 if (ret) 171 return ret; 172 173 temp = (data & ~mask) | (val & mask); 174 175 return __admv1013_spi_write(st, reg, temp); 176 } 177 178 static int admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg, 179 unsigned int mask, unsigned int val) 180 { 181 int ret; 182 183 mutex_lock(&st->lock); 184 ret = __admv1013_spi_update_bits(st, reg, mask, val); 185 mutex_unlock(&st->lock); 186 187 return ret; 188 } 189 190 static int admv1013_read_raw(struct iio_dev *indio_dev, 191 struct iio_chan_spec const *chan, 192 int *val, int *val2, long info) 193 { 194 struct admv1013_state *st = iio_priv(indio_dev); 195 unsigned int data, addr; 196 int ret; 197 198 switch (info) { 199 case IIO_CHAN_INFO_CALIBBIAS: 200 switch (chan->channel) { 201 case IIO_MOD_I: 202 addr = ADMV1013_REG_OFFSET_ADJUST_I; 203 break; 204 case IIO_MOD_Q: 205 addr = ADMV1013_REG_OFFSET_ADJUST_Q; 206 break; 207 default: 208 return -EINVAL; 209 } 210 211 ret = admv1013_spi_read(st, addr, &data); 212 if (ret) 213 return ret; 214 215 if (!chan->channel) 216 *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_P_MSK, data); 217 else 218 *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_N_MSK, data); 219 220 return IIO_VAL_INT; 221 default: 222 return -EINVAL; 223 } 224 } 225 226 static int admv1013_write_raw(struct iio_dev *indio_dev, 227 struct iio_chan_spec const *chan, 228 int val, int val2, long info) 229 { 230 struct admv1013_state *st = iio_priv(indio_dev); 231 unsigned int addr, data, msk; 232 233 switch (info) { 234 case IIO_CHAN_INFO_CALIBBIAS: 235 switch (chan->channel2) { 236 case IIO_MOD_I: 237 addr = ADMV1013_REG_OFFSET_ADJUST_I; 238 break; 239 case IIO_MOD_Q: 240 addr = ADMV1013_REG_OFFSET_ADJUST_Q; 241 break; 242 default: 243 return -EINVAL; 244 } 245 246 if (!chan->channel) { 247 msk = ADMV1013_MIXER_OFF_ADJ_P_MSK; 248 data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_P_MSK, val); 249 } else { 250 msk = ADMV1013_MIXER_OFF_ADJ_N_MSK; 251 data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_N_MSK, val); 252 } 253 254 return admv1013_spi_update_bits(st, addr, msk, data); 255 default: 256 return -EINVAL; 257 } 258 } 259 260 static ssize_t admv1013_read(struct iio_dev *indio_dev, 261 uintptr_t private, 262 const struct iio_chan_spec *chan, 263 char *buf) 264 { 265 struct admv1013_state *st = iio_priv(indio_dev); 266 unsigned int data, addr; 267 int ret; 268 269 switch ((u32)private) { 270 case ADMV1013_RFMOD_I_CALIBPHASE: 271 addr = ADMV1013_REG_LO_AMP_I; 272 break; 273 case ADMV1013_RFMOD_Q_CALIBPHASE: 274 addr = ADMV1013_REG_LO_AMP_Q; 275 break; 276 default: 277 return -EINVAL; 278 } 279 280 ret = admv1013_spi_read(st, addr, &data); 281 if (ret) 282 return ret; 283 284 data = FIELD_GET(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data); 285 286 return sysfs_emit(buf, "%u\n", data); 287 } 288 289 static ssize_t admv1013_write(struct iio_dev *indio_dev, 290 uintptr_t private, 291 const struct iio_chan_spec *chan, 292 const char *buf, size_t len) 293 { 294 struct admv1013_state *st = iio_priv(indio_dev); 295 unsigned int data; 296 int ret; 297 298 ret = kstrtou32(buf, 10, &data); 299 if (ret) 300 return ret; 301 302 data = FIELD_PREP(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data); 303 304 switch ((u32)private) { 305 case ADMV1013_RFMOD_I_CALIBPHASE: 306 ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I, 307 ADMV1013_LOAMP_PH_ADJ_FINE_MSK, 308 data); 309 if (ret) 310 return ret; 311 break; 312 case ADMV1013_RFMOD_Q_CALIBPHASE: 313 ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_Q, 314 ADMV1013_LOAMP_PH_ADJ_FINE_MSK, 315 data); 316 if (ret) 317 return ret; 318 break; 319 default: 320 return -EINVAL; 321 } 322 323 return ret ? ret : len; 324 } 325 326 static int admv1013_update_quad_filters(struct admv1013_state *st) 327 { 328 unsigned int filt_raw; 329 u64 rate = clk_get_rate(st->clkin); 330 331 if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ)) 332 filt_raw = 15; 333 else if (rate >= (5400 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ)) 334 filt_raw = 10; 335 else if (rate >= (6600 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ)) 336 filt_raw = 5; 337 else 338 filt_raw = 0; 339 340 return __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD, 341 ADMV1013_QUAD_FILTERS_MSK, 342 FIELD_PREP(ADMV1013_QUAD_FILTERS_MSK, filt_raw)); 343 } 344 345 static int admv1013_update_mixer_vgate(struct admv1013_state *st) 346 { 347 unsigned int vcm, mixer_vgate; 348 349 vcm = regulator_get_voltage(st->reg); 350 351 if (vcm < 1800000) 352 mixer_vgate = (2389 * vcm / 1000000 + 8100) / 100; 353 else if (vcm > 1800000 && vcm < 2600000) 354 mixer_vgate = (2375 * vcm / 1000000 + 125) / 100; 355 else 356 return -EINVAL; 357 358 return __admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I, 359 ADMV1013_MIXER_VGATE_MSK, 360 FIELD_PREP(ADMV1013_MIXER_VGATE_MSK, mixer_vgate)); 361 } 362 363 static int admv1013_reg_access(struct iio_dev *indio_dev, 364 unsigned int reg, 365 unsigned int write_val, 366 unsigned int *read_val) 367 { 368 struct admv1013_state *st = iio_priv(indio_dev); 369 370 if (read_val) 371 return admv1013_spi_read(st, reg, read_val); 372 else 373 return admv1013_spi_write(st, reg, write_val); 374 } 375 376 static const struct iio_info admv1013_info = { 377 .read_raw = admv1013_read_raw, 378 .write_raw = admv1013_write_raw, 379 .debugfs_reg_access = &admv1013_reg_access, 380 }; 381 382 static const char * const admv1013_vcc_regs[] = { 383 "vcc-drv", "vcc2-drv", "vcc-vva", "vcc-amp1", "vcc-amp2", 384 "vcc-env", "vcc-bg", "vcc-bg2", "vcc-mixer", "vcc-quad" 385 }; 386 387 static int admv1013_freq_change(struct notifier_block *nb, unsigned long action, void *data) 388 { 389 struct admv1013_state *st = container_of(nb, struct admv1013_state, nb); 390 int ret; 391 392 if (action == POST_RATE_CHANGE) { 393 mutex_lock(&st->lock); 394 ret = notifier_from_errno(admv1013_update_quad_filters(st)); 395 mutex_unlock(&st->lock); 396 return ret; 397 } 398 399 return NOTIFY_OK; 400 } 401 402 #define _ADMV1013_EXT_INFO(_name, _shared, _ident) { \ 403 .name = _name, \ 404 .read = admv1013_read, \ 405 .write = admv1013_write, \ 406 .private = _ident, \ 407 .shared = _shared, \ 408 } 409 410 static const struct iio_chan_spec_ext_info admv1013_ext_info[] = { 411 _ADMV1013_EXT_INFO("i_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_I_CALIBPHASE), 412 _ADMV1013_EXT_INFO("q_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_Q_CALIBPHASE), 413 { }, 414 }; 415 416 #define ADMV1013_CHAN_PHASE(_channel, _channel2, _admv1013_ext_info) { \ 417 .type = IIO_ALTVOLTAGE, \ 418 .output = 0, \ 419 .indexed = 1, \ 420 .channel2 = _channel2, \ 421 .channel = _channel, \ 422 .differential = 1, \ 423 .ext_info = _admv1013_ext_info, \ 424 } 425 426 #define ADMV1013_CHAN_CALIB(_channel, rf_comp) { \ 427 .type = IIO_ALTVOLTAGE, \ 428 .output = 0, \ 429 .indexed = 1, \ 430 .channel = _channel, \ 431 .channel2 = IIO_MOD_##rf_comp, \ 432 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBBIAS), \ 433 } 434 435 static const struct iio_chan_spec admv1013_channels[] = { 436 ADMV1013_CHAN_PHASE(0, 1, admv1013_ext_info), 437 ADMV1013_CHAN_CALIB(0, I), 438 ADMV1013_CHAN_CALIB(0, Q), 439 ADMV1013_CHAN_CALIB(1, I), 440 ADMV1013_CHAN_CALIB(1, Q), 441 }; 442 443 static int admv1013_init(struct admv1013_state *st) 444 { 445 int ret; 446 unsigned int data; 447 struct spi_device *spi = st->spi; 448 449 /* Perform a software reset */ 450 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL, 451 ADMV1013_SPI_SOFT_RESET_MSK, 452 FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 1)); 453 if (ret) 454 return ret; 455 456 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL, 457 ADMV1013_SPI_SOFT_RESET_MSK, 458 FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 0)); 459 if (ret) 460 return ret; 461 462 ret = __admv1013_spi_read(st, ADMV1013_REG_SPI_CONTROL, &data); 463 if (ret) 464 return ret; 465 466 data = FIELD_GET(ADMV1013_CHIP_ID_MSK, data); 467 if (data != ADMV1013_CHIP_ID) { 468 dev_err(&spi->dev, "Invalid Chip ID.\n"); 469 return -EINVAL; 470 } 471 472 ret = __admv1013_spi_write(st, ADMV1013_REG_VVA_TEMP_COMP, 0xE700); 473 if (ret) 474 return ret; 475 476 data = FIELD_PREP(ADMV1013_QUAD_SE_MODE_MSK, st->quad_se_mode); 477 478 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD, 479 ADMV1013_QUAD_SE_MODE_MSK, data); 480 if (ret) 481 return ret; 482 483 ret = admv1013_update_mixer_vgate(st); 484 if (ret) 485 return ret; 486 487 ret = admv1013_update_quad_filters(st); 488 if (ret) 489 return ret; 490 491 return __admv1013_spi_update_bits(st, ADMV1013_REG_ENABLE, 492 ADMV1013_DET_EN_MSK | 493 ADMV1013_MIXER_IF_EN_MSK, 494 st->det_en | 495 st->input_mode); 496 } 497 498 static void admv1013_reg_disable(void *data) 499 { 500 regulator_disable(data); 501 } 502 503 static void admv1013_powerdown(void *data) 504 { 505 unsigned int enable_reg, enable_reg_msk; 506 507 /* Disable all components in the Enable Register */ 508 enable_reg_msk = ADMV1013_VGA_PD_MSK | 509 ADMV1013_MIXER_PD_MSK | 510 ADMV1013_QUAD_PD_MSK | 511 ADMV1013_BG_PD_MSK | 512 ADMV1013_MIXER_IF_EN_MSK | 513 ADMV1013_DET_EN_MSK; 514 515 enable_reg = FIELD_PREP(ADMV1013_VGA_PD_MSK, 1) | 516 FIELD_PREP(ADMV1013_MIXER_PD_MSK, 1) | 517 FIELD_PREP(ADMV1013_QUAD_PD_MSK, 7) | 518 FIELD_PREP(ADMV1013_BG_PD_MSK, 1) | 519 FIELD_PREP(ADMV1013_MIXER_IF_EN_MSK, 0) | 520 FIELD_PREP(ADMV1013_DET_EN_MSK, 0); 521 522 admv1013_spi_update_bits(data, ADMV1013_REG_ENABLE, enable_reg_msk, enable_reg); 523 } 524 525 static int admv1013_properties_parse(struct admv1013_state *st) 526 { 527 int ret; 528 const char *str; 529 struct spi_device *spi = st->spi; 530 531 st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable"); 532 533 ret = device_property_read_string(&spi->dev, "adi,input-mode", &str); 534 if (ret) 535 st->input_mode = ADMV1013_IQ_MODE; 536 537 if (!strcmp(str, "iq")) 538 st->input_mode = ADMV1013_IQ_MODE; 539 else if (!strcmp(str, "if")) 540 st->input_mode = ADMV1013_IF_MODE; 541 else 542 return -EINVAL; 543 544 ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str); 545 if (ret) 546 st->quad_se_mode = ADMV1013_SE_MODE_DIFF; 547 548 if (!strcmp(str, "diff")) 549 st->quad_se_mode = ADMV1013_SE_MODE_DIFF; 550 else if (!strcmp(str, "se-pos")) 551 st->quad_se_mode = ADMV1013_SE_MODE_POS; 552 else if (!strcmp(str, "se-neg")) 553 st->quad_se_mode = ADMV1013_SE_MODE_NEG; 554 else 555 return -EINVAL; 556 557 st->reg = devm_regulator_get(&spi->dev, "vcm"); 558 if (IS_ERR(st->reg)) 559 return dev_err_probe(&spi->dev, PTR_ERR(st->reg), 560 "failed to get the common-mode voltage\n"); 561 562 ret = devm_regulator_bulk_get_enable(&st->spi->dev, 563 ARRAY_SIZE(admv1013_vcc_regs), 564 admv1013_vcc_regs); 565 if (ret) { 566 dev_err_probe(&spi->dev, ret, 567 "Failed to request VCC regulators\n"); 568 return ret; 569 } 570 571 return 0; 572 } 573 574 static int admv1013_probe(struct spi_device *spi) 575 { 576 struct iio_dev *indio_dev; 577 struct admv1013_state *st; 578 int ret; 579 580 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 581 if (!indio_dev) 582 return -ENOMEM; 583 584 st = iio_priv(indio_dev); 585 586 indio_dev->info = &admv1013_info; 587 indio_dev->name = "admv1013"; 588 indio_dev->channels = admv1013_channels; 589 indio_dev->num_channels = ARRAY_SIZE(admv1013_channels); 590 591 st->spi = spi; 592 593 ret = admv1013_properties_parse(st); 594 if (ret) 595 return ret; 596 597 ret = regulator_enable(st->reg); 598 if (ret) { 599 dev_err(&spi->dev, "Failed to enable specified Common-Mode Voltage!\n"); 600 return ret; 601 } 602 603 ret = devm_add_action_or_reset(&spi->dev, admv1013_reg_disable, 604 st->reg); 605 if (ret) 606 return ret; 607 608 st->clkin = devm_clk_get_enabled(&spi->dev, "lo_in"); 609 if (IS_ERR(st->clkin)) 610 return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), 611 "failed to get the LO input clock\n"); 612 613 st->nb.notifier_call = admv1013_freq_change; 614 ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb); 615 if (ret) 616 return ret; 617 618 mutex_init(&st->lock); 619 620 ret = admv1013_init(st); 621 if (ret) { 622 dev_err(&spi->dev, "admv1013 init failed\n"); 623 return ret; 624 } 625 626 ret = devm_add_action_or_reset(&spi->dev, admv1013_powerdown, st); 627 if (ret) 628 return ret; 629 630 return devm_iio_device_register(&spi->dev, indio_dev); 631 } 632 633 static const struct spi_device_id admv1013_id[] = { 634 { "admv1013", 0 }, 635 {} 636 }; 637 MODULE_DEVICE_TABLE(spi, admv1013_id); 638 639 static const struct of_device_id admv1013_of_match[] = { 640 { .compatible = "adi,admv1013" }, 641 {}, 642 }; 643 MODULE_DEVICE_TABLE(of, admv1013_of_match); 644 645 static struct spi_driver admv1013_driver = { 646 .driver = { 647 .name = "admv1013", 648 .of_match_table = admv1013_of_match, 649 }, 650 .probe = admv1013_probe, 651 .id_table = admv1013_id, 652 }; 653 module_spi_driver(admv1013_driver); 654 655 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); 656 MODULE_DESCRIPTION("Analog Devices ADMV1013"); 657 MODULE_LICENSE("GPL v2"); 658