1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADF4377 driver 4 * 5 * Copyright 2022 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/clkdev.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/module.h> 16 #include <linux/notifier.h> 17 #include <linux/property.h> 18 #include <linux/spi/spi.h> 19 #include <linux/iio/iio.h> 20 #include <linux/regmap.h> 21 #include <linux/units.h> 22 23 #include <linux/unaligned.h> 24 25 /* ADF4377 REG0000 Map */ 26 #define ADF4377_0000_SOFT_RESET_R_MSK BIT(7) 27 #define ADF4377_0000_LSB_FIRST_R_MSK BIT(6) 28 #define ADF4377_0000_ADDRESS_ASC_R_MSK BIT(5) 29 #define ADF4377_0000_SDO_ACTIVE_R_MSK BIT(4) 30 #define ADF4377_0000_SDO_ACTIVE_MSK BIT(3) 31 #define ADF4377_0000_ADDRESS_ASC_MSK BIT(2) 32 #define ADF4377_0000_LSB_FIRST_MSK BIT(1) 33 #define ADF4377_0000_SOFT_RESET_MSK BIT(0) 34 35 /* ADF4377 REG0000 Bit Definition */ 36 #define ADF4377_0000_SDO_ACTIVE_SPI_3W 0x0 37 #define ADF4377_0000_SDO_ACTIVE_SPI_4W 0x1 38 39 #define ADF4377_0000_ADDR_ASC_AUTO_DECR 0x0 40 #define ADF4377_0000_ADDR_ASC_AUTO_INCR 0x1 41 42 #define ADF4377_0000_LSB_FIRST_MSB 0x0 43 #define ADF4377_0000_LSB_FIRST_LSB 0x1 44 45 #define ADF4377_0000_SOFT_RESET_N_OP 0x0 46 #define ADF4377_0000_SOFT_RESET_EN 0x1 47 48 /* ADF4377 REG0001 Map */ 49 #define ADF4377_0001_SINGLE_INSTR_MSK BIT(7) 50 #define ADF4377_0001_MASTER_RB_CTRL_MSK BIT(5) 51 52 /* ADF4377 REG0003 Bit Definition */ 53 #define ADF4377_0003_CHIP_TYPE 0x06 54 55 /* ADF4377 REG0004 Bit Definition */ 56 #define ADF4377_0004_PRODUCT_ID_LSB 0x0005 57 58 /* ADF4377 REG0005 Bit Definition */ 59 #define ADF4377_0005_PRODUCT_ID_MSB 0x0005 60 61 /* ADF4377 REG000A Map */ 62 #define ADF4377_000A_SCRATCHPAD_MSK GENMASK(7, 0) 63 64 /* ADF4377 REG000C Bit Definition */ 65 #define ADF4377_000C_VENDOR_ID_LSB 0x56 66 67 /* ADF4377 REG000D Bit Definition */ 68 #define ADF4377_000D_VENDOR_ID_MSB 0x04 69 70 /* ADF4377 REG000F Bit Definition */ 71 #define ADF4377_000F_R00F_RSV1_MSK GENMASK(7, 0) 72 73 /* ADF4377 REG0010 Map*/ 74 #define ADF4377_0010_N_INT_LSB_MSK GENMASK(7, 0) 75 76 /* ADF4377 REG0011 Map*/ 77 #define ADF4377_0011_EN_AUTOCAL_MSK BIT(7) 78 #define ADF4377_0011_EN_RDBLR_MSK BIT(6) 79 #define ADF4377_0011_DCLK_DIV2_MSK GENMASK(5, 4) 80 #define ADF4377_0011_N_INT_MSB_MSK GENMASK(3, 0) 81 82 /* ADF4377 REG0011 Bit Definition */ 83 #define ADF4377_0011_DCLK_DIV2_1 0x0 84 #define ADF4377_0011_DCLK_DIV2_2 0x1 85 #define ADF4377_0011_DCLK_DIV2_4 0x2 86 #define ADF4377_0011_DCLK_DIV2_8 0x3 87 88 /* ADF4377 REG0012 Map*/ 89 #define ADF4377_0012_CLKOUT_DIV_MSK GENMASK(7, 6) 90 #define ADF4377_0012_R_DIV_MSK GENMASK(5, 0) 91 92 /* ADF4377 REG0012 Bit Definition */ 93 #define ADF4377_0012_CLKOUT_DIV_1 0x0 94 #define ADF4377_0012_CLKOUT_DIV_2 0x1 95 #define ADF4377_0012_CLKOUT_DIV_4 0x2 96 #define ADF4377_0012_CLKOUT_DIV_8 0x3 97 98 /* ADF4377 REG0013 Map */ 99 #define ADF4377_0013_M_VCO_CORE_MSK GENMASK(5, 4) 100 #define ADF4377_0013_VCO_BIAS_MSK GENMASK(3, 0) 101 102 /* ADF4377 REG0013 Bit Definition */ 103 #define ADF4377_0013_M_VCO_0 0x0 104 #define ADF4377_0013_M_VCO_1 0x1 105 #define ADF4377_0013_M_VCO_2 0x2 106 #define ADF4377_0013_M_VCO_3 0x3 107 108 /* ADF4377 REG0014 Map */ 109 #define ADF4377_0014_M_VCO_BAND_MSK GENMASK(7, 0) 110 111 /* ADF4377 REG0015 Map */ 112 #define ADF4377_0015_BLEED_I_LSB_MSK GENMASK(7, 6) 113 #define ADF4377_0015_BLEED_POL_MSK BIT(5) 114 #define ADF4377_0015_EN_BLEED_MSK BIT(4) 115 #define ADF4377_0015_CP_I_MSK GENMASK(3, 0) 116 117 /* ADF4377 REG0015 Bit Definition */ 118 #define ADF4377_CURRENT_SINK 0x0 119 #define ADF4377_CURRENT_SOURCE 0x1 120 121 #define ADF4377_0015_CP_0MA7 0x0 122 #define ADF4377_0015_CP_0MA9 0x1 123 #define ADF4377_0015_CP_1MA1 0x2 124 #define ADF4377_0015_CP_1MA3 0x3 125 #define ADF4377_0015_CP_1MA4 0x4 126 #define ADF4377_0015_CP_1MA8 0x5 127 #define ADF4377_0015_CP_2MA2 0x6 128 #define ADF4377_0015_CP_2MA5 0x7 129 #define ADF4377_0015_CP_2MA9 0x8 130 #define ADF4377_0015_CP_3MA6 0x9 131 #define ADF4377_0015_CP_4MA3 0xA 132 #define ADF4377_0015_CP_5MA0 0xB 133 #define ADF4377_0015_CP_5MA7 0xC 134 #define ADF4377_0015_CP_7MA2 0xD 135 #define ADF4377_0015_CP_8MA6 0xE 136 #define ADF4377_0015_CP_10MA1 0xF 137 138 /* ADF4377 REG0016 Map */ 139 #define ADF4377_0016_BLEED_I_MSB_MSK GENMASK(7, 0) 140 141 /* ADF4377 REG0017 Map */ 142 #define ADF4377_0016_INV_CLKOUT_MSK BIT(7) 143 #define ADF4377_0016_N_DEL_MSK GENMASK(6, 0) 144 145 /* ADF4377 REG0018 Map */ 146 #define ADF4377_0018_CMOS_OV_MSK BIT(7) 147 #define ADF4377_0018_R_DEL_MSK GENMASK(6, 0) 148 149 /* ADF4377 REG0018 Bit Definition */ 150 #define ADF4377_0018_1V8_LOGIC 0x0 151 #define ADF4377_0018_3V3_LOGIC 0x1 152 153 /* ADF4377 REG0019 Map */ 154 #define ADF4377_0019_CLKOUT2_OP_MSK GENMASK(7, 6) 155 #define ADF4377_0019_CLKOUT1_OP_MSK GENMASK(5, 4) 156 #define ADF4377_0019_PD_CLK_MSK BIT(3) 157 #define ADF4377_0019_PD_RDET_MSK BIT(2) 158 #define ADF4377_0019_PD_ADC_MSK BIT(1) 159 #define ADF4377_0019_PD_CALADC_MSK BIT(0) 160 161 /* ADF4377 REG0019 Bit Definition */ 162 #define ADF4377_0019_CLKOUT_320MV 0x0 163 #define ADF4377_0019_CLKOUT_420MV 0x1 164 #define ADF4377_0019_CLKOUT_530MV 0x2 165 #define ADF4377_0019_CLKOUT_640MV 0x3 166 167 /* ADF4377 REG001A Map */ 168 #define ADF4377_001A_PD_ALL_MSK BIT(7) 169 #define ADF4377_001A_PD_RDIV_MSK BIT(6) 170 #define ADF4377_001A_PD_NDIV_MSK BIT(5) 171 #define ADF4377_001A_PD_VCO_MSK BIT(4) 172 #define ADF4377_001A_PD_LD_MSK BIT(3) 173 #define ADF4377_001A_PD_PFDCP_MSK BIT(2) 174 #define ADF4377_001A_PD_CLKOUT1_MSK BIT(1) 175 #define ADF4377_001A_PD_CLKOUT2_MSK BIT(0) 176 177 /* ADF4377 REG001B Map */ 178 #define ADF4377_001B_EN_LOL_MSK BIT(7) 179 #define ADF4377_001B_LDWIN_PW_MSK BIT(6) 180 #define ADF4377_001B_EN_LDWIN_MSK BIT(5) 181 #define ADF4377_001B_LD_COUNT_MSK GENMASK(4, 0) 182 183 /* ADF4377 REG001B Bit Definition */ 184 #define ADF4377_001B_LDWIN_PW_NARROW 0x0 185 #define ADF4377_001B_LDWIN_PW_WIDE 0x1 186 187 /* ADF4377 REG001C Map */ 188 #define ADF4377_001C_EN_DNCLK_MSK BIT(7) 189 #define ADF4377_001C_EN_DRCLK_MSK BIT(6) 190 #define ADF4377_001C_RST_LD_MSK BIT(2) 191 #define ADF4377_001C_R01C_RSV1_MSK BIT(0) 192 193 /* ADF4377 REG001C Bit Definition */ 194 #define ADF4377_001C_RST_LD_INACTIVE 0x0 195 #define ADF4377_001C_RST_LD_ACTIVE 0x1 196 197 #define ADF4377_001C_R01C_RSV1 0x1 198 199 /* ADF4377 REG001D Map */ 200 #define ADF4377_001D_MUXOUT_MSK GENMASK(7, 4) 201 #define ADF4377_001D_EN_CPTEST_MSK BIT(2) 202 #define ADF4377_001D_CP_DOWN_MSK BIT(1) 203 #define ADF4377_001D_CP_UP_MSK BIT(0) 204 205 #define ADF4377_001D_EN_CPTEST_OFF 0x0 206 #define ADF4377_001D_EN_CPTEST_ON 0x1 207 208 #define ADF4377_001D_CP_DOWN_OFF 0x0 209 #define ADF4377_001D_CP_DOWN_ON 0x1 210 211 #define ADF4377_001D_CP_UP_OFF 0x0 212 #define ADF4377_001D_CP_UP_ON 0x1 213 214 /* ADF4377 REG001F Map */ 215 #define ADF4377_001F_BST_REF_MSK BIT(7) 216 #define ADF4377_001F_FILT_REF_MSK BIT(6) 217 #define ADF4377_001F_REF_SEL_MSK BIT(5) 218 #define ADF4377_001F_R01F_RSV1_MSK GENMASK(4, 0) 219 220 /* ADF4377 REG001F Bit Definition */ 221 #define ADF4377_001F_BST_LARGE_REF_IN 0x0 222 #define ADF4377_001F_BST_SMALL_REF_IN 0x1 223 224 #define ADF4377_001F_FILT_REF_OFF 0x0 225 #define ADF4377_001F_FILT_REF_ON 0x1 226 227 #define ADF4377_001F_REF_SEL_DMA 0x0 228 #define ADF4377_001F_REF_SEL_LNA 0x1 229 230 #define ADF4377_001F_R01F_RSV1 0x7 231 232 /* ADF4377 REG0020 Map */ 233 #define ADF4377_0020_RST_SYS_MSK BIT(4) 234 #define ADF4377_0020_EN_ADC_CLK_MSK BIT(3) 235 #define ADF4377_0020_R020_RSV1_MSK BIT(0) 236 237 /* ADF4377 REG0021 Bit Definition */ 238 #define ADF4377_0021_R021_RSV1 0xD3 239 240 /* ADF4377 REG0022 Bit Definition */ 241 #define ADF4377_0022_R022_RSV1 0x32 242 243 /* ADF4377 REG0023 Map */ 244 #define ADF4377_0023_CAT_CT_SEL BIT(7) 245 #define ADF4377_0023_R023_RSV1_MSK GENMASK(6, 0) 246 247 /* ADF4377 REG0023 Bit Definition */ 248 #define ADF4377_0023_R023_RSV1 0x18 249 250 /* ADF4377 REG0024 Map */ 251 #define ADF4377_0024_DCLK_MODE_MSK BIT(2) 252 253 /* ADF4377 REG0025 Map */ 254 #define ADF4377_0025_CLKODIV_DB_MSK BIT(7) 255 #define ADF4377_0025_DCLK_DB_MSK BIT(6) 256 #define ADF4377_0025_R025_RSV1_MSK GENMASK(5, 0) 257 258 /* ADF4377 REG0025 Bit Definition */ 259 #define ADF4377_0025_R025_RSV1 0x16 260 261 /* ADF4377 REG0026 Map */ 262 #define ADF4377_0026_VCO_BAND_DIV_MSK GENMASK(7, 0) 263 264 /* ADF4377 REG0027 Map */ 265 #define ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK GENMASK(7, 0) 266 267 /* ADF4377 REG0028 Map */ 268 #define ADF4377_0028_O_VCO_DB_MSK BIT(7) 269 #define ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK GENMASK(6, 0) 270 271 /* ADF4377 REG0029 Map */ 272 #define ADF4377_0029_VCO_ALC_TO_LSB_MSK GENMASK(7, 0) 273 274 /* ADF4377 REG002A Map */ 275 #define ADF4377_002A_DEL_CTRL_DB_MSK BIT(7) 276 #define ADF4377_002A_VCO_ALC_TO_MSB_MSK GENMASK(6, 0) 277 278 /* ADF4377 REG002C Map */ 279 #define ADF4377_002C_R02C_RSV1 0xC0 280 281 /* ADF4377 REG002D Map */ 282 #define ADF4377_002D_ADC_CLK_DIV_MSK GENMASK(7, 0) 283 284 /* ADF4377 REG002E Map */ 285 #define ADF4377_002E_EN_ADC_CNV_MSK BIT(7) 286 #define ADF4377_002E_EN_ADC_MSK BIT(1) 287 #define ADF4377_002E_ADC_A_CONV_MSK BIT(0) 288 289 /* ADF4377 REG002E Bit Definition */ 290 #define ADF4377_002E_ADC_A_CONV_ADC_ST_CNV 0x0 291 #define ADF4377_002E_ADC_A_CONV_VCO_CALIB 0x1 292 293 /* ADF4377 REG002F Map */ 294 #define ADF4377_002F_DCLK_DIV1_MSK GENMASK(1, 0) 295 296 /* ADF4377 REG002F Bit Definition */ 297 #define ADF4377_002F_DCLK_DIV1_1 0x0 298 #define ADF4377_002F_DCLK_DIV1_2 0x1 299 #define ADF4377_002F_DCLK_DIV1_8 0x2 300 #define ADF4377_002F_DCLK_DIV1_32 0x3 301 302 /* ADF4377 REG0031 Bit Definition */ 303 #define ADF4377_0031_R031_RSV1 0x09 304 305 /* ADF4377 REG0032 Map */ 306 #define ADF4377_0032_ADC_CLK_SEL_MSK BIT(6) 307 #define ADF4377_0032_R032_RSV1_MSK GENMASK(5, 0) 308 309 /* ADF4377 REG0032 Bit Definition */ 310 #define ADF4377_0032_ADC_CLK_SEL_N_OP 0x0 311 #define ADF4377_0032_ADC_CLK_SEL_SPI_CLK 0x1 312 313 #define ADF4377_0032_R032_RSV1 0x9 314 315 /* ADF4377 REG0033 Bit Definition */ 316 #define ADF4377_0033_R033_RSV1 0x18 317 318 /* ADF4377 REG0034 Bit Definition */ 319 #define ADF4377_0034_R034_RSV1 0x08 320 321 /* ADF4377 REG003A Bit Definition */ 322 #define ADF4377_003A_R03A_RSV1 0x5D 323 324 /* ADF4377 REG003B Bit Definition */ 325 #define ADF4377_003B_R03B_RSV1 0x2B 326 327 /* ADF4377 REG003D Map */ 328 #define ADF4377_003D_O_VCO_BAND_MSK BIT(3) 329 #define ADF4377_003D_O_VCO_CORE_MSK BIT(2) 330 #define ADF4377_003D_O_VCO_BIAS_MSK BIT(1) 331 332 /* ADF4377 REG003D Bit Definition */ 333 #define ADF4377_003D_O_VCO_BAND_VCO_CALIB 0x0 334 #define ADF4377_003D_O_VCO_BAND_M_VCO 0x1 335 336 #define ADF4377_003D_O_VCO_CORE_VCO_CALIB 0x0 337 #define ADF4377_003D_O_VCO_CORE_M_VCO 0x1 338 339 #define ADF4377_003D_O_VCO_BIAS_VCO_CALIB 0x0 340 #define ADF4377_003D_O_VCO_BIAS_M_VCO 0x1 341 342 /* ADF4377 REG0042 Map */ 343 #define ADF4377_0042_R042_RSV1 0x05 344 345 /* ADF4377 REG0045 Map */ 346 #define ADF4377_0045_ADC_ST_CNV_MSK BIT(0) 347 348 /* ADF4377 REG0049 Map */ 349 #define ADF4377_0049_EN_CLK2_MSK BIT(7) 350 #define ADF4377_0049_EN_CLK1_MSK BIT(6) 351 #define ADF4377_0049_REF_OK_MSK BIT(3) 352 #define ADF4377_0049_ADC_BUSY_MSK BIT(2) 353 #define ADF4377_0049_FSM_BUSY_MSK BIT(1) 354 #define ADF4377_0049_LOCKED_MSK BIT(0) 355 356 /* ADF4377 REG004B Map */ 357 #define ADF4377_004B_VCO_CORE_MSK GENMASK(1, 0) 358 359 /* ADF4377 REG004C Map */ 360 #define ADF4377_004C_CHIP_TEMP_LSB_MSK GENMASK(7, 0) 361 362 /* ADF4377 REG004D Map */ 363 #define ADF4377_004D_CHIP_TEMP_MSB_MSK BIT(0) 364 365 /* ADF4377 REG004F Map */ 366 #define ADF4377_004F_VCO_BAND_MSK GENMASK(7, 0) 367 368 /* ADF4377 REG0051 Map */ 369 #define ADF4377_0051_VCO_BIAS_MSK GENMASK(3, 0) 370 371 /* ADF4377 REG0054 Map */ 372 #define ADF4377_0054_CHIP_VERSION_MSK GENMASK(7, 0) 373 374 /* Specifications */ 375 #define ADF4377_SPI_READ_CMD BIT(7) 376 #define ADF4377_MAX_VCO_FREQ (12800ULL * HZ_PER_MHZ) 377 #define ADF4377_MIN_VCO_FREQ (6400ULL * HZ_PER_MHZ) 378 #define ADF4377_MAX_REFIN_FREQ (1000 * HZ_PER_MHZ) 379 #define ADF4377_MIN_REFIN_FREQ (10 * HZ_PER_MHZ) 380 #define ADF4377_MAX_FREQ_PFD (500 * HZ_PER_MHZ) 381 #define ADF4377_MIN_FREQ_PFD (3 * HZ_PER_MHZ) 382 #define ADF4377_MAX_CLKPN_FREQ ADF4377_MAX_VCO_FREQ 383 #define ADF4377_MIN_CLKPN_FREQ (ADF4377_MIN_VCO_FREQ / 8) 384 #define ADF4377_FREQ_PFD_80MHZ (80 * HZ_PER_MHZ) 385 #define ADF4377_FREQ_PFD_125MHZ (125 * HZ_PER_MHZ) 386 #define ADF4377_FREQ_PFD_160MHZ (160 * HZ_PER_MHZ) 387 #define ADF4377_FREQ_PFD_250MHZ (250 * HZ_PER_MHZ) 388 #define ADF4377_FREQ_PFD_320MHZ (320 * HZ_PER_MHZ) 389 390 enum { 391 ADF4377_FREQ, 392 }; 393 394 enum muxout_select_mode { 395 ADF4377_MUXOUT_HIGH_Z = 0x0, 396 ADF4377_MUXOUT_LKDET = 0x1, 397 ADF4377_MUXOUT_LOW = 0x2, 398 ADF4377_MUXOUT_DIV_RCLK_2 = 0x4, 399 ADF4377_MUXOUT_DIV_NCLK_2 = 0x5, 400 ADF4377_MUXOUT_HIGH = 0x8, 401 }; 402 403 struct adf4377_chip_info { 404 const char *name; 405 bool has_gpio_enclk2; 406 }; 407 408 struct adf4377_state { 409 const struct adf4377_chip_info *chip_info; 410 struct spi_device *spi; 411 struct regmap *regmap; 412 struct clk *clkin; 413 /* Protect against concurrent accesses to the device and data content */ 414 struct mutex lock; 415 struct notifier_block nb; 416 /* Reference Divider */ 417 unsigned int ref_div_factor; 418 /* PFD Frequency */ 419 unsigned int f_pfd; 420 /* Input Reference Clock */ 421 unsigned int clkin_freq; 422 /* CLKOUT Divider */ 423 u8 clkout_div_sel; 424 /* Feedback Divider (N) */ 425 u16 n_int; 426 u16 synth_lock_timeout; 427 u16 vco_alc_timeout; 428 u16 adc_clk_div; 429 u16 vco_band_div; 430 u8 dclk_div1; 431 u8 dclk_div2; 432 u8 dclk_mode; 433 unsigned int f_div_rclk; 434 enum muxout_select_mode muxout_select; 435 struct gpio_desc *gpio_ce; 436 struct gpio_desc *gpio_enclk1; 437 struct gpio_desc *gpio_enclk2; 438 u8 buf[2] __aligned(IIO_DMA_MINALIGN); 439 }; 440 441 static const char * const adf4377_muxout_modes[] = { 442 [ADF4377_MUXOUT_HIGH_Z] = "high_z", 443 [ADF4377_MUXOUT_LKDET] = "lock_detect", 444 [ADF4377_MUXOUT_LOW] = "muxout_low", 445 [ADF4377_MUXOUT_DIV_RCLK_2] = "f_div_rclk_2", 446 [ADF4377_MUXOUT_DIV_NCLK_2] = "f_div_nclk_2", 447 [ADF4377_MUXOUT_HIGH] = "muxout_high", 448 }; 449 450 static const struct reg_sequence adf4377_reg_defaults[] = { 451 { 0x42, ADF4377_0042_R042_RSV1 }, 452 { 0x3B, ADF4377_003B_R03B_RSV1 }, 453 { 0x3A, ADF4377_003A_R03A_RSV1 }, 454 { 0x34, ADF4377_0034_R034_RSV1 }, 455 { 0x33, ADF4377_0033_R033_RSV1 }, 456 { 0x32, ADF4377_0032_R032_RSV1 }, 457 { 0x31, ADF4377_0031_R031_RSV1 }, 458 { 0x2C, ADF4377_002C_R02C_RSV1 }, 459 { 0x25, ADF4377_0025_R025_RSV1 }, 460 { 0x23, ADF4377_0023_R023_RSV1 }, 461 { 0x22, ADF4377_0022_R022_RSV1 }, 462 { 0x21, ADF4377_0021_R021_RSV1 }, 463 { 0x1f, ADF4377_001F_R01F_RSV1 }, 464 { 0x1c, ADF4377_001C_R01C_RSV1 }, 465 }; 466 467 static const struct regmap_config adf4377_regmap_config = { 468 .reg_bits = 16, 469 .val_bits = 8, 470 .read_flag_mask = BIT(7), 471 .max_register = 0x54, 472 }; 473 474 static int adf4377_reg_access(struct iio_dev *indio_dev, 475 unsigned int reg, 476 unsigned int write_val, 477 unsigned int *read_val) 478 { 479 struct adf4377_state *st = iio_priv(indio_dev); 480 481 if (read_val) 482 return regmap_read(st->regmap, reg, read_val); 483 484 return regmap_write(st->regmap, reg, write_val); 485 } 486 487 static const struct iio_info adf4377_info = { 488 .debugfs_reg_access = &adf4377_reg_access, 489 }; 490 491 static int adf4377_soft_reset(struct adf4377_state *st) 492 { 493 unsigned int read_val; 494 int ret; 495 496 ret = regmap_update_bits(st->regmap, 0x0, ADF4377_0000_SOFT_RESET_MSK | 497 ADF4377_0000_SOFT_RESET_R_MSK, 498 FIELD_PREP(ADF4377_0000_SOFT_RESET_MSK, 1) | 499 FIELD_PREP(ADF4377_0000_SOFT_RESET_R_MSK, 1)); 500 if (ret) 501 return ret; 502 503 return regmap_read_poll_timeout(st->regmap, 0x0, read_val, 504 !(read_val & (ADF4377_0000_SOFT_RESET_R_MSK | 505 ADF4377_0000_SOFT_RESET_R_MSK)), 200, 200 * 100); 506 } 507 508 static int adf4377_get_freq(struct adf4377_state *st, u64 *freq) 509 { 510 unsigned int ref_div_factor, n_int; 511 u64 clkin_freq; 512 int ret; 513 514 mutex_lock(&st->lock); 515 ret = regmap_read(st->regmap, 0x12, &ref_div_factor); 516 if (ret) 517 goto exit; 518 519 ret = regmap_bulk_read(st->regmap, 0x10, st->buf, sizeof(st->buf)); 520 if (ret) 521 goto exit; 522 523 clkin_freq = clk_get_rate(st->clkin); 524 ref_div_factor = FIELD_GET(ADF4377_0012_R_DIV_MSK, ref_div_factor); 525 n_int = FIELD_GET(ADF4377_0010_N_INT_LSB_MSK | ADF4377_0011_N_INT_MSB_MSK, 526 get_unaligned_le16(&st->buf)); 527 528 *freq = div_u64(clkin_freq, ref_div_factor) * n_int; 529 exit: 530 mutex_unlock(&st->lock); 531 532 return ret; 533 } 534 535 static int adf4377_set_freq(struct adf4377_state *st, u64 freq) 536 { 537 unsigned int read_val; 538 u64 f_vco; 539 int ret; 540 541 mutex_lock(&st->lock); 542 543 if (freq > ADF4377_MAX_CLKPN_FREQ || freq < ADF4377_MIN_CLKPN_FREQ) { 544 ret = -EINVAL; 545 goto exit; 546 } 547 548 ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK | 549 ADF4377_001C_EN_DRCLK_MSK, 550 FIELD_PREP(ADF4377_001C_EN_DNCLK_MSK, 1) | 551 FIELD_PREP(ADF4377_001C_EN_DRCLK_MSK, 1)); 552 if (ret) 553 goto exit; 554 555 ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_AUTOCAL_MSK | 556 ADF4377_0011_DCLK_DIV2_MSK, 557 FIELD_PREP(ADF4377_0011_EN_AUTOCAL_MSK, 1) | 558 FIELD_PREP(ADF4377_0011_DCLK_DIV2_MSK, st->dclk_div2)); 559 if (ret) 560 goto exit; 561 562 ret = regmap_update_bits(st->regmap, 0x2E, ADF4377_002E_EN_ADC_CNV_MSK | 563 ADF4377_002E_EN_ADC_MSK | 564 ADF4377_002E_ADC_A_CONV_MSK, 565 FIELD_PREP(ADF4377_002E_EN_ADC_CNV_MSK, 1) | 566 FIELD_PREP(ADF4377_002E_EN_ADC_MSK, 1) | 567 FIELD_PREP(ADF4377_002E_ADC_A_CONV_MSK, 568 ADF4377_002E_ADC_A_CONV_VCO_CALIB)); 569 if (ret) 570 goto exit; 571 572 ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK, 573 FIELD_PREP(ADF4377_0020_EN_ADC_CLK_MSK, 1)); 574 if (ret) 575 goto exit; 576 577 ret = regmap_update_bits(st->regmap, 0x2F, ADF4377_002F_DCLK_DIV1_MSK, 578 FIELD_PREP(ADF4377_002F_DCLK_DIV1_MSK, st->dclk_div1)); 579 if (ret) 580 goto exit; 581 582 ret = regmap_update_bits(st->regmap, 0x24, ADF4377_0024_DCLK_MODE_MSK, 583 FIELD_PREP(ADF4377_0024_DCLK_MODE_MSK, st->dclk_mode)); 584 if (ret) 585 goto exit; 586 587 ret = regmap_write(st->regmap, 0x27, 588 FIELD_PREP(ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK, 589 st->synth_lock_timeout)); 590 if (ret) 591 goto exit; 592 593 ret = regmap_update_bits(st->regmap, 0x28, ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK, 594 FIELD_PREP(ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK, 595 st->synth_lock_timeout >> 8)); 596 if (ret) 597 goto exit; 598 599 ret = regmap_write(st->regmap, 0x29, 600 FIELD_PREP(ADF4377_0029_VCO_ALC_TO_LSB_MSK, 601 st->vco_alc_timeout)); 602 if (ret) 603 goto exit; 604 605 ret = regmap_update_bits(st->regmap, 0x2A, ADF4377_002A_VCO_ALC_TO_MSB_MSK, 606 FIELD_PREP(ADF4377_002A_VCO_ALC_TO_MSB_MSK, 607 st->vco_alc_timeout >> 8)); 608 if (ret) 609 goto exit; 610 611 ret = regmap_write(st->regmap, 0x26, 612 FIELD_PREP(ADF4377_0026_VCO_BAND_DIV_MSK, st->vco_band_div)); 613 if (ret) 614 goto exit; 615 616 ret = regmap_write(st->regmap, 0x2D, 617 FIELD_PREP(ADF4377_002D_ADC_CLK_DIV_MSK, st->adc_clk_div)); 618 if (ret) 619 goto exit; 620 621 st->clkout_div_sel = 0; 622 623 f_vco = freq; 624 625 while (f_vco < ADF4377_MIN_VCO_FREQ) { 626 f_vco <<= 1; 627 st->clkout_div_sel++; 628 } 629 630 st->n_int = div_u64(freq, st->f_pfd); 631 632 ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_RDBLR_MSK | 633 ADF4377_0011_N_INT_MSB_MSK, 634 FIELD_PREP(ADF4377_0011_EN_RDBLR_MSK, 0) | 635 FIELD_PREP(ADF4377_0011_N_INT_MSB_MSK, st->n_int >> 8)); 636 if (ret) 637 goto exit; 638 639 ret = regmap_update_bits(st->regmap, 0x12, ADF4377_0012_R_DIV_MSK | 640 ADF4377_0012_CLKOUT_DIV_MSK, 641 FIELD_PREP(ADF4377_0012_CLKOUT_DIV_MSK, st->clkout_div_sel) | 642 FIELD_PREP(ADF4377_0012_R_DIV_MSK, st->ref_div_factor)); 643 if (ret) 644 goto exit; 645 646 ret = regmap_write(st->regmap, 0x10, 647 FIELD_PREP(ADF4377_0010_N_INT_LSB_MSK, st->n_int)); 648 if (ret) 649 goto exit; 650 651 ret = regmap_read_poll_timeout(st->regmap, 0x49, read_val, 652 !(read_val & (ADF4377_0049_FSM_BUSY_MSK)), 200, 200 * 100); 653 if (ret) 654 goto exit; 655 656 /* Disable EN_DNCLK, EN_DRCLK */ 657 ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK | 658 ADF4377_001C_EN_DRCLK_MSK, 659 FIELD_PREP(ADF4377_001C_EN_DNCLK_MSK, 0) | 660 FIELD_PREP(ADF4377_001C_EN_DRCLK_MSK, 0)); 661 if (ret) 662 goto exit; 663 664 /* Disable EN_ADC_CLK */ 665 ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK, 666 FIELD_PREP(ADF4377_0020_EN_ADC_CLK_MSK, 0)); 667 if (ret) 668 goto exit; 669 670 /* Set output Amplitude */ 671 ret = regmap_update_bits(st->regmap, 0x19, ADF4377_0019_CLKOUT2_OP_MSK | 672 ADF4377_0019_CLKOUT1_OP_MSK, 673 FIELD_PREP(ADF4377_0019_CLKOUT1_OP_MSK, 674 ADF4377_0019_CLKOUT_420MV) | 675 FIELD_PREP(ADF4377_0019_CLKOUT2_OP_MSK, 676 ADF4377_0019_CLKOUT_420MV)); 677 678 exit: 679 mutex_unlock(&st->lock); 680 681 return ret; 682 } 683 684 static void adf4377_gpio_init(struct adf4377_state *st) 685 { 686 if (st->gpio_ce) { 687 gpiod_set_value(st->gpio_ce, 1); 688 689 /* Delay for SPI register bits to settle to their power-on reset state */ 690 fsleep(200); 691 } 692 693 if (st->gpio_enclk1) 694 gpiod_set_value(st->gpio_enclk1, 1); 695 696 if (st->gpio_enclk2) 697 gpiod_set_value(st->gpio_enclk2, 1); 698 } 699 700 static int adf4377_init(struct adf4377_state *st) 701 { 702 struct spi_device *spi = st->spi; 703 int ret; 704 705 adf4377_gpio_init(st); 706 707 ret = adf4377_soft_reset(st); 708 if (ret) { 709 dev_err(&spi->dev, "Failed to soft reset.\n"); 710 return ret; 711 } 712 713 ret = regmap_multi_reg_write(st->regmap, adf4377_reg_defaults, 714 ARRAY_SIZE(adf4377_reg_defaults)); 715 if (ret) { 716 dev_err(&spi->dev, "Failed to set default registers.\n"); 717 return ret; 718 } 719 720 ret = regmap_update_bits(st->regmap, 0x00, 721 ADF4377_0000_SDO_ACTIVE_MSK | ADF4377_0000_SDO_ACTIVE_R_MSK, 722 FIELD_PREP(ADF4377_0000_SDO_ACTIVE_MSK, 723 ADF4377_0000_SDO_ACTIVE_SPI_4W) | 724 FIELD_PREP(ADF4377_0000_SDO_ACTIVE_R_MSK, 725 ADF4377_0000_SDO_ACTIVE_SPI_4W)); 726 if (ret) { 727 dev_err(&spi->dev, "Failed to set 4-Wire Operation.\n"); 728 return ret; 729 } 730 731 st->clkin_freq = clk_get_rate(st->clkin); 732 733 /* Power Up */ 734 ret = regmap_write(st->regmap, 0x1a, 735 FIELD_PREP(ADF4377_001A_PD_ALL_MSK, 0) | 736 FIELD_PREP(ADF4377_001A_PD_RDIV_MSK, 0) | 737 FIELD_PREP(ADF4377_001A_PD_NDIV_MSK, 0) | 738 FIELD_PREP(ADF4377_001A_PD_VCO_MSK, 0) | 739 FIELD_PREP(ADF4377_001A_PD_LD_MSK, 0) | 740 FIELD_PREP(ADF4377_001A_PD_PFDCP_MSK, 0) | 741 FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) | 742 FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0)); 743 if (ret) { 744 dev_err(&spi->dev, "Failed to set power down registers.\n"); 745 return ret; 746 } 747 748 /* Set Mux Output */ 749 ret = regmap_update_bits(st->regmap, 0x1D, 750 ADF4377_001D_MUXOUT_MSK, 751 FIELD_PREP(ADF4377_001D_MUXOUT_MSK, st->muxout_select)); 752 if (ret) 753 return ret; 754 755 /* Compute PFD */ 756 st->ref_div_factor = 0; 757 do { 758 st->ref_div_factor++; 759 st->f_pfd = st->clkin_freq / st->ref_div_factor; 760 } while (st->f_pfd > ADF4377_MAX_FREQ_PFD); 761 762 if (st->f_pfd > ADF4377_MAX_FREQ_PFD || st->f_pfd < ADF4377_MIN_FREQ_PFD) 763 return -EINVAL; 764 765 st->f_div_rclk = st->f_pfd; 766 767 if (st->f_pfd <= ADF4377_FREQ_PFD_80MHZ) { 768 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1; 769 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; 770 st->dclk_mode = 0; 771 } else if (st->f_pfd <= ADF4377_FREQ_PFD_125MHZ) { 772 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1; 773 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; 774 st->dclk_mode = 1; 775 } else if (st->f_pfd <= ADF4377_FREQ_PFD_160MHZ) { 776 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; 777 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; 778 st->dclk_mode = 0; 779 st->f_div_rclk /= 2; 780 } else if (st->f_pfd <= ADF4377_FREQ_PFD_250MHZ) { 781 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; 782 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; 783 st->dclk_mode = 1; 784 st->f_div_rclk /= 2; 785 } else if (st->f_pfd <= ADF4377_FREQ_PFD_320MHZ) { 786 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; 787 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2; 788 st->dclk_mode = 0; 789 st->f_div_rclk /= 4; 790 } else { 791 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; 792 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2; 793 st->dclk_mode = 1; 794 st->f_div_rclk /= 4; 795 } 796 797 st->synth_lock_timeout = DIV_ROUND_UP(st->f_div_rclk, 50000); 798 st->vco_alc_timeout = DIV_ROUND_UP(st->f_div_rclk, 20000); 799 st->vco_band_div = DIV_ROUND_UP(st->f_div_rclk, 150000 * 16 * (1 << st->dclk_mode)); 800 st->adc_clk_div = DIV_ROUND_UP((st->f_div_rclk / 400000 - 2), 4); 801 802 return 0; 803 } 804 805 static ssize_t adf4377_read(struct iio_dev *indio_dev, uintptr_t private, 806 const struct iio_chan_spec *chan, char *buf) 807 { 808 struct adf4377_state *st = iio_priv(indio_dev); 809 u64 val = 0; 810 int ret; 811 812 switch ((u32)private) { 813 case ADF4377_FREQ: 814 ret = adf4377_get_freq(st, &val); 815 if (ret) 816 return ret; 817 818 return sysfs_emit(buf, "%llu\n", val); 819 default: 820 return -EINVAL; 821 } 822 } 823 824 static ssize_t adf4377_write(struct iio_dev *indio_dev, uintptr_t private, 825 const struct iio_chan_spec *chan, const char *buf, 826 size_t len) 827 { 828 struct adf4377_state *st = iio_priv(indio_dev); 829 unsigned long long freq; 830 int ret; 831 832 switch ((u32)private) { 833 case ADF4377_FREQ: 834 ret = kstrtoull(buf, 10, &freq); 835 if (ret) 836 return ret; 837 838 ret = adf4377_set_freq(st, freq); 839 if (ret) 840 return ret; 841 842 return len; 843 default: 844 return -EINVAL; 845 } 846 } 847 848 #define _ADF4377_EXT_INFO(_name, _shared, _ident) { \ 849 .name = _name, \ 850 .read = adf4377_read, \ 851 .write = adf4377_write, \ 852 .private = _ident, \ 853 .shared = _shared, \ 854 } 855 856 static const struct iio_chan_spec_ext_info adf4377_ext_info[] = { 857 /* 858 * Usually we use IIO_CHAN_INFO_FREQUENCY, but there are 859 * values > 2^32 in order to support the entire frequency range 860 * in Hz. 861 */ 862 _ADF4377_EXT_INFO("frequency", IIO_SEPARATE, ADF4377_FREQ), 863 { } 864 }; 865 866 static const struct iio_chan_spec adf4377_channels[] = { 867 { 868 .type = IIO_ALTVOLTAGE, 869 .indexed = 1, 870 .output = 1, 871 .channel = 0, 872 .ext_info = adf4377_ext_info, 873 }, 874 }; 875 876 static int adf4377_properties_parse(struct adf4377_state *st) 877 { 878 struct spi_device *spi = st->spi; 879 int ret; 880 881 st->clkin = devm_clk_get_enabled(&spi->dev, "ref_in"); 882 if (IS_ERR(st->clkin)) 883 return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), 884 "failed to get the reference input clock\n"); 885 886 st->gpio_ce = devm_gpiod_get_optional(&st->spi->dev, "chip-enable", 887 GPIOD_OUT_LOW); 888 if (IS_ERR(st->gpio_ce)) 889 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_ce), 890 "failed to get the CE GPIO\n"); 891 892 st->gpio_enclk1 = devm_gpiod_get_optional(&st->spi->dev, "clk1-enable", 893 GPIOD_OUT_LOW); 894 if (IS_ERR(st->gpio_enclk1)) 895 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_enclk1), 896 "failed to get the CE GPIO\n"); 897 898 if (st->chip_info->has_gpio_enclk2) { 899 st->gpio_enclk2 = devm_gpiod_get_optional(&st->spi->dev, "clk2-enable", 900 GPIOD_OUT_LOW); 901 if (IS_ERR(st->gpio_enclk2)) 902 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_enclk2), 903 "failed to get the CE GPIO\n"); 904 } 905 906 ret = device_property_match_property_string(&spi->dev, "adi,muxout-select", 907 adf4377_muxout_modes, 908 ARRAY_SIZE(adf4377_muxout_modes)); 909 if (ret >= 0) 910 st->muxout_select = ret; 911 else 912 st->muxout_select = ADF4377_MUXOUT_HIGH_Z; 913 914 return 0; 915 } 916 917 static int adf4377_freq_change(struct notifier_block *nb, unsigned long action, void *data) 918 { 919 struct adf4377_state *st = container_of(nb, struct adf4377_state, nb); 920 int ret; 921 922 if (action == POST_RATE_CHANGE) { 923 mutex_lock(&st->lock); 924 ret = notifier_from_errno(adf4377_init(st)); 925 mutex_unlock(&st->lock); 926 return ret; 927 } 928 929 return NOTIFY_OK; 930 } 931 932 static const struct adf4377_chip_info adf4377_chip_info = { 933 .name = "adf4377", 934 .has_gpio_enclk2 = true, 935 }; 936 937 static const struct adf4377_chip_info adf4378_chip_info = { 938 .name = "adf4378", 939 .has_gpio_enclk2 = false, 940 }; 941 942 static int adf4377_probe(struct spi_device *spi) 943 { 944 struct iio_dev *indio_dev; 945 struct regmap *regmap; 946 struct adf4377_state *st; 947 int ret; 948 949 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 950 if (!indio_dev) 951 return -ENOMEM; 952 953 regmap = devm_regmap_init_spi(spi, &adf4377_regmap_config); 954 if (IS_ERR(regmap)) 955 return PTR_ERR(regmap); 956 957 st = iio_priv(indio_dev); 958 959 indio_dev->info = &adf4377_info; 960 indio_dev->name = "adf4377"; 961 indio_dev->channels = adf4377_channels; 962 indio_dev->num_channels = ARRAY_SIZE(adf4377_channels); 963 964 st->regmap = regmap; 965 st->spi = spi; 966 st->chip_info = spi_get_device_match_data(spi); 967 mutex_init(&st->lock); 968 969 ret = adf4377_properties_parse(st); 970 if (ret) 971 return ret; 972 973 st->nb.notifier_call = adf4377_freq_change; 974 ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb); 975 if (ret) 976 return ret; 977 978 ret = adf4377_init(st); 979 if (ret) 980 return ret; 981 982 return devm_iio_device_register(&spi->dev, indio_dev); 983 } 984 985 static const struct spi_device_id adf4377_id[] = { 986 { "adf4377", (kernel_ulong_t)&adf4377_chip_info }, 987 { "adf4378", (kernel_ulong_t)&adf4378_chip_info }, 988 {} 989 }; 990 MODULE_DEVICE_TABLE(spi, adf4377_id); 991 992 static const struct of_device_id adf4377_of_match[] = { 993 { .compatible = "adi,adf4377", .data = &adf4377_chip_info }, 994 { .compatible = "adi,adf4378", .data = &adf4378_chip_info }, 995 {} 996 }; 997 MODULE_DEVICE_TABLE(of, adf4377_of_match); 998 999 static struct spi_driver adf4377_driver = { 1000 .driver = { 1001 .name = "adf4377", 1002 .of_match_table = adf4377_of_match, 1003 }, 1004 .probe = adf4377_probe, 1005 .id_table = adf4377_id, 1006 }; 1007 module_spi_driver(adf4377_driver); 1008 1009 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>"); 1010 MODULE_DESCRIPTION("Analog Devices ADF4377"); 1011 MODULE_LICENSE("GPL"); 1012