1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADF4377 driver 4 * 5 * Copyright 2022 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/clkdev.h> 14 #include <linux/container_of.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/module.h> 19 #include <linux/notifier.h> 20 #include <linux/property.h> 21 #include <linux/spi/spi.h> 22 #include <linux/iio/iio.h> 23 #include <linux/regmap.h> 24 #include <linux/units.h> 25 26 #include <linux/unaligned.h> 27 28 /* ADF4377 REG0000 Map */ 29 #define ADF4377_0000_SOFT_RESET_R_MSK BIT(7) 30 #define ADF4377_0000_LSB_FIRST_R_MSK BIT(6) 31 #define ADF4377_0000_ADDRESS_ASC_R_MSK BIT(5) 32 #define ADF4377_0000_SDO_ACTIVE_R_MSK BIT(4) 33 #define ADF4377_0000_SDO_ACTIVE_MSK BIT(3) 34 #define ADF4377_0000_ADDRESS_ASC_MSK BIT(2) 35 #define ADF4377_0000_LSB_FIRST_MSK BIT(1) 36 #define ADF4377_0000_SOFT_RESET_MSK BIT(0) 37 38 /* ADF4377 REG0000 Bit Definition */ 39 #define ADF4377_0000_SDO_ACTIVE_SPI_3W 0x0 40 #define ADF4377_0000_SDO_ACTIVE_SPI_4W 0x1 41 42 #define ADF4377_0000_ADDR_ASC_AUTO_DECR 0x0 43 #define ADF4377_0000_ADDR_ASC_AUTO_INCR 0x1 44 45 #define ADF4377_0000_LSB_FIRST_MSB 0x0 46 #define ADF4377_0000_LSB_FIRST_LSB 0x1 47 48 #define ADF4377_0000_SOFT_RESET_N_OP 0x0 49 #define ADF4377_0000_SOFT_RESET_EN 0x1 50 51 /* ADF4377 REG0001 Map */ 52 #define ADF4377_0001_SINGLE_INSTR_MSK BIT(7) 53 #define ADF4377_0001_MASTER_RB_CTRL_MSK BIT(5) 54 55 /* ADF4377 REG0003 Bit Definition */ 56 #define ADF4377_0003_CHIP_TYPE 0x06 57 58 /* ADF4377 REG0004 Bit Definition */ 59 #define ADF4377_0004_PRODUCT_ID_LSB 0x0005 60 61 /* ADF4377 REG0005 Bit Definition */ 62 #define ADF4377_0005_PRODUCT_ID_MSB 0x0005 63 64 /* ADF4377 REG000A Map */ 65 #define ADF4377_000A_SCRATCHPAD_MSK GENMASK(7, 0) 66 67 /* ADF4377 REG000C Bit Definition */ 68 #define ADF4377_000C_VENDOR_ID_LSB 0x56 69 70 /* ADF4377 REG000D Bit Definition */ 71 #define ADF4377_000D_VENDOR_ID_MSB 0x04 72 73 /* ADF4377 REG000F Bit Definition */ 74 #define ADF4377_000F_R00F_RSV1_MSK GENMASK(7, 0) 75 76 /* ADF4377 REG0010 Map*/ 77 #define ADF4377_0010_N_INT_LSB_MSK GENMASK(7, 0) 78 79 /* ADF4377 REG0011 Map*/ 80 #define ADF4377_0011_EN_AUTOCAL_MSK BIT(7) 81 #define ADF4377_0011_EN_RDBLR_MSK BIT(6) 82 #define ADF4377_0011_DCLK_DIV2_MSK GENMASK(5, 4) 83 #define ADF4377_0011_N_INT_MSB_MSK GENMASK(3, 0) 84 85 /* ADF4377 REG0011 Bit Definition */ 86 #define ADF4377_0011_DCLK_DIV2_1 0x0 87 #define ADF4377_0011_DCLK_DIV2_2 0x1 88 #define ADF4377_0011_DCLK_DIV2_4 0x2 89 #define ADF4377_0011_DCLK_DIV2_8 0x3 90 91 /* ADF4377 REG0012 Map*/ 92 #define ADF4377_0012_CLKOUT_DIV_MSK GENMASK(7, 6) 93 #define ADF4377_0012_R_DIV_MSK GENMASK(5, 0) 94 95 /* ADF4377 REG0012 Bit Definition */ 96 #define ADF4377_0012_CLKOUT_DIV_1 0x0 97 #define ADF4377_0012_CLKOUT_DIV_2 0x1 98 #define ADF4377_0012_CLKOUT_DIV_4 0x2 99 #define ADF4377_0012_CLKOUT_DIV_8 0x3 100 101 /* ADF4377 REG0013 Map */ 102 #define ADF4377_0013_M_VCO_CORE_MSK GENMASK(5, 4) 103 #define ADF4377_0013_VCO_BIAS_MSK GENMASK(3, 0) 104 105 /* ADF4377 REG0013 Bit Definition */ 106 #define ADF4377_0013_M_VCO_0 0x0 107 #define ADF4377_0013_M_VCO_1 0x1 108 #define ADF4377_0013_M_VCO_2 0x2 109 #define ADF4377_0013_M_VCO_3 0x3 110 111 /* ADF4377 REG0014 Map */ 112 #define ADF4377_0014_M_VCO_BAND_MSK GENMASK(7, 0) 113 114 /* ADF4377 REG0015 Map */ 115 #define ADF4377_0015_BLEED_I_LSB_MSK GENMASK(7, 6) 116 #define ADF4377_0015_BLEED_POL_MSK BIT(5) 117 #define ADF4377_0015_EN_BLEED_MSK BIT(4) 118 #define ADF4377_0015_CP_I_MSK GENMASK(3, 0) 119 120 /* ADF4377 REG0015 Bit Definition */ 121 #define ADF4377_CURRENT_SINK 0x0 122 #define ADF4377_CURRENT_SOURCE 0x1 123 124 #define ADF4377_0015_CP_0MA7 0x0 125 #define ADF4377_0015_CP_0MA9 0x1 126 #define ADF4377_0015_CP_1MA1 0x2 127 #define ADF4377_0015_CP_1MA3 0x3 128 #define ADF4377_0015_CP_1MA4 0x4 129 #define ADF4377_0015_CP_1MA8 0x5 130 #define ADF4377_0015_CP_2MA2 0x6 131 #define ADF4377_0015_CP_2MA5 0x7 132 #define ADF4377_0015_CP_2MA9 0x8 133 #define ADF4377_0015_CP_3MA6 0x9 134 #define ADF4377_0015_CP_4MA3 0xA 135 #define ADF4377_0015_CP_5MA0 0xB 136 #define ADF4377_0015_CP_5MA7 0xC 137 #define ADF4377_0015_CP_7MA2 0xD 138 #define ADF4377_0015_CP_8MA6 0xE 139 #define ADF4377_0015_CP_10MA1 0xF 140 141 /* ADF4377 REG0016 Map */ 142 #define ADF4377_0016_BLEED_I_MSB_MSK GENMASK(7, 0) 143 144 /* ADF4377 REG0017 Map */ 145 #define ADF4377_0016_INV_CLKOUT_MSK BIT(7) 146 #define ADF4377_0016_N_DEL_MSK GENMASK(6, 0) 147 148 /* ADF4377 REG0018 Map */ 149 #define ADF4377_0018_CMOS_OV_MSK BIT(7) 150 #define ADF4377_0018_R_DEL_MSK GENMASK(6, 0) 151 152 /* ADF4377 REG0018 Bit Definition */ 153 #define ADF4377_0018_1V8_LOGIC 0x0 154 #define ADF4377_0018_3V3_LOGIC 0x1 155 156 /* ADF4377 REG0019 Map */ 157 #define ADF4377_0019_CLKOUT2_OP_MSK GENMASK(7, 6) 158 #define ADF4377_0019_CLKOUT1_OP_MSK GENMASK(5, 4) 159 #define ADF4377_0019_PD_CLK_MSK BIT(3) 160 #define ADF4377_0019_PD_RDET_MSK BIT(2) 161 #define ADF4377_0019_PD_ADC_MSK BIT(1) 162 #define ADF4377_0019_PD_CALADC_MSK BIT(0) 163 164 /* ADF4377 REG0019 Bit Definition */ 165 #define ADF4377_0019_CLKOUT_320MV 0x0 166 #define ADF4377_0019_CLKOUT_420MV 0x1 167 #define ADF4377_0019_CLKOUT_530MV 0x2 168 #define ADF4377_0019_CLKOUT_640MV 0x3 169 170 /* ADF4377 REG001A Map */ 171 #define ADF4377_001A_PD_ALL_MSK BIT(7) 172 #define ADF4377_001A_PD_RDIV_MSK BIT(6) 173 #define ADF4377_001A_PD_NDIV_MSK BIT(5) 174 #define ADF4377_001A_PD_VCO_MSK BIT(4) 175 #define ADF4377_001A_PD_LD_MSK BIT(3) 176 #define ADF4377_001A_PD_PFDCP_MSK BIT(2) 177 #define ADF4377_001A_PD_CLKOUT1_MSK BIT(1) 178 #define ADF4377_001A_PD_CLKOUT2_MSK BIT(0) 179 180 /* ADF4377 REG001B Map */ 181 #define ADF4377_001B_EN_LOL_MSK BIT(7) 182 #define ADF4377_001B_LDWIN_PW_MSK BIT(6) 183 #define ADF4377_001B_EN_LDWIN_MSK BIT(5) 184 #define ADF4377_001B_LD_COUNT_MSK GENMASK(4, 0) 185 186 /* ADF4377 REG001B Bit Definition */ 187 #define ADF4377_001B_LDWIN_PW_NARROW 0x0 188 #define ADF4377_001B_LDWIN_PW_WIDE 0x1 189 190 /* ADF4377 REG001C Map */ 191 #define ADF4377_001C_EN_DNCLK_MSK BIT(7) 192 #define ADF4377_001C_EN_DRCLK_MSK BIT(6) 193 #define ADF4377_001C_RST_LD_MSK BIT(2) 194 #define ADF4377_001C_R01C_RSV1_MSK BIT(0) 195 196 /* ADF4377 REG001C Bit Definition */ 197 #define ADF4377_001C_RST_LD_INACTIVE 0x0 198 #define ADF4377_001C_RST_LD_ACTIVE 0x1 199 200 #define ADF4377_001C_R01C_RSV1 0x1 201 202 /* ADF4377 REG001D Map */ 203 #define ADF4377_001D_MUXOUT_MSK GENMASK(7, 4) 204 #define ADF4377_001D_EN_CPTEST_MSK BIT(2) 205 #define ADF4377_001D_CP_DOWN_MSK BIT(1) 206 #define ADF4377_001D_CP_UP_MSK BIT(0) 207 208 #define ADF4377_001D_EN_CPTEST_OFF 0x0 209 #define ADF4377_001D_EN_CPTEST_ON 0x1 210 211 #define ADF4377_001D_CP_DOWN_OFF 0x0 212 #define ADF4377_001D_CP_DOWN_ON 0x1 213 214 #define ADF4377_001D_CP_UP_OFF 0x0 215 #define ADF4377_001D_CP_UP_ON 0x1 216 217 /* ADF4377 REG001F Map */ 218 #define ADF4377_001F_BST_REF_MSK BIT(7) 219 #define ADF4377_001F_FILT_REF_MSK BIT(6) 220 #define ADF4377_001F_REF_SEL_MSK BIT(5) 221 #define ADF4377_001F_R01F_RSV1_MSK GENMASK(4, 0) 222 223 /* ADF4377 REG001F Bit Definition */ 224 #define ADF4377_001F_BST_LARGE_REF_IN 0x0 225 #define ADF4377_001F_BST_SMALL_REF_IN 0x1 226 227 #define ADF4377_001F_FILT_REF_OFF 0x0 228 #define ADF4377_001F_FILT_REF_ON 0x1 229 230 #define ADF4377_001F_REF_SEL_DMA 0x0 231 #define ADF4377_001F_REF_SEL_LNA 0x1 232 233 #define ADF4377_001F_R01F_RSV1 0x7 234 235 /* ADF4377 REG0020 Map */ 236 #define ADF4377_0020_RST_SYS_MSK BIT(4) 237 #define ADF4377_0020_EN_ADC_CLK_MSK BIT(3) 238 #define ADF4377_0020_R020_RSV1_MSK BIT(0) 239 240 /* ADF4377 REG0021 Bit Definition */ 241 #define ADF4377_0021_R021_RSV1 0xD3 242 243 /* ADF4377 REG0022 Bit Definition */ 244 #define ADF4377_0022_R022_RSV1 0x32 245 246 /* ADF4377 REG0023 Map */ 247 #define ADF4377_0023_CAT_CT_SEL BIT(7) 248 #define ADF4377_0023_R023_RSV1_MSK GENMASK(6, 0) 249 250 /* ADF4377 REG0023 Bit Definition */ 251 #define ADF4377_0023_R023_RSV1 0x18 252 253 /* ADF4377 REG0024 Map */ 254 #define ADF4377_0024_DCLK_MODE_MSK BIT(2) 255 256 /* ADF4377 REG0025 Map */ 257 #define ADF4377_0025_CLKODIV_DB_MSK BIT(7) 258 #define ADF4377_0025_DCLK_DB_MSK BIT(6) 259 #define ADF4377_0025_R025_RSV1_MSK GENMASK(5, 0) 260 261 /* ADF4377 REG0025 Bit Definition */ 262 #define ADF4377_0025_R025_RSV1 0x16 263 264 /* ADF4377 REG0026 Map */ 265 #define ADF4377_0026_VCO_BAND_DIV_MSK GENMASK(7, 0) 266 267 /* ADF4377 REG0027 Map */ 268 #define ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK GENMASK(7, 0) 269 270 /* ADF4377 REG0028 Map */ 271 #define ADF4377_0028_O_VCO_DB_MSK BIT(7) 272 #define ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK GENMASK(6, 0) 273 274 /* ADF4377 REG0029 Map */ 275 #define ADF4377_0029_VCO_ALC_TO_LSB_MSK GENMASK(7, 0) 276 277 /* ADF4377 REG002A Map */ 278 #define ADF4377_002A_DEL_CTRL_DB_MSK BIT(7) 279 #define ADF4377_002A_VCO_ALC_TO_MSB_MSK GENMASK(6, 0) 280 281 /* ADF4377 REG002C Map */ 282 #define ADF4377_002C_R02C_RSV1 0xC0 283 284 /* ADF4377 REG002D Map */ 285 #define ADF4377_002D_ADC_CLK_DIV_MSK GENMASK(7, 0) 286 287 /* ADF4377 REG002E Map */ 288 #define ADF4377_002E_EN_ADC_CNV_MSK BIT(7) 289 #define ADF4377_002E_EN_ADC_MSK BIT(1) 290 #define ADF4377_002E_ADC_A_CONV_MSK BIT(0) 291 292 /* ADF4377 REG002E Bit Definition */ 293 #define ADF4377_002E_ADC_A_CONV_ADC_ST_CNV 0x0 294 #define ADF4377_002E_ADC_A_CONV_VCO_CALIB 0x1 295 296 /* ADF4377 REG002F Map */ 297 #define ADF4377_002F_DCLK_DIV1_MSK GENMASK(1, 0) 298 299 /* ADF4377 REG002F Bit Definition */ 300 #define ADF4377_002F_DCLK_DIV1_1 0x0 301 #define ADF4377_002F_DCLK_DIV1_2 0x1 302 #define ADF4377_002F_DCLK_DIV1_8 0x2 303 #define ADF4377_002F_DCLK_DIV1_32 0x3 304 305 /* ADF4377 REG0031 Bit Definition */ 306 #define ADF4377_0031_R031_RSV1 0x09 307 308 /* ADF4377 REG0032 Map */ 309 #define ADF4377_0032_ADC_CLK_SEL_MSK BIT(6) 310 #define ADF4377_0032_R032_RSV1_MSK GENMASK(5, 0) 311 312 /* ADF4377 REG0032 Bit Definition */ 313 #define ADF4377_0032_ADC_CLK_SEL_N_OP 0x0 314 #define ADF4377_0032_ADC_CLK_SEL_SPI_CLK 0x1 315 316 #define ADF4377_0032_R032_RSV1 0x9 317 318 /* ADF4377 REG0033 Bit Definition */ 319 #define ADF4377_0033_R033_RSV1 0x18 320 321 /* ADF4377 REG0034 Bit Definition */ 322 #define ADF4377_0034_R034_RSV1 0x08 323 324 /* ADF4377 REG003A Bit Definition */ 325 #define ADF4377_003A_R03A_RSV1 0x5D 326 327 /* ADF4377 REG003B Bit Definition */ 328 #define ADF4377_003B_R03B_RSV1 0x2B 329 330 /* ADF4377 REG003D Map */ 331 #define ADF4377_003D_O_VCO_BAND_MSK BIT(3) 332 #define ADF4377_003D_O_VCO_CORE_MSK BIT(2) 333 #define ADF4377_003D_O_VCO_BIAS_MSK BIT(1) 334 335 /* ADF4377 REG003D Bit Definition */ 336 #define ADF4377_003D_O_VCO_BAND_VCO_CALIB 0x0 337 #define ADF4377_003D_O_VCO_BAND_M_VCO 0x1 338 339 #define ADF4377_003D_O_VCO_CORE_VCO_CALIB 0x0 340 #define ADF4377_003D_O_VCO_CORE_M_VCO 0x1 341 342 #define ADF4377_003D_O_VCO_BIAS_VCO_CALIB 0x0 343 #define ADF4377_003D_O_VCO_BIAS_M_VCO 0x1 344 345 /* ADF4377 REG0042 Map */ 346 #define ADF4377_0042_R042_RSV1 0x05 347 348 /* ADF4377 REG0045 Map */ 349 #define ADF4377_0045_ADC_ST_CNV_MSK BIT(0) 350 351 /* ADF4377 REG0049 Map */ 352 #define ADF4377_0049_EN_CLK2_MSK BIT(7) 353 #define ADF4377_0049_EN_CLK1_MSK BIT(6) 354 #define ADF4377_0049_REF_OK_MSK BIT(3) 355 #define ADF4377_0049_ADC_BUSY_MSK BIT(2) 356 #define ADF4377_0049_FSM_BUSY_MSK BIT(1) 357 #define ADF4377_0049_LOCKED_MSK BIT(0) 358 359 /* ADF4377 REG004B Map */ 360 #define ADF4377_004B_VCO_CORE_MSK GENMASK(1, 0) 361 362 /* ADF4377 REG004C Map */ 363 #define ADF4377_004C_CHIP_TEMP_LSB_MSK GENMASK(7, 0) 364 365 /* ADF4377 REG004D Map */ 366 #define ADF4377_004D_CHIP_TEMP_MSB_MSK BIT(0) 367 368 /* ADF4377 REG004F Map */ 369 #define ADF4377_004F_VCO_BAND_MSK GENMASK(7, 0) 370 371 /* ADF4377 REG0051 Map */ 372 #define ADF4377_0051_VCO_BIAS_MSK GENMASK(3, 0) 373 374 /* ADF4377 REG0054 Map */ 375 #define ADF4377_0054_CHIP_VERSION_MSK GENMASK(7, 0) 376 377 /* Specifications */ 378 #define ADF4377_SPI_READ_CMD BIT(7) 379 #define ADF4377_MAX_VCO_FREQ (12800ULL * HZ_PER_MHZ) 380 #define ADF4377_MIN_VCO_FREQ (6400ULL * HZ_PER_MHZ) 381 #define ADF4377_MAX_REFIN_FREQ (1000 * HZ_PER_MHZ) 382 #define ADF4377_MIN_REFIN_FREQ (10 * HZ_PER_MHZ) 383 #define ADF4377_MAX_FREQ_PFD (500 * HZ_PER_MHZ) 384 #define ADF4377_MIN_FREQ_PFD (3 * HZ_PER_MHZ) 385 #define ADF4377_MAX_CLKPN_FREQ ADF4377_MAX_VCO_FREQ 386 #define ADF4377_MIN_CLKPN_FREQ (ADF4377_MIN_VCO_FREQ / 8) 387 #define ADF4377_FREQ_PFD_80MHZ (80 * HZ_PER_MHZ) 388 #define ADF4377_FREQ_PFD_125MHZ (125 * HZ_PER_MHZ) 389 #define ADF4377_FREQ_PFD_160MHZ (160 * HZ_PER_MHZ) 390 #define ADF4377_FREQ_PFD_250MHZ (250 * HZ_PER_MHZ) 391 #define ADF4377_FREQ_PFD_320MHZ (320 * HZ_PER_MHZ) 392 393 enum { 394 ADF4377_FREQ, 395 }; 396 397 enum muxout_select_mode { 398 ADF4377_MUXOUT_HIGH_Z = 0x0, 399 ADF4377_MUXOUT_LKDET = 0x1, 400 ADF4377_MUXOUT_LOW = 0x2, 401 ADF4377_MUXOUT_DIV_RCLK_2 = 0x4, 402 ADF4377_MUXOUT_DIV_NCLK_2 = 0x5, 403 ADF4377_MUXOUT_HIGH = 0x8, 404 }; 405 406 struct adf4377_chip_info { 407 const char *name; 408 bool has_gpio_enclk2; 409 }; 410 411 struct adf4377_state { 412 const struct adf4377_chip_info *chip_info; 413 struct spi_device *spi; 414 struct regmap *regmap; 415 struct clk *clkin; 416 /* Protect against concurrent accesses to the device and data content */ 417 struct mutex lock; 418 struct notifier_block nb; 419 /* Reference Divider */ 420 unsigned int ref_div_factor; 421 /* PFD Frequency */ 422 unsigned int f_pfd; 423 /* Input Reference Clock */ 424 unsigned int clkin_freq; 425 /* CLKOUT Divider */ 426 u8 clkout_div_sel; 427 /* Feedback Divider (N) */ 428 u16 n_int; 429 u16 synth_lock_timeout; 430 u16 vco_alc_timeout; 431 u16 adc_clk_div; 432 u16 vco_band_div; 433 u8 dclk_div1; 434 u8 dclk_div2; 435 u8 dclk_mode; 436 unsigned int f_div_rclk; 437 enum muxout_select_mode muxout_select; 438 struct gpio_desc *gpio_ce; 439 struct gpio_desc *gpio_enclk1; 440 struct gpio_desc *gpio_enclk2; 441 struct clk *clk; 442 struct clk *clkout; 443 struct clk_hw hw; 444 u8 buf[2] __aligned(IIO_DMA_MINALIGN); 445 }; 446 447 #define to_adf4377_state(h) container_of(h, struct adf4377_state, hw) 448 449 static const char * const adf4377_muxout_modes[] = { 450 [ADF4377_MUXOUT_HIGH_Z] = "high_z", 451 [ADF4377_MUXOUT_LKDET] = "lock_detect", 452 [ADF4377_MUXOUT_LOW] = "muxout_low", 453 [ADF4377_MUXOUT_DIV_RCLK_2] = "f_div_rclk_2", 454 [ADF4377_MUXOUT_DIV_NCLK_2] = "f_div_nclk_2", 455 [ADF4377_MUXOUT_HIGH] = "muxout_high", 456 }; 457 458 static const struct reg_sequence adf4377_reg_defaults[] = { 459 { 0x42, ADF4377_0042_R042_RSV1 }, 460 { 0x3B, ADF4377_003B_R03B_RSV1 }, 461 { 0x3A, ADF4377_003A_R03A_RSV1 }, 462 { 0x34, ADF4377_0034_R034_RSV1 }, 463 { 0x33, ADF4377_0033_R033_RSV1 }, 464 { 0x32, ADF4377_0032_R032_RSV1 }, 465 { 0x31, ADF4377_0031_R031_RSV1 }, 466 { 0x2C, ADF4377_002C_R02C_RSV1 }, 467 { 0x25, ADF4377_0025_R025_RSV1 }, 468 { 0x23, ADF4377_0023_R023_RSV1 }, 469 { 0x22, ADF4377_0022_R022_RSV1 }, 470 { 0x21, ADF4377_0021_R021_RSV1 }, 471 { 0x1f, ADF4377_001F_R01F_RSV1 }, 472 { 0x1c, ADF4377_001C_R01C_RSV1 }, 473 }; 474 475 static const struct regmap_config adf4377_regmap_config = { 476 .reg_bits = 16, 477 .val_bits = 8, 478 .read_flag_mask = BIT(7), 479 .max_register = 0x54, 480 }; 481 482 static int adf4377_reg_access(struct iio_dev *indio_dev, 483 unsigned int reg, 484 unsigned int write_val, 485 unsigned int *read_val) 486 { 487 struct adf4377_state *st = iio_priv(indio_dev); 488 489 if (read_val) 490 return regmap_read(st->regmap, reg, read_val); 491 492 return regmap_write(st->regmap, reg, write_val); 493 } 494 495 static const struct iio_info adf4377_info = { 496 .debugfs_reg_access = &adf4377_reg_access, 497 }; 498 499 static int adf4377_soft_reset(struct adf4377_state *st) 500 { 501 unsigned int read_val; 502 int ret; 503 504 ret = regmap_update_bits(st->regmap, 0x0, ADF4377_0000_SOFT_RESET_MSK | 505 ADF4377_0000_SOFT_RESET_R_MSK, 506 FIELD_PREP(ADF4377_0000_SOFT_RESET_MSK, 1) | 507 FIELD_PREP(ADF4377_0000_SOFT_RESET_R_MSK, 1)); 508 if (ret) 509 return ret; 510 511 return regmap_read_poll_timeout(st->regmap, 0x0, read_val, 512 !(read_val & (ADF4377_0000_SOFT_RESET_MSK | 513 ADF4377_0000_SOFT_RESET_R_MSK)), 200, 200 * 100); 514 } 515 516 static int adf4377_get_freq(struct adf4377_state *st, u64 *freq) 517 { 518 unsigned int ref_div_factor, n_int; 519 u64 clkin_freq; 520 int ret; 521 522 guard(mutex)(&st->lock); 523 524 ret = regmap_read(st->regmap, 0x12, &ref_div_factor); 525 if (ret) 526 return ret; 527 528 ret = regmap_bulk_read(st->regmap, 0x10, st->buf, sizeof(st->buf)); 529 if (ret) 530 return ret; 531 532 clkin_freq = clk_get_rate(st->clkin); 533 ref_div_factor = FIELD_GET(ADF4377_0012_R_DIV_MSK, ref_div_factor); 534 n_int = FIELD_GET(ADF4377_0010_N_INT_LSB_MSK | ADF4377_0011_N_INT_MSB_MSK, 535 get_unaligned_le16(&st->buf)); 536 537 *freq = div_u64(clkin_freq, ref_div_factor) * n_int; 538 539 return 0; 540 } 541 542 static int adf4377_set_freq(struct adf4377_state *st, u64 freq) 543 { 544 unsigned int read_val; 545 u64 f_vco; 546 int ret; 547 548 guard(mutex)(&st->lock); 549 550 if (freq > ADF4377_MAX_CLKPN_FREQ || freq < ADF4377_MIN_CLKPN_FREQ) 551 return -EINVAL; 552 553 ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK | 554 ADF4377_001C_EN_DRCLK_MSK, 555 FIELD_PREP(ADF4377_001C_EN_DNCLK_MSK, 1) | 556 FIELD_PREP(ADF4377_001C_EN_DRCLK_MSK, 1)); 557 if (ret) 558 return ret; 559 560 ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_AUTOCAL_MSK | 561 ADF4377_0011_DCLK_DIV2_MSK, 562 FIELD_PREP(ADF4377_0011_EN_AUTOCAL_MSK, 1) | 563 FIELD_PREP(ADF4377_0011_DCLK_DIV2_MSK, st->dclk_div2)); 564 if (ret) 565 return ret; 566 567 ret = regmap_update_bits(st->regmap, 0x2E, ADF4377_002E_EN_ADC_CNV_MSK | 568 ADF4377_002E_EN_ADC_MSK | 569 ADF4377_002E_ADC_A_CONV_MSK, 570 FIELD_PREP(ADF4377_002E_EN_ADC_CNV_MSK, 1) | 571 FIELD_PREP(ADF4377_002E_EN_ADC_MSK, 1) | 572 FIELD_PREP(ADF4377_002E_ADC_A_CONV_MSK, 573 ADF4377_002E_ADC_A_CONV_VCO_CALIB)); 574 if (ret) 575 return ret; 576 577 ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK, 578 FIELD_PREP(ADF4377_0020_EN_ADC_CLK_MSK, 1)); 579 if (ret) 580 return ret; 581 582 ret = regmap_update_bits(st->regmap, 0x2F, ADF4377_002F_DCLK_DIV1_MSK, 583 FIELD_PREP(ADF4377_002F_DCLK_DIV1_MSK, st->dclk_div1)); 584 if (ret) 585 return ret; 586 587 ret = regmap_update_bits(st->regmap, 0x24, ADF4377_0024_DCLK_MODE_MSK, 588 FIELD_PREP(ADF4377_0024_DCLK_MODE_MSK, st->dclk_mode)); 589 if (ret) 590 return ret; 591 592 ret = regmap_write(st->regmap, 0x27, 593 FIELD_PREP(ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK, 594 st->synth_lock_timeout)); 595 if (ret) 596 return ret; 597 598 ret = regmap_update_bits(st->regmap, 0x28, ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK, 599 FIELD_PREP(ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK, 600 st->synth_lock_timeout >> 8)); 601 if (ret) 602 return ret; 603 604 ret = regmap_write(st->regmap, 0x29, 605 FIELD_PREP(ADF4377_0029_VCO_ALC_TO_LSB_MSK, 606 st->vco_alc_timeout)); 607 if (ret) 608 return ret; 609 610 ret = regmap_update_bits(st->regmap, 0x2A, ADF4377_002A_VCO_ALC_TO_MSB_MSK, 611 FIELD_PREP(ADF4377_002A_VCO_ALC_TO_MSB_MSK, 612 st->vco_alc_timeout >> 8)); 613 if (ret) 614 return ret; 615 616 ret = regmap_write(st->regmap, 0x26, 617 FIELD_PREP(ADF4377_0026_VCO_BAND_DIV_MSK, st->vco_band_div)); 618 if (ret) 619 return ret; 620 621 ret = regmap_write(st->regmap, 0x2D, 622 FIELD_PREP(ADF4377_002D_ADC_CLK_DIV_MSK, st->adc_clk_div)); 623 if (ret) 624 return ret; 625 626 st->clkout_div_sel = 0; 627 628 f_vco = freq; 629 630 while (f_vco < ADF4377_MIN_VCO_FREQ) { 631 f_vco <<= 1; 632 st->clkout_div_sel++; 633 } 634 635 st->n_int = div_u64(freq, st->f_pfd); 636 637 ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_RDBLR_MSK | 638 ADF4377_0011_N_INT_MSB_MSK, 639 FIELD_PREP(ADF4377_0011_EN_RDBLR_MSK, 0) | 640 FIELD_PREP(ADF4377_0011_N_INT_MSB_MSK, st->n_int >> 8)); 641 if (ret) 642 return ret; 643 644 ret = regmap_update_bits(st->regmap, 0x12, ADF4377_0012_R_DIV_MSK | 645 ADF4377_0012_CLKOUT_DIV_MSK, 646 FIELD_PREP(ADF4377_0012_CLKOUT_DIV_MSK, st->clkout_div_sel) | 647 FIELD_PREP(ADF4377_0012_R_DIV_MSK, st->ref_div_factor)); 648 if (ret) 649 return ret; 650 651 ret = regmap_write(st->regmap, 0x10, 652 FIELD_PREP(ADF4377_0010_N_INT_LSB_MSK, st->n_int)); 653 if (ret) 654 return ret; 655 656 ret = regmap_read_poll_timeout(st->regmap, 0x49, read_val, 657 !(read_val & (ADF4377_0049_FSM_BUSY_MSK)), 200, 200 * 100); 658 if (ret) 659 return ret; 660 661 /* Disable EN_DNCLK, EN_DRCLK */ 662 ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK | 663 ADF4377_001C_EN_DRCLK_MSK, 664 FIELD_PREP(ADF4377_001C_EN_DNCLK_MSK, 0) | 665 FIELD_PREP(ADF4377_001C_EN_DRCLK_MSK, 0)); 666 if (ret) 667 return ret; 668 669 /* Disable EN_ADC_CLK */ 670 ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK, 671 FIELD_PREP(ADF4377_0020_EN_ADC_CLK_MSK, 0)); 672 if (ret) 673 return ret; 674 675 /* Set output Amplitude */ 676 return regmap_update_bits(st->regmap, 0x19, ADF4377_0019_CLKOUT2_OP_MSK | 677 ADF4377_0019_CLKOUT1_OP_MSK, 678 FIELD_PREP(ADF4377_0019_CLKOUT1_OP_MSK, 679 ADF4377_0019_CLKOUT_420MV) | 680 FIELD_PREP(ADF4377_0019_CLKOUT2_OP_MSK, 681 ADF4377_0019_CLKOUT_420MV)); 682 } 683 684 static void adf4377_gpio_init(struct adf4377_state *st) 685 { 686 if (st->gpio_ce) { 687 gpiod_set_value(st->gpio_ce, 1); 688 689 /* Delay for SPI register bits to settle to their power-on reset state */ 690 fsleep(200); 691 } 692 693 if (st->gpio_enclk1) 694 gpiod_set_value(st->gpio_enclk1, 1); 695 696 if (st->gpio_enclk2) 697 gpiod_set_value(st->gpio_enclk2, 1); 698 } 699 700 static int adf4377_init(struct adf4377_state *st) 701 { 702 struct device *dev = &st->spi->dev; 703 int ret; 704 705 adf4377_gpio_init(st); 706 707 ret = adf4377_soft_reset(st); 708 if (ret) 709 return dev_err_probe(dev, ret, "Failed to soft reset.\n"); 710 711 ret = regmap_multi_reg_write(st->regmap, adf4377_reg_defaults, 712 ARRAY_SIZE(adf4377_reg_defaults)); 713 if (ret) 714 return dev_err_probe(dev, ret, 715 "Failed to set default registers.\n"); 716 717 ret = regmap_update_bits(st->regmap, 0x00, 718 ADF4377_0000_SDO_ACTIVE_MSK | ADF4377_0000_SDO_ACTIVE_R_MSK, 719 FIELD_PREP(ADF4377_0000_SDO_ACTIVE_MSK, 720 ADF4377_0000_SDO_ACTIVE_SPI_4W) | 721 FIELD_PREP(ADF4377_0000_SDO_ACTIVE_R_MSK, 722 ADF4377_0000_SDO_ACTIVE_SPI_4W)); 723 if (ret) 724 return dev_err_probe(dev, ret, 725 "Failed to set 4-Wire Operation.\n"); 726 727 st->clkin_freq = clk_get_rate(st->clkin); 728 729 /* Power Up */ 730 ret = regmap_write(st->regmap, 0x1a, 731 FIELD_PREP(ADF4377_001A_PD_ALL_MSK, 0) | 732 FIELD_PREP(ADF4377_001A_PD_RDIV_MSK, 0) | 733 FIELD_PREP(ADF4377_001A_PD_NDIV_MSK, 0) | 734 FIELD_PREP(ADF4377_001A_PD_VCO_MSK, 0) | 735 FIELD_PREP(ADF4377_001A_PD_LD_MSK, 0) | 736 FIELD_PREP(ADF4377_001A_PD_PFDCP_MSK, 0) | 737 FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) | 738 FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0)); 739 if (ret) 740 return dev_err_probe(dev, ret, 741 "Failed to set power down registers.\n"); 742 743 /* Set Mux Output */ 744 ret = regmap_update_bits(st->regmap, 0x1D, 745 ADF4377_001D_MUXOUT_MSK, 746 FIELD_PREP(ADF4377_001D_MUXOUT_MSK, st->muxout_select)); 747 if (ret) 748 return ret; 749 750 /* Compute PFD */ 751 st->ref_div_factor = 0; 752 do { 753 st->ref_div_factor++; 754 st->f_pfd = st->clkin_freq / st->ref_div_factor; 755 } while (st->f_pfd > ADF4377_MAX_FREQ_PFD); 756 757 if (st->f_pfd > ADF4377_MAX_FREQ_PFD || st->f_pfd < ADF4377_MIN_FREQ_PFD) 758 return -EINVAL; 759 760 st->f_div_rclk = st->f_pfd; 761 762 if (st->f_pfd <= ADF4377_FREQ_PFD_80MHZ) { 763 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1; 764 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; 765 st->dclk_mode = 0; 766 } else if (st->f_pfd <= ADF4377_FREQ_PFD_125MHZ) { 767 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1; 768 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; 769 st->dclk_mode = 1; 770 } else if (st->f_pfd <= ADF4377_FREQ_PFD_160MHZ) { 771 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; 772 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; 773 st->dclk_mode = 0; 774 st->f_div_rclk /= 2; 775 } else if (st->f_pfd <= ADF4377_FREQ_PFD_250MHZ) { 776 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; 777 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; 778 st->dclk_mode = 1; 779 st->f_div_rclk /= 2; 780 } else if (st->f_pfd <= ADF4377_FREQ_PFD_320MHZ) { 781 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; 782 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2; 783 st->dclk_mode = 0; 784 st->f_div_rclk /= 4; 785 } else { 786 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; 787 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2; 788 st->dclk_mode = 1; 789 st->f_div_rclk /= 4; 790 } 791 792 st->synth_lock_timeout = DIV_ROUND_UP(st->f_div_rclk, 50000); 793 st->vco_alc_timeout = DIV_ROUND_UP(st->f_div_rclk, 20000); 794 st->vco_band_div = DIV_ROUND_UP(st->f_div_rclk, 150000 * 16 * (1 << st->dclk_mode)); 795 st->adc_clk_div = DIV_ROUND_UP((st->f_div_rclk / 400000 - 2), 4); 796 797 return 0; 798 } 799 800 static ssize_t adf4377_read(struct iio_dev *indio_dev, uintptr_t private, 801 const struct iio_chan_spec *chan, char *buf) 802 { 803 struct adf4377_state *st = iio_priv(indio_dev); 804 u64 val = 0; 805 int ret; 806 807 switch ((u32)private) { 808 case ADF4377_FREQ: 809 ret = adf4377_get_freq(st, &val); 810 if (ret) 811 return ret; 812 813 return sysfs_emit(buf, "%llu\n", val); 814 default: 815 return -EINVAL; 816 } 817 } 818 819 static ssize_t adf4377_write(struct iio_dev *indio_dev, uintptr_t private, 820 const struct iio_chan_spec *chan, const char *buf, 821 size_t len) 822 { 823 struct adf4377_state *st = iio_priv(indio_dev); 824 unsigned long long freq; 825 int ret; 826 827 switch ((u32)private) { 828 case ADF4377_FREQ: 829 ret = kstrtoull(buf, 10, &freq); 830 if (ret) 831 return ret; 832 833 ret = adf4377_set_freq(st, freq); 834 if (ret) 835 return ret; 836 837 return len; 838 default: 839 return -EINVAL; 840 } 841 } 842 843 #define _ADF4377_EXT_INFO(_name, _shared, _ident) { \ 844 .name = _name, \ 845 .read = adf4377_read, \ 846 .write = adf4377_write, \ 847 .private = _ident, \ 848 .shared = _shared, \ 849 } 850 851 static const struct iio_chan_spec_ext_info adf4377_ext_info[] = { 852 /* 853 * Usually we use IIO_CHAN_INFO_FREQUENCY, but there are 854 * values > 2^32 in order to support the entire frequency range 855 * in Hz. 856 */ 857 _ADF4377_EXT_INFO("frequency", IIO_SEPARATE, ADF4377_FREQ), 858 { } 859 }; 860 861 static const struct iio_chan_spec adf4377_channels[] = { 862 { 863 .type = IIO_ALTVOLTAGE, 864 .indexed = 1, 865 .output = 1, 866 .channel = 0, 867 .ext_info = adf4377_ext_info, 868 }, 869 }; 870 871 static int adf4377_properties_parse(struct adf4377_state *st) 872 { 873 struct device *dev = &st->spi->dev; 874 int ret; 875 876 st->clkin = devm_clk_get_enabled(dev, "ref_in"); 877 if (IS_ERR(st->clkin)) 878 return dev_err_probe(dev, PTR_ERR(st->clkin), 879 "failed to get the reference input clock\n"); 880 881 st->gpio_ce = devm_gpiod_get_optional(dev, "chip-enable", 882 GPIOD_OUT_LOW); 883 if (IS_ERR(st->gpio_ce)) 884 return dev_err_probe(dev, PTR_ERR(st->gpio_ce), 885 "failed to get the CE GPIO\n"); 886 887 st->gpio_enclk1 = devm_gpiod_get_optional(dev, "clk1-enable", 888 GPIOD_OUT_LOW); 889 if (IS_ERR(st->gpio_enclk1)) 890 return dev_err_probe(dev, PTR_ERR(st->gpio_enclk1), 891 "failed to get the CE GPIO\n"); 892 893 if (st->chip_info->has_gpio_enclk2) { 894 st->gpio_enclk2 = devm_gpiod_get_optional(dev, "clk2-enable", 895 GPIOD_OUT_LOW); 896 if (IS_ERR(st->gpio_enclk2)) 897 return dev_err_probe(dev, PTR_ERR(st->gpio_enclk2), 898 "failed to get the CE GPIO\n"); 899 } 900 901 ret = device_property_match_property_string(dev, "adi,muxout-select", 902 adf4377_muxout_modes, 903 ARRAY_SIZE(adf4377_muxout_modes)); 904 if (ret >= 0) 905 st->muxout_select = ret; 906 else 907 st->muxout_select = ADF4377_MUXOUT_HIGH_Z; 908 909 return 0; 910 } 911 912 static int adf4377_freq_change(struct notifier_block *nb, unsigned long action, void *data) 913 { 914 struct adf4377_state *st = container_of(nb, struct adf4377_state, nb); 915 916 if (action == POST_RATE_CHANGE) { 917 guard(mutex)(&st->lock); 918 919 return notifier_from_errno(adf4377_init(st)); 920 } 921 922 return NOTIFY_OK; 923 } 924 925 static unsigned long adf4377_clk_recalc_rate(struct clk_hw *hw, 926 unsigned long parent_rate) 927 { 928 struct adf4377_state *st = to_adf4377_state(hw); 929 u64 freq; 930 int ret; 931 932 ret = adf4377_get_freq(st, &freq); 933 if (ret) 934 return 0; 935 936 return freq; 937 } 938 939 static int adf4377_clk_set_rate(struct clk_hw *hw, 940 unsigned long rate, 941 unsigned long parent_rate) 942 { 943 struct adf4377_state *st = to_adf4377_state(hw); 944 945 return adf4377_set_freq(st, rate); 946 } 947 948 static int adf4377_clk_prepare(struct clk_hw *hw) 949 { 950 struct adf4377_state *st = to_adf4377_state(hw); 951 952 return regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK | 953 ADF4377_001A_PD_CLKOUT2_MSK, 954 FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) | 955 FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0)); 956 } 957 958 static void adf4377_clk_unprepare(struct clk_hw *hw) 959 { 960 struct adf4377_state *st = to_adf4377_state(hw); 961 962 regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK | 963 ADF4377_001A_PD_CLKOUT2_MSK, 964 FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 1) | 965 FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 1)); 966 } 967 968 static int adf4377_clk_is_prepared(struct clk_hw *hw) 969 { 970 struct adf4377_state *st = to_adf4377_state(hw); 971 unsigned int readval; 972 int ret; 973 974 ret = regmap_read(st->regmap, 0x1a, &readval); 975 if (ret) 976 return ret; 977 978 return !(readval & (ADF4377_001A_PD_CLKOUT1_MSK | ADF4377_001A_PD_CLKOUT2_MSK)); 979 } 980 981 static const struct clk_ops adf4377_clk_ops = { 982 .recalc_rate = adf4377_clk_recalc_rate, 983 .set_rate = adf4377_clk_set_rate, 984 .prepare = adf4377_clk_prepare, 985 .unprepare = adf4377_clk_unprepare, 986 .is_prepared = adf4377_clk_is_prepared, 987 }; 988 989 static int adf4377_clk_register(struct adf4377_state *st) 990 { 991 struct spi_device *spi = st->spi; 992 struct device *dev = &spi->dev; 993 struct clk_init_data init; 994 struct clk_parent_data parent_data; 995 int ret; 996 997 if (!device_property_present(dev, "#clock-cells")) 998 return 0; 999 1000 ret = device_property_read_string(dev, "clock-output-names", &init.name); 1001 if (ret) { 1002 init.name = devm_kasprintf(dev, GFP_KERNEL, "%pfw-clk", 1003 dev_fwnode(dev)); 1004 if (!init.name) 1005 return -ENOMEM; 1006 } 1007 1008 parent_data.fw_name = "ref_in"; 1009 1010 init.ops = &adf4377_clk_ops; 1011 init.parent_data = &parent_data; 1012 init.num_parents = 1; 1013 init.flags = CLK_SET_RATE_PARENT; 1014 1015 st->hw.init = &init; 1016 ret = devm_clk_hw_register(dev, &st->hw); 1017 if (ret) 1018 return ret; 1019 1020 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &st->hw); 1021 if (ret) 1022 return ret; 1023 1024 st->clkout = st->hw.clk; 1025 1026 return 0; 1027 } 1028 1029 static const struct adf4377_chip_info adf4377_chip_info = { 1030 .name = "adf4377", 1031 .has_gpio_enclk2 = true, 1032 }; 1033 1034 static const struct adf4377_chip_info adf4378_chip_info = { 1035 .name = "adf4378", 1036 .has_gpio_enclk2 = false, 1037 }; 1038 1039 static int adf4377_probe(struct spi_device *spi) 1040 { 1041 struct iio_dev *indio_dev; 1042 struct regmap *regmap; 1043 struct adf4377_state *st; 1044 struct device *dev = &spi->dev; 1045 int ret; 1046 1047 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1048 if (!indio_dev) 1049 return -ENOMEM; 1050 1051 regmap = devm_regmap_init_spi(spi, &adf4377_regmap_config); 1052 if (IS_ERR(regmap)) 1053 return PTR_ERR(regmap); 1054 1055 st = iio_priv(indio_dev); 1056 1057 indio_dev->info = &adf4377_info; 1058 indio_dev->name = "adf4377"; 1059 1060 st->regmap = regmap; 1061 st->spi = spi; 1062 st->chip_info = spi_get_device_match_data(spi); 1063 mutex_init(&st->lock); 1064 1065 ret = adf4377_properties_parse(st); 1066 if (ret) 1067 return ret; 1068 1069 st->nb.notifier_call = adf4377_freq_change; 1070 ret = devm_clk_notifier_register(dev, st->clkin, &st->nb); 1071 if (ret) 1072 return ret; 1073 1074 ret = adf4377_init(st); 1075 if (ret) 1076 return ret; 1077 1078 ret = adf4377_clk_register(st); 1079 if (ret) 1080 return ret; 1081 1082 if (!st->clkout) { 1083 indio_dev->channels = adf4377_channels; 1084 indio_dev->num_channels = ARRAY_SIZE(adf4377_channels); 1085 } 1086 1087 return devm_iio_device_register(dev, indio_dev); 1088 } 1089 1090 static const struct spi_device_id adf4377_id[] = { 1091 { .name = "adf4377", .driver_data = (kernel_ulong_t)&adf4377_chip_info }, 1092 { .name = "adf4378", .driver_data = (kernel_ulong_t)&adf4378_chip_info }, 1093 { } 1094 }; 1095 MODULE_DEVICE_TABLE(spi, adf4377_id); 1096 1097 static const struct of_device_id adf4377_of_match[] = { 1098 { .compatible = "adi,adf4377", .data = &adf4377_chip_info }, 1099 { .compatible = "adi,adf4378", .data = &adf4378_chip_info }, 1100 { } 1101 }; 1102 MODULE_DEVICE_TABLE(of, adf4377_of_match); 1103 1104 static struct spi_driver adf4377_driver = { 1105 .driver = { 1106 .name = "adf4377", 1107 .of_match_table = adf4377_of_match, 1108 }, 1109 .probe = adf4377_probe, 1110 .id_table = adf4377_id, 1111 }; 1112 module_spi_driver(adf4377_driver); 1113 1114 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>"); 1115 MODULE_DESCRIPTION("Analog Devices ADF4377"); 1116 MODULE_LICENSE("GPL"); 1117