1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices ADF4371 SPI Wideband Synthesizer driver 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7 #include "linux/dev_printk.h" 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gcd.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 #include <linux/sysfs.h> 17 #include <linux/spi/spi.h> 18 19 #include <linux/iio/iio.h> 20 21 /* Registers address macro */ 22 #define ADF4371_REG(x) (x) 23 24 /* ADF4371_REG0 */ 25 #define ADF4371_ADDR_ASC_MSK BIT(2) 26 #define ADF4371_ADDR_ASC(x) FIELD_PREP(ADF4371_ADDR_ASC_MSK, x) 27 #define ADF4371_ADDR_ASC_R_MSK BIT(5) 28 #define ADF4371_ADDR_ASC_R(x) FIELD_PREP(ADF4371_ADDR_ASC_R_MSK, x) 29 #define ADF4371_RESET_CMD 0x81 30 31 /* ADF4371_REG17 */ 32 #define ADF4371_FRAC2WORD_L_MSK GENMASK(7, 1) 33 #define ADF4371_FRAC2WORD_L(x) FIELD_PREP(ADF4371_FRAC2WORD_L_MSK, x) 34 #define ADF4371_FRAC1WORD_MSK BIT(0) 35 #define ADF4371_FRAC1WORD(x) FIELD_PREP(ADF4371_FRAC1WORD_MSK, x) 36 37 /* ADF4371_REG18 */ 38 #define ADF4371_FRAC2WORD_H_MSK GENMASK(6, 0) 39 #define ADF4371_FRAC2WORD_H(x) FIELD_PREP(ADF4371_FRAC2WORD_H_MSK, x) 40 41 /* ADF4371_REG1A */ 42 #define ADF4371_MOD2WORD_MSK GENMASK(5, 0) 43 #define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x) 44 45 /* ADF4371_REG24 */ 46 #define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4) 47 #define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x) 48 49 /* ADF4371_REG25 */ 50 #define ADF4371_MUTE_LD_MSK BIT(7) 51 #define ADF4371_MUTE_LD(x) FIELD_PREP(ADF4371_MUTE_LD_MSK, x) 52 53 /* ADF4371_REG32 */ 54 #define ADF4371_TIMEOUT_MSK GENMASK(1, 0) 55 #define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x) 56 57 /* ADF4371_REG34 */ 58 #define ADF4371_VCO_ALC_TOUT_MSK GENMASK(4, 0) 59 #define ADF4371_VCO_ALC_TOUT(x) FIELD_PREP(ADF4371_VCO_ALC_TOUT_MSK, x) 60 61 /* Specifications */ 62 #define ADF4371_MIN_VCO_FREQ 4000000000ULL /* 4000 MHz */ 63 #define ADF4371_MAX_VCO_FREQ 8000000000ULL /* 8000 MHz */ 64 #define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */ 65 #define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */ 66 #define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */ 67 #define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */ 68 #define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */ 69 #define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */ 70 71 #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */ 72 #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */ 73 74 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */ 75 #define ADF4371_MODULUS1 33554432ULL 76 /* MOD2 is the programmable, 14-bit auxiliary fractional modulus */ 77 #define ADF4371_MAX_MODULUS2 BIT(14) 78 79 #define ADF4371_CHECK_RANGE(freq, range) \ 80 ((freq > ADF4371_MAX_ ## range) || (freq < ADF4371_MIN_ ## range)) 81 82 enum { 83 ADF4371_FREQ, 84 ADF4371_POWER_DOWN, 85 ADF4371_CHANNEL_NAME 86 }; 87 88 enum { 89 ADF4371_CH_RF8, 90 ADF4371_CH_RFAUX8, 91 ADF4371_CH_RF16, 92 ADF4371_CH_RF32 93 }; 94 95 enum adf4371_variant { 96 ADF4371, 97 ADF4372 98 }; 99 100 struct adf4371_pwrdown { 101 unsigned int reg; 102 unsigned int bit; 103 }; 104 105 static const char * const adf4371_ch_names[] = { 106 "RF8x", "RFAUX8x", "RF16x", "RF32x" 107 }; 108 109 static const struct adf4371_pwrdown adf4371_pwrdown_ch[4] = { 110 [ADF4371_CH_RF8] = { ADF4371_REG(0x25), 2 }, 111 [ADF4371_CH_RFAUX8] = { ADF4371_REG(0x72), 3 }, 112 [ADF4371_CH_RF16] = { ADF4371_REG(0x25), 3 }, 113 [ADF4371_CH_RF32] = { ADF4371_REG(0x25), 4 }, 114 }; 115 116 static const struct reg_sequence adf4371_reg_defaults[] = { 117 { ADF4371_REG(0x0), 0x18 }, 118 { ADF4371_REG(0x12), 0x40 }, 119 { ADF4371_REG(0x1E), 0x48 }, 120 { ADF4371_REG(0x20), 0x14 }, 121 { ADF4371_REG(0x22), 0x00 }, 122 { ADF4371_REG(0x23), 0x00 }, 123 { ADF4371_REG(0x24), 0x80 }, 124 { ADF4371_REG(0x25), 0x07 }, 125 { ADF4371_REG(0x27), 0xC5 }, 126 { ADF4371_REG(0x28), 0x83 }, 127 { ADF4371_REG(0x2C), 0x44 }, 128 { ADF4371_REG(0x2D), 0x11 }, 129 { ADF4371_REG(0x2E), 0x12 }, 130 { ADF4371_REG(0x2F), 0x94 }, 131 { ADF4371_REG(0x32), 0x04 }, 132 { ADF4371_REG(0x35), 0xFA }, 133 { ADF4371_REG(0x36), 0x30 }, 134 { ADF4371_REG(0x39), 0x07 }, 135 { ADF4371_REG(0x3A), 0x55 }, 136 { ADF4371_REG(0x3E), 0x0C }, 137 { ADF4371_REG(0x3F), 0x80 }, 138 { ADF4371_REG(0x40), 0x50 }, 139 { ADF4371_REG(0x41), 0x28 }, 140 { ADF4371_REG(0x47), 0xC0 }, 141 { ADF4371_REG(0x52), 0xF4 }, 142 { ADF4371_REG(0x70), 0x03 }, 143 { ADF4371_REG(0x71), 0x60 }, 144 { ADF4371_REG(0x72), 0x32 }, 145 }; 146 147 static const struct regmap_config adf4371_regmap_config = { 148 .reg_bits = 16, 149 .val_bits = 8, 150 .read_flag_mask = BIT(7), 151 }; 152 153 struct adf4371_chip_info { 154 const char *name; 155 unsigned int num_channels; 156 const struct iio_chan_spec *channels; 157 }; 158 159 struct adf4371_state { 160 struct spi_device *spi; 161 struct regmap *regmap; 162 /* 163 * Lock for accessing device registers. Some operations require 164 * multiple consecutive R/W operations, during which the device 165 * shouldn't be interrupted. The buffers are also shared across 166 * all operations so need to be protected on stand alone reads and 167 * writes. 168 */ 169 struct mutex lock; 170 const struct adf4371_chip_info *chip_info; 171 unsigned long clkin_freq; 172 unsigned long fpfd; 173 unsigned int integer; 174 unsigned int fract1; 175 unsigned int fract2; 176 unsigned int mod2; 177 unsigned int rf_div_sel; 178 unsigned int ref_div_factor; 179 u8 buf[10] __aligned(IIO_DMA_MINALIGN); 180 }; 181 182 static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st, 183 u32 channel) 184 { 185 unsigned long long val, tmp; 186 unsigned int ref_div_sel; 187 188 val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd; 189 tmp = (u64)st->fract2 * st->fpfd; 190 do_div(tmp, st->mod2); 191 val += tmp + ADF4371_MODULUS1 / 2; 192 193 if (channel == ADF4371_CH_RF8 || channel == ADF4371_CH_RFAUX8) 194 ref_div_sel = st->rf_div_sel; 195 else 196 ref_div_sel = 0; 197 198 do_div(val, ADF4371_MODULUS1 * (1 << ref_div_sel)); 199 200 if (channel == ADF4371_CH_RF16) 201 val <<= 1; 202 else if (channel == ADF4371_CH_RF32) 203 val <<= 2; 204 205 return val; 206 } 207 208 static void adf4371_pll_fract_n_compute(unsigned long long vco, 209 unsigned long long pfd, 210 unsigned int *integer, 211 unsigned int *fract1, 212 unsigned int *fract2, 213 unsigned int *mod2) 214 { 215 unsigned long long tmp; 216 u32 gcd_div; 217 218 tmp = do_div(vco, pfd); 219 tmp = tmp * ADF4371_MODULUS1; 220 *fract2 = do_div(tmp, pfd); 221 222 *integer = vco; 223 *fract1 = tmp; 224 225 *mod2 = pfd; 226 227 while (*mod2 > ADF4371_MAX_MODULUS2) { 228 *mod2 >>= 1; 229 *fract2 >>= 1; 230 } 231 232 gcd_div = gcd(*fract2, *mod2); 233 *mod2 /= gcd_div; 234 *fract2 /= gcd_div; 235 } 236 237 static int adf4371_set_freq(struct adf4371_state *st, unsigned long long freq, 238 unsigned int channel) 239 { 240 u32 cp_bleed; 241 u8 int_mode = 0; 242 int ret; 243 244 switch (channel) { 245 case ADF4371_CH_RF8: 246 case ADF4371_CH_RFAUX8: 247 if (ADF4371_CHECK_RANGE(freq, OUT_RF8_FREQ)) 248 return -EINVAL; 249 250 st->rf_div_sel = 0; 251 252 while (freq < ADF4371_MIN_VCO_FREQ) { 253 freq <<= 1; 254 st->rf_div_sel++; 255 } 256 break; 257 case ADF4371_CH_RF16: 258 /* ADF4371 RF16 8000...16000 MHz */ 259 if (ADF4371_CHECK_RANGE(freq, OUT_RF16_FREQ)) 260 return -EINVAL; 261 262 freq >>= 1; 263 break; 264 case ADF4371_CH_RF32: 265 /* ADF4371 RF32 16000...32000 MHz */ 266 if (ADF4371_CHECK_RANGE(freq, OUT_RF32_FREQ)) 267 return -EINVAL; 268 269 freq >>= 2; 270 break; 271 default: 272 return -EINVAL; 273 } 274 275 adf4371_pll_fract_n_compute(freq, st->fpfd, &st->integer, &st->fract1, 276 &st->fract2, &st->mod2); 277 st->buf[0] = st->integer >> 8; 278 st->buf[1] = 0x40; /* REG12 default */ 279 st->buf[2] = 0x00; 280 st->buf[3] = st->fract1 & 0xFF; 281 st->buf[4] = st->fract1 >> 8; 282 st->buf[5] = st->fract1 >> 16; 283 st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) | 284 ADF4371_FRAC1WORD(st->fract1 >> 24); 285 st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7); 286 st->buf[8] = st->mod2 & 0xFF; 287 st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8); 288 289 ret = regmap_bulk_write(st->regmap, ADF4371_REG(0x11), st->buf, 10); 290 if (ret < 0) 291 return ret; 292 /* 293 * The R counter allows the input reference frequency to be 294 * divided down to produce the reference clock to the PFD 295 */ 296 ret = regmap_write(st->regmap, ADF4371_REG(0x1F), st->ref_div_factor); 297 if (ret < 0) 298 return ret; 299 300 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x24), 301 ADF4371_RF_DIV_SEL_MSK, 302 ADF4371_RF_DIV_SEL(st->rf_div_sel)); 303 if (ret < 0) 304 return ret; 305 306 cp_bleed = DIV_ROUND_UP(400 * 1750, st->integer * 375); 307 cp_bleed = clamp(cp_bleed, 1U, 255U); 308 ret = regmap_write(st->regmap, ADF4371_REG(0x26), cp_bleed); 309 if (ret < 0) 310 return ret; 311 /* 312 * Set to 1 when in INT mode (when FRAC1 = FRAC2 = 0), 313 * and set to 0 when in FRAC mode. 314 */ 315 if (st->fract1 == 0 && st->fract2 == 0) 316 int_mode = 0x01; 317 318 ret = regmap_write(st->regmap, ADF4371_REG(0x2B), int_mode); 319 if (ret < 0) 320 return ret; 321 322 return regmap_write(st->regmap, ADF4371_REG(0x10), st->integer & 0xFF); 323 } 324 325 static ssize_t adf4371_read(struct iio_dev *indio_dev, 326 uintptr_t private, 327 const struct iio_chan_spec *chan, 328 char *buf) 329 { 330 struct adf4371_state *st = iio_priv(indio_dev); 331 unsigned long long val = 0; 332 unsigned int readval, reg, bit; 333 int ret; 334 335 switch ((u32)private) { 336 case ADF4371_FREQ: 337 val = adf4371_pll_fract_n_get_rate(st, chan->channel); 338 ret = regmap_read(st->regmap, ADF4371_REG(0x7C), &readval); 339 if (ret < 0) 340 break; 341 342 if (readval == 0x00) { 343 dev_dbg(&st->spi->dev, "PLL un-locked\n"); 344 ret = -EBUSY; 345 } 346 break; 347 case ADF4371_POWER_DOWN: 348 reg = adf4371_pwrdown_ch[chan->channel].reg; 349 bit = adf4371_pwrdown_ch[chan->channel].bit; 350 351 ret = regmap_read(st->regmap, reg, &readval); 352 if (ret < 0) 353 break; 354 355 val = !(readval & BIT(bit)); 356 break; 357 case ADF4371_CHANNEL_NAME: 358 return sprintf(buf, "%s\n", adf4371_ch_names[chan->channel]); 359 default: 360 ret = -EINVAL; 361 val = 0; 362 break; 363 } 364 365 return ret < 0 ? ret : sprintf(buf, "%llu\n", val); 366 } 367 368 static ssize_t adf4371_write(struct iio_dev *indio_dev, 369 uintptr_t private, 370 const struct iio_chan_spec *chan, 371 const char *buf, size_t len) 372 { 373 struct adf4371_state *st = iio_priv(indio_dev); 374 unsigned long long freq; 375 bool power_down; 376 unsigned int bit, readval, reg; 377 int ret; 378 379 mutex_lock(&st->lock); 380 switch ((u32)private) { 381 case ADF4371_FREQ: 382 ret = kstrtoull(buf, 10, &freq); 383 if (ret) 384 break; 385 386 ret = adf4371_set_freq(st, freq, chan->channel); 387 break; 388 case ADF4371_POWER_DOWN: 389 ret = kstrtobool(buf, &power_down); 390 if (ret) 391 break; 392 393 reg = adf4371_pwrdown_ch[chan->channel].reg; 394 bit = adf4371_pwrdown_ch[chan->channel].bit; 395 ret = regmap_read(st->regmap, reg, &readval); 396 if (ret < 0) 397 break; 398 399 readval &= ~BIT(bit); 400 readval |= (!power_down << bit); 401 402 ret = regmap_write(st->regmap, reg, readval); 403 break; 404 default: 405 ret = -EINVAL; 406 break; 407 } 408 mutex_unlock(&st->lock); 409 410 return ret ? ret : len; 411 } 412 413 #define _ADF4371_EXT_INFO(_name, _ident) { \ 414 .name = _name, \ 415 .read = adf4371_read, \ 416 .write = adf4371_write, \ 417 .private = _ident, \ 418 .shared = IIO_SEPARATE, \ 419 } 420 421 static const struct iio_chan_spec_ext_info adf4371_ext_info[] = { 422 /* 423 * Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are 424 * values > 2^32 in order to support the entire frequency range 425 * in Hz. Using scale is a bit ugly. 426 */ 427 _ADF4371_EXT_INFO("frequency", ADF4371_FREQ), 428 _ADF4371_EXT_INFO("powerdown", ADF4371_POWER_DOWN), 429 _ADF4371_EXT_INFO("name", ADF4371_CHANNEL_NAME), 430 { }, 431 }; 432 433 #define ADF4371_CHANNEL(index) { \ 434 .type = IIO_ALTVOLTAGE, \ 435 .output = 1, \ 436 .channel = index, \ 437 .ext_info = adf4371_ext_info, \ 438 .indexed = 1, \ 439 } 440 441 static const struct iio_chan_spec adf4371_chan[] = { 442 ADF4371_CHANNEL(ADF4371_CH_RF8), 443 ADF4371_CHANNEL(ADF4371_CH_RFAUX8), 444 ADF4371_CHANNEL(ADF4371_CH_RF16), 445 ADF4371_CHANNEL(ADF4371_CH_RF32), 446 }; 447 448 static const struct adf4371_chip_info adf4371_chip_info = { 449 .name = "adf4371", 450 .channels = adf4371_chan, 451 .num_channels = 4, 452 }; 453 454 static const struct adf4371_chip_info adf4372_chip_info = { 455 .name = "adf4372", 456 .channels = adf4371_chan, 457 .num_channels = 3, 458 }; 459 460 static int adf4371_reg_access(struct iio_dev *indio_dev, 461 unsigned int reg, 462 unsigned int writeval, 463 unsigned int *readval) 464 { 465 struct adf4371_state *st = iio_priv(indio_dev); 466 467 if (readval) 468 return regmap_read(st->regmap, reg, readval); 469 else 470 return regmap_write(st->regmap, reg, writeval); 471 } 472 473 static const struct iio_info adf4371_info = { 474 .debugfs_reg_access = &adf4371_reg_access, 475 }; 476 477 static int adf4371_setup(struct adf4371_state *st) 478 { 479 unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1; 480 unsigned int vco_band_div, tmp; 481 int ret; 482 483 /* Perform a software reset */ 484 ret = regmap_write(st->regmap, ADF4371_REG(0x0), ADF4371_RESET_CMD); 485 if (ret < 0) 486 return ret; 487 488 ret = regmap_multi_reg_write(st->regmap, adf4371_reg_defaults, 489 ARRAY_SIZE(adf4371_reg_defaults)); 490 if (ret < 0) 491 return ret; 492 493 /* Mute to Lock Detect */ 494 if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) { 495 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25), 496 ADF4371_MUTE_LD_MSK, 497 ADF4371_MUTE_LD(1)); 498 if (ret < 0) 499 return ret; 500 } 501 502 /* Set address in ascending order, so the bulk_write() will work */ 503 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0), 504 ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK, 505 ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1)); 506 if (ret < 0) 507 return ret; 508 /* 509 * Calculate and maximize PFD frequency 510 * fPFD = REFIN × ((1 + D)/(R × (1 + T))) 511 * Where D is the REFIN doubler bit, T is the reference divide by 2, 512 * R is the reference division factor 513 * TODO: it is assumed D and T equal 0. 514 */ 515 do { 516 st->ref_div_factor++; 517 st->fpfd = st->clkin_freq / st->ref_div_factor; 518 } while (st->fpfd > ADF4371_MAX_FREQ_PFD); 519 520 /* Calculate Timeouts */ 521 vco_band_div = DIV_ROUND_UP(st->fpfd, 2400000U); 522 523 tmp = DIV_ROUND_CLOSEST(st->fpfd, 1000000U); 524 do { 525 timeout++; 526 if (timeout > 1023) { 527 timeout = 2; 528 synth_timeout++; 529 } 530 } while (synth_timeout * 1024 + timeout <= 20 * tmp); 531 532 do { 533 vco_alc_timeout++; 534 } while (vco_alc_timeout * 1024 - timeout <= 50 * tmp); 535 536 st->buf[0] = vco_band_div; 537 st->buf[1] = timeout & 0xFF; 538 st->buf[2] = ADF4371_TIMEOUT(timeout >> 8) | 0x04; 539 st->buf[3] = synth_timeout; 540 st->buf[4] = ADF4371_VCO_ALC_TOUT(vco_alc_timeout); 541 542 return regmap_bulk_write(st->regmap, ADF4371_REG(0x30), st->buf, 5); 543 } 544 545 static int adf4371_probe(struct spi_device *spi) 546 { 547 struct iio_dev *indio_dev; 548 struct adf4371_state *st; 549 struct regmap *regmap; 550 struct clk *clkin; 551 int ret; 552 553 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 554 if (!indio_dev) 555 return -ENOMEM; 556 557 regmap = devm_regmap_init_spi(spi, &adf4371_regmap_config); 558 if (IS_ERR(regmap)) 559 return dev_err_probe(&spi->dev, PTR_ERR(regmap), 560 "Error initializing spi regmap\n"); 561 562 st = iio_priv(indio_dev); 563 st->spi = spi; 564 st->regmap = regmap; 565 mutex_init(&st->lock); 566 567 st->chip_info = spi_get_device_match_data(spi); 568 if (!st->chip_info) 569 return -ENODEV; 570 571 indio_dev->name = st->chip_info->name; 572 indio_dev->info = &adf4371_info; 573 indio_dev->modes = INDIO_DIRECT_MODE; 574 indio_dev->channels = st->chip_info->channels; 575 indio_dev->num_channels = st->chip_info->num_channels; 576 577 clkin = devm_clk_get_enabled(&spi->dev, "clkin"); 578 if (IS_ERR(clkin)) 579 return dev_err_probe(&spi->dev, PTR_ERR(clkin), 580 "Failed to get clkin\n"); 581 582 st->clkin_freq = clk_get_rate(clkin); 583 584 ret = adf4371_setup(st); 585 if (ret < 0) 586 return dev_err_probe(&spi->dev, ret, "ADF4371 setup failed\n"); 587 588 return devm_iio_device_register(&spi->dev, indio_dev); 589 } 590 591 static const struct spi_device_id adf4371_id_table[] = { 592 { "adf4371", (kernel_ulong_t)&adf4371_chip_info }, 593 { "adf4372", (kernel_ulong_t)&adf4372_chip_info }, 594 {} 595 }; 596 MODULE_DEVICE_TABLE(spi, adf4371_id_table); 597 598 static const struct of_device_id adf4371_of_match[] = { 599 { .compatible = "adi,adf4371", .data = &adf4371_chip_info }, 600 { .compatible = "adi,adf4372", .data = &adf4372_chip_info}, 601 { }, 602 }; 603 MODULE_DEVICE_TABLE(of, adf4371_of_match); 604 605 static struct spi_driver adf4371_driver = { 606 .driver = { 607 .name = "adf4371", 608 .of_match_table = adf4371_of_match, 609 }, 610 .probe = adf4371_probe, 611 .id_table = adf4371_id_table, 612 }; 613 module_spi_driver(adf4371_driver); 614 615 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 616 MODULE_DESCRIPTION("Analog Devices ADF4371 SPI PLL"); 617 MODULE_LICENSE("GPL"); 618