1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADF41513 SPI PLL Frequency Synthesizer driver 4 * 5 * Copyright 2026 Analog Devices Inc. 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/dev_printk.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/kstrtox.h> 18 #include <linux/log2.h> 19 #include <linux/math64.h> 20 #include <linux/minmax.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/pm.h> 25 #include <linux/property.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/spi/spi.h> 28 #include <linux/sysfs.h> 29 #include <linux/types.h> 30 #include <linux/units.h> 31 32 #include <linux/iio/iio.h> 33 34 /* Registers */ 35 #define ADF41513_REG0 0 36 #define ADF41513_REG1 1 37 #define ADF41513_REG2 2 38 #define ADF41513_REG3 3 39 #define ADF41513_REG4 4 40 #define ADF41513_REG5 5 41 #define ADF41513_REG6 6 42 #define ADF41513_REG7 7 43 #define ADF41513_REG8 8 44 #define ADF41513_REG9 9 45 #define ADF41513_REG10 10 46 #define ADF41513_REG11 11 47 #define ADF41513_REG12 12 48 #define ADF41513_REG13 13 49 #define ADF41513_REG_NUM 14 50 51 #define ADF41513_SYNC_REG0 BIT(ADF41513_REG0) 52 #define ADF41513_SYNC_REG1 BIT(ADF41513_REG1) 53 #define ADF41513_SYNC_REG2 BIT(ADF41513_REG2) 54 #define ADF41513_SYNC_REG3 BIT(ADF41513_REG3) 55 #define ADF41513_SYNC_REG4 BIT(ADF41513_REG4) 56 #define ADF41513_SYNC_REG5 BIT(ADF41513_REG5) 57 #define ADF41513_SYNC_REG6 BIT(ADF41513_REG6) 58 #define ADF41513_SYNC_REG7 BIT(ADF41513_REG7) 59 #define ADF41513_SYNC_REG9 BIT(ADF41513_REG9) 60 #define ADF41513_SYNC_REG11 BIT(ADF41513_REG11) 61 #define ADF41513_SYNC_REG12 BIT(ADF41513_REG12) 62 #define ADF41513_SYNC_REG13 BIT(ADF41513_REG13) 63 #define ADF41513_SYNC_DIFF 0 64 #define ADF41513_SYNC_ALL GENMASK(ADF41513_REG13, ADF41513_REG0) 65 66 /* REG0 Bit Definitions */ 67 #define ADF41513_REG0_CTRL_BITS_MSK GENMASK(3, 0) 68 #define ADF41513_REG0_INT_MSK GENMASK(19, 4) 69 #define ADF41513_REG0_VAR_MOD_MSK BIT(28) 70 71 /* REG1 Bit Definitions */ 72 #define ADF41513_REG1_FRAC1_MSK GENMASK(28, 4) 73 #define ADF41513_REG1_DITHER2_MSK BIT(31) 74 75 /* REG2 Bit Definitions */ 76 #define ADF41513_REG2_PHASE_VAL_MSK GENMASK(15, 4) 77 #define ADF41513_REG2_PHASE_ADJ_MSK BIT(31) 78 79 /* REG3 Bit Definitions */ 80 #define ADF41513_REG3_FRAC2_MSK GENMASK(27, 4) 81 82 /* REG4 Bit Definitions */ 83 #define ADF41513_REG4_MOD2_MSK GENMASK(27, 4) 84 85 /* REG5 Bit Definitions */ 86 #define ADF41513_REG5_CLK1_DIV_MSK GENMASK(15, 4) 87 #define ADF41513_REG5_R_CNT_MSK GENMASK(20, 16) 88 #define ADF41513_REG5_REF_DOUBLER_MSK BIT(21) 89 #define ADF41513_REG5_RDIV2_MSK BIT(22) 90 #define ADF41513_REG5_PRESCALER_MSK BIT(23) 91 #define ADF41513_REG5_LSB_P1_MSK BIT(24) 92 #define ADF41513_REG5_CP_CURRENT_MSK GENMASK(28, 25) 93 #define ADF41513_REG5_DLD_MODES_MSK GENMASK(31, 30) 94 95 /* REG6 Bit Definitions */ 96 #define ADF41513_REG6_COUNTER_RESET_MSK BIT(4) 97 #define ADF41513_REG6_CP_TRISTATE_MSK BIT(5) 98 #define ADF41513_REG6_POWER_DOWN_MSK BIT(6) 99 #define ADF41513_REG6_PD_POLARITY_MSK BIT(7) 100 #define ADF41513_REG6_LDP_MSK GENMASK(9, 8) 101 #define ADF41513_REG6_CP_TRISTATE_PD_ON_MSK BIT(16) 102 #define ADF41513_REG6_SD_RESET_MSK BIT(17) 103 #define ADF41513_REG6_LOL_ENABLE_MSK BIT(18) 104 #define ADF41513_REG6_ABP_MSK BIT(19) 105 #define ADF41513_REG6_INT_MODE_MSK BIT(20) 106 #define ADF41513_REG6_BLEED_ENABLE_MSK BIT(22) 107 #define ADF41513_REG6_BLEED_POLARITY_MSK BIT(23) 108 #define ADF41513_REG6_BLEED_CURRENT_MSK GENMASK(31, 24) 109 110 /* REG7 Bit Definitions */ 111 #define ADF41513_REG7_CLK2_DIV_MSK GENMASK(17, 6) 112 #define ADF41513_REG7_CLK_DIV_MODE_MSK GENMASK(19, 18) 113 #define ADF41513_REG7_PS_BIAS_MSK GENMASK(21, 20) 114 #define ADF41513_REG7_N_DELAY_MSK GENMASK(23, 22) 115 #define ADF41513_REG7_LD_CLK_SEL_MSK BIT(26) 116 #define ADF41513_REG7_LD_COUNT_MSK GENMASK(29, 27) 117 118 /* REG9 Bit Definitions */ 119 #define ADF41513_REG9_LD_BIAS_MSK GENMASK(31, 30) 120 121 /* REG11 Bit Definitions */ 122 #define ADF41513_REG11_POWER_DOWN_SEL_MSK BIT(31) 123 124 /* REG12 Bit Definitions */ 125 #define ADF41513_REG12_READBACK_SEL_MSK GENMASK(19, 14) 126 #define ADF41513_REG12_LE_SELECT_MSK BIT(20) 127 #define ADF41513_REG12_MASTER_RESET_MSK BIT(22) 128 #define ADF41513_REG12_LOGIC_LEVEL_MSK BIT(27) 129 #define ADF41513_REG12_MUXOUT_MSK GENMASK(31, 28) 130 131 /* MUXOUT Selection */ 132 #define ADF41513_MUXOUT_TRISTATE 0x0 133 #define ADF41513_MUXOUT_DVDD 0x1 134 #define ADF41513_MUXOUT_DGND 0x2 135 #define ADF41513_MUXOUT_R_DIV 0x3 136 #define ADF41513_MUXOUT_N_DIV 0x4 137 #define ADF41513_MUXOUT_DIG_LD 0x6 138 #define ADF41513_MUXOUT_SDO 0x7 139 #define ADF41513_MUXOUT_READBACK 0x8 140 #define ADF41513_MUXOUT_CLK1_DIV 0xA 141 #define ADF41513_MUXOUT_R_DIV2 0xD 142 #define ADF41513_MUXOUT_N_DIV2 0xE 143 144 /* DLD Mode Selection */ 145 #define ADF41513_DLD_TRISTATE 0x0 146 #define ADF41513_DLD_DIG_LD 0x1 147 #define ADF41513_DLD_LOW 0x2 148 #define ADF41513_DLD_HIGH 0x3 149 150 /* Prescaler Selection */ 151 #define ADF41513_PRESCALER_4_5 0 152 #define ADF41513_PRESCALER_8_9 1 153 #define ADF41513_PRESCALER_AUTO 2 154 155 /* Specifications */ 156 #define ADF41510_MAX_RF_FREQ_HZ (10ULL * HZ_PER_GHZ) 157 #define ADF41513_MIN_RF_FREQ_HZ (1ULL * HZ_PER_GHZ) 158 #define ADF41513_MAX_RF_FREQ_HZ (26500ULL * HZ_PER_MHZ) 159 160 #define ADF41513_MIN_REF_FREQ_HZ (10 * HZ_PER_MHZ) 161 #define ADF41513_MAX_REF_FREQ_HZ (800 * HZ_PER_MHZ) 162 #define ADF41513_MAX_REF_FREQ_DOUBLER_HZ (225 * HZ_PER_MHZ) 163 164 #define ADF41513_MAX_PFD_FREQ_INT_N_UHZ (250ULL * MEGA * MICROHZ_PER_HZ) 165 #define ADF41513_MAX_PFD_FREQ_FRAC_N_UHZ (125ULL * MEGA * MICROHZ_PER_HZ) 166 #define ADF41513_MAX_FREQ_RESOLUTION_UHZ (100ULL * KILO * MICROHZ_PER_HZ) 167 168 #define ADF41513_MIN_INT_4_5 20 169 #define ADF41513_MAX_INT_4_5 511 170 #define ADF41513_MIN_INT_8_9 64 171 #define ADF41513_MAX_INT_8_9 1023 172 173 #define ADF41513_MIN_INT_FRAC_4_5 23 174 #define ADF41513_MIN_INT_FRAC_8_9 75 175 176 #define ADF41513_MIN_R_CNT 1 177 #define ADF41513_MAX_R_CNT 32 178 179 #define ADF41513_MIN_R_SET 1800 180 #define ADF41513_DEFAULT_R_SET 2700 181 #define ADF41513_MAX_R_SET 10000 182 183 #define ADF41513_MIN_CP_VOLTAGE_mV 810 184 #define ADF41513_DEFAULT_CP_VOLTAGE_mV 6480 185 #define ADF41513_MAX_CP_VOLTAGE_mV 12960 186 187 #define ADF41513_MIN_CP_CURRENT_uA 81 188 #define ADF41513_MAX_CP_CURRENT_uA 7200 189 190 #define ADF41513_LD_COUNT_FAST_MIN 2 191 #define ADF41513_LD_COUNT_FAST_LIMIT 64 192 #define ADF41513_LD_COUNT_MIN 64 193 #define ADF41513_LD_COUNT_MAX 8192 194 195 #define ADF41513_FIXED_MODULUS BIT(25) 196 #define ADF41513_MAX_MOD2 (BIT(24) - 1) 197 #define ADF41513_MAX_PHASE_VAL (BIT(12) - 1) 198 #define ADF41513_MAX_CLK_DIVIDER (BIT(12) - 1) 199 200 #define ADF41513_HZ_DECIMAL_SCALE 6 201 #define ADF41513_PS_BIAS_INIT 0x2 202 #define ADF41513_MAX_PHASE_MICRORAD ((2 * 314159265UL) / 100) 203 204 enum adf41513_pll_mode { 205 ADF41513_MODE_INVALID, 206 ADF41513_MODE_INTEGER_N, 207 ADF41513_MODE_FIXED_MODULUS, 208 ADF41513_MODE_VARIABLE_MODULUS, 209 }; 210 211 struct adf41513_chip_info { 212 const char *name; 213 u64 max_rf_freq_hz; 214 bool has_prescaler_8_9; 215 }; 216 217 struct adf41513_data { 218 u64 power_up_frequency_hz; 219 u64 freq_resolution_uhz; 220 u32 charge_pump_voltage_mv; 221 u32 lock_detect_count; 222 223 u8 ref_div_factor; 224 bool ref_doubler_en; 225 bool ref_div2_en; 226 bool phase_detector_polarity; 227 228 bool logic_lvl_1v8_en; 229 }; 230 231 struct adf41513_pll_settings { 232 enum adf41513_pll_mode mode; 233 234 /* reference path parameters */ 235 u8 r_counter; 236 u8 ref_doubler; 237 u8 ref_div2; 238 u8 prescaler; 239 240 /* frequency parameters */ 241 u64 target_frequency_uhz; 242 u64 actual_frequency_uhz; 243 u64 pfd_frequency_uhz; 244 245 /* pll parameters */ 246 u32 frac1; 247 u32 frac2; 248 u32 mod2; 249 u16 int_val; 250 }; 251 252 struct adf41513_state { 253 const struct adf41513_chip_info *chip_info; 254 struct spi_device *spi; 255 struct gpio_desc *lock_detect; 256 struct clk *ref_clk; 257 u32 ref_freq_hz; 258 259 /* 260 * Lock for accessing device registers. Some operations require 261 * multiple consecutive R/W operations, during which the device 262 * shouldn't be interrupted. The buffers are also shared across 263 * all operations so need to be protected on stand alone reads and 264 * writes. 265 */ 266 struct mutex lock; 267 268 /* Cached register values */ 269 u32 regs[ADF41513_REG_NUM]; 270 u32 regs_hw[ADF41513_REG_NUM]; 271 272 struct adf41513_data data; 273 struct adf41513_pll_settings settings; 274 275 bool powerdown; 276 }; 277 278 static const char * const adf41513_power_supplies[] = { 279 "avdd1", "avdd2", "avdd3", "avdd4", "avdd5", "vp", 280 }; 281 282 static int adf41513_sync_config(struct adf41513_state *st, u16 sync_mask) 283 { 284 __be32 d32; 285 int ret; 286 287 /* write registers in reverse order (R13 to R0)*/ 288 for (int i = ADF41513_REG13; i >= ADF41513_REG0; i--) { 289 if (st->regs_hw[i] == st->regs[i] && !(sync_mask & BIT(i))) 290 continue; 291 292 d32 = cpu_to_be32(st->regs[i] | i); 293 ret = spi_write_then_read(st->spi, &d32, sizeof(d32), NULL, 0); 294 if (ret < 0) 295 return ret; 296 st->regs_hw[i] = st->regs[i]; 297 dev_dbg(&st->spi->dev, "REG%d <= 0x%08X\n", i, st->regs[i] | i); 298 } 299 300 return 0; 301 } 302 303 static u64 adf41513_pll_get_rate(struct adf41513_state *st) 304 { 305 struct adf41513_pll_settings *cfg = &st->settings; 306 307 if (cfg->mode != ADF41513_MODE_INVALID) 308 return cfg->actual_frequency_uhz; 309 310 /* get pll settings from regs_hw */ 311 cfg->int_val = FIELD_GET(ADF41513_REG0_INT_MSK, st->regs_hw[ADF41513_REG0]); 312 cfg->frac1 = FIELD_GET(ADF41513_REG1_FRAC1_MSK, st->regs_hw[ADF41513_REG1]); 313 cfg->frac2 = FIELD_GET(ADF41513_REG3_FRAC2_MSK, st->regs_hw[ADF41513_REG3]); 314 cfg->mod2 = FIELD_GET(ADF41513_REG4_MOD2_MSK, st->regs_hw[ADF41513_REG4]); 315 cfg->r_counter = FIELD_GET(ADF41513_REG5_R_CNT_MSK, st->regs_hw[ADF41513_REG5]); 316 cfg->ref_doubler = FIELD_GET(ADF41513_REG5_REF_DOUBLER_MSK, st->regs_hw[ADF41513_REG5]); 317 cfg->ref_div2 = FIELD_GET(ADF41513_REG5_RDIV2_MSK, st->regs_hw[ADF41513_REG5]); 318 cfg->prescaler = FIELD_GET(ADF41513_REG5_PRESCALER_MSK, st->regs_hw[ADF41513_REG5]); 319 320 if (!cfg->mod2) 321 cfg->mod2 = 1; 322 if (!cfg->r_counter) 323 cfg->r_counter = ADF41513_MAX_R_CNT; 324 325 /* calculate pfd frequency */ 326 cfg->pfd_frequency_uhz = (u64)st->ref_freq_hz * MICRO; 327 if (cfg->ref_doubler) 328 cfg->pfd_frequency_uhz <<= 1; 329 if (cfg->ref_div2) 330 cfg->pfd_frequency_uhz >>= 1; 331 cfg->pfd_frequency_uhz = div_u64(cfg->pfd_frequency_uhz, cfg->r_counter); 332 cfg->actual_frequency_uhz = (u64)cfg->int_val * cfg->pfd_frequency_uhz; 333 334 /* check if int mode is selected */ 335 if (FIELD_GET(ADF41513_REG6_INT_MODE_MSK, st->regs_hw[ADF41513_REG6])) { 336 cfg->mode = ADF41513_MODE_INTEGER_N; 337 } else { 338 cfg->actual_frequency_uhz += mul_u64_u32_div(cfg->pfd_frequency_uhz, 339 cfg->frac1, 340 ADF41513_FIXED_MODULUS); 341 342 /* check if variable modulus is selected */ 343 if (FIELD_GET(ADF41513_REG0_VAR_MOD_MSK, st->regs_hw[ADF41513_REG0])) { 344 cfg->actual_frequency_uhz += 345 mul_u64_u64_div_u64(cfg->frac2, 346 cfg->pfd_frequency_uhz, 347 (u64)cfg->mod2 * ADF41513_FIXED_MODULUS); 348 349 cfg->mode = ADF41513_MODE_VARIABLE_MODULUS; 350 } else { 351 /* LSB_P1 offset */ 352 if (!FIELD_GET(ADF41513_REG5_LSB_P1_MSK, st->regs_hw[ADF41513_REG5])) 353 cfg->actual_frequency_uhz += 354 div_u64(cfg->pfd_frequency_uhz, 355 2 * ADF41513_FIXED_MODULUS); 356 cfg->mode = ADF41513_MODE_FIXED_MODULUS; 357 } 358 } 359 360 cfg->target_frequency_uhz = cfg->actual_frequency_uhz; 361 362 return cfg->actual_frequency_uhz; 363 } 364 365 static int adf41513_calc_pfd_frequency(struct adf41513_state *st, 366 struct adf41513_pll_settings *result, 367 u64 fpfd_limit_uhz) 368 { 369 result->ref_div2 = st->data.ref_div2_en; 370 result->ref_doubler = st->data.ref_doubler_en; 371 result->r_counter = st->data.ref_div_factor - 1; 372 373 do { 374 result->r_counter++; 375 /* f_PFD = REF_IN × ((1 + D)/(R × (1 + T))) */ 376 result->pfd_frequency_uhz = (u64)st->ref_freq_hz * MICRO; 377 if (result->ref_doubler) 378 result->pfd_frequency_uhz <<= 1; 379 if (result->ref_div2) 380 result->pfd_frequency_uhz >>= 1; 381 result->pfd_frequency_uhz = div_u64(result->pfd_frequency_uhz, 382 result->r_counter); 383 } while (result->pfd_frequency_uhz > fpfd_limit_uhz); 384 385 if (result->r_counter > ADF41513_MAX_R_CNT) { 386 dev_err(&st->spi->dev, "Cannot optimize PFD frequency\n"); 387 return -ERANGE; 388 } 389 390 return 0; 391 } 392 393 static int adf41513_calc_integer_n(struct adf41513_state *st, 394 struct adf41513_pll_settings *result) 395 { 396 u32 max_int = st->chip_info->has_prescaler_8_9 ? 397 ADF41513_MAX_INT_8_9 : ADF41513_MAX_INT_4_5; 398 u64 freq_error_uhz; 399 u32 int_val = div64_u64_rem(result->target_frequency_uhz, result->pfd_frequency_uhz, 400 &freq_error_uhz); 401 402 /* check if freq error is within a tolerance of 1/2 resolution */ 403 if (freq_error_uhz > (result->pfd_frequency_uhz >> 1) && int_val < max_int) { 404 int_val++; 405 freq_error_uhz = result->pfd_frequency_uhz - freq_error_uhz; 406 } 407 408 if (freq_error_uhz > st->data.freq_resolution_uhz) 409 return -ERANGE; 410 411 /* set prescaler */ 412 if (st->chip_info->has_prescaler_8_9 && int_val >= ADF41513_MIN_INT_8_9 && 413 int_val <= ADF41513_MAX_INT_8_9) 414 result->prescaler = 1; 415 else if (int_val >= ADF41513_MIN_INT_4_5 && int_val <= ADF41513_MAX_INT_4_5) 416 result->prescaler = 0; 417 else 418 return -ERANGE; 419 420 result->actual_frequency_uhz = (u64)int_val * result->pfd_frequency_uhz; 421 result->mode = ADF41513_MODE_INTEGER_N; 422 result->int_val = int_val; 423 result->frac1 = 0; 424 result->frac2 = 0; 425 result->mod2 = 0; 426 427 return 0; 428 } 429 430 static int adf41513_calc_fixed_mod(struct adf41513_state *st, 431 struct adf41513_pll_settings *result) 432 { 433 u64 resolution_uhz = div_u64(result->pfd_frequency_uhz, ADF41513_FIXED_MODULUS); 434 u64 target_frequency_uhz = result->target_frequency_uhz; 435 u64 freq_error_uhz; 436 u32 int_val, frac1; 437 bool lsb_p1_offset = !FIELD_GET(ADF41513_REG5_LSB_P1_MSK, st->regs[ADF41513_REG5]); 438 439 /* LSB_P1 adds a frequency offset of f_pfd/2^26 */ 440 if (lsb_p1_offset) 441 target_frequency_uhz -= resolution_uhz >> 1; 442 443 int_val = div64_u64_rem(target_frequency_uhz, result->pfd_frequency_uhz, 444 &freq_error_uhz); 445 446 if (st->chip_info->has_prescaler_8_9 && int_val >= ADF41513_MIN_INT_FRAC_8_9 && 447 int_val <= ADF41513_MAX_INT_8_9) 448 result->prescaler = 1; 449 else if (int_val >= ADF41513_MIN_INT_FRAC_4_5 && int_val <= ADF41513_MAX_INT_4_5) 450 result->prescaler = 0; 451 else 452 return -ERANGE; 453 454 /* compute frac1 and fixed modulus error */ 455 frac1 = mul_u64_u64_div_u64(freq_error_uhz, ADF41513_FIXED_MODULUS, 456 result->pfd_frequency_uhz); 457 freq_error_uhz -= mul_u64_u32_div(result->pfd_frequency_uhz, frac1, 458 ADF41513_FIXED_MODULUS); 459 460 /* check if freq error is within a tolerance of 1/2 resolution */ 461 if (freq_error_uhz > (resolution_uhz >> 1) && frac1 < (ADF41513_FIXED_MODULUS - 1)) { 462 frac1++; 463 freq_error_uhz = freq_error_uhz < resolution_uhz ? 464 resolution_uhz - freq_error_uhz : 0; 465 } 466 467 if (freq_error_uhz > st->data.freq_resolution_uhz) 468 return -ERANGE; 469 470 /* integer part */ 471 result->actual_frequency_uhz = (u64)int_val * result->pfd_frequency_uhz; 472 /* fractional part */ 473 if (lsb_p1_offset) 474 result->actual_frequency_uhz += (resolution_uhz >> 1); 475 result->actual_frequency_uhz += mul_u64_u32_div(result->pfd_frequency_uhz, frac1, 476 ADF41513_FIXED_MODULUS); 477 result->mode = ADF41513_MODE_FIXED_MODULUS; 478 result->int_val = int_val; 479 result->frac1 = frac1; 480 result->frac2 = 0; 481 result->mod2 = 0; 482 483 return 0; 484 } 485 486 static int adf41513_calc_variable_mod(struct adf41513_state *st, 487 struct adf41513_pll_settings *result) 488 { 489 u64 freq_error_uhz, mod2; 490 u32 frac1, frac2; 491 u32 int_val = div64_u64_rem(result->target_frequency_uhz, 492 result->pfd_frequency_uhz, &freq_error_uhz); 493 494 if (st->chip_info->has_prescaler_8_9 && int_val >= ADF41513_MIN_INT_FRAC_8_9 && 495 int_val <= ADF41513_MAX_INT_8_9) 496 result->prescaler = 1; 497 else if (int_val >= ADF41513_MIN_INT_FRAC_4_5 && int_val <= ADF41513_MAX_INT_4_5) 498 result->prescaler = 0; 499 else 500 return -ERANGE; 501 502 /* calculate required mod2 based on target resolution / 2 */ 503 mod2 = DIV64_U64_ROUND_CLOSEST(result->pfd_frequency_uhz << 1, 504 st->data.freq_resolution_uhz * ADF41513_FIXED_MODULUS); 505 /* ensure mod2 is at least 2 for meaningful operation */ 506 mod2 = clamp(mod2, 2, ADF41513_MAX_MOD2); 507 508 /* calculate frac1 and frac2 */ 509 frac1 = mul_u64_u64_div_u64(freq_error_uhz, ADF41513_FIXED_MODULUS, 510 result->pfd_frequency_uhz); 511 frac2 = mul_u64_u64_div_u64(freq_error_uhz, mod2 * ADF41513_FIXED_MODULUS, 512 result->pfd_frequency_uhz) - mod2 * frac1; 513 514 /* integer part */ 515 result->actual_frequency_uhz = (u64)int_val * result->pfd_frequency_uhz; 516 /* fractional part */ 517 result->actual_frequency_uhz += mul_u64_u64_div_u64(mod2 * frac1 + frac2, 518 result->pfd_frequency_uhz, 519 mod2 * ADF41513_FIXED_MODULUS); 520 result->mode = ADF41513_MODE_VARIABLE_MODULUS; 521 result->int_val = int_val; 522 result->frac1 = frac1; 523 result->frac2 = frac2; 524 result->mod2 = mod2; 525 526 return 0; 527 } 528 529 static int adf41513_calc_pll_settings(struct adf41513_state *st, 530 struct adf41513_pll_settings *result, 531 u64 rf_out_uhz) 532 { 533 u64 max_rf_freq_uhz = st->chip_info->max_rf_freq_hz * MICRO; 534 u64 min_rf_freq_uhz = ADF41513_MIN_RF_FREQ_HZ * MICRO; 535 u64 pfd_freq_limit_uhz; 536 int ret; 537 538 if (rf_out_uhz < min_rf_freq_uhz || rf_out_uhz > max_rf_freq_uhz) { 539 dev_err(&st->spi->dev, "RF frequency %llu uHz out of range [%llu, %llu] uHz\n", 540 rf_out_uhz, min_rf_freq_uhz, max_rf_freq_uhz); 541 return -EINVAL; 542 } 543 544 result->target_frequency_uhz = rf_out_uhz; 545 546 /* try integer-N first (best phase noise performance) */ 547 pfd_freq_limit_uhz = min(div_u64(rf_out_uhz, ADF41513_MIN_INT_4_5), 548 ADF41513_MAX_PFD_FREQ_INT_N_UHZ); 549 ret = adf41513_calc_pfd_frequency(st, result, pfd_freq_limit_uhz); 550 if (ret) 551 return ret; 552 553 if (adf41513_calc_integer_n(st, result) == 0) 554 return 0; 555 556 /* try fractional-N: recompute pfd frequency if necessary */ 557 pfd_freq_limit_uhz = min(div_u64(rf_out_uhz, ADF41513_MIN_INT_FRAC_4_5), 558 ADF41513_MAX_PFD_FREQ_FRAC_N_UHZ); 559 if (pfd_freq_limit_uhz < result->pfd_frequency_uhz) { 560 ret = adf41513_calc_pfd_frequency(st, result, pfd_freq_limit_uhz); 561 if (ret) 562 return ret; 563 } 564 565 /* fixed-modulus attempt */ 566 if (adf41513_calc_fixed_mod(st, result) == 0) 567 return 0; 568 569 /* variable-modulus attempt */ 570 ret = adf41513_calc_variable_mod(st, result); 571 if (ret) { 572 dev_err(&st->spi->dev, 573 "no valid PLL configuration found for %llu uHz\n", 574 rf_out_uhz); 575 return ret; 576 } 577 578 return 0; 579 } 580 581 static int adf41513_set_frequency(struct adf41513_state *st, u64 freq_uhz, u16 sync_mask) 582 { 583 struct adf41513_pll_settings result; 584 int ret; 585 586 ret = adf41513_calc_pll_settings(st, &result, freq_uhz); 587 if (ret < 0) 588 return ret; 589 590 /* apply computed results to pll settings */ 591 st->settings = result; 592 593 dev_dbg(&st->spi->dev, 594 "%s mode: int=%u, frac1=%u, frac2=%u, mod2=%u, fpdf=%llu Hz, prescaler=%s\n", 595 (result.mode == ADF41513_MODE_INTEGER_N) ? "integer-n" : 596 (result.mode == ADF41513_MODE_FIXED_MODULUS) ? "fixed-modulus" : "variable-modulus", 597 result.int_val, result.frac1, result.frac2, result.mod2, 598 div64_u64(result.pfd_frequency_uhz, MICRO), 599 result.prescaler ? "8/9" : "4/5"); 600 601 st->regs[ADF41513_REG0] = FIELD_PREP(ADF41513_REG0_INT_MSK, 602 st->settings.int_val); 603 if (st->settings.mode == ADF41513_MODE_VARIABLE_MODULUS) 604 st->regs[ADF41513_REG0] |= ADF41513_REG0_VAR_MOD_MSK; 605 606 st->regs[ADF41513_REG1] = FIELD_PREP(ADF41513_REG1_FRAC1_MSK, 607 st->settings.frac1); 608 if (st->settings.mode != ADF41513_MODE_INTEGER_N) 609 st->regs[ADF41513_REG1] |= ADF41513_REG1_DITHER2_MSK; 610 611 st->regs[ADF41513_REG3] = FIELD_PREP(ADF41513_REG3_FRAC2_MSK, 612 st->settings.frac2); 613 FIELD_MODIFY(ADF41513_REG4_MOD2_MSK, &st->regs[ADF41513_REG4], 614 st->settings.mod2); 615 FIELD_MODIFY(ADF41513_REG5_R_CNT_MSK, &st->regs[ADF41513_REG5], 616 st->settings.r_counter % ADF41513_MAX_R_CNT); 617 FIELD_MODIFY(ADF41513_REG5_REF_DOUBLER_MSK, &st->regs[ADF41513_REG5], 618 st->settings.ref_doubler); 619 FIELD_MODIFY(ADF41513_REG5_RDIV2_MSK, &st->regs[ADF41513_REG5], 620 st->settings.ref_div2); 621 FIELD_MODIFY(ADF41513_REG5_PRESCALER_MSK, &st->regs[ADF41513_REG5], 622 st->settings.prescaler); 623 624 if (st->settings.mode == ADF41513_MODE_INTEGER_N) { 625 st->regs[ADF41513_REG6] |= ADF41513_REG6_INT_MODE_MSK; 626 st->regs[ADF41513_REG6] &= ~ADF41513_REG6_BLEED_ENABLE_MSK; 627 } else { 628 st->regs[ADF41513_REG6] &= ~ADF41513_REG6_INT_MODE_MSK; 629 st->regs[ADF41513_REG6] |= ADF41513_REG6_BLEED_ENABLE_MSK; 630 } 631 632 return adf41513_sync_config(st, sync_mask | ADF41513_SYNC_REG0); 633 } 634 635 static int adf41513_suspend(struct adf41513_state *st) 636 { 637 st->regs[ADF41513_REG6] |= FIELD_PREP(ADF41513_REG6_POWER_DOWN_MSK, 1); 638 return adf41513_sync_config(st, ADF41513_SYNC_DIFF); 639 } 640 641 static int adf41513_resume(struct adf41513_state *st) 642 { 643 st->regs[ADF41513_REG6] &= ~ADF41513_REG6_POWER_DOWN_MSK; 644 return adf41513_sync_config(st, ADF41513_SYNC_ALL); 645 } 646 647 static ssize_t adf41513_read_resolution(struct iio_dev *indio_dev, 648 uintptr_t private, 649 const struct iio_chan_spec *chan, 650 char *buf) 651 { 652 struct adf41513_state *st = iio_priv(indio_dev); 653 int vals[2]; 654 655 guard(mutex)(&st->lock); 656 657 iio_val_s64_decompose(st->data.freq_resolution_uhz, &vals[0], &vals[1]); 658 return iio_format_value(buf, IIO_VAL_DECIMAL64_MICRO, ARRAY_SIZE(vals), vals); 659 } 660 661 static ssize_t adf41513_read_powerdown(struct iio_dev *indio_dev, 662 uintptr_t private, 663 const struct iio_chan_spec *chan, 664 char *buf) 665 { 666 struct adf41513_state *st = iio_priv(indio_dev); 667 u32 val; 668 669 guard(mutex)(&st->lock); 670 671 val = FIELD_GET(ADF41513_REG6_POWER_DOWN_MSK, st->regs_hw[ADF41513_REG6]); 672 return sysfs_emit(buf, "%u\n", val); 673 } 674 675 static ssize_t adf41513_write_resolution(struct iio_dev *indio_dev, 676 uintptr_t private, 677 const struct iio_chan_spec *chan, 678 const char *buf, size_t len) 679 { 680 struct adf41513_state *st = iio_priv(indio_dev); 681 u64 freq_uhz; 682 int ret; 683 684 ret = kstrtoudec64(buf, ADF41513_HZ_DECIMAL_SCALE, &freq_uhz); 685 if (ret) 686 return ret; 687 688 if (freq_uhz == 0 || freq_uhz > ADF41513_MAX_FREQ_RESOLUTION_UHZ) 689 return -EINVAL; 690 691 guard(mutex)(&st->lock); 692 693 st->data.freq_resolution_uhz = freq_uhz; 694 return len; 695 } 696 697 static ssize_t adf41513_write_powerdown(struct iio_dev *indio_dev, 698 uintptr_t private, 699 const struct iio_chan_spec *chan, 700 const char *buf, size_t len) 701 { 702 struct adf41513_state *st = iio_priv(indio_dev); 703 bool val; 704 int ret; 705 706 ret = kstrtobool(buf, &val); 707 if (ret) 708 return ret; 709 710 guard(mutex)(&st->lock); 711 712 if (val) 713 ret = adf41513_suspend(st); 714 else 715 ret = adf41513_resume(st); 716 if (ret) 717 return ret; 718 719 st->powerdown = val; 720 return len; 721 } 722 723 static const struct iio_chan_spec_ext_info adf41513_ext_info[] = { 724 { 725 .name = "frequency_resolution", 726 .read = adf41513_read_resolution, 727 .write = adf41513_write_resolution, 728 .shared = IIO_SEPARATE, 729 }, 730 { 731 .name = "powerdown", 732 .read = adf41513_read_powerdown, 733 .write = adf41513_write_powerdown, 734 .shared = IIO_SEPARATE, 735 }, 736 { } 737 }; 738 739 static const struct iio_chan_spec adf41513_chan = { 740 .type = IIO_ALTVOLTAGE, 741 .indexed = 1, 742 .output = 1, 743 .channel = 0, 744 .info_mask_separate = BIT(IIO_CHAN_INFO_FREQUENCY) | 745 BIT(IIO_CHAN_INFO_PHASE), 746 .ext_info = adf41513_ext_info, 747 }; 748 749 static int adf41513_read_raw(struct iio_dev *indio_dev, 750 struct iio_chan_spec const *chan, 751 int *val, int *val2, long info) 752 { 753 struct adf41513_state *st = iio_priv(indio_dev); 754 u64 tmp64; 755 756 guard(mutex)(&st->lock); 757 758 switch (info) { 759 case IIO_CHAN_INFO_FREQUENCY: 760 if (st->lock_detect && 761 !gpiod_get_value_cansleep(st->lock_detect)) { 762 dev_dbg(&st->spi->dev, "PLL un-locked\n"); 763 return -EBUSY; 764 } 765 tmp64 = adf41513_pll_get_rate(st); 766 iio_val_s64_decompose(tmp64, val, val2); 767 return IIO_VAL_DECIMAL64_MICRO; 768 case IIO_CHAN_INFO_PHASE: 769 tmp64 = FIELD_GET(ADF41513_REG2_PHASE_VAL_MSK, 770 st->regs_hw[ADF41513_REG2]); 771 tmp64 = (tmp64 * ADF41513_MAX_PHASE_MICRORAD) >> 12; 772 iio_val_s64_decompose(tmp64, val, val2); 773 return IIO_VAL_DECIMAL64_MICRO; 774 default: 775 return -EINVAL; 776 } 777 } 778 779 static int adf41513_write_raw(struct iio_dev *indio_dev, 780 struct iio_chan_spec const *chan, 781 int val, int val2, long info) 782 { 783 struct adf41513_state *st = iio_priv(indio_dev); 784 u64 tmp64 = iio_val_s64_compose(val, val2); 785 u16 phase_val; 786 int ret; 787 788 guard(mutex)(&st->lock); 789 790 switch (info) { 791 case IIO_CHAN_INFO_FREQUENCY: 792 return adf41513_set_frequency(st, tmp64, ADF41513_SYNC_DIFF); 793 case IIO_CHAN_INFO_PHASE: 794 if (tmp64 >= ADF41513_MAX_PHASE_MICRORAD) 795 return -EINVAL; 796 797 phase_val = DIV_U64_ROUND_CLOSEST(tmp64 << 12, 798 ADF41513_MAX_PHASE_MICRORAD); 799 phase_val = min(phase_val, ADF41513_MAX_PHASE_VAL); 800 st->regs[ADF41513_REG2] |= ADF41513_REG2_PHASE_ADJ_MSK; 801 FIELD_MODIFY(ADF41513_REG2_PHASE_VAL_MSK, 802 &st->regs[ADF41513_REG2], phase_val); 803 ret = adf41513_sync_config(st, ADF41513_SYNC_REG0); 804 /* clear phase adjust for the next sync */ 805 st->regs[ADF41513_REG2] &= ~ADF41513_REG2_PHASE_ADJ_MSK; 806 return ret; 807 default: 808 return -EINVAL; 809 } 810 } 811 812 static int adf41513_write_raw_get_fmt(struct iio_dev *indio_dev, 813 struct iio_chan_spec const *chan, 814 long mask) 815 { 816 switch (mask) { 817 case IIO_CHAN_INFO_FREQUENCY: 818 case IIO_CHAN_INFO_PHASE: 819 return IIO_VAL_DECIMAL64_MICRO; 820 default: 821 return -EINVAL; 822 } 823 } 824 825 static int adf41513_reg_access(struct iio_dev *indio_dev, unsigned int reg, 826 unsigned int writeval, unsigned int *readval) 827 { 828 struct adf41513_state *st = iio_priv(indio_dev); 829 830 if (reg > ADF41513_REG13) 831 return -EINVAL; 832 833 guard(mutex)(&st->lock); 834 835 if (!readval) { 836 if (reg <= ADF41513_REG6) 837 st->settings.mode = ADF41513_MODE_INVALID; 838 st->regs[reg] = writeval & ~0xF; /* Clear control bits */ 839 return adf41513_sync_config(st, BIT(reg)); 840 } 841 842 *readval = st->regs_hw[reg]; 843 return 0; 844 } 845 846 static const struct iio_info adf41513_info = { 847 .read_raw = adf41513_read_raw, 848 .write_raw = adf41513_write_raw, 849 .write_raw_get_fmt = adf41513_write_raw_get_fmt, 850 .debugfs_reg_access = &adf41513_reg_access, 851 }; 852 853 static int adf41513_parse_fw(struct adf41513_state *st) 854 { 855 struct device *dev = &st->spi->dev; 856 u32 tmp, cp_resistance, cp_current; 857 int ret; 858 859 tmp = ADF41510_MAX_RF_FREQ_HZ / MEGA; 860 device_property_read_u32(dev, "adi,power-up-frequency-mhz", &tmp); 861 st->data.power_up_frequency_hz = (u64)tmp * MEGA; 862 if (st->data.power_up_frequency_hz < ADF41513_MIN_RF_FREQ_HZ || 863 st->data.power_up_frequency_hz > st->chip_info->max_rf_freq_hz) 864 return dev_err_probe(dev, -ERANGE, 865 "power-up frequency %llu Hz out of range\n", 866 st->data.power_up_frequency_hz); 867 868 tmp = ADF41513_MIN_R_CNT; 869 device_property_read_u32(dev, "adi,reference-div-factor", &tmp); 870 if (tmp < ADF41513_MIN_R_CNT || tmp > ADF41513_MAX_R_CNT) 871 return dev_err_probe(dev, -ERANGE, 872 "invalid reference div factor %u\n", tmp); 873 st->data.ref_div_factor = tmp; 874 875 st->data.ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable"); 876 st->data.ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable"); 877 878 if (st->data.ref_doubler_en && 879 st->ref_freq_hz > ADF41513_MAX_REF_FREQ_DOUBLER_HZ) { 880 return dev_err_probe(dev, -ERANGE, 881 "Ref frequency not supported with doubler enabled\n"); 882 } 883 884 cp_resistance = ADF41513_DEFAULT_R_SET; 885 device_property_read_u32(dev, "adi,charge-pump-resistor-ohms", &cp_resistance); 886 if (cp_resistance < ADF41513_MIN_R_SET || cp_resistance > ADF41513_MAX_R_SET) 887 return dev_err_probe(dev, -ERANGE, "R_SET %u Ohms out of range\n", cp_resistance); 888 889 st->data.charge_pump_voltage_mv = ADF41513_DEFAULT_CP_VOLTAGE_mV; 890 ret = device_property_read_u32(dev, "adi,charge-pump-current-microamp", &cp_current); 891 if (!ret) { 892 if (cp_current < ADF41513_MIN_CP_CURRENT_uA || 893 cp_current > ADF41513_MAX_CP_CURRENT_uA) 894 return dev_err_probe(dev, -ERANGE, 895 "I_CP %u uA out of range\n", cp_current); 896 897 tmp = DIV_ROUND_CLOSEST(cp_current * cp_resistance, MILLI); 898 if (tmp < ADF41513_MIN_CP_VOLTAGE_mV || tmp > ADF41513_MAX_CP_VOLTAGE_mV) 899 return dev_err_probe(dev, -ERANGE, "I_CP %u uA (%u Ohms) out of range\n", 900 cp_current, cp_resistance); 901 st->data.charge_pump_voltage_mv = tmp; 902 } 903 904 st->data.phase_detector_polarity = 905 device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable"); 906 907 st->data.logic_lvl_1v8_en = device_property_read_bool(dev, "adi,logic-level-1v8-enable"); 908 909 tmp = ADF41513_LD_COUNT_MIN; 910 device_property_read_u32(dev, "adi,lock-detector-count", &tmp); 911 if (tmp < ADF41513_LD_COUNT_FAST_MIN || tmp > ADF41513_LD_COUNT_MAX || 912 !is_power_of_2(tmp)) 913 return dev_err_probe(dev, -ERANGE, 914 "invalid lock detect count: %u\n", tmp); 915 st->data.lock_detect_count = tmp; 916 917 st->data.freq_resolution_uhz = MICROHZ_PER_HZ; 918 919 return 0; 920 } 921 922 static void adf41513_chip_disable(void *data) 923 { 924 gpiod_set_value_cansleep(data, 0); 925 } 926 927 static void adf41513_close(void *data) 928 { 929 adf41513_suspend(data); 930 } 931 932 static int adf41513_setup(struct device *dev, struct adf41513_state *st) 933 { 934 u32 tmp; 935 int ret; 936 937 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); 938 939 /* assuming DLD pin is used for lock detection */ 940 st->regs[ADF41513_REG5] = FIELD_PREP(ADF41513_REG5_DLD_MODES_MSK, 941 ADF41513_DLD_DIG_LD); 942 943 tmp = DIV_ROUND_CLOSEST(st->data.charge_pump_voltage_mv, ADF41513_MIN_CP_VOLTAGE_mV); 944 st->regs[ADF41513_REG5] |= FIELD_PREP(ADF41513_REG5_CP_CURRENT_MSK, tmp - 1); 945 946 st->regs[ADF41513_REG6] = ADF41513_REG6_ABP_MSK | 947 ADF41513_REG6_LOL_ENABLE_MSK | 948 ADF41513_REG6_SD_RESET_MSK; 949 if (st->data.phase_detector_polarity) 950 st->regs[ADF41513_REG6] |= ADF41513_REG6_PD_POLARITY_MSK; 951 952 st->regs[ADF41513_REG7] = FIELD_PREP(ADF41513_REG7_PS_BIAS_MSK, 953 ADF41513_PS_BIAS_INIT); 954 tmp = ilog2(st->data.lock_detect_count); 955 if (st->data.lock_detect_count < ADF41513_LD_COUNT_FAST_LIMIT) { 956 tmp -= const_ilog2(ADF41513_LD_COUNT_FAST_MIN); 957 st->regs[ADF41513_REG7] |= ADF41513_REG7_LD_CLK_SEL_MSK; 958 } else { 959 tmp -= const_ilog2(ADF41513_LD_COUNT_MIN); 960 } 961 st->regs[ADF41513_REG7] |= FIELD_PREP(ADF41513_REG7_LD_COUNT_MSK, tmp); 962 963 st->regs[ADF41513_REG11] = ADF41513_REG11_POWER_DOWN_SEL_MSK; 964 st->regs[ADF41513_REG12] = FIELD_PREP(ADF41513_REG12_LOGIC_LEVEL_MSK, 965 st->data.logic_lvl_1v8_en ? 0 : 1); 966 967 /* perform initialization sequence with power-up frequency */ 968 ret = adf41513_set_frequency(st, st->data.power_up_frequency_hz * MICRO, 969 ADF41513_SYNC_ALL); 970 if (ret) 971 return ret; 972 973 return devm_add_action_or_reset(dev, adf41513_close, st); 974 } 975 976 static int adf41513_pm_suspend(struct device *dev) 977 { 978 struct adf41513_state *st = dev_get_drvdata(dev); 979 980 guard(mutex)(&st->lock); 981 return adf41513_suspend(st); 982 } 983 984 static int adf41513_pm_resume(struct device *dev) 985 { 986 struct adf41513_state *st = dev_get_drvdata(dev); 987 988 guard(mutex)(&st->lock); 989 if (st->powerdown) 990 return 0; /* nothing to do */ 991 992 return adf41513_resume(st); 993 } 994 995 static const struct adf41513_chip_info adf41510_chip_info = { 996 .name = "adf41510", 997 .max_rf_freq_hz = ADF41510_MAX_RF_FREQ_HZ, 998 .has_prescaler_8_9 = false, 999 }; 1000 1001 static const struct adf41513_chip_info adf41513_chip_info = { 1002 .name = "adf41513", 1003 .max_rf_freq_hz = ADF41513_MAX_RF_FREQ_HZ, 1004 .has_prescaler_8_9 = true, 1005 }; 1006 1007 static int adf41513_probe(struct spi_device *spi) 1008 { 1009 struct device *dev = &spi->dev; 1010 struct gpio_desc *chip_enable; 1011 struct iio_dev *indio_dev; 1012 struct adf41513_state *st; 1013 int ret; 1014 1015 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1016 if (!indio_dev) 1017 return -ENOMEM; 1018 1019 st = iio_priv(indio_dev); 1020 st->spi = spi; 1021 st->chip_info = spi_get_device_match_data(spi); 1022 if (!st->chip_info) 1023 return -EINVAL; 1024 1025 spi_set_drvdata(spi, st); 1026 1027 st->ref_clk = devm_clk_get_enabled(dev, NULL); 1028 if (IS_ERR(st->ref_clk)) 1029 return PTR_ERR(st->ref_clk); 1030 1031 st->ref_freq_hz = clk_get_rate(st->ref_clk); 1032 if (st->ref_freq_hz < ADF41513_MIN_REF_FREQ_HZ || 1033 st->ref_freq_hz > ADF41513_MAX_REF_FREQ_HZ) 1034 return dev_err_probe(dev, -ERANGE, 1035 "reference frequency %u Hz out of range\n", 1036 st->ref_freq_hz); 1037 1038 ret = adf41513_parse_fw(st); 1039 if (ret) 1040 return ret; 1041 1042 ret = devm_regulator_bulk_get_enable(dev, 1043 ARRAY_SIZE(adf41513_power_supplies), 1044 adf41513_power_supplies); 1045 if (ret) 1046 return dev_err_probe(dev, ret, 1047 "failed to get and enable regulators\n"); 1048 1049 st->lock_detect = devm_gpiod_get_optional(dev, "lock-detect", GPIOD_IN); 1050 if (IS_ERR(st->lock_detect)) 1051 return dev_err_probe(dev, PTR_ERR(st->lock_detect), 1052 "fail to request lock detect GPIO\n"); 1053 1054 chip_enable = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); 1055 if (IS_ERR(chip_enable)) 1056 return dev_err_probe(dev, PTR_ERR(chip_enable), 1057 "fail to request chip enable GPIO\n"); 1058 1059 ret = devm_add_action_or_reset(dev, adf41513_chip_disable, chip_enable); 1060 if (ret) 1061 return dev_err_probe(dev, ret, "Failed to add disable action\n"); 1062 1063 ret = devm_mutex_init(dev, &st->lock); 1064 if (ret) 1065 return ret; 1066 1067 indio_dev->name = st->chip_info->name; 1068 indio_dev->info = &adf41513_info; 1069 indio_dev->modes = INDIO_DIRECT_MODE; 1070 indio_dev->channels = &adf41513_chan; 1071 indio_dev->num_channels = 1; 1072 1073 ret = adf41513_setup(dev, st); 1074 if (ret < 0) 1075 return dev_err_probe(dev, ret, "failed to setup device\n"); 1076 1077 return devm_iio_device_register(dev, indio_dev); 1078 } 1079 1080 static const struct spi_device_id adf41513_id[] = { 1081 { .name = "adf41510", .driver_data = (kernel_ulong_t)&adf41510_chip_info }, 1082 { .name = "adf41513", .driver_data = (kernel_ulong_t)&adf41513_chip_info }, 1083 { } 1084 }; 1085 MODULE_DEVICE_TABLE(spi, adf41513_id); 1086 1087 static const struct of_device_id adf41513_of_match[] = { 1088 { .compatible = "adi,adf41510", .data = &adf41510_chip_info }, 1089 { .compatible = "adi,adf41513", .data = &adf41513_chip_info }, 1090 { } 1091 }; 1092 MODULE_DEVICE_TABLE(of, adf41513_of_match); 1093 1094 static DEFINE_SIMPLE_DEV_PM_OPS(adf41513_pm_ops, adf41513_pm_suspend, adf41513_pm_resume); 1095 1096 static struct spi_driver adf41513_driver = { 1097 .driver = { 1098 .name = "adf41513", 1099 .pm = pm_ptr(&adf41513_pm_ops), 1100 .of_match_table = adf41513_of_match, 1101 }, 1102 .probe = adf41513_probe, 1103 .id_table = adf41513_id, 1104 }; 1105 module_spi_driver(adf41513_driver); 1106 1107 MODULE_AUTHOR("Rodrigo Alencar <rodrigo.alencar@analog.com>"); 1108 MODULE_DESCRIPTION("Analog Devices ADF41513 PLL Frequency Synthesizer"); 1109 MODULE_LICENSE("GPL"); 1110