1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADF41513 SPI PLL Frequency Synthesizer driver 4 * 5 * Copyright 2026 Analog Devices Inc. 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/dev_printk.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/kstrtox.h> 18 #include <linux/log2.h> 19 #include <linux/math64.h> 20 #include <linux/minmax.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/pm.h> 25 #include <linux/property.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/spi/spi.h> 28 #include <linux/sysfs.h> 29 #include <linux/time64.h> 30 #include <linux/types.h> 31 #include <linux/units.h> 32 33 #include <linux/iio/iio.h> 34 35 /* Registers */ 36 #define ADF41513_REG0 0 37 #define ADF41513_REG1 1 38 #define ADF41513_REG2 2 39 #define ADF41513_REG3 3 40 #define ADF41513_REG4 4 41 #define ADF41513_REG5 5 42 #define ADF41513_REG6 6 43 #define ADF41513_REG7 7 44 #define ADF41513_REG8 8 45 #define ADF41513_REG9 9 46 #define ADF41513_REG10 10 47 #define ADF41513_REG11 11 48 #define ADF41513_REG12 12 49 #define ADF41513_REG13 13 50 #define ADF41513_REG_NUM 14 51 52 #define ADF41513_SYNC_REG0 BIT(ADF41513_REG0) 53 #define ADF41513_SYNC_REG1 BIT(ADF41513_REG1) 54 #define ADF41513_SYNC_REG2 BIT(ADF41513_REG2) 55 #define ADF41513_SYNC_REG3 BIT(ADF41513_REG3) 56 #define ADF41513_SYNC_REG4 BIT(ADF41513_REG4) 57 #define ADF41513_SYNC_REG5 BIT(ADF41513_REG5) 58 #define ADF41513_SYNC_REG6 BIT(ADF41513_REG6) 59 #define ADF41513_SYNC_REG7 BIT(ADF41513_REG7) 60 #define ADF41513_SYNC_REG9 BIT(ADF41513_REG9) 61 #define ADF41513_SYNC_REG11 BIT(ADF41513_REG11) 62 #define ADF41513_SYNC_REG12 BIT(ADF41513_REG12) 63 #define ADF41513_SYNC_REG13 BIT(ADF41513_REG13) 64 #define ADF41513_SYNC_DIFF 0 65 #define ADF41513_SYNC_ALL GENMASK(ADF41513_REG13, ADF41513_REG0) 66 67 /* REG0 Bit Definitions */ 68 #define ADF41513_REG0_CTRL_BITS_MSK GENMASK(3, 0) 69 #define ADF41513_REG0_INT_MSK GENMASK(19, 4) 70 #define ADF41513_REG0_VAR_MOD_MSK BIT(28) 71 72 /* REG1 Bit Definitions */ 73 #define ADF41513_REG1_FRAC1_MSK GENMASK(28, 4) 74 #define ADF41513_REG1_DITHER2_MSK BIT(31) 75 76 /* REG2 Bit Definitions */ 77 #define ADF41513_REG2_PHASE_VAL_MSK GENMASK(15, 4) 78 #define ADF41513_REG2_PHASE_ADJ_MSK BIT(31) 79 80 /* REG3 Bit Definitions */ 81 #define ADF41513_REG3_FRAC2_MSK GENMASK(27, 4) 82 83 /* REG4 Bit Definitions */ 84 #define ADF41513_REG4_MOD2_MSK GENMASK(27, 4) 85 86 /* REG5 Bit Definitions */ 87 #define ADF41513_REG5_CLK1_DIV_MSK GENMASK(15, 4) 88 #define ADF41513_REG5_R_CNT_MSK GENMASK(20, 16) 89 #define ADF41513_REG5_REF_DOUBLER_MSK BIT(21) 90 #define ADF41513_REG5_RDIV2_MSK BIT(22) 91 #define ADF41513_REG5_PRESCALER_MSK BIT(23) 92 #define ADF41513_REG5_LSB_P1_MSK BIT(24) 93 #define ADF41513_REG5_CP_CURRENT_MSK GENMASK(28, 25) 94 #define ADF41513_REG5_DLD_MODES_MSK GENMASK(31, 30) 95 96 /* REG6 Bit Definitions */ 97 #define ADF41513_REG6_COUNTER_RESET_MSK BIT(4) 98 #define ADF41513_REG6_CP_TRISTATE_MSK BIT(5) 99 #define ADF41513_REG6_POWER_DOWN_MSK BIT(6) 100 #define ADF41513_REG6_PD_POLARITY_MSK BIT(7) 101 #define ADF41513_REG6_LDP_MSK GENMASK(9, 8) 102 #define ADF41513_REG6_CP_TRISTATE_PD_ON_MSK BIT(16) 103 #define ADF41513_REG6_SD_RESET_MSK BIT(17) 104 #define ADF41513_REG6_LOL_ENABLE_MSK BIT(18) 105 #define ADF41513_REG6_ABP_MSK BIT(19) 106 #define ADF41513_REG6_INT_MODE_MSK BIT(20) 107 #define ADF41513_REG6_BLEED_ENABLE_MSK BIT(22) 108 #define ADF41513_REG6_BLEED_POLARITY_MSK BIT(23) 109 #define ADF41513_REG6_BLEED_CURRENT_MSK GENMASK(31, 24) 110 111 /* REG7 Bit Definitions */ 112 #define ADF41513_REG7_CLK2_DIV_MSK GENMASK(17, 6) 113 #define ADF41513_REG7_CLK_DIV_MODE_MSK GENMASK(19, 18) 114 #define ADF41513_REG7_PS_BIAS_MSK GENMASK(21, 20) 115 #define ADF41513_REG7_N_DELAY_MSK GENMASK(23, 22) 116 #define ADF41513_REG7_LD_CLK_SEL_MSK BIT(26) 117 #define ADF41513_REG7_LD_COUNT_MSK GENMASK(29, 27) 118 119 /* REG9 Bit Definitions */ 120 #define ADF41513_REG9_LD_BIAS_MSK GENMASK(31, 30) 121 122 /* REG11 Bit Definitions */ 123 #define ADF41513_REG11_POWER_DOWN_SEL_MSK BIT(31) 124 125 /* REG12 Bit Definitions */ 126 #define ADF41513_REG12_READBACK_SEL_MSK GENMASK(19, 14) 127 #define ADF41513_REG12_LE_SELECT_MSK BIT(20) 128 #define ADF41513_REG12_MASTER_RESET_MSK BIT(22) 129 #define ADF41513_REG12_LOGIC_LEVEL_MSK BIT(27) 130 #define ADF41513_REG12_MUXOUT_MSK GENMASK(31, 28) 131 132 /* MUXOUT Selection */ 133 #define ADF41513_MUXOUT_TRISTATE 0x0 134 #define ADF41513_MUXOUT_DVDD 0x1 135 #define ADF41513_MUXOUT_DGND 0x2 136 #define ADF41513_MUXOUT_R_DIV 0x3 137 #define ADF41513_MUXOUT_N_DIV 0x4 138 #define ADF41513_MUXOUT_DIG_LD 0x6 139 #define ADF41513_MUXOUT_SDO 0x7 140 #define ADF41513_MUXOUT_READBACK 0x8 141 #define ADF41513_MUXOUT_CLK1_DIV 0xA 142 #define ADF41513_MUXOUT_R_DIV2 0xD 143 #define ADF41513_MUXOUT_N_DIV2 0xE 144 145 /* DLD Mode Selection */ 146 #define ADF41513_DLD_TRISTATE 0x0 147 #define ADF41513_DLD_DIG_LD 0x1 148 #define ADF41513_DLD_LOW 0x2 149 #define ADF41513_DLD_HIGH 0x3 150 151 /* Prescaler Selection */ 152 #define ADF41513_PRESCALER_4_5 0 153 #define ADF41513_PRESCALER_8_9 1 154 #define ADF41513_PRESCALER_AUTO 2 155 156 /* CLK Divider mode */ 157 #define ADF41513_CLK_DIV_MODE_OFF 0 158 #define ADF41513_CLK_DIV_MODE_PHASE_RESYNC 2 159 160 /* Specifications */ 161 #define ADF41510_MAX_RF_FREQ_HZ (10ULL * HZ_PER_GHZ) 162 #define ADF41513_MIN_RF_FREQ_HZ (1ULL * HZ_PER_GHZ) 163 #define ADF41513_MAX_RF_FREQ_HZ (26500ULL * HZ_PER_MHZ) 164 165 #define ADF41513_MIN_REF_FREQ_HZ (10 * HZ_PER_MHZ) 166 #define ADF41513_MAX_REF_FREQ_HZ (800 * HZ_PER_MHZ) 167 #define ADF41513_MAX_REF_FREQ_DOUBLER_HZ (225 * HZ_PER_MHZ) 168 169 #define ADF41513_MAX_PFD_FREQ_INT_N_UHZ (250ULL * MEGA * MICROHZ_PER_HZ) 170 #define ADF41513_MAX_PFD_FREQ_FRAC_N_UHZ (125ULL * MEGA * MICROHZ_PER_HZ) 171 #define ADF41513_MAX_FREQ_RESOLUTION_UHZ (100ULL * KILO * MICROHZ_PER_HZ) 172 173 #define ADF41513_MIN_INT_4_5 20 174 #define ADF41513_MAX_INT_4_5 511 175 #define ADF41513_MIN_INT_8_9 64 176 #define ADF41513_MAX_INT_8_9 1023 177 178 #define ADF41513_MIN_INT_FRAC_4_5 23 179 #define ADF41513_MIN_INT_FRAC_8_9 75 180 181 #define ADF41513_MIN_R_CNT 1 182 #define ADF41513_MAX_R_CNT 32 183 184 #define ADF41513_MIN_R_SET 1800 185 #define ADF41513_DEFAULT_R_SET 2700 186 #define ADF41513_MAX_R_SET 10000 187 188 #define ADF41513_MIN_CP_VOLTAGE_mV 810 189 #define ADF41513_DEFAULT_CP_VOLTAGE_mV 6480 190 #define ADF41513_MAX_CP_VOLTAGE_mV 12960 191 192 #define ADF41513_MIN_CP_CURRENT_uA 81 193 #define ADF41513_MAX_CP_CURRENT_uA 7200 194 195 #define ADF41513_LD_COUNT_FAST_MIN 2 196 #define ADF41513_LD_COUNT_FAST_LIMIT 64 197 #define ADF41513_LD_COUNT_MIN 64 198 #define ADF41513_LD_COUNT_MAX 8192 199 200 #define ADF41513_FIXED_MODULUS BIT(25) 201 #define ADF41513_MAX_MOD2 (BIT(24) - 1) 202 #define ADF41513_MAX_PHASE_VAL (BIT(12) - 1) 203 #define ADF41513_MAX_CLK_DIVIDER (BIT(12) - 1) 204 205 #define ADF41513_HZ_DECIMAL_SCALE 6 206 #define ADF41513_PS_BIAS_INIT 0x2 207 #define ADF41513_MAX_PHASE_MICRORAD ((2 * 314159265UL) / 100) 208 209 enum adf41513_pll_mode { 210 ADF41513_MODE_INVALID, 211 ADF41513_MODE_INTEGER_N, 212 ADF41513_MODE_FIXED_MODULUS, 213 ADF41513_MODE_VARIABLE_MODULUS, 214 }; 215 216 struct adf41513_chip_info { 217 const char *name; 218 u64 max_rf_freq_hz; 219 bool has_prescaler_8_9; 220 }; 221 222 struct adf41513_data { 223 u64 power_up_frequency_hz; 224 u64 freq_resolution_uhz; 225 u32 phase_resync_period_ns; 226 u32 charge_pump_voltage_mv; 227 u32 lock_detect_count; 228 229 u8 ref_div_factor; 230 bool ref_doubler_en; 231 bool ref_div2_en; 232 bool phase_detector_polarity; 233 234 bool logic_lvl_1v8_en; 235 bool le_sync_en; 236 }; 237 238 struct adf41513_pll_settings { 239 enum adf41513_pll_mode mode; 240 241 /* reference path parameters */ 242 u8 r_counter; 243 u8 ref_doubler; 244 u8 ref_div2; 245 u8 prescaler; 246 247 /* frequency parameters */ 248 u64 target_frequency_uhz; 249 u64 actual_frequency_uhz; 250 u64 pfd_frequency_uhz; 251 252 /* pll parameters */ 253 u32 frac1; 254 u32 frac2; 255 u32 mod2; 256 u16 int_val; 257 }; 258 259 struct adf41513_state { 260 const struct adf41513_chip_info *chip_info; 261 struct spi_device *spi; 262 struct gpio_desc *lock_detect; 263 struct clk *ref_clk; 264 u32 ref_freq_hz; 265 266 /* 267 * Lock for accessing device registers. Some operations require 268 * multiple consecutive R/W operations, during which the device 269 * shouldn't be interrupted. The buffers are also shared across 270 * all operations so need to be protected on stand alone reads and 271 * writes. 272 */ 273 struct mutex lock; 274 275 /* Cached register values */ 276 u32 regs[ADF41513_REG_NUM]; 277 u32 regs_hw[ADF41513_REG_NUM]; 278 279 struct adf41513_data data; 280 struct adf41513_pll_settings settings; 281 282 bool powerdown; 283 }; 284 285 static const u16 adf41513_ld_window_x10_ns[] = { 286 9, 12, 16, 17, 21, 28, 29, 35, /* 0 - 7 */ 287 43, 47, 49, 52, 70, 79, 115, /* 8 - 14 */ 288 }; 289 290 static const u8 adf41513_ldp_bias[] = { 291 0xC, 0xD, 0xE, 0x8, 0x9, 0x4, 0xA, 0x5, /* 0 - 7 */ 292 0x0, 0x6, 0xB, 0x1, 0x2, 0x7, 0x3, /* 8 - 14 */ 293 }; 294 295 static const char * const adf41513_power_supplies[] = { 296 "avdd1", "avdd2", "avdd3", "avdd4", "avdd5", "vp", 297 }; 298 299 static int adf41513_sync_config(struct adf41513_state *st, u16 sync_mask) 300 { 301 __be32 d32; 302 int ret; 303 304 /* write registers in reverse order (R13 to R0)*/ 305 for (int i = ADF41513_REG13; i >= ADF41513_REG0; i--) { 306 if (st->regs_hw[i] == st->regs[i] && !(sync_mask & BIT(i))) 307 continue; 308 309 d32 = cpu_to_be32(st->regs[i] | i); 310 ret = spi_write_then_read(st->spi, &d32, sizeof(d32), NULL, 0); 311 if (ret < 0) 312 return ret; 313 st->regs_hw[i] = st->regs[i]; 314 dev_dbg(&st->spi->dev, "REG%d <= 0x%08X\n", i, st->regs[i] | i); 315 } 316 317 return 0; 318 } 319 320 static u64 adf41513_pll_get_rate(struct adf41513_state *st) 321 { 322 struct adf41513_pll_settings *cfg = &st->settings; 323 324 if (cfg->mode != ADF41513_MODE_INVALID) 325 return cfg->actual_frequency_uhz; 326 327 /* get pll settings from regs_hw */ 328 cfg->int_val = FIELD_GET(ADF41513_REG0_INT_MSK, st->regs_hw[ADF41513_REG0]); 329 cfg->frac1 = FIELD_GET(ADF41513_REG1_FRAC1_MSK, st->regs_hw[ADF41513_REG1]); 330 cfg->frac2 = FIELD_GET(ADF41513_REG3_FRAC2_MSK, st->regs_hw[ADF41513_REG3]); 331 cfg->mod2 = FIELD_GET(ADF41513_REG4_MOD2_MSK, st->regs_hw[ADF41513_REG4]); 332 cfg->r_counter = FIELD_GET(ADF41513_REG5_R_CNT_MSK, st->regs_hw[ADF41513_REG5]); 333 cfg->ref_doubler = FIELD_GET(ADF41513_REG5_REF_DOUBLER_MSK, st->regs_hw[ADF41513_REG5]); 334 cfg->ref_div2 = FIELD_GET(ADF41513_REG5_RDIV2_MSK, st->regs_hw[ADF41513_REG5]); 335 cfg->prescaler = FIELD_GET(ADF41513_REG5_PRESCALER_MSK, st->regs_hw[ADF41513_REG5]); 336 337 if (!cfg->mod2) 338 cfg->mod2 = 1; 339 if (!cfg->r_counter) 340 cfg->r_counter = ADF41513_MAX_R_CNT; 341 342 /* calculate pfd frequency */ 343 cfg->pfd_frequency_uhz = (u64)st->ref_freq_hz * MICRO; 344 if (cfg->ref_doubler) 345 cfg->pfd_frequency_uhz <<= 1; 346 if (cfg->ref_div2) 347 cfg->pfd_frequency_uhz >>= 1; 348 cfg->pfd_frequency_uhz = div_u64(cfg->pfd_frequency_uhz, cfg->r_counter); 349 cfg->actual_frequency_uhz = (u64)cfg->int_val * cfg->pfd_frequency_uhz; 350 351 /* check if int mode is selected */ 352 if (FIELD_GET(ADF41513_REG6_INT_MODE_MSK, st->regs_hw[ADF41513_REG6])) { 353 cfg->mode = ADF41513_MODE_INTEGER_N; 354 } else { 355 cfg->actual_frequency_uhz += mul_u64_u32_div(cfg->pfd_frequency_uhz, 356 cfg->frac1, 357 ADF41513_FIXED_MODULUS); 358 359 /* check if variable modulus is selected */ 360 if (FIELD_GET(ADF41513_REG0_VAR_MOD_MSK, st->regs_hw[ADF41513_REG0])) { 361 cfg->actual_frequency_uhz += 362 mul_u64_u64_div_u64(cfg->frac2, 363 cfg->pfd_frequency_uhz, 364 (u64)cfg->mod2 * ADF41513_FIXED_MODULUS); 365 366 cfg->mode = ADF41513_MODE_VARIABLE_MODULUS; 367 } else { 368 /* LSB_P1 offset */ 369 if (!FIELD_GET(ADF41513_REG5_LSB_P1_MSK, st->regs_hw[ADF41513_REG5])) 370 cfg->actual_frequency_uhz += 371 div_u64(cfg->pfd_frequency_uhz, 372 2 * ADF41513_FIXED_MODULUS); 373 cfg->mode = ADF41513_MODE_FIXED_MODULUS; 374 } 375 } 376 377 cfg->target_frequency_uhz = cfg->actual_frequency_uhz; 378 379 return cfg->actual_frequency_uhz; 380 } 381 382 static int adf41513_calc_pfd_frequency(struct adf41513_state *st, 383 struct adf41513_pll_settings *result, 384 u64 fpfd_limit_uhz) 385 { 386 result->ref_div2 = st->data.ref_div2_en; 387 result->ref_doubler = st->data.ref_doubler_en; 388 result->r_counter = st->data.ref_div_factor - 1; 389 390 do { 391 result->r_counter++; 392 /* f_PFD = REF_IN × ((1 + D)/(R × (1 + T))) */ 393 result->pfd_frequency_uhz = (u64)st->ref_freq_hz * MICRO; 394 if (result->ref_doubler) 395 result->pfd_frequency_uhz <<= 1; 396 if (result->ref_div2) 397 result->pfd_frequency_uhz >>= 1; 398 result->pfd_frequency_uhz = div_u64(result->pfd_frequency_uhz, 399 result->r_counter); 400 } while (result->pfd_frequency_uhz > fpfd_limit_uhz); 401 402 if (result->r_counter > ADF41513_MAX_R_CNT) { 403 dev_err(&st->spi->dev, "Cannot optimize PFD frequency\n"); 404 return -ERANGE; 405 } 406 407 return 0; 408 } 409 410 static int adf41513_calc_integer_n(struct adf41513_state *st, 411 struct adf41513_pll_settings *result) 412 { 413 u32 max_int = st->chip_info->has_prescaler_8_9 ? 414 ADF41513_MAX_INT_8_9 : ADF41513_MAX_INT_4_5; 415 u64 freq_error_uhz; 416 u32 int_val = div64_u64_rem(result->target_frequency_uhz, result->pfd_frequency_uhz, 417 &freq_error_uhz); 418 419 /* check if freq error is within a tolerance of 1/2 resolution */ 420 if (freq_error_uhz > (result->pfd_frequency_uhz >> 1) && int_val < max_int) { 421 int_val++; 422 freq_error_uhz = result->pfd_frequency_uhz - freq_error_uhz; 423 } 424 425 if (freq_error_uhz > st->data.freq_resolution_uhz) 426 return -ERANGE; 427 428 /* set prescaler */ 429 if (st->chip_info->has_prescaler_8_9 && int_val >= ADF41513_MIN_INT_8_9 && 430 int_val <= ADF41513_MAX_INT_8_9) 431 result->prescaler = 1; 432 else if (int_val >= ADF41513_MIN_INT_4_5 && int_val <= ADF41513_MAX_INT_4_5) 433 result->prescaler = 0; 434 else 435 return -ERANGE; 436 437 result->actual_frequency_uhz = (u64)int_val * result->pfd_frequency_uhz; 438 result->mode = ADF41513_MODE_INTEGER_N; 439 result->int_val = int_val; 440 result->frac1 = 0; 441 result->frac2 = 0; 442 result->mod2 = 0; 443 444 return 0; 445 } 446 447 static int adf41513_calc_fixed_mod(struct adf41513_state *st, 448 struct adf41513_pll_settings *result) 449 { 450 u64 resolution_uhz = div_u64(result->pfd_frequency_uhz, ADF41513_FIXED_MODULUS); 451 u64 target_frequency_uhz = result->target_frequency_uhz; 452 u64 freq_error_uhz; 453 u32 int_val, frac1; 454 bool lsb_p1_offset = !FIELD_GET(ADF41513_REG5_LSB_P1_MSK, st->regs[ADF41513_REG5]); 455 456 /* LSB_P1 adds a frequency offset of f_pfd/2^26 */ 457 if (lsb_p1_offset) 458 target_frequency_uhz -= resolution_uhz >> 1; 459 460 int_val = div64_u64_rem(target_frequency_uhz, result->pfd_frequency_uhz, 461 &freq_error_uhz); 462 463 if (st->chip_info->has_prescaler_8_9 && int_val >= ADF41513_MIN_INT_FRAC_8_9 && 464 int_val <= ADF41513_MAX_INT_8_9) 465 result->prescaler = 1; 466 else if (int_val >= ADF41513_MIN_INT_FRAC_4_5 && int_val <= ADF41513_MAX_INT_4_5) 467 result->prescaler = 0; 468 else 469 return -ERANGE; 470 471 /* compute frac1 and fixed modulus error */ 472 frac1 = mul_u64_u64_div_u64(freq_error_uhz, ADF41513_FIXED_MODULUS, 473 result->pfd_frequency_uhz); 474 freq_error_uhz -= mul_u64_u32_div(result->pfd_frequency_uhz, frac1, 475 ADF41513_FIXED_MODULUS); 476 477 /* check if freq error is within a tolerance of 1/2 resolution */ 478 if (freq_error_uhz > (resolution_uhz >> 1) && frac1 < (ADF41513_FIXED_MODULUS - 1)) { 479 frac1++; 480 freq_error_uhz = freq_error_uhz < resolution_uhz ? 481 resolution_uhz - freq_error_uhz : 0; 482 } 483 484 if (freq_error_uhz > st->data.freq_resolution_uhz) 485 return -ERANGE; 486 487 /* integer part */ 488 result->actual_frequency_uhz = (u64)int_val * result->pfd_frequency_uhz; 489 /* fractional part */ 490 if (lsb_p1_offset) 491 result->actual_frequency_uhz += (resolution_uhz >> 1); 492 result->actual_frequency_uhz += mul_u64_u32_div(result->pfd_frequency_uhz, frac1, 493 ADF41513_FIXED_MODULUS); 494 result->mode = ADF41513_MODE_FIXED_MODULUS; 495 result->int_val = int_val; 496 result->frac1 = frac1; 497 result->frac2 = 0; 498 result->mod2 = 0; 499 500 return 0; 501 } 502 503 static int adf41513_calc_variable_mod(struct adf41513_state *st, 504 struct adf41513_pll_settings *result) 505 { 506 u64 freq_error_uhz, mod2; 507 u32 frac1, frac2; 508 u32 int_val = div64_u64_rem(result->target_frequency_uhz, 509 result->pfd_frequency_uhz, &freq_error_uhz); 510 511 if (st->chip_info->has_prescaler_8_9 && int_val >= ADF41513_MIN_INT_FRAC_8_9 && 512 int_val <= ADF41513_MAX_INT_8_9) 513 result->prescaler = 1; 514 else if (int_val >= ADF41513_MIN_INT_FRAC_4_5 && int_val <= ADF41513_MAX_INT_4_5) 515 result->prescaler = 0; 516 else 517 return -ERANGE; 518 519 /* calculate required mod2 based on target resolution / 2 */ 520 mod2 = DIV64_U64_ROUND_CLOSEST(result->pfd_frequency_uhz << 1, 521 st->data.freq_resolution_uhz * ADF41513_FIXED_MODULUS); 522 /* ensure mod2 is at least 2 for meaningful operation */ 523 mod2 = clamp(mod2, 2, ADF41513_MAX_MOD2); 524 525 /* calculate frac1 and frac2 */ 526 frac1 = mul_u64_u64_div_u64(freq_error_uhz, ADF41513_FIXED_MODULUS, 527 result->pfd_frequency_uhz); 528 frac2 = mul_u64_u64_div_u64(freq_error_uhz, mod2 * ADF41513_FIXED_MODULUS, 529 result->pfd_frequency_uhz) - mod2 * frac1; 530 531 /* integer part */ 532 result->actual_frequency_uhz = (u64)int_val * result->pfd_frequency_uhz; 533 /* fractional part */ 534 result->actual_frequency_uhz += mul_u64_u64_div_u64(mod2 * frac1 + frac2, 535 result->pfd_frequency_uhz, 536 mod2 * ADF41513_FIXED_MODULUS); 537 result->mode = ADF41513_MODE_VARIABLE_MODULUS; 538 result->int_val = int_val; 539 result->frac1 = frac1; 540 result->frac2 = frac2; 541 result->mod2 = mod2; 542 543 return 0; 544 } 545 546 static int adf41513_calc_pll_settings(struct adf41513_state *st, 547 struct adf41513_pll_settings *result, 548 u64 rf_out_uhz) 549 { 550 u64 max_rf_freq_uhz = st->chip_info->max_rf_freq_hz * MICRO; 551 u64 min_rf_freq_uhz = ADF41513_MIN_RF_FREQ_HZ * MICRO; 552 u64 pfd_freq_limit_uhz; 553 int ret; 554 555 if (rf_out_uhz < min_rf_freq_uhz || rf_out_uhz > max_rf_freq_uhz) { 556 dev_err(&st->spi->dev, "RF frequency %llu uHz out of range [%llu, %llu] uHz\n", 557 rf_out_uhz, min_rf_freq_uhz, max_rf_freq_uhz); 558 return -EINVAL; 559 } 560 561 result->target_frequency_uhz = rf_out_uhz; 562 563 /* try integer-N first (best phase noise performance) */ 564 pfd_freq_limit_uhz = min(div_u64(rf_out_uhz, ADF41513_MIN_INT_4_5), 565 ADF41513_MAX_PFD_FREQ_INT_N_UHZ); 566 ret = adf41513_calc_pfd_frequency(st, result, pfd_freq_limit_uhz); 567 if (ret) 568 return ret; 569 570 if (adf41513_calc_integer_n(st, result) == 0) 571 return 0; 572 573 /* try fractional-N: recompute pfd frequency if necessary */ 574 pfd_freq_limit_uhz = min(div_u64(rf_out_uhz, ADF41513_MIN_INT_FRAC_4_5), 575 ADF41513_MAX_PFD_FREQ_FRAC_N_UHZ); 576 if (pfd_freq_limit_uhz < result->pfd_frequency_uhz) { 577 ret = adf41513_calc_pfd_frequency(st, result, pfd_freq_limit_uhz); 578 if (ret) 579 return ret; 580 } 581 582 /* fixed-modulus attempt */ 583 if (adf41513_calc_fixed_mod(st, result) == 0) 584 return 0; 585 586 /* variable-modulus attempt */ 587 ret = adf41513_calc_variable_mod(st, result); 588 if (ret) { 589 dev_err(&st->spi->dev, 590 "no valid PLL configuration found for %llu uHz\n", 591 rf_out_uhz); 592 return ret; 593 } 594 595 return 0; 596 } 597 598 static void adf41513_set_bleed_val(struct adf41513_state *st) 599 { 600 u32 bleed_value, cp_index; 601 602 if (!(st->regs[ADF41513_REG6] & ADF41513_REG6_BLEED_ENABLE_MSK)) 603 return; 604 605 if (st->data.phase_detector_polarity) 606 bleed_value = 90; 607 else 608 bleed_value = 144; 609 610 cp_index = 1 + FIELD_GET(ADF41513_REG5_CP_CURRENT_MSK, 611 st->regs[ADF41513_REG5]); 612 bleed_value = div64_u64(st->settings.pfd_frequency_uhz * cp_index * bleed_value, 613 1600ULL * MEGA * MICROHZ_PER_HZ); 614 615 FIELD_MODIFY(ADF41513_REG6_BLEED_CURRENT_MSK, &st->regs[ADF41513_REG6], 616 bleed_value); 617 } 618 619 static void adf41513_set_ld_window(struct adf41513_state *st) 620 { 621 /* 622 * The ideal lock detector window size is halfway between the max 623 * window, set by the phase comparison period t_PFD = (1 / f_PFD), 624 * and the minimum is set by (I_BLEED/I_CP) × t_PFD 625 */ 626 u16 ld_window_10x_ns = div64_u64(10ULL * NSEC_PER_SEC * MICROHZ_PER_HZ, 627 st->settings.pfd_frequency_uhz << 1); 628 u8 ld_idx, ldp, ld_bias; 629 630 if (st->settings.mode != ADF41513_MODE_INTEGER_N) { 631 /* account for bleed current (deduced from eq.6 and eq.7) */ 632 if (st->data.phase_detector_polarity) 633 ld_window_10x_ns += 4; 634 else 635 ld_window_10x_ns += 6; 636 } 637 638 ld_idx = find_closest(ld_window_10x_ns, adf41513_ld_window_x10_ns, 639 ARRAY_SIZE(adf41513_ld_window_x10_ns)); 640 ldp = (adf41513_ldp_bias[ld_idx] >> 2) & 0x3; 641 ld_bias = adf41513_ldp_bias[ld_idx] & 0x3; 642 643 FIELD_MODIFY(ADF41513_REG6_LDP_MSK, &st->regs[ADF41513_REG6], ldp); 644 FIELD_MODIFY(ADF41513_REG9_LD_BIAS_MSK, &st->regs[ADF41513_REG9], ld_bias); 645 } 646 647 static void adf41513_set_phase_resync(struct adf41513_state *st) 648 { 649 u32 total_div, clk1_div, clk2_div; 650 651 if (!st->data.phase_resync_period_ns) 652 return; 653 654 /* assuming both clock dividers hold similar values */ 655 total_div = mul_u64_u64_div_u64(st->settings.pfd_frequency_uhz, 656 st->data.phase_resync_period_ns, 657 1ULL * MICROHZ_PER_HZ * NSEC_PER_SEC); 658 clk1_div = clamp(int_sqrt(total_div), 1, 659 ADF41513_MAX_CLK_DIVIDER); 660 clk2_div = clamp(DIV_ROUND_CLOSEST(total_div, clk1_div), 1, 661 ADF41513_MAX_CLK_DIVIDER); 662 663 FIELD_MODIFY(ADF41513_REG5_CLK1_DIV_MSK, &st->regs[ADF41513_REG5], 664 clk1_div); 665 FIELD_MODIFY(ADF41513_REG7_CLK2_DIV_MSK, &st->regs[ADF41513_REG7], 666 clk2_div); 667 668 /* enable phase resync */ 669 FIELD_MODIFY(ADF41513_REG7_CLK_DIV_MODE_MSK, &st->regs[ADF41513_REG7], 670 ADF41513_CLK_DIV_MODE_PHASE_RESYNC); 671 } 672 673 static int adf41513_set_frequency(struct adf41513_state *st, u64 freq_uhz, u16 sync_mask) 674 { 675 struct adf41513_pll_settings result; 676 bool pfd_change = false; 677 bool mode_change = false; 678 int ret; 679 680 ret = adf41513_calc_pll_settings(st, &result, freq_uhz); 681 if (ret < 0) 682 return ret; 683 684 /* apply computed results to pll settings */ 685 pfd_change = st->settings.pfd_frequency_uhz != result.pfd_frequency_uhz; 686 mode_change = st->settings.mode != result.mode; 687 st->settings = result; 688 689 dev_dbg(&st->spi->dev, 690 "%s mode: int=%u, frac1=%u, frac2=%u, mod2=%u, fpdf=%llu Hz, prescaler=%s\n", 691 (result.mode == ADF41513_MODE_INTEGER_N) ? "integer-n" : 692 (result.mode == ADF41513_MODE_FIXED_MODULUS) ? "fixed-modulus" : "variable-modulus", 693 result.int_val, result.frac1, result.frac2, result.mod2, 694 div64_u64(result.pfd_frequency_uhz, MICRO), 695 result.prescaler ? "8/9" : "4/5"); 696 697 st->regs[ADF41513_REG0] = FIELD_PREP(ADF41513_REG0_INT_MSK, 698 st->settings.int_val); 699 if (st->settings.mode == ADF41513_MODE_VARIABLE_MODULUS) 700 st->regs[ADF41513_REG0] |= ADF41513_REG0_VAR_MOD_MSK; 701 702 st->regs[ADF41513_REG1] = FIELD_PREP(ADF41513_REG1_FRAC1_MSK, 703 st->settings.frac1); 704 if (st->settings.mode != ADF41513_MODE_INTEGER_N) 705 st->regs[ADF41513_REG1] |= ADF41513_REG1_DITHER2_MSK; 706 707 st->regs[ADF41513_REG3] = FIELD_PREP(ADF41513_REG3_FRAC2_MSK, 708 st->settings.frac2); 709 FIELD_MODIFY(ADF41513_REG4_MOD2_MSK, &st->regs[ADF41513_REG4], 710 st->settings.mod2); 711 FIELD_MODIFY(ADF41513_REG5_R_CNT_MSK, &st->regs[ADF41513_REG5], 712 st->settings.r_counter % ADF41513_MAX_R_CNT); 713 FIELD_MODIFY(ADF41513_REG5_REF_DOUBLER_MSK, &st->regs[ADF41513_REG5], 714 st->settings.ref_doubler); 715 FIELD_MODIFY(ADF41513_REG5_RDIV2_MSK, &st->regs[ADF41513_REG5], 716 st->settings.ref_div2); 717 FIELD_MODIFY(ADF41513_REG5_PRESCALER_MSK, &st->regs[ADF41513_REG5], 718 st->settings.prescaler); 719 720 if (st->settings.mode == ADF41513_MODE_INTEGER_N) { 721 st->regs[ADF41513_REG6] |= ADF41513_REG6_INT_MODE_MSK; 722 st->regs[ADF41513_REG6] &= ~ADF41513_REG6_BLEED_ENABLE_MSK; 723 } else { 724 st->regs[ADF41513_REG6] &= ~ADF41513_REG6_INT_MODE_MSK; 725 st->regs[ADF41513_REG6] |= ADF41513_REG6_BLEED_ENABLE_MSK; 726 } 727 728 if (pfd_change) 729 adf41513_set_phase_resync(st); 730 731 if (pfd_change || mode_change) { 732 adf41513_set_bleed_val(st); 733 adf41513_set_ld_window(st); 734 } 735 736 return adf41513_sync_config(st, sync_mask | ADF41513_SYNC_REG0); 737 } 738 739 static int adf41513_suspend(struct adf41513_state *st) 740 { 741 st->regs[ADF41513_REG6] |= FIELD_PREP(ADF41513_REG6_POWER_DOWN_MSK, 1); 742 st->regs[ADF41513_REG12] &= ~ADF41513_REG12_LE_SELECT_MSK; 743 return adf41513_sync_config(st, ADF41513_SYNC_DIFF); 744 } 745 746 static int adf41513_resume(struct adf41513_state *st) 747 { 748 int ret; 749 750 st->regs[ADF41513_REG6] &= ~ADF41513_REG6_POWER_DOWN_MSK; 751 st->regs[ADF41513_REG12] &= ~ADF41513_REG12_LE_SELECT_MSK; 752 ret = adf41513_sync_config(st, ADF41513_SYNC_ALL); 753 if (ret) 754 return ret; 755 756 if (st->data.le_sync_en) { 757 st->regs[ADF41513_REG12] |= ADF41513_REG12_LE_SELECT_MSK; 758 ret = adf41513_sync_config(st, ADF41513_SYNC_DIFF); 759 if (ret) 760 return ret; 761 } 762 763 return 0; 764 } 765 766 static ssize_t adf41513_read_resolution(struct iio_dev *indio_dev, 767 uintptr_t private, 768 const struct iio_chan_spec *chan, 769 char *buf) 770 { 771 struct adf41513_state *st = iio_priv(indio_dev); 772 int vals[2]; 773 774 guard(mutex)(&st->lock); 775 776 iio_val_s64_decompose(st->data.freq_resolution_uhz, &vals[0], &vals[1]); 777 return iio_format_value(buf, IIO_VAL_DECIMAL64_MICRO, ARRAY_SIZE(vals), vals); 778 } 779 780 static ssize_t adf41513_read_powerdown(struct iio_dev *indio_dev, 781 uintptr_t private, 782 const struct iio_chan_spec *chan, 783 char *buf) 784 { 785 struct adf41513_state *st = iio_priv(indio_dev); 786 u32 val; 787 788 guard(mutex)(&st->lock); 789 790 val = FIELD_GET(ADF41513_REG6_POWER_DOWN_MSK, st->regs_hw[ADF41513_REG6]); 791 return sysfs_emit(buf, "%u\n", val); 792 } 793 794 static ssize_t adf41513_write_resolution(struct iio_dev *indio_dev, 795 uintptr_t private, 796 const struct iio_chan_spec *chan, 797 const char *buf, size_t len) 798 { 799 struct adf41513_state *st = iio_priv(indio_dev); 800 u64 freq_uhz; 801 int ret; 802 803 ret = kstrtoudec64(buf, ADF41513_HZ_DECIMAL_SCALE, &freq_uhz); 804 if (ret) 805 return ret; 806 807 if (freq_uhz == 0 || freq_uhz > ADF41513_MAX_FREQ_RESOLUTION_UHZ) 808 return -EINVAL; 809 810 guard(mutex)(&st->lock); 811 812 st->data.freq_resolution_uhz = freq_uhz; 813 return len; 814 } 815 816 static ssize_t adf41513_write_powerdown(struct iio_dev *indio_dev, 817 uintptr_t private, 818 const struct iio_chan_spec *chan, 819 const char *buf, size_t len) 820 { 821 struct adf41513_state *st = iio_priv(indio_dev); 822 bool val; 823 int ret; 824 825 ret = kstrtobool(buf, &val); 826 if (ret) 827 return ret; 828 829 guard(mutex)(&st->lock); 830 831 if (val) 832 ret = adf41513_suspend(st); 833 else 834 ret = adf41513_resume(st); 835 if (ret) 836 return ret; 837 838 st->powerdown = val; 839 return len; 840 } 841 842 static const struct iio_chan_spec_ext_info adf41513_ext_info[] = { 843 { 844 .name = "frequency_resolution", 845 .read = adf41513_read_resolution, 846 .write = adf41513_write_resolution, 847 .shared = IIO_SEPARATE, 848 }, 849 { 850 .name = "powerdown", 851 .read = adf41513_read_powerdown, 852 .write = adf41513_write_powerdown, 853 .shared = IIO_SEPARATE, 854 }, 855 { } 856 }; 857 858 static const struct iio_chan_spec adf41513_chan = { 859 .type = IIO_ALTVOLTAGE, 860 .indexed = 1, 861 .output = 1, 862 .channel = 0, 863 .info_mask_separate = BIT(IIO_CHAN_INFO_FREQUENCY) | 864 BIT(IIO_CHAN_INFO_PHASE), 865 .ext_info = adf41513_ext_info, 866 }; 867 868 static int adf41513_read_raw(struct iio_dev *indio_dev, 869 struct iio_chan_spec const *chan, 870 int *val, int *val2, long info) 871 { 872 struct adf41513_state *st = iio_priv(indio_dev); 873 u64 tmp64; 874 875 guard(mutex)(&st->lock); 876 877 switch (info) { 878 case IIO_CHAN_INFO_FREQUENCY: 879 if (st->lock_detect && 880 !gpiod_get_value_cansleep(st->lock_detect)) { 881 dev_dbg(&st->spi->dev, "PLL un-locked\n"); 882 return -EBUSY; 883 } 884 tmp64 = adf41513_pll_get_rate(st); 885 iio_val_s64_decompose(tmp64, val, val2); 886 return IIO_VAL_DECIMAL64_MICRO; 887 case IIO_CHAN_INFO_PHASE: 888 tmp64 = FIELD_GET(ADF41513_REG2_PHASE_VAL_MSK, 889 st->regs_hw[ADF41513_REG2]); 890 tmp64 = (tmp64 * ADF41513_MAX_PHASE_MICRORAD) >> 12; 891 iio_val_s64_decompose(tmp64, val, val2); 892 return IIO_VAL_DECIMAL64_MICRO; 893 default: 894 return -EINVAL; 895 } 896 } 897 898 static int adf41513_write_raw(struct iio_dev *indio_dev, 899 struct iio_chan_spec const *chan, 900 int val, int val2, long info) 901 { 902 struct adf41513_state *st = iio_priv(indio_dev); 903 u64 tmp64 = iio_val_s64_compose(val, val2); 904 u16 phase_val; 905 int ret; 906 907 guard(mutex)(&st->lock); 908 909 switch (info) { 910 case IIO_CHAN_INFO_FREQUENCY: 911 return adf41513_set_frequency(st, tmp64, ADF41513_SYNC_DIFF); 912 case IIO_CHAN_INFO_PHASE: 913 if (tmp64 >= ADF41513_MAX_PHASE_MICRORAD) 914 return -EINVAL; 915 916 phase_val = DIV_U64_ROUND_CLOSEST(tmp64 << 12, 917 ADF41513_MAX_PHASE_MICRORAD); 918 phase_val = min(phase_val, ADF41513_MAX_PHASE_VAL); 919 st->regs[ADF41513_REG2] |= ADF41513_REG2_PHASE_ADJ_MSK; 920 FIELD_MODIFY(ADF41513_REG2_PHASE_VAL_MSK, 921 &st->regs[ADF41513_REG2], phase_val); 922 ret = adf41513_sync_config(st, ADF41513_SYNC_REG0); 923 /* clear phase adjust for the next sync */ 924 st->regs[ADF41513_REG2] &= ~ADF41513_REG2_PHASE_ADJ_MSK; 925 return ret; 926 default: 927 return -EINVAL; 928 } 929 } 930 931 static int adf41513_write_raw_get_fmt(struct iio_dev *indio_dev, 932 struct iio_chan_spec const *chan, 933 long mask) 934 { 935 switch (mask) { 936 case IIO_CHAN_INFO_FREQUENCY: 937 case IIO_CHAN_INFO_PHASE: 938 return IIO_VAL_DECIMAL64_MICRO; 939 default: 940 return -EINVAL; 941 } 942 } 943 944 static int adf41513_reg_access(struct iio_dev *indio_dev, unsigned int reg, 945 unsigned int writeval, unsigned int *readval) 946 { 947 struct adf41513_state *st = iio_priv(indio_dev); 948 949 if (reg > ADF41513_REG13) 950 return -EINVAL; 951 952 guard(mutex)(&st->lock); 953 954 if (!readval) { 955 if (reg <= ADF41513_REG6) 956 st->settings.mode = ADF41513_MODE_INVALID; 957 st->regs[reg] = writeval & ~0xF; /* Clear control bits */ 958 return adf41513_sync_config(st, BIT(reg)); 959 } 960 961 *readval = st->regs_hw[reg]; 962 return 0; 963 } 964 965 static const struct iio_info adf41513_info = { 966 .read_raw = adf41513_read_raw, 967 .write_raw = adf41513_write_raw, 968 .write_raw_get_fmt = adf41513_write_raw_get_fmt, 969 .debugfs_reg_access = &adf41513_reg_access, 970 }; 971 972 static int adf41513_parse_fw(struct adf41513_state *st) 973 { 974 struct device *dev = &st->spi->dev; 975 u32 tmp, cp_resistance, cp_current; 976 int ret; 977 978 tmp = ADF41510_MAX_RF_FREQ_HZ / MEGA; 979 device_property_read_u32(dev, "adi,power-up-frequency-mhz", &tmp); 980 st->data.power_up_frequency_hz = (u64)tmp * MEGA; 981 if (st->data.power_up_frequency_hz < ADF41513_MIN_RF_FREQ_HZ || 982 st->data.power_up_frequency_hz > st->chip_info->max_rf_freq_hz) 983 return dev_err_probe(dev, -ERANGE, 984 "power-up frequency %llu Hz out of range\n", 985 st->data.power_up_frequency_hz); 986 987 tmp = ADF41513_MIN_R_CNT; 988 device_property_read_u32(dev, "adi,reference-div-factor", &tmp); 989 if (tmp < ADF41513_MIN_R_CNT || tmp > ADF41513_MAX_R_CNT) 990 return dev_err_probe(dev, -ERANGE, 991 "invalid reference div factor %u\n", tmp); 992 st->data.ref_div_factor = tmp; 993 994 st->data.ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable"); 995 st->data.ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable"); 996 997 if (st->data.ref_doubler_en && 998 st->ref_freq_hz > ADF41513_MAX_REF_FREQ_DOUBLER_HZ) { 999 return dev_err_probe(dev, -ERANGE, 1000 "Ref frequency not supported with doubler enabled\n"); 1001 } 1002 1003 cp_resistance = ADF41513_DEFAULT_R_SET; 1004 device_property_read_u32(dev, "adi,charge-pump-resistor-ohms", &cp_resistance); 1005 if (cp_resistance < ADF41513_MIN_R_SET || cp_resistance > ADF41513_MAX_R_SET) 1006 return dev_err_probe(dev, -ERANGE, "R_SET %u Ohms out of range\n", cp_resistance); 1007 1008 st->data.charge_pump_voltage_mv = ADF41513_DEFAULT_CP_VOLTAGE_mV; 1009 ret = device_property_read_u32(dev, "adi,charge-pump-current-microamp", &cp_current); 1010 if (!ret) { 1011 if (cp_current < ADF41513_MIN_CP_CURRENT_uA || 1012 cp_current > ADF41513_MAX_CP_CURRENT_uA) 1013 return dev_err_probe(dev, -ERANGE, 1014 "I_CP %u uA out of range\n", cp_current); 1015 1016 tmp = DIV_ROUND_CLOSEST(cp_current * cp_resistance, MILLI); 1017 if (tmp < ADF41513_MIN_CP_VOLTAGE_mV || tmp > ADF41513_MAX_CP_VOLTAGE_mV) 1018 return dev_err_probe(dev, -ERANGE, "I_CP %u uA (%u Ohms) out of range\n", 1019 cp_current, cp_resistance); 1020 st->data.charge_pump_voltage_mv = tmp; 1021 } 1022 1023 st->data.phase_detector_polarity = 1024 device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable"); 1025 1026 st->data.phase_resync_period_ns = 0; 1027 ret = device_property_read_u32(dev, "adi,phase-resync-period-ns", &tmp); 1028 if (!ret) 1029 st->data.phase_resync_period_ns = tmp; 1030 1031 st->data.logic_lvl_1v8_en = device_property_read_bool(dev, "adi,logic-level-1v8-enable"); 1032 1033 tmp = ADF41513_LD_COUNT_MIN; 1034 device_property_read_u32(dev, "adi,lock-detector-count", &tmp); 1035 if (tmp < ADF41513_LD_COUNT_FAST_MIN || tmp > ADF41513_LD_COUNT_MAX || 1036 !is_power_of_2(tmp)) 1037 return dev_err_probe(dev, -ERANGE, 1038 "invalid lock detect count: %u\n", tmp); 1039 st->data.lock_detect_count = tmp; 1040 1041 /* load enable sync */ 1042 st->data.le_sync_en = device_property_read_bool(dev, "adi,le-sync-enable"); 1043 st->data.freq_resolution_uhz = MICROHZ_PER_HZ; 1044 1045 return 0; 1046 } 1047 1048 static void adf41513_chip_disable(void *data) 1049 { 1050 gpiod_set_value_cansleep(data, 0); 1051 } 1052 1053 static void adf41513_close(void *data) 1054 { 1055 adf41513_suspend(data); 1056 } 1057 1058 static int adf41513_setup(struct device *dev, struct adf41513_state *st) 1059 { 1060 u32 tmp; 1061 int ret; 1062 1063 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); 1064 1065 /* assuming DLD pin is used for lock detection */ 1066 st->regs[ADF41513_REG5] = FIELD_PREP(ADF41513_REG5_DLD_MODES_MSK, 1067 ADF41513_DLD_DIG_LD); 1068 1069 tmp = DIV_ROUND_CLOSEST(st->data.charge_pump_voltage_mv, ADF41513_MIN_CP_VOLTAGE_mV); 1070 st->regs[ADF41513_REG5] |= FIELD_PREP(ADF41513_REG5_CP_CURRENT_MSK, tmp - 1); 1071 1072 st->regs[ADF41513_REG6] = ADF41513_REG6_ABP_MSK | 1073 ADF41513_REG6_LOL_ENABLE_MSK | 1074 ADF41513_REG6_SD_RESET_MSK; 1075 if (st->data.phase_detector_polarity) 1076 st->regs[ADF41513_REG6] |= ADF41513_REG6_PD_POLARITY_MSK; 1077 1078 st->regs[ADF41513_REG7] = FIELD_PREP(ADF41513_REG7_PS_BIAS_MSK, 1079 ADF41513_PS_BIAS_INIT); 1080 tmp = ilog2(st->data.lock_detect_count); 1081 if (st->data.lock_detect_count < ADF41513_LD_COUNT_FAST_LIMIT) { 1082 tmp -= const_ilog2(ADF41513_LD_COUNT_FAST_MIN); 1083 st->regs[ADF41513_REG7] |= ADF41513_REG7_LD_CLK_SEL_MSK; 1084 } else { 1085 tmp -= const_ilog2(ADF41513_LD_COUNT_MIN); 1086 } 1087 st->regs[ADF41513_REG7] |= FIELD_PREP(ADF41513_REG7_LD_COUNT_MSK, tmp); 1088 1089 st->regs[ADF41513_REG11] = ADF41513_REG11_POWER_DOWN_SEL_MSK; 1090 st->regs[ADF41513_REG12] = FIELD_PREP(ADF41513_REG12_LOGIC_LEVEL_MSK, 1091 st->data.logic_lvl_1v8_en ? 0 : 1); 1092 1093 /* perform initialization sequence with power-up frequency */ 1094 ret = adf41513_set_frequency(st, st->data.power_up_frequency_hz * MICRO, 1095 ADF41513_SYNC_ALL); 1096 if (ret) 1097 return ret; 1098 1099 ret = devm_add_action_or_reset(dev, adf41513_close, st); 1100 if (ret) 1101 return ret; 1102 1103 if (st->data.le_sync_en) { 1104 st->regs[ADF41513_REG12] |= ADF41513_REG12_LE_SELECT_MSK; 1105 ret = adf41513_sync_config(st, ADF41513_SYNC_DIFF); 1106 if (ret) 1107 return ret; 1108 } 1109 1110 return 0; 1111 } 1112 1113 static int adf41513_pm_suspend(struct device *dev) 1114 { 1115 struct adf41513_state *st = dev_get_drvdata(dev); 1116 1117 guard(mutex)(&st->lock); 1118 return adf41513_suspend(st); 1119 } 1120 1121 static int adf41513_pm_resume(struct device *dev) 1122 { 1123 struct adf41513_state *st = dev_get_drvdata(dev); 1124 1125 guard(mutex)(&st->lock); 1126 if (st->powerdown) 1127 return 0; /* nothing to do */ 1128 1129 return adf41513_resume(st); 1130 } 1131 1132 static const struct adf41513_chip_info adf41510_chip_info = { 1133 .name = "adf41510", 1134 .max_rf_freq_hz = ADF41510_MAX_RF_FREQ_HZ, 1135 .has_prescaler_8_9 = false, 1136 }; 1137 1138 static const struct adf41513_chip_info adf41513_chip_info = { 1139 .name = "adf41513", 1140 .max_rf_freq_hz = ADF41513_MAX_RF_FREQ_HZ, 1141 .has_prescaler_8_9 = true, 1142 }; 1143 1144 static int adf41513_probe(struct spi_device *spi) 1145 { 1146 struct device *dev = &spi->dev; 1147 struct gpio_desc *chip_enable; 1148 struct iio_dev *indio_dev; 1149 struct adf41513_state *st; 1150 int ret; 1151 1152 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1153 if (!indio_dev) 1154 return -ENOMEM; 1155 1156 st = iio_priv(indio_dev); 1157 st->spi = spi; 1158 st->chip_info = spi_get_device_match_data(spi); 1159 if (!st->chip_info) 1160 return -EINVAL; 1161 1162 spi_set_drvdata(spi, st); 1163 1164 st->ref_clk = devm_clk_get_enabled(dev, NULL); 1165 if (IS_ERR(st->ref_clk)) 1166 return PTR_ERR(st->ref_clk); 1167 1168 st->ref_freq_hz = clk_get_rate(st->ref_clk); 1169 if (st->ref_freq_hz < ADF41513_MIN_REF_FREQ_HZ || 1170 st->ref_freq_hz > ADF41513_MAX_REF_FREQ_HZ) 1171 return dev_err_probe(dev, -ERANGE, 1172 "reference frequency %u Hz out of range\n", 1173 st->ref_freq_hz); 1174 1175 ret = adf41513_parse_fw(st); 1176 if (ret) 1177 return ret; 1178 1179 ret = devm_regulator_bulk_get_enable(dev, 1180 ARRAY_SIZE(adf41513_power_supplies), 1181 adf41513_power_supplies); 1182 if (ret) 1183 return dev_err_probe(dev, ret, 1184 "failed to get and enable regulators\n"); 1185 1186 st->lock_detect = devm_gpiod_get_optional(dev, "lock-detect", GPIOD_IN); 1187 if (IS_ERR(st->lock_detect)) 1188 return dev_err_probe(dev, PTR_ERR(st->lock_detect), 1189 "fail to request lock detect GPIO\n"); 1190 1191 chip_enable = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); 1192 if (IS_ERR(chip_enable)) 1193 return dev_err_probe(dev, PTR_ERR(chip_enable), 1194 "fail to request chip enable GPIO\n"); 1195 1196 ret = devm_add_action_or_reset(dev, adf41513_chip_disable, chip_enable); 1197 if (ret) 1198 return dev_err_probe(dev, ret, "Failed to add disable action\n"); 1199 1200 ret = devm_mutex_init(dev, &st->lock); 1201 if (ret) 1202 return ret; 1203 1204 indio_dev->name = st->chip_info->name; 1205 indio_dev->info = &adf41513_info; 1206 indio_dev->modes = INDIO_DIRECT_MODE; 1207 indio_dev->channels = &adf41513_chan; 1208 indio_dev->num_channels = 1; 1209 1210 ret = adf41513_setup(dev, st); 1211 if (ret < 0) 1212 return dev_err_probe(dev, ret, "failed to setup device\n"); 1213 1214 return devm_iio_device_register(dev, indio_dev); 1215 } 1216 1217 static const struct spi_device_id adf41513_id[] = { 1218 { .name = "adf41510", .driver_data = (kernel_ulong_t)&adf41510_chip_info }, 1219 { .name = "adf41513", .driver_data = (kernel_ulong_t)&adf41513_chip_info }, 1220 { } 1221 }; 1222 MODULE_DEVICE_TABLE(spi, adf41513_id); 1223 1224 static const struct of_device_id adf41513_of_match[] = { 1225 { .compatible = "adi,adf41510", .data = &adf41510_chip_info }, 1226 { .compatible = "adi,adf41513", .data = &adf41513_chip_info }, 1227 { } 1228 }; 1229 MODULE_DEVICE_TABLE(of, adf41513_of_match); 1230 1231 static DEFINE_SIMPLE_DEV_PM_OPS(adf41513_pm_ops, adf41513_pm_suspend, adf41513_pm_resume); 1232 1233 static struct spi_driver adf41513_driver = { 1234 .driver = { 1235 .name = "adf41513", 1236 .pm = pm_ptr(&adf41513_pm_ops), 1237 .of_match_table = adf41513_of_match, 1238 }, 1239 .probe = adf41513_probe, 1240 .id_table = adf41513_id, 1241 }; 1242 module_spi_driver(adf41513_driver); 1243 1244 MODULE_AUTHOR("Rodrigo Alencar <rodrigo.alencar@analog.com>"); 1245 MODULE_DESCRIPTION("Analog Devices ADF41513 PLL Frequency Synthesizer"); 1246 MODULE_LICENSE("GPL"); 1247