1*02b829f9SMaxime Roussin-Belanger /* 2*02b829f9SMaxime Roussin-Belanger * LTC2632 Digital to analog convertors spi driver 3*02b829f9SMaxime Roussin-Belanger * 4*02b829f9SMaxime Roussin-Belanger * Copyright 2017 Maxime Roussin-B�langer 5*02b829f9SMaxime Roussin-Belanger * 6*02b829f9SMaxime Roussin-Belanger * Licensed under the GPL-2. 7*02b829f9SMaxime Roussin-Belanger */ 8*02b829f9SMaxime Roussin-Belanger 9*02b829f9SMaxime Roussin-Belanger #include <linux/device.h> 10*02b829f9SMaxime Roussin-Belanger #include <linux/spi/spi.h> 11*02b829f9SMaxime Roussin-Belanger #include <linux/module.h> 12*02b829f9SMaxime Roussin-Belanger #include <linux/iio/iio.h> 13*02b829f9SMaxime Roussin-Belanger 14*02b829f9SMaxime Roussin-Belanger #define LTC2632_DAC_CHANNELS 2 15*02b829f9SMaxime Roussin-Belanger 16*02b829f9SMaxime Roussin-Belanger #define LTC2632_ADDR_DAC0 0x0 17*02b829f9SMaxime Roussin-Belanger #define LTC2632_ADDR_DAC1 0x1 18*02b829f9SMaxime Roussin-Belanger 19*02b829f9SMaxime Roussin-Belanger #define LTC2632_CMD_WRITE_INPUT_N 0x0 20*02b829f9SMaxime Roussin-Belanger #define LTC2632_CMD_UPDATE_DAC_N 0x1 21*02b829f9SMaxime Roussin-Belanger #define LTC2632_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2 22*02b829f9SMaxime Roussin-Belanger #define LTC2632_CMD_WRITE_INPUT_N_UPDATE_N 0x3 23*02b829f9SMaxime Roussin-Belanger #define LTC2632_CMD_POWERDOWN_DAC_N 0x4 24*02b829f9SMaxime Roussin-Belanger #define LTC2632_CMD_POWERDOWN_CHIP 0x5 25*02b829f9SMaxime Roussin-Belanger #define LTC2632_CMD_INTERNAL_REFER 0x6 26*02b829f9SMaxime Roussin-Belanger #define LTC2632_CMD_EXTERNAL_REFER 0x7 27*02b829f9SMaxime Roussin-Belanger 28*02b829f9SMaxime Roussin-Belanger /** 29*02b829f9SMaxime Roussin-Belanger * struct ltc2632_chip_info - chip specific information 30*02b829f9SMaxime Roussin-Belanger * @channels: channel spec for the DAC 31*02b829f9SMaxime Roussin-Belanger * @vref_mv: reference voltage 32*02b829f9SMaxime Roussin-Belanger */ 33*02b829f9SMaxime Roussin-Belanger struct ltc2632_chip_info { 34*02b829f9SMaxime Roussin-Belanger const struct iio_chan_spec *channels; 35*02b829f9SMaxime Roussin-Belanger const int vref_mv; 36*02b829f9SMaxime Roussin-Belanger }; 37*02b829f9SMaxime Roussin-Belanger 38*02b829f9SMaxime Roussin-Belanger /** 39*02b829f9SMaxime Roussin-Belanger * struct ltc2632_state - driver instance specific data 40*02b829f9SMaxime Roussin-Belanger * @spi_dev: pointer to the spi_device struct 41*02b829f9SMaxime Roussin-Belanger * @powerdown_cache_mask used to show current channel powerdown state 42*02b829f9SMaxime Roussin-Belanger */ 43*02b829f9SMaxime Roussin-Belanger struct ltc2632_state { 44*02b829f9SMaxime Roussin-Belanger struct spi_device *spi_dev; 45*02b829f9SMaxime Roussin-Belanger unsigned int powerdown_cache_mask; 46*02b829f9SMaxime Roussin-Belanger }; 47*02b829f9SMaxime Roussin-Belanger 48*02b829f9SMaxime Roussin-Belanger enum ltc2632_supported_device_ids { 49*02b829f9SMaxime Roussin-Belanger ID_LTC2632L12, 50*02b829f9SMaxime Roussin-Belanger ID_LTC2632L10, 51*02b829f9SMaxime Roussin-Belanger ID_LTC2632L8, 52*02b829f9SMaxime Roussin-Belanger ID_LTC2632H12, 53*02b829f9SMaxime Roussin-Belanger ID_LTC2632H10, 54*02b829f9SMaxime Roussin-Belanger ID_LTC2632H8, 55*02b829f9SMaxime Roussin-Belanger }; 56*02b829f9SMaxime Roussin-Belanger 57*02b829f9SMaxime Roussin-Belanger static int ltc2632_spi_write(struct spi_device *spi, 58*02b829f9SMaxime Roussin-Belanger u8 cmd, u8 addr, u16 val, u8 shift) 59*02b829f9SMaxime Roussin-Belanger { 60*02b829f9SMaxime Roussin-Belanger u32 data; 61*02b829f9SMaxime Roussin-Belanger u8 msg[3]; 62*02b829f9SMaxime Roussin-Belanger 63*02b829f9SMaxime Roussin-Belanger /* 64*02b829f9SMaxime Roussin-Belanger * The input shift register is 24 bits wide. 65*02b829f9SMaxime Roussin-Belanger * The next four are the command bits, C3 to C0, 66*02b829f9SMaxime Roussin-Belanger * followed by the 4-bit DAC address, A3 to A0, and then the 67*02b829f9SMaxime Roussin-Belanger * 12-, 10-, 8-bit data-word. The data-word comprises the 12-, 68*02b829f9SMaxime Roussin-Belanger * 10-, 8-bit input code followed by 4, 6, or 8 don't care bits. 69*02b829f9SMaxime Roussin-Belanger */ 70*02b829f9SMaxime Roussin-Belanger data = (cmd << 20) | (addr << 16) | (val << shift); 71*02b829f9SMaxime Roussin-Belanger msg[0] = data >> 16; 72*02b829f9SMaxime Roussin-Belanger msg[1] = data >> 8; 73*02b829f9SMaxime Roussin-Belanger msg[2] = data; 74*02b829f9SMaxime Roussin-Belanger 75*02b829f9SMaxime Roussin-Belanger return spi_write(spi, msg, sizeof(msg)); 76*02b829f9SMaxime Roussin-Belanger } 77*02b829f9SMaxime Roussin-Belanger 78*02b829f9SMaxime Roussin-Belanger static int ltc2632_read_raw(struct iio_dev *indio_dev, 79*02b829f9SMaxime Roussin-Belanger struct iio_chan_spec const *chan, 80*02b829f9SMaxime Roussin-Belanger int *val, 81*02b829f9SMaxime Roussin-Belanger int *val2, 82*02b829f9SMaxime Roussin-Belanger long m) 83*02b829f9SMaxime Roussin-Belanger { 84*02b829f9SMaxime Roussin-Belanger struct ltc2632_chip_info *chip_info; 85*02b829f9SMaxime Roussin-Belanger 86*02b829f9SMaxime Roussin-Belanger const struct ltc2632_state *st = iio_priv(indio_dev); 87*02b829f9SMaxime Roussin-Belanger const struct spi_device_id *spi_dev_id = spi_get_device_id(st->spi_dev); 88*02b829f9SMaxime Roussin-Belanger 89*02b829f9SMaxime Roussin-Belanger chip_info = (struct ltc2632_chip_info *)spi_dev_id->driver_data; 90*02b829f9SMaxime Roussin-Belanger 91*02b829f9SMaxime Roussin-Belanger switch (m) { 92*02b829f9SMaxime Roussin-Belanger case IIO_CHAN_INFO_SCALE: 93*02b829f9SMaxime Roussin-Belanger *val = chip_info->vref_mv; 94*02b829f9SMaxime Roussin-Belanger *val2 = chan->scan_type.realbits; 95*02b829f9SMaxime Roussin-Belanger return IIO_VAL_FRACTIONAL_LOG2; 96*02b829f9SMaxime Roussin-Belanger } 97*02b829f9SMaxime Roussin-Belanger return -EINVAL; 98*02b829f9SMaxime Roussin-Belanger } 99*02b829f9SMaxime Roussin-Belanger 100*02b829f9SMaxime Roussin-Belanger static int ltc2632_write_raw(struct iio_dev *indio_dev, 101*02b829f9SMaxime Roussin-Belanger struct iio_chan_spec const *chan, 102*02b829f9SMaxime Roussin-Belanger int val, 103*02b829f9SMaxime Roussin-Belanger int val2, 104*02b829f9SMaxime Roussin-Belanger long mask) 105*02b829f9SMaxime Roussin-Belanger { 106*02b829f9SMaxime Roussin-Belanger struct ltc2632_state *st = iio_priv(indio_dev); 107*02b829f9SMaxime Roussin-Belanger 108*02b829f9SMaxime Roussin-Belanger switch (mask) { 109*02b829f9SMaxime Roussin-Belanger case IIO_CHAN_INFO_RAW: 110*02b829f9SMaxime Roussin-Belanger if (val >= (1 << chan->scan_type.realbits) || val < 0) 111*02b829f9SMaxime Roussin-Belanger return -EINVAL; 112*02b829f9SMaxime Roussin-Belanger 113*02b829f9SMaxime Roussin-Belanger return ltc2632_spi_write(st->spi_dev, 114*02b829f9SMaxime Roussin-Belanger LTC2632_CMD_WRITE_INPUT_N_UPDATE_N, 115*02b829f9SMaxime Roussin-Belanger chan->address, val, 116*02b829f9SMaxime Roussin-Belanger chan->scan_type.shift); 117*02b829f9SMaxime Roussin-Belanger default: 118*02b829f9SMaxime Roussin-Belanger return -EINVAL; 119*02b829f9SMaxime Roussin-Belanger } 120*02b829f9SMaxime Roussin-Belanger } 121*02b829f9SMaxime Roussin-Belanger 122*02b829f9SMaxime Roussin-Belanger static ssize_t ltc2632_read_dac_powerdown(struct iio_dev *indio_dev, 123*02b829f9SMaxime Roussin-Belanger uintptr_t private, 124*02b829f9SMaxime Roussin-Belanger const struct iio_chan_spec *chan, 125*02b829f9SMaxime Roussin-Belanger char *buf) 126*02b829f9SMaxime Roussin-Belanger { 127*02b829f9SMaxime Roussin-Belanger struct ltc2632_state *st = iio_priv(indio_dev); 128*02b829f9SMaxime Roussin-Belanger 129*02b829f9SMaxime Roussin-Belanger return sprintf(buf, "%d\n", 130*02b829f9SMaxime Roussin-Belanger !!(st->powerdown_cache_mask & (1 << chan->channel))); 131*02b829f9SMaxime Roussin-Belanger } 132*02b829f9SMaxime Roussin-Belanger 133*02b829f9SMaxime Roussin-Belanger static ssize_t ltc2632_write_dac_powerdown(struct iio_dev *indio_dev, 134*02b829f9SMaxime Roussin-Belanger uintptr_t private, 135*02b829f9SMaxime Roussin-Belanger const struct iio_chan_spec *chan, 136*02b829f9SMaxime Roussin-Belanger const char *buf, 137*02b829f9SMaxime Roussin-Belanger size_t len) 138*02b829f9SMaxime Roussin-Belanger { 139*02b829f9SMaxime Roussin-Belanger bool pwr_down; 140*02b829f9SMaxime Roussin-Belanger int ret; 141*02b829f9SMaxime Roussin-Belanger struct ltc2632_state *st = iio_priv(indio_dev); 142*02b829f9SMaxime Roussin-Belanger 143*02b829f9SMaxime Roussin-Belanger ret = strtobool(buf, &pwr_down); 144*02b829f9SMaxime Roussin-Belanger if (ret) 145*02b829f9SMaxime Roussin-Belanger return ret; 146*02b829f9SMaxime Roussin-Belanger 147*02b829f9SMaxime Roussin-Belanger if (pwr_down) 148*02b829f9SMaxime Roussin-Belanger st->powerdown_cache_mask |= (1 << chan->channel); 149*02b829f9SMaxime Roussin-Belanger else 150*02b829f9SMaxime Roussin-Belanger st->powerdown_cache_mask &= ~(1 << chan->channel); 151*02b829f9SMaxime Roussin-Belanger 152*02b829f9SMaxime Roussin-Belanger ret = ltc2632_spi_write(st->spi_dev, 153*02b829f9SMaxime Roussin-Belanger LTC2632_CMD_POWERDOWN_DAC_N, 154*02b829f9SMaxime Roussin-Belanger chan->channel, 0, 0); 155*02b829f9SMaxime Roussin-Belanger 156*02b829f9SMaxime Roussin-Belanger return ret ? ret : len; 157*02b829f9SMaxime Roussin-Belanger } 158*02b829f9SMaxime Roussin-Belanger 159*02b829f9SMaxime Roussin-Belanger static const struct iio_info ltc2632_info = { 160*02b829f9SMaxime Roussin-Belanger .write_raw = ltc2632_write_raw, 161*02b829f9SMaxime Roussin-Belanger .read_raw = ltc2632_read_raw, 162*02b829f9SMaxime Roussin-Belanger .driver_module = THIS_MODULE, 163*02b829f9SMaxime Roussin-Belanger }; 164*02b829f9SMaxime Roussin-Belanger 165*02b829f9SMaxime Roussin-Belanger static const struct iio_chan_spec_ext_info ltc2632_ext_info[] = { 166*02b829f9SMaxime Roussin-Belanger { 167*02b829f9SMaxime Roussin-Belanger .name = "powerdown", 168*02b829f9SMaxime Roussin-Belanger .read = ltc2632_read_dac_powerdown, 169*02b829f9SMaxime Roussin-Belanger .write = ltc2632_write_dac_powerdown, 170*02b829f9SMaxime Roussin-Belanger .shared = IIO_SEPARATE, 171*02b829f9SMaxime Roussin-Belanger }, 172*02b829f9SMaxime Roussin-Belanger { }, 173*02b829f9SMaxime Roussin-Belanger }; 174*02b829f9SMaxime Roussin-Belanger 175*02b829f9SMaxime Roussin-Belanger #define LTC2632_CHANNEL(_chan, _bits) { \ 176*02b829f9SMaxime Roussin-Belanger .type = IIO_VOLTAGE, \ 177*02b829f9SMaxime Roussin-Belanger .indexed = 1, \ 178*02b829f9SMaxime Roussin-Belanger .output = 1, \ 179*02b829f9SMaxime Roussin-Belanger .channel = (_chan), \ 180*02b829f9SMaxime Roussin-Belanger .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 181*02b829f9SMaxime Roussin-Belanger .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 182*02b829f9SMaxime Roussin-Belanger .address = (_chan), \ 183*02b829f9SMaxime Roussin-Belanger .scan_type = { \ 184*02b829f9SMaxime Roussin-Belanger .realbits = (_bits), \ 185*02b829f9SMaxime Roussin-Belanger .shift = 16 - (_bits), \ 186*02b829f9SMaxime Roussin-Belanger }, \ 187*02b829f9SMaxime Roussin-Belanger .ext_info = ltc2632_ext_info, \ 188*02b829f9SMaxime Roussin-Belanger } 189*02b829f9SMaxime Roussin-Belanger 190*02b829f9SMaxime Roussin-Belanger #define DECLARE_LTC2632_CHANNELS(_name, _bits) \ 191*02b829f9SMaxime Roussin-Belanger const struct iio_chan_spec _name ## _channels[] = { \ 192*02b829f9SMaxime Roussin-Belanger LTC2632_CHANNEL(0, _bits), \ 193*02b829f9SMaxime Roussin-Belanger LTC2632_CHANNEL(1, _bits), \ 194*02b829f9SMaxime Roussin-Belanger } 195*02b829f9SMaxime Roussin-Belanger 196*02b829f9SMaxime Roussin-Belanger static DECLARE_LTC2632_CHANNELS(ltc2632l12, 12); 197*02b829f9SMaxime Roussin-Belanger static DECLARE_LTC2632_CHANNELS(ltc2632l10, 10); 198*02b829f9SMaxime Roussin-Belanger static DECLARE_LTC2632_CHANNELS(ltc2632l8, 8); 199*02b829f9SMaxime Roussin-Belanger 200*02b829f9SMaxime Roussin-Belanger static DECLARE_LTC2632_CHANNELS(ltc2632h12, 12); 201*02b829f9SMaxime Roussin-Belanger static DECLARE_LTC2632_CHANNELS(ltc2632h10, 10); 202*02b829f9SMaxime Roussin-Belanger static DECLARE_LTC2632_CHANNELS(ltc2632h8, 8); 203*02b829f9SMaxime Roussin-Belanger 204*02b829f9SMaxime Roussin-Belanger static const struct ltc2632_chip_info ltc2632_chip_info_tbl[] = { 205*02b829f9SMaxime Roussin-Belanger [ID_LTC2632L12] = { 206*02b829f9SMaxime Roussin-Belanger .channels = ltc2632l12_channels, 207*02b829f9SMaxime Roussin-Belanger .vref_mv = 2500, 208*02b829f9SMaxime Roussin-Belanger }, 209*02b829f9SMaxime Roussin-Belanger [ID_LTC2632L10] = { 210*02b829f9SMaxime Roussin-Belanger .channels = ltc2632l10_channels, 211*02b829f9SMaxime Roussin-Belanger .vref_mv = 2500, 212*02b829f9SMaxime Roussin-Belanger }, 213*02b829f9SMaxime Roussin-Belanger [ID_LTC2632L8] = { 214*02b829f9SMaxime Roussin-Belanger .channels = ltc2632l8_channels, 215*02b829f9SMaxime Roussin-Belanger .vref_mv = 2500, 216*02b829f9SMaxime Roussin-Belanger }, 217*02b829f9SMaxime Roussin-Belanger [ID_LTC2632H12] = { 218*02b829f9SMaxime Roussin-Belanger .channels = ltc2632h12_channels, 219*02b829f9SMaxime Roussin-Belanger .vref_mv = 4096, 220*02b829f9SMaxime Roussin-Belanger }, 221*02b829f9SMaxime Roussin-Belanger [ID_LTC2632H10] = { 222*02b829f9SMaxime Roussin-Belanger .channels = ltc2632h10_channels, 223*02b829f9SMaxime Roussin-Belanger .vref_mv = 4096, 224*02b829f9SMaxime Roussin-Belanger }, 225*02b829f9SMaxime Roussin-Belanger [ID_LTC2632H8] = { 226*02b829f9SMaxime Roussin-Belanger .channels = ltc2632h8_channels, 227*02b829f9SMaxime Roussin-Belanger .vref_mv = 4096, 228*02b829f9SMaxime Roussin-Belanger }, 229*02b829f9SMaxime Roussin-Belanger }; 230*02b829f9SMaxime Roussin-Belanger 231*02b829f9SMaxime Roussin-Belanger static int ltc2632_probe(struct spi_device *spi) 232*02b829f9SMaxime Roussin-Belanger { 233*02b829f9SMaxime Roussin-Belanger struct ltc2632_state *st; 234*02b829f9SMaxime Roussin-Belanger struct iio_dev *indio_dev; 235*02b829f9SMaxime Roussin-Belanger struct ltc2632_chip_info *chip_info; 236*02b829f9SMaxime Roussin-Belanger int ret; 237*02b829f9SMaxime Roussin-Belanger 238*02b829f9SMaxime Roussin-Belanger indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 239*02b829f9SMaxime Roussin-Belanger if (!indio_dev) 240*02b829f9SMaxime Roussin-Belanger return -ENOMEM; 241*02b829f9SMaxime Roussin-Belanger 242*02b829f9SMaxime Roussin-Belanger st = iio_priv(indio_dev); 243*02b829f9SMaxime Roussin-Belanger 244*02b829f9SMaxime Roussin-Belanger spi_set_drvdata(spi, indio_dev); 245*02b829f9SMaxime Roussin-Belanger st->spi_dev = spi; 246*02b829f9SMaxime Roussin-Belanger 247*02b829f9SMaxime Roussin-Belanger chip_info = (struct ltc2632_chip_info *) 248*02b829f9SMaxime Roussin-Belanger spi_get_device_id(spi)->driver_data; 249*02b829f9SMaxime Roussin-Belanger 250*02b829f9SMaxime Roussin-Belanger indio_dev->dev.parent = &spi->dev; 251*02b829f9SMaxime Roussin-Belanger indio_dev->name = dev_of_node(&spi->dev) ? dev_of_node(&spi->dev)->name 252*02b829f9SMaxime Roussin-Belanger : spi_get_device_id(spi)->name; 253*02b829f9SMaxime Roussin-Belanger indio_dev->info = <c2632_info; 254*02b829f9SMaxime Roussin-Belanger indio_dev->modes = INDIO_DIRECT_MODE; 255*02b829f9SMaxime Roussin-Belanger indio_dev->channels = chip_info->channels; 256*02b829f9SMaxime Roussin-Belanger indio_dev->num_channels = LTC2632_DAC_CHANNELS; 257*02b829f9SMaxime Roussin-Belanger 258*02b829f9SMaxime Roussin-Belanger ret = ltc2632_spi_write(spi, LTC2632_CMD_INTERNAL_REFER, 0, 0, 0); 259*02b829f9SMaxime Roussin-Belanger if (ret) { 260*02b829f9SMaxime Roussin-Belanger dev_err(&spi->dev, 261*02b829f9SMaxime Roussin-Belanger "Set internal reference command failed, %d\n", ret); 262*02b829f9SMaxime Roussin-Belanger return ret; 263*02b829f9SMaxime Roussin-Belanger } 264*02b829f9SMaxime Roussin-Belanger 265*02b829f9SMaxime Roussin-Belanger return devm_iio_device_register(&spi->dev, indio_dev); 266*02b829f9SMaxime Roussin-Belanger } 267*02b829f9SMaxime Roussin-Belanger 268*02b829f9SMaxime Roussin-Belanger static const struct spi_device_id ltc2632_id[] = { 269*02b829f9SMaxime Roussin-Belanger { "ltc2632-l12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L12] }, 270*02b829f9SMaxime Roussin-Belanger { "ltc2632-l10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L10] }, 271*02b829f9SMaxime Roussin-Belanger { "ltc2632-l8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L8] }, 272*02b829f9SMaxime Roussin-Belanger { "ltc2632-h12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H12] }, 273*02b829f9SMaxime Roussin-Belanger { "ltc2632-h10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H10] }, 274*02b829f9SMaxime Roussin-Belanger { "ltc2632-h8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H8] }, 275*02b829f9SMaxime Roussin-Belanger {} 276*02b829f9SMaxime Roussin-Belanger }; 277*02b829f9SMaxime Roussin-Belanger MODULE_DEVICE_TABLE(spi, ltc2632_id); 278*02b829f9SMaxime Roussin-Belanger 279*02b829f9SMaxime Roussin-Belanger static struct spi_driver ltc2632_driver = { 280*02b829f9SMaxime Roussin-Belanger .driver = { 281*02b829f9SMaxime Roussin-Belanger .name = "ltc2632", 282*02b829f9SMaxime Roussin-Belanger }, 283*02b829f9SMaxime Roussin-Belanger .probe = ltc2632_probe, 284*02b829f9SMaxime Roussin-Belanger .id_table = ltc2632_id, 285*02b829f9SMaxime Roussin-Belanger }; 286*02b829f9SMaxime Roussin-Belanger module_spi_driver(ltc2632_driver); 287*02b829f9SMaxime Roussin-Belanger 288*02b829f9SMaxime Roussin-Belanger static const struct of_device_id ltc2632_of_match[] = { 289*02b829f9SMaxime Roussin-Belanger { 290*02b829f9SMaxime Roussin-Belanger .compatible = "lltc,ltc2632-l12", 291*02b829f9SMaxime Roussin-Belanger .data = <c2632_chip_info_tbl[ID_LTC2632L12] 292*02b829f9SMaxime Roussin-Belanger }, { 293*02b829f9SMaxime Roussin-Belanger .compatible = "lltc,ltc2632-l10", 294*02b829f9SMaxime Roussin-Belanger .data = <c2632_chip_info_tbl[ID_LTC2632L10] 295*02b829f9SMaxime Roussin-Belanger }, { 296*02b829f9SMaxime Roussin-Belanger .compatible = "lltc,ltc2632-l8", 297*02b829f9SMaxime Roussin-Belanger .data = <c2632_chip_info_tbl[ID_LTC2632L8] 298*02b829f9SMaxime Roussin-Belanger }, { 299*02b829f9SMaxime Roussin-Belanger .compatible = "lltc,ltc2632-h12", 300*02b829f9SMaxime Roussin-Belanger .data = <c2632_chip_info_tbl[ID_LTC2632H12] 301*02b829f9SMaxime Roussin-Belanger }, { 302*02b829f9SMaxime Roussin-Belanger .compatible = "lltc,ltc2632-h10", 303*02b829f9SMaxime Roussin-Belanger .data = <c2632_chip_info_tbl[ID_LTC2632H10] 304*02b829f9SMaxime Roussin-Belanger }, { 305*02b829f9SMaxime Roussin-Belanger .compatible = "lltc,ltc2632-h8", 306*02b829f9SMaxime Roussin-Belanger .data = <c2632_chip_info_tbl[ID_LTC2632H8] 307*02b829f9SMaxime Roussin-Belanger }, 308*02b829f9SMaxime Roussin-Belanger {} 309*02b829f9SMaxime Roussin-Belanger }; 310*02b829f9SMaxime Roussin-Belanger MODULE_DEVICE_TABLE(of, ltc2632_of_match); 311*02b829f9SMaxime Roussin-Belanger 312*02b829f9SMaxime Roussin-Belanger MODULE_AUTHOR("Maxime Roussin-Belanger <maxime.roussinbelanger@gmail.com>"); 313*02b829f9SMaxime Roussin-Belanger MODULE_DESCRIPTION("LTC2632 DAC SPI driver"); 314*02b829f9SMaxime Roussin-Belanger MODULE_LICENSE("GPL v2"); 315