1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices Generic AXI DAC IP core 4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip 5 * 6 * Copyright 2016-2024 Analog Devices Inc. 7 */ 8 #include <linux/adi-axi-common.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/limits.h> 16 #include <linux/kstrtox.h> 17 #include <linux/math.h> 18 #include <linux/math64.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/mutex.h> 22 #include <linux/platform_device.h> 23 #include <linux/property.h> 24 #include <linux/regmap.h> 25 #include <linux/units.h> 26 27 #include <linux/iio/backend.h> 28 #include <linux/iio/buffer-dmaengine.h> 29 #include <linux/iio/buffer.h> 30 #include <linux/iio/iio.h> 31 32 #include "ad3552r-hs.h" 33 34 /* 35 * Register definitions: 36 * https://wiki.analog.com/resources/fpga/docs/axi_dac_ip#register_map 37 */ 38 39 /* Base controls */ 40 #define AXI_DAC_CONFIG_REG 0x0c 41 #define AXI_DAC_CONFIG_DDS_DISABLE BIT(6) 42 43 /* DAC controls */ 44 #define AXI_DAC_RSTN_REG 0x0040 45 #define AXI_DAC_RSTN_CE_N BIT(2) 46 #define AXI_DAC_RSTN_MMCM_RSTN BIT(1) 47 #define AXI_DAC_RSTN_RSTN BIT(0) 48 #define AXI_DAC_CNTRL_1_REG 0x0044 49 #define AXI_DAC_CNTRL_1_SYNC BIT(0) 50 #define AXI_DAC_CNTRL_2_REG 0x0048 51 #define AXI_DAC_CNTRL_2_SDR_DDR_N BIT(16) 52 #define AXI_DAC_CNTRL_2_SYMB_8B BIT(14) 53 #define ADI_DAC_CNTRL_2_R1_MODE BIT(5) 54 #define AXI_DAC_CNTRL_2_UNSIGNED_DATA BIT(4) 55 #define AXI_DAC_STATUS_1_REG 0x0054 56 #define AXI_DAC_STATUS_2_REG 0x0058 57 #define AXI_DAC_DRP_STATUS_REG 0x0074 58 #define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17) 59 #define AXI_DAC_CUSTOM_RD_REG 0x0080 60 #define AXI_DAC_CUSTOM_WR_REG 0x0084 61 #define AXI_DAC_CUSTOM_WR_DATA_8 GENMASK(23, 16) 62 #define AXI_DAC_CUSTOM_WR_DATA_16 GENMASK(23, 8) 63 #define AXI_DAC_UI_STATUS_REG 0x0088 64 #define AXI_DAC_UI_STATUS_IF_BUSY BIT(4) 65 #define AXI_DAC_CUSTOM_CTRL_REG 0x008C 66 #define AXI_DAC_CUSTOM_CTRL_ADDRESS GENMASK(31, 24) 67 #define AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE GENMASK(3, 2) 68 #define AXI_DAC_CUSTOM_CTRL_STREAM BIT(1) 69 #define AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA BIT(0) 70 71 #define AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE (AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA | \ 72 AXI_DAC_CUSTOM_CTRL_STREAM) 73 74 /* DAC Channel controls */ 75 #define AXI_DAC_CHAN_CNTRL_1_REG(c) (0x0400 + (c) * 0x40) 76 #define AXI_DAC_CHAN_CNTRL_3_REG(c) (0x0408 + (c) * 0x40) 77 #define AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN BIT(15) 78 #define AXI_DAC_CHAN_CNTRL_3_SCALE_INT BIT(14) 79 #define AXI_DAC_CHAN_CNTRL_3_SCALE GENMASK(14, 0) 80 #define AXI_DAC_CHAN_CNTRL_2_REG(c) (0x0404 + (c) * 0x40) 81 #define AXI_DAC_CHAN_CNTRL_2_PHASE GENMASK(31, 16) 82 #define AXI_DAC_CHAN_CNTRL_2_FREQUENCY GENMASK(15, 0) 83 #define AXI_DAC_CHAN_CNTRL_4_REG(c) (0x040c + (c) * 0x40) 84 #define AXI_DAC_CHAN_CNTRL_7_REG(c) (0x0418 + (c) * 0x40) 85 #define AXI_DAC_CHAN_CNTRL_7_DATA_SEL GENMASK(3, 0) 86 87 #define AXI_DAC_CHAN_CNTRL_MAX 15 88 #define AXI_DAC_RD_ADDR(x) (BIT(7) | (x)) 89 90 /* 360 degrees in rad */ 91 #define AXI_DAC_2_PI_MEGA 6283190 92 93 enum { 94 AXI_DAC_DATA_INTERNAL_TONE, 95 AXI_DAC_DATA_DMA = 2, 96 AXI_DAC_DATA_INTERNAL_RAMP_16BIT = 11, 97 }; 98 99 struct axi_dac_info { 100 unsigned int version; 101 const struct iio_backend_info *backend_info; 102 bool has_dac_clk; 103 bool has_child_nodes; 104 }; 105 106 struct axi_dac_state { 107 struct regmap *regmap; 108 struct device *dev; 109 /* 110 * lock to protect multiple accesses to the device registers and global 111 * data/variables. 112 */ 113 struct mutex lock; 114 const struct axi_dac_info *info; 115 u64 dac_clk; 116 u32 reg_config; 117 int dac_clk_rate; 118 }; 119 120 static int axi_dac_enable(struct iio_backend *back) 121 { 122 struct axi_dac_state *st = iio_backend_get_priv(back); 123 unsigned int __val; 124 int ret; 125 126 guard(mutex)(&st->lock); 127 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, 128 AXI_DAC_RSTN_MMCM_RSTN); 129 if (ret) 130 return ret; 131 /* 132 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all 133 * designs really use it but if they don't we still get the lock bit 134 * set. So let's do it all the time so the code is generic. 135 */ 136 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, 137 __val, 138 __val & AXI_DAC_DRP_STATUS_DRP_LOCKED, 139 100, 1000); 140 if (ret) 141 return ret; 142 143 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, 144 AXI_DAC_RSTN_RSTN | AXI_DAC_RSTN_MMCM_RSTN); 145 } 146 147 static void axi_dac_disable(struct iio_backend *back) 148 { 149 struct axi_dac_state *st = iio_backend_get_priv(back); 150 151 guard(mutex)(&st->lock); 152 regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); 153 } 154 155 static struct iio_buffer *axi_dac_request_buffer(struct iio_backend *back, 156 struct iio_dev *indio_dev) 157 { 158 struct axi_dac_state *st = iio_backend_get_priv(back); 159 const char *dma_name; 160 161 if (device_property_read_string(st->dev, "dma-names", &dma_name)) 162 dma_name = "tx"; 163 164 return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name, 165 IIO_BUFFER_DIRECTION_OUT); 166 } 167 168 static void axi_dac_free_buffer(struct iio_backend *back, 169 struct iio_buffer *buffer) 170 { 171 iio_dmaengine_buffer_teardown(buffer); 172 } 173 174 enum { 175 AXI_DAC_FREQ_TONE_1, 176 AXI_DAC_FREQ_TONE_2, 177 AXI_DAC_SCALE_TONE_1, 178 AXI_DAC_SCALE_TONE_2, 179 AXI_DAC_PHASE_TONE_1, 180 AXI_DAC_PHASE_TONE_2, 181 }; 182 183 static int __axi_dac_frequency_get(struct axi_dac_state *st, unsigned int chan, 184 unsigned int tone_2, unsigned int *freq) 185 { 186 u32 reg, raw; 187 int ret; 188 189 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 190 return -EINVAL; 191 192 if (!st->dac_clk) { 193 dev_err(st->dev, "Sampling rate is 0...\n"); 194 return -EINVAL; 195 } 196 197 if (tone_2) 198 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan); 199 else 200 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan); 201 202 ret = regmap_read(st->regmap, reg, &raw); 203 if (ret) 204 return ret; 205 206 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw); 207 *freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16)); 208 209 return 0; 210 } 211 212 static int axi_dac_frequency_get(struct axi_dac_state *st, 213 const struct iio_chan_spec *chan, char *buf, 214 unsigned int tone_2) 215 { 216 unsigned int freq; 217 int ret; 218 219 scoped_guard(mutex, &st->lock) { 220 ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq); 221 if (ret) 222 return ret; 223 } 224 225 return sysfs_emit(buf, "%u\n", freq); 226 } 227 228 static int axi_dac_scale_get(struct axi_dac_state *st, 229 const struct iio_chan_spec *chan, char *buf, 230 unsigned int tone_2) 231 { 232 unsigned int scale, sign; 233 int ret, vals[2]; 234 u32 reg, raw; 235 236 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) 237 return -EINVAL; 238 239 if (tone_2) 240 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); 241 else 242 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); 243 244 ret = regmap_read(st->regmap, reg, &raw); 245 if (ret) 246 return ret; 247 248 sign = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, raw); 249 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE, raw); 250 scale = DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA, 251 AXI_DAC_CHAN_CNTRL_3_SCALE_INT); 252 253 vals[0] = scale / MEGA; 254 vals[1] = scale % MEGA; 255 256 if (sign) { 257 vals[0] *= -1; 258 if (!vals[0]) 259 vals[1] *= -1; 260 } 261 262 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals), 263 vals); 264 } 265 266 static int axi_dac_phase_get(struct axi_dac_state *st, 267 const struct iio_chan_spec *chan, char *buf, 268 unsigned int tone_2) 269 { 270 u32 reg, raw, phase; 271 int ret, vals[2]; 272 273 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) 274 return -EINVAL; 275 276 if (tone_2) 277 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); 278 else 279 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); 280 281 ret = regmap_read(st->regmap, reg, &raw); 282 if (ret) 283 return ret; 284 285 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_PHASE, raw); 286 phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX); 287 288 vals[0] = phase / MEGA; 289 vals[1] = phase % MEGA; 290 291 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals), 292 vals); 293 } 294 295 static int __axi_dac_frequency_set(struct axi_dac_state *st, unsigned int chan, 296 u64 sample_rate, unsigned int freq, 297 unsigned int tone_2) 298 { 299 u32 reg; 300 u16 raw; 301 int ret; 302 303 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 304 return -EINVAL; 305 306 if (!sample_rate || freq > sample_rate / 2) { 307 dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n", 308 freq, sample_rate); 309 return -EINVAL; 310 } 311 312 if (tone_2) 313 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan); 314 else 315 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan); 316 317 raw = DIV64_U64_ROUND_CLOSEST((u64)freq * BIT(16), sample_rate); 318 319 ret = regmap_update_bits(st->regmap, reg, 320 AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw); 321 if (ret) 322 return ret; 323 324 /* synchronize channels */ 325 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, 326 AXI_DAC_CNTRL_1_SYNC); 327 } 328 329 static int axi_dac_frequency_set(struct axi_dac_state *st, 330 const struct iio_chan_spec *chan, 331 const char *buf, size_t len, unsigned int tone_2) 332 { 333 unsigned int freq; 334 int ret; 335 336 ret = kstrtou32(buf, 10, &freq); 337 if (ret) 338 return ret; 339 340 guard(mutex)(&st->lock); 341 ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq, 342 tone_2); 343 if (ret) 344 return ret; 345 346 return len; 347 } 348 349 static int axi_dac_scale_set(struct axi_dac_state *st, 350 const struct iio_chan_spec *chan, 351 const char *buf, size_t len, unsigned int tone_2) 352 { 353 int integer, frac, scale; 354 u32 raw = 0, reg; 355 int ret; 356 357 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) 358 return -EINVAL; 359 360 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac); 361 if (ret) 362 return ret; 363 364 scale = integer * MEGA + frac; 365 if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA) 366 return -EINVAL; 367 368 /* format is 1.1.14 (sign, integer and fractional bits) */ 369 if (scale < 0) { 370 raw = FIELD_PREP(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, 1); 371 scale *= -1; 372 } 373 374 raw |= div_u64((u64)scale * AXI_DAC_CHAN_CNTRL_3_SCALE_INT, MEGA); 375 376 if (tone_2) 377 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); 378 else 379 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); 380 381 guard(mutex)(&st->lock); 382 ret = regmap_write(st->regmap, reg, raw); 383 if (ret) 384 return ret; 385 386 /* synchronize channels */ 387 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, 388 AXI_DAC_CNTRL_1_SYNC); 389 if (ret) 390 return ret; 391 392 return len; 393 } 394 395 static int axi_dac_phase_set(struct axi_dac_state *st, 396 const struct iio_chan_spec *chan, 397 const char *buf, size_t len, unsigned int tone_2) 398 { 399 int integer, frac, phase; 400 u32 raw, reg; 401 int ret; 402 403 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) 404 return -EINVAL; 405 406 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac); 407 if (ret) 408 return ret; 409 410 phase = integer * MEGA + frac; 411 if (phase < 0 || phase > AXI_DAC_2_PI_MEGA) 412 return -EINVAL; 413 414 raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA); 415 416 if (tone_2) 417 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); 418 else 419 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); 420 421 guard(mutex)(&st->lock); 422 ret = regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE, 423 FIELD_PREP(AXI_DAC_CHAN_CNTRL_2_PHASE, raw)); 424 if (ret) 425 return ret; 426 427 /* synchronize channels */ 428 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, 429 AXI_DAC_CNTRL_1_SYNC); 430 if (ret) 431 return ret; 432 433 return len; 434 } 435 436 static int axi_dac_ext_info_set(struct iio_backend *back, uintptr_t private, 437 const struct iio_chan_spec *chan, 438 const char *buf, size_t len) 439 { 440 struct axi_dac_state *st = iio_backend_get_priv(back); 441 442 switch (private) { 443 case AXI_DAC_FREQ_TONE_1: 444 case AXI_DAC_FREQ_TONE_2: 445 return axi_dac_frequency_set(st, chan, buf, len, 446 private == AXI_DAC_FREQ_TONE_2); 447 case AXI_DAC_SCALE_TONE_1: 448 case AXI_DAC_SCALE_TONE_2: 449 return axi_dac_scale_set(st, chan, buf, len, 450 private == AXI_DAC_SCALE_TONE_2); 451 case AXI_DAC_PHASE_TONE_1: 452 case AXI_DAC_PHASE_TONE_2: 453 return axi_dac_phase_set(st, chan, buf, len, 454 private == AXI_DAC_PHASE_TONE_2); 455 default: 456 return -EOPNOTSUPP; 457 } 458 } 459 460 static int axi_dac_ext_info_get(struct iio_backend *back, uintptr_t private, 461 const struct iio_chan_spec *chan, char *buf) 462 { 463 struct axi_dac_state *st = iio_backend_get_priv(back); 464 465 switch (private) { 466 case AXI_DAC_FREQ_TONE_1: 467 case AXI_DAC_FREQ_TONE_2: 468 return axi_dac_frequency_get(st, chan, buf, 469 private - AXI_DAC_FREQ_TONE_1); 470 case AXI_DAC_SCALE_TONE_1: 471 case AXI_DAC_SCALE_TONE_2: 472 return axi_dac_scale_get(st, chan, buf, 473 private - AXI_DAC_SCALE_TONE_1); 474 case AXI_DAC_PHASE_TONE_1: 475 case AXI_DAC_PHASE_TONE_2: 476 return axi_dac_phase_get(st, chan, buf, 477 private - AXI_DAC_PHASE_TONE_1); 478 default: 479 return -EOPNOTSUPP; 480 } 481 } 482 483 static const struct iio_chan_spec_ext_info axi_dac_ext_info[] = { 484 IIO_BACKEND_EX_INFO("frequency0", IIO_SEPARATE, AXI_DAC_FREQ_TONE_1), 485 IIO_BACKEND_EX_INFO("frequency1", IIO_SEPARATE, AXI_DAC_FREQ_TONE_2), 486 IIO_BACKEND_EX_INFO("scale0", IIO_SEPARATE, AXI_DAC_SCALE_TONE_1), 487 IIO_BACKEND_EX_INFO("scale1", IIO_SEPARATE, AXI_DAC_SCALE_TONE_2), 488 IIO_BACKEND_EX_INFO("phase0", IIO_SEPARATE, AXI_DAC_PHASE_TONE_1), 489 IIO_BACKEND_EX_INFO("phase1", IIO_SEPARATE, AXI_DAC_PHASE_TONE_2), 490 { } 491 }; 492 493 static int axi_dac_extend_chan(struct iio_backend *back, 494 struct iio_chan_spec *chan) 495 { 496 struct axi_dac_state *st = iio_backend_get_priv(back); 497 498 if (chan->type != IIO_ALTVOLTAGE) 499 return -EINVAL; 500 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) 501 /* nothing to extend */ 502 return 0; 503 504 chan->ext_info = axi_dac_ext_info; 505 506 return 0; 507 } 508 509 static int axi_dac_data_source_set(struct iio_backend *back, unsigned int chan, 510 enum iio_backend_data_source data) 511 { 512 struct axi_dac_state *st = iio_backend_get_priv(back); 513 514 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 515 return -EINVAL; 516 517 switch (data) { 518 case IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE: 519 return regmap_update_bits(st->regmap, 520 AXI_DAC_CHAN_CNTRL_7_REG(chan), 521 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, 522 AXI_DAC_DATA_INTERNAL_TONE); 523 case IIO_BACKEND_EXTERNAL: 524 return regmap_update_bits(st->regmap, 525 AXI_DAC_CHAN_CNTRL_7_REG(chan), 526 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, 527 AXI_DAC_DATA_DMA); 528 case IIO_BACKEND_INTERNAL_RAMP_16BIT: 529 return regmap_update_bits(st->regmap, 530 AXI_DAC_CHAN_CNTRL_7_REG(chan), 531 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, 532 AXI_DAC_DATA_INTERNAL_RAMP_16BIT); 533 default: 534 return -EINVAL; 535 } 536 } 537 538 static int axi_dac_data_source_get(struct iio_backend *back, unsigned int chan, 539 enum iio_backend_data_source *data) 540 { 541 struct axi_dac_state *st = iio_backend_get_priv(back); 542 int ret; 543 u32 val; 544 545 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 546 return -EINVAL; 547 548 ret = regmap_read(st->regmap, AXI_DAC_CHAN_CNTRL_7_REG(chan), &val); 549 if (ret) 550 return ret; 551 552 switch (val) { 553 case AXI_DAC_DATA_INTERNAL_TONE: 554 *data = IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE; 555 return 0; 556 case AXI_DAC_DATA_DMA: 557 *data = IIO_BACKEND_EXTERNAL; 558 return 0; 559 case AXI_DAC_DATA_INTERNAL_RAMP_16BIT: 560 *data = IIO_BACKEND_INTERNAL_RAMP_16BIT; 561 return 0; 562 default: 563 return -EIO; 564 } 565 } 566 567 static int axi_dac_set_sample_rate(struct iio_backend *back, unsigned int chan, 568 u64 sample_rate) 569 { 570 struct axi_dac_state *st = iio_backend_get_priv(back); 571 unsigned int freq; 572 int ret, tone; 573 574 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 575 return -EINVAL; 576 if (!sample_rate) 577 return -EINVAL; 578 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) 579 /* sample_rate has no meaning if DDS is disabled */ 580 return 0; 581 582 guard(mutex)(&st->lock); 583 /* 584 * If dac_clk is 0 then this must be the first time we're being notified 585 * about the interface sample rate. Hence, just update our internal 586 * variable and bail... If it's not 0, then we get the current DDS 587 * frequency (for the old rate) and update the registers for the new 588 * sample rate. 589 */ 590 if (!st->dac_clk) { 591 st->dac_clk = sample_rate; 592 return 0; 593 } 594 595 for (tone = 0; tone <= AXI_DAC_FREQ_TONE_2; tone++) { 596 ret = __axi_dac_frequency_get(st, chan, tone, &freq); 597 if (ret) 598 return ret; 599 600 ret = __axi_dac_frequency_set(st, chan, sample_rate, tone, freq); 601 if (ret) 602 return ret; 603 } 604 605 st->dac_clk = sample_rate; 606 607 return 0; 608 } 609 610 static int axi_dac_reg_access(struct iio_backend *back, unsigned int reg, 611 unsigned int writeval, unsigned int *readval) 612 { 613 struct axi_dac_state *st = iio_backend_get_priv(back); 614 615 if (readval) 616 return regmap_read(st->regmap, reg, readval); 617 618 return regmap_write(st->regmap, reg, writeval); 619 } 620 621 static int axi_dac_ddr_enable(struct iio_backend *back) 622 { 623 struct axi_dac_state *st = iio_backend_get_priv(back); 624 625 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 626 AXI_DAC_CNTRL_2_SDR_DDR_N); 627 } 628 629 static int axi_dac_ddr_disable(struct iio_backend *back) 630 { 631 struct axi_dac_state *st = iio_backend_get_priv(back); 632 633 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 634 AXI_DAC_CNTRL_2_SDR_DDR_N); 635 } 636 637 static int axi_dac_wait_bus_free(struct axi_dac_state *st) 638 { 639 u32 val; 640 int ret; 641 642 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_UI_STATUS_REG, val, 643 FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, val) == 0, 10, 644 100 * KILO); 645 if (ret == -ETIMEDOUT) 646 dev_err(st->dev, "AXI bus timeout\n"); 647 648 return ret; 649 } 650 651 static int axi_dac_data_stream_enable(struct iio_backend *back) 652 { 653 struct axi_dac_state *st = iio_backend_get_priv(back); 654 int ret; 655 656 ret = axi_dac_wait_bus_free(st); 657 if (ret) 658 return ret; 659 660 return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 661 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE); 662 } 663 664 static int axi_dac_data_stream_disable(struct iio_backend *back) 665 { 666 struct axi_dac_state *st = iio_backend_get_priv(back); 667 668 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 669 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE); 670 } 671 672 static int axi_dac_data_transfer_addr(struct iio_backend *back, u32 address) 673 { 674 struct axi_dac_state *st = iio_backend_get_priv(back); 675 676 if (address > FIELD_MAX(AXI_DAC_CUSTOM_CTRL_ADDRESS)) 677 return -EINVAL; 678 679 /* 680 * Sample register address, when the DAC is configured, or stream 681 * start address when the FSM is in stream state. 682 */ 683 return regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 684 AXI_DAC_CUSTOM_CTRL_ADDRESS, 685 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, 686 address)); 687 } 688 689 static int axi_dac_data_format_set(struct iio_backend *back, unsigned int ch, 690 const struct iio_backend_data_fmt *data) 691 { 692 struct axi_dac_state *st = iio_backend_get_priv(back); 693 694 switch (data->type) { 695 case IIO_BACKEND_DATA_UNSIGNED: 696 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 697 AXI_DAC_CNTRL_2_UNSIGNED_DATA); 698 default: 699 return -EINVAL; 700 } 701 } 702 703 static int __axi_dac_bus_reg_write(struct iio_backend *back, u32 reg, 704 u32 val, size_t data_size) 705 { 706 struct axi_dac_state *st = iio_backend_get_priv(back); 707 int ret; 708 u32 ival; 709 710 /* 711 * Both AXI_DAC_CNTRL_2_REG and AXI_DAC_CUSTOM_WR_REG need to know 712 * the data size. So keeping data size control here only, 713 * since data size is mandatory for the current transfer. 714 * DDR state handled separately by specific backend calls, 715 * generally all raw register writes are SDR. 716 */ 717 if (data_size == sizeof(u16)) 718 ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_16, val); 719 else 720 ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_8, val); 721 722 ret = regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival); 723 if (ret) 724 return ret; 725 726 if (data_size == sizeof(u8)) 727 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 728 AXI_DAC_CNTRL_2_SYMB_8B); 729 else 730 ret = regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 731 AXI_DAC_CNTRL_2_SYMB_8B); 732 if (ret) 733 return ret; 734 735 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 736 AXI_DAC_CUSTOM_CTRL_ADDRESS, 737 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, reg)); 738 if (ret) 739 return ret; 740 741 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 742 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA, 743 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA); 744 if (ret) 745 return ret; 746 747 ret = axi_dac_wait_bus_free(st); 748 if (ret) 749 return ret; 750 751 /* Cleaning always AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA */ 752 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 753 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA); 754 } 755 756 static int axi_dac_bus_reg_write(struct iio_backend *back, u32 reg, 757 u32 val, size_t data_size) 758 { 759 struct axi_dac_state *st = iio_backend_get_priv(back); 760 761 guard(mutex)(&st->lock); 762 return __axi_dac_bus_reg_write(back, reg, val, data_size); 763 } 764 765 static int axi_dac_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val, 766 size_t data_size) 767 { 768 struct axi_dac_state *st = iio_backend_get_priv(back); 769 int ret; 770 771 guard(mutex)(&st->lock); 772 773 /* 774 * SPI, we write with read flag, then we read just at the AXI 775 * io address space to get data read. 776 */ 777 ret = __axi_dac_bus_reg_write(back, AXI_DAC_RD_ADDR(reg), 0, 778 data_size); 779 if (ret) 780 return ret; 781 782 ret = axi_dac_wait_bus_free(st); 783 if (ret) 784 return ret; 785 786 return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val); 787 } 788 789 static int axi_dac_bus_set_io_mode(struct iio_backend *back, 790 enum ad3552r_io_mode mode) 791 { 792 struct axi_dac_state *st = iio_backend_get_priv(back); 793 int ret; 794 795 if (mode > AD3552R_IO_MODE_QSPI) 796 return -EINVAL; 797 798 guard(mutex)(&st->lock); 799 800 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 801 AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, 802 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, mode)); 803 if (ret) 804 return ret; 805 806 return axi_dac_wait_bus_free(st); 807 } 808 809 static void axi_dac_child_remove(void *data) 810 { 811 platform_device_unregister(data); 812 } 813 814 static int axi_dac_create_platform_device(struct axi_dac_state *st, 815 struct fwnode_handle *child) 816 { 817 struct ad3552r_hs_platform_data pdata = { 818 .bus_reg_read = axi_dac_bus_reg_read, 819 .bus_reg_write = axi_dac_bus_reg_write, 820 .bus_set_io_mode = axi_dac_bus_set_io_mode, 821 .bus_sample_data_clock_hz = st->dac_clk_rate, 822 }; 823 struct platform_device_info pi = { 824 .parent = st->dev, 825 .name = fwnode_get_name(child), 826 .id = PLATFORM_DEVID_AUTO, 827 .fwnode = child, 828 .data = &pdata, 829 .size_data = sizeof(pdata), 830 }; 831 struct platform_device *pdev; 832 833 pdev = platform_device_register_full(&pi); 834 if (IS_ERR(pdev)) 835 return PTR_ERR(pdev); 836 837 return devm_add_action_or_reset(st->dev, axi_dac_child_remove, pdev); 838 } 839 840 static const struct iio_backend_ops axi_dac_generic_ops = { 841 .enable = axi_dac_enable, 842 .disable = axi_dac_disable, 843 .request_buffer = axi_dac_request_buffer, 844 .free_buffer = axi_dac_free_buffer, 845 .extend_chan_spec = axi_dac_extend_chan, 846 .ext_info_set = axi_dac_ext_info_set, 847 .ext_info_get = axi_dac_ext_info_get, 848 .data_source_set = axi_dac_data_source_set, 849 .set_sample_rate = axi_dac_set_sample_rate, 850 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_dac_reg_access), 851 }; 852 853 static const struct iio_backend_ops axi_ad3552r_ops = { 854 .enable = axi_dac_enable, 855 .disable = axi_dac_disable, 856 .request_buffer = axi_dac_request_buffer, 857 .free_buffer = axi_dac_free_buffer, 858 .data_source_set = axi_dac_data_source_set, 859 .data_source_get = axi_dac_data_source_get, 860 .ddr_enable = axi_dac_ddr_enable, 861 .ddr_disable = axi_dac_ddr_disable, 862 .data_stream_enable = axi_dac_data_stream_enable, 863 .data_stream_disable = axi_dac_data_stream_disable, 864 .data_format_set = axi_dac_data_format_set, 865 .data_transfer_addr = axi_dac_data_transfer_addr, 866 }; 867 868 static const struct iio_backend_info axi_dac_generic = { 869 .name = "axi-dac", 870 .ops = &axi_dac_generic_ops, 871 .caps = IIO_BACKEND_CAP_BUFFER | IIO_BACKEND_CAP_ENABLE, 872 }; 873 874 static const struct iio_backend_info axi_ad3552r = { 875 .name = "axi-ad3552r", 876 .ops = &axi_ad3552r_ops, 877 .caps = IIO_BACKEND_CAP_BUFFER | IIO_BACKEND_CAP_ENABLE, 878 }; 879 880 static const struct regmap_config axi_dac_regmap_config = { 881 .val_bits = 32, 882 .reg_bits = 32, 883 .reg_stride = 4, 884 .max_register = 0x0800, 885 }; 886 887 static int axi_dac_probe(struct platform_device *pdev) 888 { 889 struct device *dev = &pdev->dev; 890 struct axi_dac_state *st; 891 void __iomem *base; 892 unsigned int ver; 893 struct clk *clk; 894 int ret; 895 896 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 897 if (!st) 898 return -ENOMEM; 899 900 st->info = device_get_match_data(dev); 901 if (!st->info) 902 return -ENODEV; 903 clk = devm_clk_get_enabled(dev, "s_axi_aclk"); 904 if (IS_ERR(clk)) { 905 /* Backward compat., old fdt versions without clock-names. */ 906 clk = devm_clk_get_enabled(dev, NULL); 907 if (IS_ERR(clk)) 908 return dev_err_probe(dev, PTR_ERR(clk), 909 "failed to get clock\n"); 910 } 911 912 if (st->info->has_dac_clk) { 913 struct clk *dac_clk; 914 915 dac_clk = devm_clk_get_enabled(dev, "dac_clk"); 916 if (IS_ERR(dac_clk)) 917 return dev_err_probe(dev, PTR_ERR(dac_clk), 918 "failed to get dac_clk clock\n"); 919 920 /* We only care about the streaming mode rate */ 921 st->dac_clk_rate = clk_get_rate(dac_clk) / 2; 922 } 923 924 base = devm_platform_ioremap_resource(pdev, 0); 925 if (IS_ERR(base)) 926 return PTR_ERR(base); 927 928 st->dev = dev; 929 st->regmap = devm_regmap_init_mmio(dev, base, &axi_dac_regmap_config); 930 if (IS_ERR(st->regmap)) 931 return dev_err_probe(dev, PTR_ERR(st->regmap), 932 "failed to init register map\n"); 933 934 /* 935 * Force disable the core. Up to the frontend to enable us. And we can 936 * still read/write registers... 937 */ 938 ret = regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); 939 if (ret) 940 return ret; 941 942 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); 943 if (ret) 944 return ret; 945 946 if (ADI_AXI_PCORE_VER_MAJOR(ver) != ADI_AXI_PCORE_VER_MAJOR(st->info->version)) 947 return dev_err_probe(dev, -ENODEV, 948 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 949 ADI_AXI_PCORE_VER_MAJOR(st->info->version), 950 ADI_AXI_PCORE_VER_MINOR(st->info->version), 951 ADI_AXI_PCORE_VER_PATCH(st->info->version), 952 ADI_AXI_PCORE_VER_MAJOR(ver), 953 ADI_AXI_PCORE_VER_MINOR(ver), 954 ADI_AXI_PCORE_VER_PATCH(ver)); 955 956 /* Let's get the core read only configuration */ 957 ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config); 958 if (ret) 959 return ret; 960 961 /* 962 * In some designs, setting the R1_MODE bit to 0 (which is the default 963 * value) causes all channels of the frontend to be routed to the same 964 * DMA (so they are sampled together). This is for things like 965 * Multiple-Input and Multiple-Output (MIMO). As most of the times we 966 * want independent channels let's override the core's default value and 967 * set the R1_MODE bit. 968 */ 969 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 970 ADI_DAC_CNTRL_2_R1_MODE); 971 if (ret) 972 return ret; 973 974 mutex_init(&st->lock); 975 976 ret = devm_iio_backend_register(dev, st->info->backend_info, st); 977 if (ret) 978 return dev_err_probe(dev, ret, 979 "failed to register iio backend\n"); 980 981 device_for_each_child_node_scoped(dev, child) { 982 int val; 983 984 if (!st->info->has_child_nodes) 985 return dev_err_probe(dev, -EINVAL, 986 "invalid fdt axi-dac compatible."); 987 988 /* Processing only reg 0 node */ 989 ret = fwnode_property_read_u32(child, "reg", &val); 990 if (ret) 991 return dev_err_probe(dev, ret, "invalid reg property."); 992 if (val != 0) 993 return dev_err_probe(dev, -EINVAL, 994 "invalid node address."); 995 996 ret = axi_dac_create_platform_device(st, child); 997 if (ret) 998 return dev_err_probe(dev, -EINVAL, 999 "cannot create device."); 1000 } 1001 1002 dev_info(dev, "AXI DAC IP core (%d.%.2d.%c) probed\n", 1003 ADI_AXI_PCORE_VER_MAJOR(ver), 1004 ADI_AXI_PCORE_VER_MINOR(ver), 1005 ADI_AXI_PCORE_VER_PATCH(ver)); 1006 1007 return 0; 1008 } 1009 1010 static const struct axi_dac_info dac_generic = { 1011 .version = ADI_AXI_PCORE_VER(9, 1, 'b'), 1012 .backend_info = &axi_dac_generic, 1013 }; 1014 1015 static const struct axi_dac_info dac_ad3552r = { 1016 .version = ADI_AXI_PCORE_VER(9, 1, 'b'), 1017 .backend_info = &axi_ad3552r, 1018 .has_dac_clk = true, 1019 .has_child_nodes = true, 1020 }; 1021 1022 static const struct of_device_id axi_dac_of_match[] = { 1023 { .compatible = "adi,axi-dac-9.1.b", .data = &dac_generic }, 1024 { .compatible = "adi,axi-ad3552r", .data = &dac_ad3552r }, 1025 { } 1026 }; 1027 MODULE_DEVICE_TABLE(of, axi_dac_of_match); 1028 1029 static struct platform_driver axi_dac_driver = { 1030 .driver = { 1031 .name = "adi-axi-dac", 1032 .of_match_table = axi_dac_of_match, 1033 }, 1034 .probe = axi_dac_probe, 1035 }; 1036 module_platform_driver(axi_dac_driver); 1037 1038 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1039 MODULE_DESCRIPTION("Analog Devices Generic AXI DAC IP core driver"); 1040 MODULE_LICENSE("GPL"); 1041 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 1042 MODULE_IMPORT_NS("IIO_BACKEND"); 1043