1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices Generic AXI DAC IP core 4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip 5 * 6 * Copyright 2016-2024 Analog Devices Inc. 7 */ 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/limits.h> 15 #include <linux/kstrtox.h> 16 #include <linux/math.h> 17 #include <linux/math64.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/mutex.h> 21 #include <linux/platform_device.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/units.h> 25 26 #include <linux/fpga/adi-axi-common.h> 27 #include <linux/iio/backend.h> 28 #include <linux/iio/buffer-dmaengine.h> 29 #include <linux/iio/buffer.h> 30 #include <linux/iio/iio.h> 31 32 /* 33 * Register definitions: 34 * https://wiki.analog.com/resources/fpga/docs/axi_dac_ip#register_map 35 */ 36 37 /* Base controls */ 38 #define AXI_DAC_CONFIG_REG 0x0c 39 #define AXI_DAC_CONFIG_DDS_DISABLE BIT(6) 40 41 /* DAC controls */ 42 #define AXI_DAC_RSTN_REG 0x0040 43 #define AXI_DAC_RSTN_CE_N BIT(2) 44 #define AXI_DAC_RSTN_MMCM_RSTN BIT(1) 45 #define AXI_DAC_RSTN_RSTN BIT(0) 46 #define AXI_DAC_CNTRL_1_REG 0x0044 47 #define AXI_DAC_CNTRL_1_SYNC BIT(0) 48 #define AXI_DAC_CNTRL_2_REG 0x0048 49 #define ADI_DAC_CNTRL_2_R1_MODE BIT(5) 50 #define AXI_DAC_DRP_STATUS_REG 0x0074 51 #define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17) 52 53 /* DAC Channel controls */ 54 #define AXI_DAC_CHAN_CNTRL_1_REG(c) (0x0400 + (c) * 0x40) 55 #define AXI_DAC_CHAN_CNTRL_3_REG(c) (0x0408 + (c) * 0x40) 56 #define AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN BIT(15) 57 #define AXI_DAC_CHAN_CNTRL_3_SCALE_INT BIT(14) 58 #define AXI_DAC_CHAN_CNTRL_3_SCALE GENMASK(14, 0) 59 #define AXI_DAC_CHAN_CNTRL_2_REG(c) (0x0404 + (c) * 0x40) 60 #define AXI_DAC_CHAN_CNTRL_2_PHASE GENMASK(31, 16) 61 #define AXI_DAC_CHAN_CNTRL_2_FREQUENCY GENMASK(15, 0) 62 #define AXI_DAC_CHAN_CNTRL_4_REG(c) (0x040c + (c) * 0x40) 63 #define AXI_DAC_CHAN_CNTRL_7_REG(c) (0x0418 + (c) * 0x40) 64 #define AXI_DAC_CHAN_CNTRL_7_DATA_SEL GENMASK(3, 0) 65 66 /* 360 degrees in rad */ 67 #define AXI_DAC_2_PI_MEGA 6283190 68 69 enum { 70 AXI_DAC_DATA_INTERNAL_TONE, 71 AXI_DAC_DATA_DMA = 2, 72 }; 73 74 struct axi_dac_state { 75 struct regmap *regmap; 76 struct device *dev; 77 /* 78 * lock to protect multiple accesses to the device registers and global 79 * data/variables. 80 */ 81 struct mutex lock; 82 u64 dac_clk; 83 u32 reg_config; 84 bool int_tone; 85 }; 86 87 static int axi_dac_enable(struct iio_backend *back) 88 { 89 struct axi_dac_state *st = iio_backend_get_priv(back); 90 unsigned int __val; 91 int ret; 92 93 guard(mutex)(&st->lock); 94 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, 95 AXI_DAC_RSTN_MMCM_RSTN); 96 if (ret) 97 return ret; 98 /* 99 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all 100 * designs really use it but if they don't we still get the lock bit 101 * set. So let's do it all the time so the code is generic. 102 */ 103 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, 104 __val, 105 __val & AXI_DAC_DRP_STATUS_DRP_LOCKED, 106 100, 1000); 107 if (ret) 108 return ret; 109 110 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, 111 AXI_DAC_RSTN_RSTN | AXI_DAC_RSTN_MMCM_RSTN); 112 } 113 114 static void axi_dac_disable(struct iio_backend *back) 115 { 116 struct axi_dac_state *st = iio_backend_get_priv(back); 117 118 guard(mutex)(&st->lock); 119 regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); 120 } 121 122 static struct iio_buffer *axi_dac_request_buffer(struct iio_backend *back, 123 struct iio_dev *indio_dev) 124 { 125 struct axi_dac_state *st = iio_backend_get_priv(back); 126 const char *dma_name; 127 128 if (device_property_read_string(st->dev, "dma-names", &dma_name)) 129 dma_name = "tx"; 130 131 return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name, 132 IIO_BUFFER_DIRECTION_OUT); 133 } 134 135 static void axi_dac_free_buffer(struct iio_backend *back, 136 struct iio_buffer *buffer) 137 { 138 iio_dmaengine_buffer_free(buffer); 139 } 140 141 enum { 142 AXI_DAC_FREQ_TONE_1, 143 AXI_DAC_FREQ_TONE_2, 144 AXI_DAC_SCALE_TONE_1, 145 AXI_DAC_SCALE_TONE_2, 146 AXI_DAC_PHASE_TONE_1, 147 AXI_DAC_PHASE_TONE_2, 148 }; 149 150 static int __axi_dac_frequency_get(struct axi_dac_state *st, unsigned int chan, 151 unsigned int tone_2, unsigned int *freq) 152 { 153 u32 reg, raw; 154 int ret; 155 156 if (!st->dac_clk) { 157 dev_err(st->dev, "Sampling rate is 0...\n"); 158 return -EINVAL; 159 } 160 161 if (tone_2) 162 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan); 163 else 164 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan); 165 166 ret = regmap_read(st->regmap, reg, &raw); 167 if (ret) 168 return ret; 169 170 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw); 171 *freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16)); 172 173 return 0; 174 } 175 176 static int axi_dac_frequency_get(struct axi_dac_state *st, 177 const struct iio_chan_spec *chan, char *buf, 178 unsigned int tone_2) 179 { 180 unsigned int freq; 181 int ret; 182 183 scoped_guard(mutex, &st->lock) { 184 ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq); 185 if (ret) 186 return ret; 187 } 188 189 return sysfs_emit(buf, "%u\n", freq); 190 } 191 192 static int axi_dac_scale_get(struct axi_dac_state *st, 193 const struct iio_chan_spec *chan, char *buf, 194 unsigned int tone_2) 195 { 196 unsigned int scale, sign; 197 int ret, vals[2]; 198 u32 reg, raw; 199 200 if (tone_2) 201 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); 202 else 203 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); 204 205 ret = regmap_read(st->regmap, reg, &raw); 206 if (ret) 207 return ret; 208 209 sign = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, raw); 210 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE, raw); 211 scale = DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA, 212 AXI_DAC_CHAN_CNTRL_3_SCALE_INT); 213 214 vals[0] = scale / MEGA; 215 vals[1] = scale % MEGA; 216 217 if (sign) { 218 vals[0] *= -1; 219 if (!vals[0]) 220 vals[1] *= -1; 221 } 222 223 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals), 224 vals); 225 } 226 227 static int axi_dac_phase_get(struct axi_dac_state *st, 228 const struct iio_chan_spec *chan, char *buf, 229 unsigned int tone_2) 230 { 231 u32 reg, raw, phase; 232 int ret, vals[2]; 233 234 if (tone_2) 235 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); 236 else 237 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); 238 239 ret = regmap_read(st->regmap, reg, &raw); 240 if (ret) 241 return ret; 242 243 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_PHASE, raw); 244 phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX); 245 246 vals[0] = phase / MEGA; 247 vals[1] = phase % MEGA; 248 249 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals), 250 vals); 251 } 252 253 static int __axi_dac_frequency_set(struct axi_dac_state *st, unsigned int chan, 254 u64 sample_rate, unsigned int freq, 255 unsigned int tone_2) 256 { 257 u32 reg; 258 u16 raw; 259 int ret; 260 261 if (!sample_rate || freq > sample_rate / 2) { 262 dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n", 263 freq, sample_rate); 264 return -EINVAL; 265 } 266 267 if (tone_2) 268 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan); 269 else 270 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan); 271 272 raw = DIV64_U64_ROUND_CLOSEST((u64)freq * BIT(16), sample_rate); 273 274 ret = regmap_update_bits(st->regmap, reg, 275 AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw); 276 if (ret) 277 return ret; 278 279 /* synchronize channels */ 280 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, 281 AXI_DAC_CNTRL_1_SYNC); 282 } 283 284 static int axi_dac_frequency_set(struct axi_dac_state *st, 285 const struct iio_chan_spec *chan, 286 const char *buf, size_t len, unsigned int tone_2) 287 { 288 unsigned int freq; 289 int ret; 290 291 ret = kstrtou32(buf, 10, &freq); 292 if (ret) 293 return ret; 294 295 guard(mutex)(&st->lock); 296 ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq, 297 tone_2); 298 if (ret) 299 return ret; 300 301 return len; 302 } 303 304 static int axi_dac_scale_set(struct axi_dac_state *st, 305 const struct iio_chan_spec *chan, 306 const char *buf, size_t len, unsigned int tone_2) 307 { 308 int integer, frac, scale; 309 u32 raw = 0, reg; 310 int ret; 311 312 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac); 313 if (ret) 314 return ret; 315 316 scale = integer * MEGA + frac; 317 if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA) 318 return -EINVAL; 319 320 /* format is 1.1.14 (sign, integer and fractional bits) */ 321 if (scale < 0) { 322 raw = FIELD_PREP(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, 1); 323 scale *= -1; 324 } 325 326 raw |= div_u64((u64)scale * AXI_DAC_CHAN_CNTRL_3_SCALE_INT, MEGA); 327 328 if (tone_2) 329 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); 330 else 331 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); 332 333 guard(mutex)(&st->lock); 334 ret = regmap_write(st->regmap, reg, raw); 335 if (ret) 336 return ret; 337 338 /* synchronize channels */ 339 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, 340 AXI_DAC_CNTRL_1_SYNC); 341 if (ret) 342 return ret; 343 344 return len; 345 } 346 347 static int axi_dac_phase_set(struct axi_dac_state *st, 348 const struct iio_chan_spec *chan, 349 const char *buf, size_t len, unsigned int tone_2) 350 { 351 int integer, frac, phase; 352 u32 raw, reg; 353 int ret; 354 355 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac); 356 if (ret) 357 return ret; 358 359 phase = integer * MEGA + frac; 360 if (phase < 0 || phase > AXI_DAC_2_PI_MEGA) 361 return -EINVAL; 362 363 raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA); 364 365 if (tone_2) 366 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); 367 else 368 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); 369 370 guard(mutex)(&st->lock); 371 ret = regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE, 372 FIELD_PREP(AXI_DAC_CHAN_CNTRL_2_PHASE, raw)); 373 if (ret) 374 return ret; 375 376 /* synchronize channels */ 377 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, 378 AXI_DAC_CNTRL_1_SYNC); 379 if (ret) 380 return ret; 381 382 return len; 383 } 384 385 static int axi_dac_ext_info_set(struct iio_backend *back, uintptr_t private, 386 const struct iio_chan_spec *chan, 387 const char *buf, size_t len) 388 { 389 struct axi_dac_state *st = iio_backend_get_priv(back); 390 391 switch (private) { 392 case AXI_DAC_FREQ_TONE_1: 393 case AXI_DAC_FREQ_TONE_2: 394 return axi_dac_frequency_set(st, chan, buf, len, 395 private == AXI_DAC_FREQ_TONE_2); 396 case AXI_DAC_SCALE_TONE_1: 397 case AXI_DAC_SCALE_TONE_2: 398 return axi_dac_scale_set(st, chan, buf, len, 399 private == AXI_DAC_SCALE_TONE_2); 400 case AXI_DAC_PHASE_TONE_1: 401 case AXI_DAC_PHASE_TONE_2: 402 return axi_dac_phase_set(st, chan, buf, len, 403 private == AXI_DAC_PHASE_TONE_2); 404 default: 405 return -EOPNOTSUPP; 406 } 407 } 408 409 static int axi_dac_ext_info_get(struct iio_backend *back, uintptr_t private, 410 const struct iio_chan_spec *chan, char *buf) 411 { 412 struct axi_dac_state *st = iio_backend_get_priv(back); 413 414 switch (private) { 415 case AXI_DAC_FREQ_TONE_1: 416 case AXI_DAC_FREQ_TONE_2: 417 return axi_dac_frequency_get(st, chan, buf, 418 private - AXI_DAC_FREQ_TONE_1); 419 case AXI_DAC_SCALE_TONE_1: 420 case AXI_DAC_SCALE_TONE_2: 421 return axi_dac_scale_get(st, chan, buf, 422 private - AXI_DAC_SCALE_TONE_1); 423 case AXI_DAC_PHASE_TONE_1: 424 case AXI_DAC_PHASE_TONE_2: 425 return axi_dac_phase_get(st, chan, buf, 426 private - AXI_DAC_PHASE_TONE_1); 427 default: 428 return -EOPNOTSUPP; 429 } 430 } 431 432 static const struct iio_chan_spec_ext_info axi_dac_ext_info[] = { 433 IIO_BACKEND_EX_INFO("frequency0", IIO_SEPARATE, AXI_DAC_FREQ_TONE_1), 434 IIO_BACKEND_EX_INFO("frequency1", IIO_SEPARATE, AXI_DAC_FREQ_TONE_2), 435 IIO_BACKEND_EX_INFO("scale0", IIO_SEPARATE, AXI_DAC_SCALE_TONE_1), 436 IIO_BACKEND_EX_INFO("scale1", IIO_SEPARATE, AXI_DAC_SCALE_TONE_2), 437 IIO_BACKEND_EX_INFO("phase0", IIO_SEPARATE, AXI_DAC_PHASE_TONE_1), 438 IIO_BACKEND_EX_INFO("phase1", IIO_SEPARATE, AXI_DAC_PHASE_TONE_2), 439 {} 440 }; 441 442 static int axi_dac_extend_chan(struct iio_backend *back, 443 struct iio_chan_spec *chan) 444 { 445 struct axi_dac_state *st = iio_backend_get_priv(back); 446 447 if (chan->type != IIO_ALTVOLTAGE) 448 return -EINVAL; 449 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) 450 /* nothing to extend */ 451 return 0; 452 453 chan->ext_info = axi_dac_ext_info; 454 455 return 0; 456 } 457 458 static int axi_dac_data_source_set(struct iio_backend *back, unsigned int chan, 459 enum iio_backend_data_source data) 460 { 461 struct axi_dac_state *st = iio_backend_get_priv(back); 462 463 switch (data) { 464 case IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE: 465 return regmap_update_bits(st->regmap, 466 AXI_DAC_CHAN_CNTRL_7_REG(chan), 467 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, 468 AXI_DAC_DATA_INTERNAL_TONE); 469 case IIO_BACKEND_EXTERNAL: 470 return regmap_update_bits(st->regmap, 471 AXI_DAC_CHAN_CNTRL_7_REG(chan), 472 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, 473 AXI_DAC_DATA_DMA); 474 default: 475 return -EINVAL; 476 } 477 } 478 479 static int axi_dac_set_sample_rate(struct iio_backend *back, unsigned int chan, 480 u64 sample_rate) 481 { 482 struct axi_dac_state *st = iio_backend_get_priv(back); 483 unsigned int freq; 484 int ret, tone; 485 486 if (!sample_rate) 487 return -EINVAL; 488 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) 489 /* sample_rate has no meaning if DDS is disabled */ 490 return 0; 491 492 guard(mutex)(&st->lock); 493 /* 494 * If dac_clk is 0 then this must be the first time we're being notified 495 * about the interface sample rate. Hence, just update our internal 496 * variable and bail... If it's not 0, then we get the current DDS 497 * frequency (for the old rate) and update the registers for the new 498 * sample rate. 499 */ 500 if (!st->dac_clk) { 501 st->dac_clk = sample_rate; 502 return 0; 503 } 504 505 for (tone = 0; tone <= AXI_DAC_FREQ_TONE_2; tone++) { 506 ret = __axi_dac_frequency_get(st, chan, tone, &freq); 507 if (ret) 508 return ret; 509 510 ret = __axi_dac_frequency_set(st, chan, sample_rate, tone, freq); 511 if (ret) 512 return ret; 513 } 514 515 st->dac_clk = sample_rate; 516 517 return 0; 518 } 519 520 static int axi_dac_reg_access(struct iio_backend *back, unsigned int reg, 521 unsigned int writeval, unsigned int *readval) 522 { 523 struct axi_dac_state *st = iio_backend_get_priv(back); 524 525 if (readval) 526 return regmap_read(st->regmap, reg, readval); 527 528 return regmap_write(st->regmap, reg, writeval); 529 } 530 531 static const struct iio_backend_ops axi_dac_generic_ops = { 532 .enable = axi_dac_enable, 533 .disable = axi_dac_disable, 534 .request_buffer = axi_dac_request_buffer, 535 .free_buffer = axi_dac_free_buffer, 536 .extend_chan_spec = axi_dac_extend_chan, 537 .ext_info_set = axi_dac_ext_info_set, 538 .ext_info_get = axi_dac_ext_info_get, 539 .data_source_set = axi_dac_data_source_set, 540 .set_sample_rate = axi_dac_set_sample_rate, 541 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_dac_reg_access), 542 }; 543 544 static const struct iio_backend_info axi_dac_generic = { 545 .name = "axi-dac", 546 .ops = &axi_dac_generic_ops, 547 }; 548 549 static const struct regmap_config axi_dac_regmap_config = { 550 .val_bits = 32, 551 .reg_bits = 32, 552 .reg_stride = 4, 553 .max_register = 0x0800, 554 }; 555 556 static int axi_dac_probe(struct platform_device *pdev) 557 { 558 const unsigned int *expected_ver; 559 struct axi_dac_state *st; 560 void __iomem *base; 561 unsigned int ver; 562 struct clk *clk; 563 int ret; 564 565 st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); 566 if (!st) 567 return -ENOMEM; 568 569 expected_ver = device_get_match_data(&pdev->dev); 570 if (!expected_ver) 571 return -ENODEV; 572 573 clk = devm_clk_get_enabled(&pdev->dev, NULL); 574 if (IS_ERR(clk)) 575 return dev_err_probe(&pdev->dev, PTR_ERR(clk), 576 "failed to get clock\n"); 577 578 base = devm_platform_ioremap_resource(pdev, 0); 579 if (IS_ERR(base)) 580 return PTR_ERR(base); 581 582 st->dev = &pdev->dev; 583 st->regmap = devm_regmap_init_mmio(&pdev->dev, base, 584 &axi_dac_regmap_config); 585 if (IS_ERR(st->regmap)) 586 return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap), 587 "failed to init register map\n"); 588 589 /* 590 * Force disable the core. Up to the frontend to enable us. And we can 591 * still read/write registers... 592 */ 593 ret = regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); 594 if (ret) 595 return ret; 596 597 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); 598 if (ret) 599 return ret; 600 601 if (ADI_AXI_PCORE_VER_MAJOR(ver) != ADI_AXI_PCORE_VER_MAJOR(*expected_ver)) { 602 dev_err(&pdev->dev, 603 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 604 ADI_AXI_PCORE_VER_MAJOR(*expected_ver), 605 ADI_AXI_PCORE_VER_MINOR(*expected_ver), 606 ADI_AXI_PCORE_VER_PATCH(*expected_ver), 607 ADI_AXI_PCORE_VER_MAJOR(ver), 608 ADI_AXI_PCORE_VER_MINOR(ver), 609 ADI_AXI_PCORE_VER_PATCH(ver)); 610 return -ENODEV; 611 } 612 613 /* Let's get the core read only configuration */ 614 ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config); 615 if (ret) 616 return ret; 617 618 /* 619 * In some designs, setting the R1_MODE bit to 0 (which is the default 620 * value) causes all channels of the frontend to be routed to the same 621 * DMA (so they are sampled together). This is for things like 622 * Multiple-Input and Multiple-Output (MIMO). As most of the times we 623 * want independent channels let's override the core's default value and 624 * set the R1_MODE bit. 625 */ 626 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 627 ADI_DAC_CNTRL_2_R1_MODE); 628 if (ret) 629 return ret; 630 631 mutex_init(&st->lock); 632 ret = devm_iio_backend_register(&pdev->dev, &axi_dac_generic, st); 633 if (ret) 634 return dev_err_probe(&pdev->dev, ret, 635 "failed to register iio backend\n"); 636 637 dev_info(&pdev->dev, "AXI DAC IP core (%d.%.2d.%c) probed\n", 638 ADI_AXI_PCORE_VER_MAJOR(ver), 639 ADI_AXI_PCORE_VER_MINOR(ver), 640 ADI_AXI_PCORE_VER_PATCH(ver)); 641 642 return 0; 643 } 644 645 static unsigned int axi_dac_9_1_b_info = ADI_AXI_PCORE_VER(9, 1, 'b'); 646 647 static const struct of_device_id axi_dac_of_match[] = { 648 { .compatible = "adi,axi-dac-9.1.b", .data = &axi_dac_9_1_b_info }, 649 {} 650 }; 651 MODULE_DEVICE_TABLE(of, axi_dac_of_match); 652 653 static struct platform_driver axi_dac_driver = { 654 .driver = { 655 .name = "adi-axi-dac", 656 .of_match_table = axi_dac_of_match, 657 }, 658 .probe = axi_dac_probe, 659 }; 660 module_platform_driver(axi_dac_driver); 661 662 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 663 MODULE_DESCRIPTION("Analog Devices Generic AXI DAC IP core driver"); 664 MODULE_LICENSE("GPL"); 665 MODULE_IMPORT_NS(IIO_DMAENGINE_BUFFER); 666 MODULE_IMPORT_NS(IIO_BACKEND); 667