1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices Generic AXI DAC IP core 4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip 5 * 6 * Copyright 2016-2024 Analog Devices Inc. 7 */ 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/limits.h> 15 #include <linux/kstrtox.h> 16 #include <linux/math.h> 17 #include <linux/math64.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/mutex.h> 21 #include <linux/platform_device.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/units.h> 25 26 #include <linux/fpga/adi-axi-common.h> 27 #include <linux/iio/backend.h> 28 #include <linux/iio/buffer-dmaengine.h> 29 #include <linux/iio/buffer.h> 30 #include <linux/iio/iio.h> 31 32 #include "ad3552r-hs.h" 33 34 /* 35 * Register definitions: 36 * https://wiki.analog.com/resources/fpga/docs/axi_dac_ip#register_map 37 */ 38 39 /* Base controls */ 40 #define AXI_DAC_CONFIG_REG 0x0c 41 #define AXI_DAC_CONFIG_DDS_DISABLE BIT(6) 42 43 /* DAC controls */ 44 #define AXI_DAC_RSTN_REG 0x0040 45 #define AXI_DAC_RSTN_CE_N BIT(2) 46 #define AXI_DAC_RSTN_MMCM_RSTN BIT(1) 47 #define AXI_DAC_RSTN_RSTN BIT(0) 48 #define AXI_DAC_CNTRL_1_REG 0x0044 49 #define AXI_DAC_CNTRL_1_SYNC BIT(0) 50 #define AXI_DAC_CNTRL_2_REG 0x0048 51 #define AXI_DAC_CNTRL_2_SDR_DDR_N BIT(16) 52 #define AXI_DAC_CNTRL_2_SYMB_8B BIT(14) 53 #define ADI_DAC_CNTRL_2_R1_MODE BIT(5) 54 #define AXI_DAC_CNTRL_2_UNSIGNED_DATA BIT(4) 55 #define AXI_DAC_STATUS_1_REG 0x0054 56 #define AXI_DAC_STATUS_2_REG 0x0058 57 #define AXI_DAC_DRP_STATUS_REG 0x0074 58 #define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17) 59 #define AXI_DAC_CUSTOM_RD_REG 0x0080 60 #define AXI_DAC_CUSTOM_WR_REG 0x0084 61 #define AXI_DAC_CUSTOM_WR_DATA_8 GENMASK(23, 16) 62 #define AXI_DAC_CUSTOM_WR_DATA_16 GENMASK(23, 8) 63 #define AXI_DAC_UI_STATUS_REG 0x0088 64 #define AXI_DAC_UI_STATUS_IF_BUSY BIT(4) 65 #define AXI_DAC_CUSTOM_CTRL_REG 0x008C 66 #define AXI_DAC_CUSTOM_CTRL_ADDRESS GENMASK(31, 24) 67 #define AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE GENMASK(3, 2) 68 #define AXI_DAC_CUSTOM_CTRL_STREAM BIT(1) 69 #define AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA BIT(0) 70 71 #define AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE (AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA | \ 72 AXI_DAC_CUSTOM_CTRL_STREAM) 73 74 /* DAC Channel controls */ 75 #define AXI_DAC_CHAN_CNTRL_1_REG(c) (0x0400 + (c) * 0x40) 76 #define AXI_DAC_CHAN_CNTRL_3_REG(c) (0x0408 + (c) * 0x40) 77 #define AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN BIT(15) 78 #define AXI_DAC_CHAN_CNTRL_3_SCALE_INT BIT(14) 79 #define AXI_DAC_CHAN_CNTRL_3_SCALE GENMASK(14, 0) 80 #define AXI_DAC_CHAN_CNTRL_2_REG(c) (0x0404 + (c) * 0x40) 81 #define AXI_DAC_CHAN_CNTRL_2_PHASE GENMASK(31, 16) 82 #define AXI_DAC_CHAN_CNTRL_2_FREQUENCY GENMASK(15, 0) 83 #define AXI_DAC_CHAN_CNTRL_4_REG(c) (0x040c + (c) * 0x40) 84 #define AXI_DAC_CHAN_CNTRL_7_REG(c) (0x0418 + (c) * 0x40) 85 #define AXI_DAC_CHAN_CNTRL_7_DATA_SEL GENMASK(3, 0) 86 87 #define AXI_DAC_CHAN_CNTRL_MAX 15 88 #define AXI_DAC_RD_ADDR(x) (BIT(7) | (x)) 89 90 /* 360 degrees in rad */ 91 #define AXI_DAC_2_PI_MEGA 6283190 92 93 enum { 94 AXI_DAC_DATA_INTERNAL_TONE, 95 AXI_DAC_DATA_DMA = 2, 96 AXI_DAC_DATA_INTERNAL_RAMP_16BIT = 11, 97 }; 98 99 struct axi_dac_info { 100 unsigned int version; 101 const struct iio_backend_info *backend_info; 102 bool has_dac_clk; 103 bool has_child_nodes; 104 }; 105 106 struct axi_dac_state { 107 struct regmap *regmap; 108 struct device *dev; 109 /* 110 * lock to protect multiple accesses to the device registers and global 111 * data/variables. 112 */ 113 struct mutex lock; 114 const struct axi_dac_info *info; 115 u64 dac_clk; 116 u32 reg_config; 117 bool int_tone; 118 int dac_clk_rate; 119 }; 120 121 static int axi_dac_enable(struct iio_backend *back) 122 { 123 struct axi_dac_state *st = iio_backend_get_priv(back); 124 unsigned int __val; 125 int ret; 126 127 guard(mutex)(&st->lock); 128 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, 129 AXI_DAC_RSTN_MMCM_RSTN); 130 if (ret) 131 return ret; 132 /* 133 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all 134 * designs really use it but if they don't we still get the lock bit 135 * set. So let's do it all the time so the code is generic. 136 */ 137 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, 138 __val, 139 __val & AXI_DAC_DRP_STATUS_DRP_LOCKED, 140 100, 1000); 141 if (ret) 142 return ret; 143 144 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, 145 AXI_DAC_RSTN_RSTN | AXI_DAC_RSTN_MMCM_RSTN); 146 } 147 148 static void axi_dac_disable(struct iio_backend *back) 149 { 150 struct axi_dac_state *st = iio_backend_get_priv(back); 151 152 guard(mutex)(&st->lock); 153 regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); 154 } 155 156 static struct iio_buffer *axi_dac_request_buffer(struct iio_backend *back, 157 struct iio_dev *indio_dev) 158 { 159 struct axi_dac_state *st = iio_backend_get_priv(back); 160 const char *dma_name; 161 162 if (device_property_read_string(st->dev, "dma-names", &dma_name)) 163 dma_name = "tx"; 164 165 return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name, 166 IIO_BUFFER_DIRECTION_OUT); 167 } 168 169 static void axi_dac_free_buffer(struct iio_backend *back, 170 struct iio_buffer *buffer) 171 { 172 iio_dmaengine_buffer_teardown(buffer); 173 } 174 175 enum { 176 AXI_DAC_FREQ_TONE_1, 177 AXI_DAC_FREQ_TONE_2, 178 AXI_DAC_SCALE_TONE_1, 179 AXI_DAC_SCALE_TONE_2, 180 AXI_DAC_PHASE_TONE_1, 181 AXI_DAC_PHASE_TONE_2, 182 }; 183 184 static int __axi_dac_frequency_get(struct axi_dac_state *st, unsigned int chan, 185 unsigned int tone_2, unsigned int *freq) 186 { 187 u32 reg, raw; 188 int ret; 189 190 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 191 return -EINVAL; 192 193 if (!st->dac_clk) { 194 dev_err(st->dev, "Sampling rate is 0...\n"); 195 return -EINVAL; 196 } 197 198 if (tone_2) 199 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan); 200 else 201 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan); 202 203 ret = regmap_read(st->regmap, reg, &raw); 204 if (ret) 205 return ret; 206 207 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw); 208 *freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16)); 209 210 return 0; 211 } 212 213 static int axi_dac_frequency_get(struct axi_dac_state *st, 214 const struct iio_chan_spec *chan, char *buf, 215 unsigned int tone_2) 216 { 217 unsigned int freq; 218 int ret; 219 220 scoped_guard(mutex, &st->lock) { 221 ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq); 222 if (ret) 223 return ret; 224 } 225 226 return sysfs_emit(buf, "%u\n", freq); 227 } 228 229 static int axi_dac_scale_get(struct axi_dac_state *st, 230 const struct iio_chan_spec *chan, char *buf, 231 unsigned int tone_2) 232 { 233 unsigned int scale, sign; 234 int ret, vals[2]; 235 u32 reg, raw; 236 237 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) 238 return -EINVAL; 239 240 if (tone_2) 241 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); 242 else 243 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); 244 245 ret = regmap_read(st->regmap, reg, &raw); 246 if (ret) 247 return ret; 248 249 sign = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, raw); 250 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE, raw); 251 scale = DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA, 252 AXI_DAC_CHAN_CNTRL_3_SCALE_INT); 253 254 vals[0] = scale / MEGA; 255 vals[1] = scale % MEGA; 256 257 if (sign) { 258 vals[0] *= -1; 259 if (!vals[0]) 260 vals[1] *= -1; 261 } 262 263 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals), 264 vals); 265 } 266 267 static int axi_dac_phase_get(struct axi_dac_state *st, 268 const struct iio_chan_spec *chan, char *buf, 269 unsigned int tone_2) 270 { 271 u32 reg, raw, phase; 272 int ret, vals[2]; 273 274 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) 275 return -EINVAL; 276 277 if (tone_2) 278 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); 279 else 280 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); 281 282 ret = regmap_read(st->regmap, reg, &raw); 283 if (ret) 284 return ret; 285 286 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_PHASE, raw); 287 phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX); 288 289 vals[0] = phase / MEGA; 290 vals[1] = phase % MEGA; 291 292 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals), 293 vals); 294 } 295 296 static int __axi_dac_frequency_set(struct axi_dac_state *st, unsigned int chan, 297 u64 sample_rate, unsigned int freq, 298 unsigned int tone_2) 299 { 300 u32 reg; 301 u16 raw; 302 int ret; 303 304 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 305 return -EINVAL; 306 307 if (!sample_rate || freq > sample_rate / 2) { 308 dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n", 309 freq, sample_rate); 310 return -EINVAL; 311 } 312 313 if (tone_2) 314 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan); 315 else 316 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan); 317 318 raw = DIV64_U64_ROUND_CLOSEST((u64)freq * BIT(16), sample_rate); 319 320 ret = regmap_update_bits(st->regmap, reg, 321 AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw); 322 if (ret) 323 return ret; 324 325 /* synchronize channels */ 326 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, 327 AXI_DAC_CNTRL_1_SYNC); 328 } 329 330 static int axi_dac_frequency_set(struct axi_dac_state *st, 331 const struct iio_chan_spec *chan, 332 const char *buf, size_t len, unsigned int tone_2) 333 { 334 unsigned int freq; 335 int ret; 336 337 ret = kstrtou32(buf, 10, &freq); 338 if (ret) 339 return ret; 340 341 guard(mutex)(&st->lock); 342 ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq, 343 tone_2); 344 if (ret) 345 return ret; 346 347 return len; 348 } 349 350 static int axi_dac_scale_set(struct axi_dac_state *st, 351 const struct iio_chan_spec *chan, 352 const char *buf, size_t len, unsigned int tone_2) 353 { 354 int integer, frac, scale; 355 u32 raw = 0, reg; 356 int ret; 357 358 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) 359 return -EINVAL; 360 361 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac); 362 if (ret) 363 return ret; 364 365 scale = integer * MEGA + frac; 366 if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA) 367 return -EINVAL; 368 369 /* format is 1.1.14 (sign, integer and fractional bits) */ 370 if (scale < 0) { 371 raw = FIELD_PREP(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, 1); 372 scale *= -1; 373 } 374 375 raw |= div_u64((u64)scale * AXI_DAC_CHAN_CNTRL_3_SCALE_INT, MEGA); 376 377 if (tone_2) 378 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); 379 else 380 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); 381 382 guard(mutex)(&st->lock); 383 ret = regmap_write(st->regmap, reg, raw); 384 if (ret) 385 return ret; 386 387 /* synchronize channels */ 388 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, 389 AXI_DAC_CNTRL_1_SYNC); 390 if (ret) 391 return ret; 392 393 return len; 394 } 395 396 static int axi_dac_phase_set(struct axi_dac_state *st, 397 const struct iio_chan_spec *chan, 398 const char *buf, size_t len, unsigned int tone_2) 399 { 400 int integer, frac, phase; 401 u32 raw, reg; 402 int ret; 403 404 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) 405 return -EINVAL; 406 407 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac); 408 if (ret) 409 return ret; 410 411 phase = integer * MEGA + frac; 412 if (phase < 0 || phase > AXI_DAC_2_PI_MEGA) 413 return -EINVAL; 414 415 raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA); 416 417 if (tone_2) 418 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); 419 else 420 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); 421 422 guard(mutex)(&st->lock); 423 ret = regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE, 424 FIELD_PREP(AXI_DAC_CHAN_CNTRL_2_PHASE, raw)); 425 if (ret) 426 return ret; 427 428 /* synchronize channels */ 429 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, 430 AXI_DAC_CNTRL_1_SYNC); 431 if (ret) 432 return ret; 433 434 return len; 435 } 436 437 static int axi_dac_ext_info_set(struct iio_backend *back, uintptr_t private, 438 const struct iio_chan_spec *chan, 439 const char *buf, size_t len) 440 { 441 struct axi_dac_state *st = iio_backend_get_priv(back); 442 443 switch (private) { 444 case AXI_DAC_FREQ_TONE_1: 445 case AXI_DAC_FREQ_TONE_2: 446 return axi_dac_frequency_set(st, chan, buf, len, 447 private == AXI_DAC_FREQ_TONE_2); 448 case AXI_DAC_SCALE_TONE_1: 449 case AXI_DAC_SCALE_TONE_2: 450 return axi_dac_scale_set(st, chan, buf, len, 451 private == AXI_DAC_SCALE_TONE_2); 452 case AXI_DAC_PHASE_TONE_1: 453 case AXI_DAC_PHASE_TONE_2: 454 return axi_dac_phase_set(st, chan, buf, len, 455 private == AXI_DAC_PHASE_TONE_2); 456 default: 457 return -EOPNOTSUPP; 458 } 459 } 460 461 static int axi_dac_ext_info_get(struct iio_backend *back, uintptr_t private, 462 const struct iio_chan_spec *chan, char *buf) 463 { 464 struct axi_dac_state *st = iio_backend_get_priv(back); 465 466 switch (private) { 467 case AXI_DAC_FREQ_TONE_1: 468 case AXI_DAC_FREQ_TONE_2: 469 return axi_dac_frequency_get(st, chan, buf, 470 private - AXI_DAC_FREQ_TONE_1); 471 case AXI_DAC_SCALE_TONE_1: 472 case AXI_DAC_SCALE_TONE_2: 473 return axi_dac_scale_get(st, chan, buf, 474 private - AXI_DAC_SCALE_TONE_1); 475 case AXI_DAC_PHASE_TONE_1: 476 case AXI_DAC_PHASE_TONE_2: 477 return axi_dac_phase_get(st, chan, buf, 478 private - AXI_DAC_PHASE_TONE_1); 479 default: 480 return -EOPNOTSUPP; 481 } 482 } 483 484 static const struct iio_chan_spec_ext_info axi_dac_ext_info[] = { 485 IIO_BACKEND_EX_INFO("frequency0", IIO_SEPARATE, AXI_DAC_FREQ_TONE_1), 486 IIO_BACKEND_EX_INFO("frequency1", IIO_SEPARATE, AXI_DAC_FREQ_TONE_2), 487 IIO_BACKEND_EX_INFO("scale0", IIO_SEPARATE, AXI_DAC_SCALE_TONE_1), 488 IIO_BACKEND_EX_INFO("scale1", IIO_SEPARATE, AXI_DAC_SCALE_TONE_2), 489 IIO_BACKEND_EX_INFO("phase0", IIO_SEPARATE, AXI_DAC_PHASE_TONE_1), 490 IIO_BACKEND_EX_INFO("phase1", IIO_SEPARATE, AXI_DAC_PHASE_TONE_2), 491 { } 492 }; 493 494 static int axi_dac_extend_chan(struct iio_backend *back, 495 struct iio_chan_spec *chan) 496 { 497 struct axi_dac_state *st = iio_backend_get_priv(back); 498 499 if (chan->type != IIO_ALTVOLTAGE) 500 return -EINVAL; 501 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) 502 /* nothing to extend */ 503 return 0; 504 505 chan->ext_info = axi_dac_ext_info; 506 507 return 0; 508 } 509 510 static int axi_dac_data_source_set(struct iio_backend *back, unsigned int chan, 511 enum iio_backend_data_source data) 512 { 513 struct axi_dac_state *st = iio_backend_get_priv(back); 514 515 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 516 return -EINVAL; 517 518 switch (data) { 519 case IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE: 520 return regmap_update_bits(st->regmap, 521 AXI_DAC_CHAN_CNTRL_7_REG(chan), 522 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, 523 AXI_DAC_DATA_INTERNAL_TONE); 524 case IIO_BACKEND_EXTERNAL: 525 return regmap_update_bits(st->regmap, 526 AXI_DAC_CHAN_CNTRL_7_REG(chan), 527 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, 528 AXI_DAC_DATA_DMA); 529 case IIO_BACKEND_INTERNAL_RAMP_16BIT: 530 return regmap_update_bits(st->regmap, 531 AXI_DAC_CHAN_CNTRL_7_REG(chan), 532 AXI_DAC_CHAN_CNTRL_7_DATA_SEL, 533 AXI_DAC_DATA_INTERNAL_RAMP_16BIT); 534 default: 535 return -EINVAL; 536 } 537 } 538 539 static int axi_dac_data_source_get(struct iio_backend *back, unsigned int chan, 540 enum iio_backend_data_source *data) 541 { 542 struct axi_dac_state *st = iio_backend_get_priv(back); 543 int ret; 544 u32 val; 545 546 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 547 return -EINVAL; 548 549 ret = regmap_read(st->regmap, AXI_DAC_CHAN_CNTRL_7_REG(chan), &val); 550 if (ret) 551 return ret; 552 553 switch (val) { 554 case AXI_DAC_DATA_INTERNAL_TONE: 555 *data = IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE; 556 return 0; 557 case AXI_DAC_DATA_DMA: 558 *data = IIO_BACKEND_EXTERNAL; 559 return 0; 560 case AXI_DAC_DATA_INTERNAL_RAMP_16BIT: 561 *data = IIO_BACKEND_INTERNAL_RAMP_16BIT; 562 return 0; 563 default: 564 return -EIO; 565 } 566 } 567 568 static int axi_dac_set_sample_rate(struct iio_backend *back, unsigned int chan, 569 u64 sample_rate) 570 { 571 struct axi_dac_state *st = iio_backend_get_priv(back); 572 unsigned int freq; 573 int ret, tone; 574 575 if (chan > AXI_DAC_CHAN_CNTRL_MAX) 576 return -EINVAL; 577 if (!sample_rate) 578 return -EINVAL; 579 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) 580 /* sample_rate has no meaning if DDS is disabled */ 581 return 0; 582 583 guard(mutex)(&st->lock); 584 /* 585 * If dac_clk is 0 then this must be the first time we're being notified 586 * about the interface sample rate. Hence, just update our internal 587 * variable and bail... If it's not 0, then we get the current DDS 588 * frequency (for the old rate) and update the registers for the new 589 * sample rate. 590 */ 591 if (!st->dac_clk) { 592 st->dac_clk = sample_rate; 593 return 0; 594 } 595 596 for (tone = 0; tone <= AXI_DAC_FREQ_TONE_2; tone++) { 597 ret = __axi_dac_frequency_get(st, chan, tone, &freq); 598 if (ret) 599 return ret; 600 601 ret = __axi_dac_frequency_set(st, chan, sample_rate, tone, freq); 602 if (ret) 603 return ret; 604 } 605 606 st->dac_clk = sample_rate; 607 608 return 0; 609 } 610 611 static int axi_dac_reg_access(struct iio_backend *back, unsigned int reg, 612 unsigned int writeval, unsigned int *readval) 613 { 614 struct axi_dac_state *st = iio_backend_get_priv(back); 615 616 if (readval) 617 return regmap_read(st->regmap, reg, readval); 618 619 return regmap_write(st->regmap, reg, writeval); 620 } 621 622 static int axi_dac_ddr_enable(struct iio_backend *back) 623 { 624 struct axi_dac_state *st = iio_backend_get_priv(back); 625 626 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 627 AXI_DAC_CNTRL_2_SDR_DDR_N); 628 } 629 630 static int axi_dac_ddr_disable(struct iio_backend *back) 631 { 632 struct axi_dac_state *st = iio_backend_get_priv(back); 633 634 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 635 AXI_DAC_CNTRL_2_SDR_DDR_N); 636 } 637 638 static int axi_dac_data_stream_enable(struct iio_backend *back) 639 { 640 struct axi_dac_state *st = iio_backend_get_priv(back); 641 int ret, val; 642 643 ret = regmap_read_poll_timeout(st->regmap, 644 AXI_DAC_UI_STATUS_REG, val, 645 FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, val) == 0, 646 10, 100 * KILO); 647 if (ret) 648 return ret; 649 650 return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 651 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE); 652 } 653 654 static int axi_dac_data_stream_disable(struct iio_backend *back) 655 { 656 struct axi_dac_state *st = iio_backend_get_priv(back); 657 658 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 659 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE); 660 } 661 662 static int axi_dac_data_transfer_addr(struct iio_backend *back, u32 address) 663 { 664 struct axi_dac_state *st = iio_backend_get_priv(back); 665 666 if (address > FIELD_MAX(AXI_DAC_CUSTOM_CTRL_ADDRESS)) 667 return -EINVAL; 668 669 /* 670 * Sample register address, when the DAC is configured, or stream 671 * start address when the FSM is in stream state. 672 */ 673 return regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 674 AXI_DAC_CUSTOM_CTRL_ADDRESS, 675 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, 676 address)); 677 } 678 679 static int axi_dac_data_format_set(struct iio_backend *back, unsigned int ch, 680 const struct iio_backend_data_fmt *data) 681 { 682 struct axi_dac_state *st = iio_backend_get_priv(back); 683 684 switch (data->type) { 685 case IIO_BACKEND_DATA_UNSIGNED: 686 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 687 AXI_DAC_CNTRL_2_UNSIGNED_DATA); 688 default: 689 return -EINVAL; 690 } 691 } 692 693 static int __axi_dac_bus_reg_write(struct iio_backend *back, u32 reg, 694 u32 val, size_t data_size) 695 { 696 struct axi_dac_state *st = iio_backend_get_priv(back); 697 int ret; 698 u32 ival; 699 700 /* 701 * Both AXI_DAC_CNTRL_2_REG and AXI_DAC_CUSTOM_WR_REG need to know 702 * the data size. So keeping data size control here only, 703 * since data size is mandatory for the current transfer. 704 * DDR state handled separately by specific backend calls, 705 * generally all raw register writes are SDR. 706 */ 707 if (data_size == sizeof(u16)) 708 ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_16, val); 709 else 710 ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_8, val); 711 712 ret = regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival); 713 if (ret) 714 return ret; 715 716 if (data_size == sizeof(u8)) 717 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 718 AXI_DAC_CNTRL_2_SYMB_8B); 719 else 720 ret = regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 721 AXI_DAC_CNTRL_2_SYMB_8B); 722 if (ret) 723 return ret; 724 725 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 726 AXI_DAC_CUSTOM_CTRL_ADDRESS, 727 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, reg)); 728 if (ret) 729 return ret; 730 731 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 732 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA, 733 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA); 734 if (ret) 735 return ret; 736 737 ret = regmap_read_poll_timeout(st->regmap, 738 AXI_DAC_UI_STATUS_REG, ival, 739 FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) == 0, 740 10, 100 * KILO); 741 if (ret == -ETIMEDOUT) 742 dev_err(st->dev, "AXI read timeout\n"); 743 744 /* Cleaning always AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA */ 745 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 746 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA); 747 } 748 749 static int axi_dac_bus_reg_write(struct iio_backend *back, u32 reg, 750 u32 val, size_t data_size) 751 { 752 struct axi_dac_state *st = iio_backend_get_priv(back); 753 754 guard(mutex)(&st->lock); 755 return __axi_dac_bus_reg_write(back, reg, val, data_size); 756 } 757 758 static int axi_dac_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val, 759 size_t data_size) 760 { 761 struct axi_dac_state *st = iio_backend_get_priv(back); 762 int ret; 763 u32 ival; 764 765 guard(mutex)(&st->lock); 766 767 /* 768 * SPI, we write with read flag, then we read just at the AXI 769 * io address space to get data read. 770 */ 771 ret = __axi_dac_bus_reg_write(back, AXI_DAC_RD_ADDR(reg), 0, 772 data_size); 773 if (ret) 774 return ret; 775 776 ret = regmap_read_poll_timeout(st->regmap, 777 AXI_DAC_UI_STATUS_REG, ival, 778 FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) == 0, 779 10, 100 * KILO); 780 if (ret) 781 return ret; 782 783 return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val); 784 } 785 786 static int axi_dac_bus_set_io_mode(struct iio_backend *back, 787 enum ad3552r_io_mode mode) 788 { 789 struct axi_dac_state *st = iio_backend_get_priv(back); 790 int ival, ret; 791 792 if (mode > AD3552R_IO_MODE_QSPI) 793 return -EINVAL; 794 795 guard(mutex)(&st->lock); 796 797 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, 798 AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, 799 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, mode)); 800 if (ret) 801 return ret; 802 803 return regmap_read_poll_timeout(st->regmap, AXI_DAC_UI_STATUS_REG, ival, 804 FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) == 0, 10, 805 100 * KILO); 806 } 807 808 static void axi_dac_child_remove(void *data) 809 { 810 platform_device_unregister(data); 811 } 812 813 static int axi_dac_create_platform_device(struct axi_dac_state *st, 814 struct fwnode_handle *child) 815 { 816 struct ad3552r_hs_platform_data pdata = { 817 .bus_reg_read = axi_dac_bus_reg_read, 818 .bus_reg_write = axi_dac_bus_reg_write, 819 .bus_set_io_mode = axi_dac_bus_set_io_mode, 820 .bus_sample_data_clock_hz = st->dac_clk_rate, 821 }; 822 struct platform_device_info pi = { 823 .parent = st->dev, 824 .name = fwnode_get_name(child), 825 .id = PLATFORM_DEVID_AUTO, 826 .fwnode = child, 827 .data = &pdata, 828 .size_data = sizeof(pdata), 829 }; 830 struct platform_device *pdev; 831 832 pdev = platform_device_register_full(&pi); 833 if (IS_ERR(pdev)) 834 return PTR_ERR(pdev); 835 836 return devm_add_action_or_reset(st->dev, axi_dac_child_remove, pdev); 837 } 838 839 static const struct iio_backend_ops axi_dac_generic_ops = { 840 .enable = axi_dac_enable, 841 .disable = axi_dac_disable, 842 .request_buffer = axi_dac_request_buffer, 843 .free_buffer = axi_dac_free_buffer, 844 .extend_chan_spec = axi_dac_extend_chan, 845 .ext_info_set = axi_dac_ext_info_set, 846 .ext_info_get = axi_dac_ext_info_get, 847 .data_source_set = axi_dac_data_source_set, 848 .set_sample_rate = axi_dac_set_sample_rate, 849 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_dac_reg_access), 850 }; 851 852 static const struct iio_backend_ops axi_ad3552r_ops = { 853 .enable = axi_dac_enable, 854 .disable = axi_dac_disable, 855 .request_buffer = axi_dac_request_buffer, 856 .free_buffer = axi_dac_free_buffer, 857 .data_source_set = axi_dac_data_source_set, 858 .data_source_get = axi_dac_data_source_get, 859 .ddr_enable = axi_dac_ddr_enable, 860 .ddr_disable = axi_dac_ddr_disable, 861 .data_stream_enable = axi_dac_data_stream_enable, 862 .data_stream_disable = axi_dac_data_stream_disable, 863 .data_format_set = axi_dac_data_format_set, 864 .data_transfer_addr = axi_dac_data_transfer_addr, 865 }; 866 867 static const struct iio_backend_info axi_dac_generic = { 868 .name = "axi-dac", 869 .ops = &axi_dac_generic_ops, 870 }; 871 872 static const struct iio_backend_info axi_ad3552r = { 873 .name = "axi-ad3552r", 874 .ops = &axi_ad3552r_ops, 875 }; 876 877 static const struct regmap_config axi_dac_regmap_config = { 878 .val_bits = 32, 879 .reg_bits = 32, 880 .reg_stride = 4, 881 .max_register = 0x0800, 882 }; 883 884 static int axi_dac_probe(struct platform_device *pdev) 885 { 886 struct axi_dac_state *st; 887 void __iomem *base; 888 unsigned int ver; 889 struct clk *clk; 890 int ret; 891 892 st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); 893 if (!st) 894 return -ENOMEM; 895 896 st->info = device_get_match_data(&pdev->dev); 897 if (!st->info) 898 return -ENODEV; 899 clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); 900 if (IS_ERR(clk)) { 901 /* Backward compat., old fdt versions without clock-names. */ 902 clk = devm_clk_get_enabled(&pdev->dev, NULL); 903 if (IS_ERR(clk)) 904 return dev_err_probe(&pdev->dev, PTR_ERR(clk), 905 "failed to get clock\n"); 906 } 907 908 if (st->info->has_dac_clk) { 909 struct clk *dac_clk; 910 911 dac_clk = devm_clk_get_enabled(&pdev->dev, "dac_clk"); 912 if (IS_ERR(dac_clk)) 913 return dev_err_probe(&pdev->dev, PTR_ERR(dac_clk), 914 "failed to get dac_clk clock\n"); 915 916 /* We only care about the streaming mode rate */ 917 st->dac_clk_rate = clk_get_rate(dac_clk) / 2; 918 } 919 920 base = devm_platform_ioremap_resource(pdev, 0); 921 if (IS_ERR(base)) 922 return PTR_ERR(base); 923 924 st->dev = &pdev->dev; 925 st->regmap = devm_regmap_init_mmio(&pdev->dev, base, 926 &axi_dac_regmap_config); 927 if (IS_ERR(st->regmap)) 928 return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap), 929 "failed to init register map\n"); 930 931 /* 932 * Force disable the core. Up to the frontend to enable us. And we can 933 * still read/write registers... 934 */ 935 ret = regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); 936 if (ret) 937 return ret; 938 939 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); 940 if (ret) 941 return ret; 942 943 if (ADI_AXI_PCORE_VER_MAJOR(ver) != 944 ADI_AXI_PCORE_VER_MAJOR(st->info->version)) { 945 dev_err(&pdev->dev, 946 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 947 ADI_AXI_PCORE_VER_MAJOR(st->info->version), 948 ADI_AXI_PCORE_VER_MINOR(st->info->version), 949 ADI_AXI_PCORE_VER_PATCH(st->info->version), 950 ADI_AXI_PCORE_VER_MAJOR(ver), 951 ADI_AXI_PCORE_VER_MINOR(ver), 952 ADI_AXI_PCORE_VER_PATCH(ver)); 953 return -ENODEV; 954 } 955 956 /* Let's get the core read only configuration */ 957 ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config); 958 if (ret) 959 return ret; 960 961 /* 962 * In some designs, setting the R1_MODE bit to 0 (which is the default 963 * value) causes all channels of the frontend to be routed to the same 964 * DMA (so they are sampled together). This is for things like 965 * Multiple-Input and Multiple-Output (MIMO). As most of the times we 966 * want independent channels let's override the core's default value and 967 * set the R1_MODE bit. 968 */ 969 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, 970 ADI_DAC_CNTRL_2_R1_MODE); 971 if (ret) 972 return ret; 973 974 mutex_init(&st->lock); 975 976 ret = devm_iio_backend_register(&pdev->dev, st->info->backend_info, st); 977 if (ret) 978 return dev_err_probe(&pdev->dev, ret, 979 "failed to register iio backend\n"); 980 981 device_for_each_child_node_scoped(&pdev->dev, child) { 982 int val; 983 984 if (!st->info->has_child_nodes) 985 return dev_err_probe(&pdev->dev, -EINVAL, 986 "invalid fdt axi-dac compatible."); 987 988 /* Processing only reg 0 node */ 989 ret = fwnode_property_read_u32(child, "reg", &val); 990 if (ret) 991 return dev_err_probe(&pdev->dev, ret, 992 "invalid reg property."); 993 if (val != 0) 994 return dev_err_probe(&pdev->dev, -EINVAL, 995 "invalid node address."); 996 997 ret = axi_dac_create_platform_device(st, child); 998 if (ret) 999 return dev_err_probe(&pdev->dev, -EINVAL, 1000 "cannot create device."); 1001 } 1002 1003 dev_info(&pdev->dev, "AXI DAC IP core (%d.%.2d.%c) probed\n", 1004 ADI_AXI_PCORE_VER_MAJOR(ver), 1005 ADI_AXI_PCORE_VER_MINOR(ver), 1006 ADI_AXI_PCORE_VER_PATCH(ver)); 1007 1008 return 0; 1009 } 1010 1011 static const struct axi_dac_info dac_generic = { 1012 .version = ADI_AXI_PCORE_VER(9, 1, 'b'), 1013 .backend_info = &axi_dac_generic, 1014 }; 1015 1016 static const struct axi_dac_info dac_ad3552r = { 1017 .version = ADI_AXI_PCORE_VER(9, 1, 'b'), 1018 .backend_info = &axi_ad3552r, 1019 .has_dac_clk = true, 1020 .has_child_nodes = true, 1021 }; 1022 1023 static const struct of_device_id axi_dac_of_match[] = { 1024 { .compatible = "adi,axi-dac-9.1.b", .data = &dac_generic }, 1025 { .compatible = "adi,axi-ad3552r", .data = &dac_ad3552r }, 1026 { } 1027 }; 1028 MODULE_DEVICE_TABLE(of, axi_dac_of_match); 1029 1030 static struct platform_driver axi_dac_driver = { 1031 .driver = { 1032 .name = "adi-axi-dac", 1033 .of_match_table = axi_dac_of_match, 1034 }, 1035 .probe = axi_dac_probe, 1036 }; 1037 module_platform_driver(axi_dac_driver); 1038 1039 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1040 MODULE_DESCRIPTION("Analog Devices Generic AXI DAC IP core driver"); 1041 MODULE_LICENSE("GPL"); 1042 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 1043 MODULE_IMPORT_NS("IIO_BACKEND"); 1044