1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD8460 Waveform generator DAC Driver 4 * 5 * Copyright (C) 2024 Analog Devices, Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/buffer-dma.h> 24 #include <linux/iio/buffer-dmaengine.h> 25 #include <linux/iio/consumer.h> 26 #include <linux/iio/events.h> 27 #include <linux/iio/iio.h> 28 29 #define AD8460_CTRL_REG(x) (x) 30 #define AD8460_HVDAC_DATA_WORD(x) (0x60 + (2 * (x))) 31 32 #define AD8460_HV_RESET_MSK BIT(7) 33 #define AD8460_HV_SLEEP_MSK BIT(4) 34 #define AD8460_WAVE_GEN_MODE_MSK BIT(0) 35 36 #define AD8460_HVDAC_SLEEP_MSK BIT(3) 37 38 #define AD8460_FAULT_ARM_MSK BIT(7) 39 #define AD8460_FAULT_LIMIT_MSK GENMASK(6, 0) 40 41 #define AD8460_APG_MODE_ENABLE_MSK BIT(5) 42 #define AD8460_PATTERN_DEPTH_MSK GENMASK(3, 0) 43 44 #define AD8460_QUIESCENT_CURRENT_MSK GENMASK(7, 0) 45 46 #define AD8460_SHUTDOWN_FLAG_MSK BIT(7) 47 48 #define AD8460_DATA_BYTE_LOW_MSK GENMASK(7, 0) 49 #define AD8460_DATA_BYTE_HIGH_MSK GENMASK(5, 0) 50 #define AD8460_DATA_BYTE_FULL_MSK GENMASK(13, 0) 51 52 #define AD8460_DEFAULT_FAULT_PROTECT 0x00 53 #define AD8460_DATA_BYTE_WORD_LENGTH 2 54 #define AD8460_NUM_DATA_WORDS 16 55 #define AD8460_NOMINAL_VOLTAGE_SPAN 80 56 #define AD8460_MIN_EXT_RESISTOR_OHMS 2000 57 #define AD8460_MAX_EXT_RESISTOR_OHMS 20000 58 #define AD8460_MIN_VREFIO_UV 120000 59 #define AD8460_MAX_VREFIO_UV 1200000 60 #define AD8460_ABS_MAX_OVERVOLTAGE_UV 55000000 61 #define AD8460_ABS_MAX_OVERCURRENT_UA 1000000 62 #define AD8460_MAX_OVERTEMPERATURE_MC 150000 63 #define AD8460_MIN_OVERTEMPERATURE_MC 20000 64 #define AD8460_CURRENT_LIMIT_CONV(x) ((x) / 15625) 65 #define AD8460_VOLTAGE_LIMIT_CONV(x) ((x) / 1953000) 66 #define AD8460_TEMP_LIMIT_CONV(x) (((x) + 266640) / 6510) 67 68 enum ad8460_fault_type { 69 AD8460_OVERCURRENT_SRC, 70 AD8460_OVERCURRENT_SNK, 71 AD8460_OVERVOLTAGE_POS, 72 AD8460_OVERVOLTAGE_NEG, 73 AD8460_OVERTEMPERATURE, 74 }; 75 76 struct ad8460_state { 77 struct spi_device *spi; 78 struct regmap *regmap; 79 struct iio_channel *tmp_adc_channel; 80 struct clk *sync_clk; 81 /* lock to protect against multiple access to the device and shared data */ 82 struct mutex lock; 83 int refio_1p2v_mv; 84 u32 ext_resistor_ohms; 85 /* 86 * DMA (thus cache coherency maintenance) requires the 87 * transfer buffers to live in their own cache lines. 88 */ 89 __le16 spi_tx_buf __aligned(IIO_DMA_MINALIGN); 90 }; 91 92 static int ad8460_hv_reset(struct ad8460_state *state) 93 { 94 int ret; 95 96 ret = regmap_set_bits(state->regmap, AD8460_CTRL_REG(0x00), 97 AD8460_HV_RESET_MSK); 98 if (ret) 99 return ret; 100 101 fsleep(20); 102 103 return regmap_clear_bits(state->regmap, AD8460_CTRL_REG(0x00), 104 AD8460_HV_RESET_MSK); 105 } 106 107 static int ad8460_reset(const struct ad8460_state *state) 108 { 109 struct device *dev = &state->spi->dev; 110 struct gpio_desc *reset; 111 112 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 113 if (IS_ERR(reset)) 114 return dev_err_probe(dev, PTR_ERR(reset), 115 "Failed to get reset gpio"); 116 if (reset) { 117 /* minimum duration of 10ns */ 118 ndelay(10); 119 gpiod_set_value_cansleep(reset, 1); 120 return 0; 121 } 122 123 /* bring all registers to their default state */ 124 return regmap_write(state->regmap, AD8460_CTRL_REG(0x03), 1); 125 } 126 127 static int ad8460_enable_apg_mode(struct ad8460_state *state, int val) 128 { 129 int ret; 130 131 ret = regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x02), 132 AD8460_APG_MODE_ENABLE_MSK, 133 FIELD_PREP(AD8460_APG_MODE_ENABLE_MSK, val)); 134 if (ret) 135 return ret; 136 137 return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x00), 138 AD8460_WAVE_GEN_MODE_MSK, 139 FIELD_PREP(AD8460_WAVE_GEN_MODE_MSK, val)); 140 } 141 142 static int ad8460_read_shutdown_flag(struct ad8460_state *state, u64 *flag) 143 { 144 int ret, val; 145 146 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x0E), &val); 147 if (ret) 148 return ret; 149 150 *flag = FIELD_GET(AD8460_SHUTDOWN_FLAG_MSK, val); 151 return 0; 152 } 153 154 static int ad8460_get_hvdac_word(struct ad8460_state *state, int index, int *val) 155 { 156 int ret; 157 158 ret = regmap_bulk_read(state->regmap, AD8460_HVDAC_DATA_WORD(index), 159 &state->spi_tx_buf, AD8460_DATA_BYTE_WORD_LENGTH); 160 if (ret) 161 return ret; 162 163 *val = le16_to_cpu(state->spi_tx_buf); 164 165 return ret; 166 } 167 168 static int ad8460_set_hvdac_word(struct ad8460_state *state, int index, int val) 169 { 170 state->spi_tx_buf = cpu_to_le16(FIELD_PREP(AD8460_DATA_BYTE_FULL_MSK, val)); 171 172 return regmap_bulk_write(state->regmap, AD8460_HVDAC_DATA_WORD(index), 173 &state->spi_tx_buf, AD8460_DATA_BYTE_WORD_LENGTH); 174 } 175 176 static ssize_t ad8460_dac_input_read(struct iio_dev *indio_dev, uintptr_t private, 177 const struct iio_chan_spec *chan, char *buf) 178 { 179 struct ad8460_state *state = iio_priv(indio_dev); 180 unsigned int reg; 181 int ret; 182 183 ret = ad8460_get_hvdac_word(state, private, ®); 184 if (ret) 185 return ret; 186 187 return sysfs_emit(buf, "%u\n", reg); 188 } 189 190 static ssize_t ad8460_dac_input_write(struct iio_dev *indio_dev, uintptr_t private, 191 const struct iio_chan_spec *chan, 192 const char *buf, size_t len) 193 { 194 struct ad8460_state *state = iio_priv(indio_dev); 195 unsigned int reg; 196 int ret; 197 198 ret = kstrtou32(buf, 10, ®); 199 if (ret) 200 return ret; 201 202 guard(mutex)(&state->lock); 203 204 return ad8460_set_hvdac_word(state, private, reg); 205 } 206 207 static ssize_t ad8460_read_symbol(struct iio_dev *indio_dev, uintptr_t private, 208 const struct iio_chan_spec *chan, char *buf) 209 { 210 struct ad8460_state *state = iio_priv(indio_dev); 211 unsigned int reg; 212 int ret; 213 214 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x02), ®); 215 if (ret) 216 return ret; 217 218 return sysfs_emit(buf, "%lu\n", FIELD_GET(AD8460_PATTERN_DEPTH_MSK, reg)); 219 } 220 221 static ssize_t ad8460_write_symbol(struct iio_dev *indio_dev, uintptr_t private, 222 const struct iio_chan_spec *chan, 223 const char *buf, size_t len) 224 { 225 struct ad8460_state *state = iio_priv(indio_dev); 226 uint16_t sym; 227 int ret; 228 229 ret = kstrtou16(buf, 10, &sym); 230 if (ret) 231 return ret; 232 233 guard(mutex)(&state->lock); 234 235 return regmap_update_bits(state->regmap, 236 AD8460_CTRL_REG(0x02), 237 AD8460_PATTERN_DEPTH_MSK, 238 FIELD_PREP(AD8460_PATTERN_DEPTH_MSK, sym)); 239 } 240 241 static ssize_t ad8460_read_toggle_en(struct iio_dev *indio_dev, uintptr_t private, 242 const struct iio_chan_spec *chan, char *buf) 243 { 244 struct ad8460_state *state = iio_priv(indio_dev); 245 unsigned int reg; 246 int ret; 247 248 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x02), ®); 249 if (ret) 250 return ret; 251 252 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD8460_APG_MODE_ENABLE_MSK, reg)); 253 } 254 255 static ssize_t ad8460_write_toggle_en(struct iio_dev *indio_dev, uintptr_t private, 256 const struct iio_chan_spec *chan, 257 const char *buf, size_t len) 258 { 259 struct ad8460_state *state = iio_priv(indio_dev); 260 bool toggle_en; 261 int ret; 262 263 ret = kstrtobool(buf, &toggle_en); 264 if (ret) 265 return ret; 266 267 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) 268 return ad8460_enable_apg_mode(state, toggle_en); 269 unreachable(); 270 } 271 272 static ssize_t ad8460_read_powerdown(struct iio_dev *indio_dev, uintptr_t private, 273 const struct iio_chan_spec *chan, char *buf) 274 { 275 struct ad8460_state *state = iio_priv(indio_dev); 276 unsigned int reg; 277 int ret; 278 279 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x01), ®); 280 if (ret) 281 return ret; 282 283 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD8460_HVDAC_SLEEP_MSK, reg)); 284 } 285 286 static ssize_t ad8460_write_powerdown(struct iio_dev *indio_dev, uintptr_t private, 287 const struct iio_chan_spec *chan, 288 const char *buf, size_t len) 289 { 290 struct ad8460_state *state = iio_priv(indio_dev); 291 bool pwr_down; 292 u64 sdn_flag; 293 int ret; 294 295 ret = kstrtobool(buf, &pwr_down); 296 if (ret) 297 return ret; 298 299 guard(mutex)(&state->lock); 300 301 /* 302 * If powerdown is set, HVDAC is enabled and the HV driver is 303 * enabled via HV_RESET in case it is in shutdown mode, 304 * If powerdown is cleared, HVDAC is set to shutdown state 305 * as well as the HV driver. Quiescent current decreases and ouput is 306 * floating (high impedance). 307 */ 308 309 ret = regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x01), 310 AD8460_HVDAC_SLEEP_MSK, 311 FIELD_PREP(AD8460_HVDAC_SLEEP_MSK, pwr_down)); 312 if (ret) 313 return ret; 314 315 if (!pwr_down) { 316 ret = ad8460_read_shutdown_flag(state, &sdn_flag); 317 if (ret) 318 return ret; 319 320 if (sdn_flag) { 321 ret = ad8460_hv_reset(state); 322 if (ret) 323 return ret; 324 } 325 } 326 327 ret = regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x00), 328 AD8460_HV_SLEEP_MSK, 329 FIELD_PREP(AD8460_HV_SLEEP_MSK, !pwr_down)); 330 if (ret) 331 return ret; 332 333 return len; 334 } 335 336 static const char * const ad8460_powerdown_modes[] = { 337 "three_state", 338 }; 339 340 static int ad8460_get_powerdown_mode(struct iio_dev *indio_dev, 341 const struct iio_chan_spec *chan) 342 { 343 return 0; 344 } 345 346 static int ad8460_set_powerdown_mode(struct iio_dev *indio_dev, 347 const struct iio_chan_spec *chan, 348 unsigned int type) 349 { 350 return 0; 351 } 352 353 static int ad8460_set_sample(struct ad8460_state *state, int val) 354 { 355 int ret; 356 357 ret = ad8460_enable_apg_mode(state, 1); 358 if (ret) 359 return ret; 360 361 guard(mutex)(&state->lock); 362 ret = ad8460_set_hvdac_word(state, 0, val); 363 if (ret) 364 return ret; 365 366 return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x02), 367 AD8460_PATTERN_DEPTH_MSK, 368 FIELD_PREP(AD8460_PATTERN_DEPTH_MSK, 0)); 369 } 370 371 static int ad8460_set_fault_threshold(struct ad8460_state *state, 372 enum ad8460_fault_type fault, 373 unsigned int threshold) 374 { 375 return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x08 + fault), 376 AD8460_FAULT_LIMIT_MSK, 377 FIELD_PREP(AD8460_FAULT_LIMIT_MSK, threshold)); 378 } 379 380 static int ad8460_get_fault_threshold(struct ad8460_state *state, 381 enum ad8460_fault_type fault, 382 unsigned int *threshold) 383 { 384 unsigned int val; 385 int ret; 386 387 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x08 + fault), &val); 388 if (ret) 389 return ret; 390 391 *threshold = FIELD_GET(AD8460_FAULT_LIMIT_MSK, val); 392 393 return ret; 394 } 395 396 static int ad8460_set_fault_threshold_en(struct ad8460_state *state, 397 enum ad8460_fault_type fault, bool en) 398 { 399 return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x08 + fault), 400 AD8460_FAULT_ARM_MSK, 401 FIELD_PREP(AD8460_FAULT_ARM_MSK, en)); 402 } 403 404 static int ad8460_get_fault_threshold_en(struct ad8460_state *state, 405 enum ad8460_fault_type fault, bool *en) 406 { 407 unsigned int val; 408 int ret; 409 410 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x08 + fault), &val); 411 if (ret) 412 return ret; 413 414 *en = FIELD_GET(AD8460_FAULT_ARM_MSK, val); 415 416 return 0; 417 } 418 419 static int ad8460_write_raw(struct iio_dev *indio_dev, 420 struct iio_chan_spec const *chan, int val, int val2, 421 long mask) 422 { 423 struct ad8460_state *state = iio_priv(indio_dev); 424 425 switch (mask) { 426 case IIO_CHAN_INFO_RAW: 427 switch (chan->type) { 428 case IIO_VOLTAGE: 429 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) 430 return ad8460_set_sample(state, val); 431 unreachable(); 432 case IIO_CURRENT: 433 return regmap_write(state->regmap, AD8460_CTRL_REG(0x04), 434 FIELD_PREP(AD8460_QUIESCENT_CURRENT_MSK, val)); 435 default: 436 return -EINVAL; 437 } 438 default: 439 return -EINVAL; 440 } 441 } 442 443 static int ad8460_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, 444 int *val, int *val2, long mask) 445 { 446 struct ad8460_state *state = iio_priv(indio_dev); 447 int data, ret; 448 449 switch (mask) { 450 case IIO_CHAN_INFO_RAW: 451 switch (chan->type) { 452 case IIO_VOLTAGE: 453 scoped_guard(mutex, &state->lock) { 454 ret = ad8460_get_hvdac_word(state, 0, &data); 455 if (ret) 456 return ret; 457 } 458 *val = data; 459 return IIO_VAL_INT; 460 case IIO_CURRENT: 461 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x04), 462 &data); 463 if (ret) 464 return ret; 465 *val = data; 466 return IIO_VAL_INT; 467 case IIO_TEMP: 468 ret = iio_read_channel_raw(state->tmp_adc_channel, &data); 469 if (ret) 470 return ret; 471 *val = data; 472 return IIO_VAL_INT; 473 default: 474 return -EINVAL; 475 } 476 case IIO_CHAN_INFO_SAMP_FREQ: 477 *val = clk_get_rate(state->sync_clk); 478 return IIO_VAL_INT; 479 case IIO_CHAN_INFO_SCALE: 480 /* 481 * vCONV = vNOMINAL_SPAN * (DAC_CODE / 2**14) - 40V 482 * vMAX = vNOMINAL_SPAN * (2**14 / 2**14) - 40V 483 * vMIN = vNOMINAL_SPAN * (0 / 2**14) - 40V 484 * vADJ = vCONV * (2000 / rSET) * (vREF / 1.2) 485 * vSPAN = vADJ_MAX - vADJ_MIN 486 * See datasheet page 49, section FULL-SCALE REDUCTION 487 */ 488 *val = AD8460_NOMINAL_VOLTAGE_SPAN * 2000 * state->refio_1p2v_mv; 489 *val2 = state->ext_resistor_ohms * 1200; 490 return IIO_VAL_FRACTIONAL; 491 default: 492 return -EINVAL; 493 } 494 } 495 496 static int ad8460_select_fault_type(int chan_type, enum iio_event_direction dir) 497 { 498 switch (chan_type) { 499 case IIO_VOLTAGE: 500 switch (dir) { 501 case IIO_EV_DIR_RISING: 502 return AD8460_OVERVOLTAGE_POS; 503 case IIO_EV_DIR_FALLING: 504 return AD8460_OVERVOLTAGE_NEG; 505 default: 506 return -EINVAL; 507 } 508 case IIO_CURRENT: 509 switch (dir) { 510 case IIO_EV_DIR_RISING: 511 return AD8460_OVERCURRENT_SRC; 512 case IIO_EV_DIR_FALLING: 513 return AD8460_OVERCURRENT_SNK; 514 default: 515 return -EINVAL; 516 } 517 case IIO_TEMP: 518 switch (dir) { 519 case IIO_EV_DIR_RISING: 520 return AD8460_OVERTEMPERATURE; 521 default: 522 return -EINVAL; 523 } 524 default: 525 return -EINVAL; 526 } 527 } 528 529 static int ad8460_write_event_value(struct iio_dev *indio_dev, 530 const struct iio_chan_spec *chan, 531 enum iio_event_type type, 532 enum iio_event_direction dir, 533 enum iio_event_info info, int val, int val2) 534 { 535 struct ad8460_state *state = iio_priv(indio_dev); 536 int fault; 537 538 if (type != IIO_EV_TYPE_THRESH) 539 return -EINVAL; 540 541 if (info != IIO_EV_INFO_VALUE) 542 return -EINVAL; 543 544 fault = ad8460_select_fault_type(chan->type, dir); 545 if (fault < 0) 546 return fault; 547 548 return ad8460_set_fault_threshold(state, fault, val); 549 } 550 551 static int ad8460_read_event_value(struct iio_dev *indio_dev, 552 const struct iio_chan_spec *chan, 553 enum iio_event_type type, 554 enum iio_event_direction dir, 555 enum iio_event_info info, int *val, int *val2) 556 { 557 struct ad8460_state *state = iio_priv(indio_dev); 558 int fault; 559 560 if (type != IIO_EV_TYPE_THRESH) 561 return -EINVAL; 562 563 if (info != IIO_EV_INFO_VALUE) 564 return -EINVAL; 565 566 fault = ad8460_select_fault_type(chan->type, dir); 567 if (fault < 0) 568 return fault; 569 570 return ad8460_get_fault_threshold(state, fault, val); 571 } 572 573 static int ad8460_write_event_config(struct iio_dev *indio_dev, 574 const struct iio_chan_spec *chan, 575 enum iio_event_type type, 576 enum iio_event_direction dir, bool val) 577 { 578 struct ad8460_state *state = iio_priv(indio_dev); 579 int fault; 580 581 if (type != IIO_EV_TYPE_THRESH) 582 return -EINVAL; 583 584 fault = ad8460_select_fault_type(chan->type, dir); 585 if (fault < 0) 586 return fault; 587 588 return ad8460_set_fault_threshold_en(state, fault, val); 589 } 590 591 static int ad8460_read_event_config(struct iio_dev *indio_dev, 592 const struct iio_chan_spec *chan, 593 enum iio_event_type type, 594 enum iio_event_direction dir) 595 { 596 struct ad8460_state *state = iio_priv(indio_dev); 597 int fault, ret; 598 bool en; 599 600 if (type != IIO_EV_TYPE_THRESH) 601 return -EINVAL; 602 603 fault = ad8460_select_fault_type(chan->type, dir); 604 if (fault < 0) 605 return fault; 606 607 ret = ad8460_get_fault_threshold_en(state, fault, &en); 608 if (ret) 609 return ret; 610 611 return en; 612 } 613 614 static int ad8460_reg_access(struct iio_dev *indio_dev, unsigned int reg, 615 unsigned int writeval, unsigned int *readval) 616 { 617 struct ad8460_state *state = iio_priv(indio_dev); 618 619 if (readval) 620 return regmap_read(state->regmap, reg, readval); 621 622 return regmap_write(state->regmap, reg, writeval); 623 } 624 625 static int ad8460_buffer_preenable(struct iio_dev *indio_dev) 626 { 627 struct ad8460_state *state = iio_priv(indio_dev); 628 629 return ad8460_enable_apg_mode(state, 0); 630 } 631 632 static int ad8460_buffer_postdisable(struct iio_dev *indio_dev) 633 { 634 struct ad8460_state *state = iio_priv(indio_dev); 635 636 return ad8460_enable_apg_mode(state, 1); 637 } 638 639 static const struct iio_buffer_setup_ops ad8460_buffer_setup_ops = { 640 .preenable = &ad8460_buffer_preenable, 641 .postdisable = &ad8460_buffer_postdisable, 642 }; 643 644 static const struct iio_info ad8460_info = { 645 .read_raw = &ad8460_read_raw, 646 .write_raw = &ad8460_write_raw, 647 .write_event_value = &ad8460_write_event_value, 648 .read_event_value = &ad8460_read_event_value, 649 .write_event_config = &ad8460_write_event_config, 650 .read_event_config = &ad8460_read_event_config, 651 .debugfs_reg_access = &ad8460_reg_access, 652 }; 653 654 static const struct iio_enum ad8460_powerdown_mode_enum = { 655 .items = ad8460_powerdown_modes, 656 .num_items = ARRAY_SIZE(ad8460_powerdown_modes), 657 .get = ad8460_get_powerdown_mode, 658 .set = ad8460_set_powerdown_mode, 659 }; 660 661 #define AD8460_CHAN_EXT_INFO(_name, _what, _read, _write) { \ 662 .name = (_name), \ 663 .read = (_read), \ 664 .write = (_write), \ 665 .private = (_what), \ 666 .shared = IIO_SEPARATE, \ 667 } 668 669 static const struct iio_chan_spec_ext_info ad8460_ext_info[] = { 670 AD8460_CHAN_EXT_INFO("raw0", 0, ad8460_dac_input_read, 671 ad8460_dac_input_write), 672 AD8460_CHAN_EXT_INFO("raw1", 1, ad8460_dac_input_read, 673 ad8460_dac_input_write), 674 AD8460_CHAN_EXT_INFO("raw2", 2, ad8460_dac_input_read, 675 ad8460_dac_input_write), 676 AD8460_CHAN_EXT_INFO("raw3", 3, ad8460_dac_input_read, 677 ad8460_dac_input_write), 678 AD8460_CHAN_EXT_INFO("raw4", 4, ad8460_dac_input_read, 679 ad8460_dac_input_write), 680 AD8460_CHAN_EXT_INFO("raw5", 5, ad8460_dac_input_read, 681 ad8460_dac_input_write), 682 AD8460_CHAN_EXT_INFO("raw6", 6, ad8460_dac_input_read, 683 ad8460_dac_input_write), 684 AD8460_CHAN_EXT_INFO("raw7", 7, ad8460_dac_input_read, 685 ad8460_dac_input_write), 686 AD8460_CHAN_EXT_INFO("raw8", 8, ad8460_dac_input_read, 687 ad8460_dac_input_write), 688 AD8460_CHAN_EXT_INFO("raw9", 9, ad8460_dac_input_read, 689 ad8460_dac_input_write), 690 AD8460_CHAN_EXT_INFO("raw10", 10, ad8460_dac_input_read, 691 ad8460_dac_input_write), 692 AD8460_CHAN_EXT_INFO("raw11", 11, ad8460_dac_input_read, 693 ad8460_dac_input_write), 694 AD8460_CHAN_EXT_INFO("raw12", 12, ad8460_dac_input_read, 695 ad8460_dac_input_write), 696 AD8460_CHAN_EXT_INFO("raw13", 13, ad8460_dac_input_read, 697 ad8460_dac_input_write), 698 AD8460_CHAN_EXT_INFO("raw14", 14, ad8460_dac_input_read, 699 ad8460_dac_input_write), 700 AD8460_CHAN_EXT_INFO("raw15", 15, ad8460_dac_input_read, 701 ad8460_dac_input_write), 702 AD8460_CHAN_EXT_INFO("toggle_en", 0, ad8460_read_toggle_en, 703 ad8460_write_toggle_en), 704 AD8460_CHAN_EXT_INFO("symbol", 0, ad8460_read_symbol, 705 ad8460_write_symbol), 706 AD8460_CHAN_EXT_INFO("powerdown", 0, ad8460_read_powerdown, 707 ad8460_write_powerdown), 708 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad8460_powerdown_mode_enum), 709 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, 710 &ad8460_powerdown_mode_enum), 711 { } 712 }; 713 714 static const struct iio_event_spec ad8460_events[] = { 715 { 716 .type = IIO_EV_TYPE_THRESH, 717 .dir = IIO_EV_DIR_RISING, 718 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 719 BIT(IIO_EV_INFO_ENABLE), 720 }, 721 { 722 .type = IIO_EV_TYPE_THRESH, 723 .dir = IIO_EV_DIR_FALLING, 724 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 725 BIT(IIO_EV_INFO_ENABLE), 726 }, 727 }; 728 729 #define AD8460_VOLTAGE_CHAN { \ 730 .type = IIO_VOLTAGE, \ 731 .info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 732 BIT(IIO_CHAN_INFO_RAW) | \ 733 BIT(IIO_CHAN_INFO_SCALE), \ 734 .output = 1, \ 735 .indexed = 1, \ 736 .channel = 0, \ 737 .scan_index = 0, \ 738 .scan_type = { \ 739 .sign = 'u', \ 740 .realbits = 14, \ 741 .storagebits = 16, \ 742 .endianness = IIO_CPU, \ 743 }, \ 744 .ext_info = ad8460_ext_info, \ 745 .event_spec = ad8460_events, \ 746 .num_event_specs = ARRAY_SIZE(ad8460_events), \ 747 } 748 749 #define AD8460_CURRENT_CHAN { \ 750 .type = IIO_CURRENT, \ 751 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 752 .output = 1, \ 753 .indexed = 1, \ 754 .channel = 0, \ 755 .scan_index = -1, \ 756 .event_spec = ad8460_events, \ 757 .num_event_specs = ARRAY_SIZE(ad8460_events), \ 758 } 759 760 #define AD8460_TEMP_CHAN { \ 761 .type = IIO_TEMP, \ 762 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 763 .indexed = 1, \ 764 .channel = 0, \ 765 .scan_index = -1, \ 766 .event_spec = ad8460_events, \ 767 .num_event_specs = 1, \ 768 } 769 770 static const struct iio_chan_spec ad8460_channels[] = { 771 AD8460_VOLTAGE_CHAN, 772 AD8460_CURRENT_CHAN, 773 }; 774 775 static const struct iio_chan_spec ad8460_channels_with_tmp_adc[] = { 776 AD8460_VOLTAGE_CHAN, 777 AD8460_CURRENT_CHAN, 778 AD8460_TEMP_CHAN, 779 }; 780 781 static const struct regmap_config ad8460_regmap_config = { 782 .reg_bits = 8, 783 .val_bits = 8, 784 .max_register = 0x7F, 785 }; 786 787 static const char * const ad8460_supplies[] = { 788 "avdd_3p3v", "dvdd_3p3v", "vcc_5v", "hvcc", "hvee", "vref_5v" 789 }; 790 791 static int ad8460_probe(struct spi_device *spi) 792 { 793 struct device *dev = &spi->dev; 794 struct ad8460_state *state; 795 struct iio_dev *indio_dev; 796 u32 tmp[2], temp; 797 int ret; 798 799 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state)); 800 if (!indio_dev) 801 return -ENOMEM; 802 803 state = iio_priv(indio_dev); 804 805 indio_dev->name = "ad8460"; 806 indio_dev->info = &ad8460_info; 807 808 state->spi = spi; 809 810 state->regmap = devm_regmap_init_spi(spi, &ad8460_regmap_config); 811 if (IS_ERR(state->regmap)) 812 return dev_err_probe(dev, PTR_ERR(state->regmap), 813 "Failed to initialize regmap"); 814 815 ret = devm_mutex_init(dev, &state->lock); 816 if (ret) 817 return ret; 818 819 state->sync_clk = devm_clk_get_enabled(dev, NULL); 820 if (IS_ERR(state->sync_clk)) 821 return dev_err_probe(dev, PTR_ERR(state->sync_clk), 822 "Failed to get sync clk\n"); 823 824 state->tmp_adc_channel = devm_iio_channel_get(dev, "ad8460-tmp"); 825 if (IS_ERR(state->tmp_adc_channel)) { 826 if (PTR_ERR(state->tmp_adc_channel) == -EPROBE_DEFER) 827 return -EPROBE_DEFER; 828 indio_dev->channels = ad8460_channels; 829 indio_dev->num_channels = ARRAY_SIZE(ad8460_channels); 830 } else { 831 indio_dev->channels = ad8460_channels_with_tmp_adc; 832 indio_dev->num_channels = ARRAY_SIZE(ad8460_channels_with_tmp_adc); 833 } 834 835 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad8460_supplies), 836 ad8460_supplies); 837 if (ret) 838 return dev_err_probe(dev, ret, 839 "Failed to enable power supplies\n"); 840 841 ret = devm_regulator_get_enable_read_voltage(dev, "refio_1p2v"); 842 if (ret < 0 && ret != -ENODEV) 843 return dev_err_probe(dev, ret, "Failed to get reference voltage\n"); 844 845 state->refio_1p2v_mv = ret == -ENODEV ? 1200 : ret / 1000; 846 847 if (!in_range(state->refio_1p2v_mv, AD8460_MIN_VREFIO_UV / 1000, 848 AD8460_MAX_VREFIO_UV / 1000)) 849 return dev_err_probe(dev, -EINVAL, 850 "Invalid ref voltage range(%u mV) [%u mV, %u mV]\n", 851 state->refio_1p2v_mv, 852 AD8460_MIN_VREFIO_UV / 1000, 853 AD8460_MAX_VREFIO_UV / 1000); 854 855 ret = device_property_read_u32(dev, "adi,external-resistor-ohms", 856 &state->ext_resistor_ohms); 857 if (ret) 858 state->ext_resistor_ohms = 2000; 859 else if (!in_range(state->ext_resistor_ohms, AD8460_MIN_EXT_RESISTOR_OHMS, 860 AD8460_MAX_EXT_RESISTOR_OHMS)) 861 return dev_err_probe(dev, -EINVAL, 862 "Invalid resistor set range(%u) [%u, %u]\n", 863 state->ext_resistor_ohms, 864 AD8460_MIN_EXT_RESISTOR_OHMS, 865 AD8460_MAX_EXT_RESISTOR_OHMS); 866 867 ret = device_property_read_u32_array(dev, "adi,range-microamp", 868 tmp, ARRAY_SIZE(tmp)); 869 if (!ret) { 870 if (in_range(tmp[1], 0, AD8460_ABS_MAX_OVERCURRENT_UA)) 871 regmap_write(state->regmap, AD8460_CTRL_REG(0x08), 872 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 873 AD8460_CURRENT_LIMIT_CONV(tmp[1])); 874 875 if (in_range(tmp[0], -AD8460_ABS_MAX_OVERCURRENT_UA, 0)) 876 regmap_write(state->regmap, AD8460_CTRL_REG(0x09), 877 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 878 AD8460_CURRENT_LIMIT_CONV(abs(tmp[0]))); 879 } 880 881 ret = device_property_read_u32_array(dev, "adi,range-microvolt", 882 tmp, ARRAY_SIZE(tmp)); 883 if (!ret) { 884 if (in_range(tmp[1], 0, AD8460_ABS_MAX_OVERVOLTAGE_UV)) 885 regmap_write(state->regmap, AD8460_CTRL_REG(0x0A), 886 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 887 AD8460_VOLTAGE_LIMIT_CONV(tmp[1])); 888 889 if (in_range(tmp[0], -AD8460_ABS_MAX_OVERVOLTAGE_UV, 0)) 890 regmap_write(state->regmap, AD8460_CTRL_REG(0x0B), 891 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 892 AD8460_VOLTAGE_LIMIT_CONV(abs(tmp[0]))); 893 } 894 895 ret = device_property_read_u32(dev, "adi,max-millicelsius", &temp); 896 if (!ret) { 897 if (in_range(temp, AD8460_MIN_OVERTEMPERATURE_MC, 898 AD8460_MAX_OVERTEMPERATURE_MC)) 899 regmap_write(state->regmap, AD8460_CTRL_REG(0x0C), 900 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 901 AD8460_TEMP_LIMIT_CONV(abs(temp))); 902 } 903 904 ret = ad8460_reset(state); 905 if (ret) 906 return ret; 907 908 /* Enables DAC by default */ 909 ret = regmap_clear_bits(state->regmap, AD8460_CTRL_REG(0x01), 910 AD8460_HVDAC_SLEEP_MSK); 911 if (ret) 912 return ret; 913 914 indio_dev->modes = INDIO_DIRECT_MODE; 915 indio_dev->setup_ops = &ad8460_buffer_setup_ops; 916 917 ret = devm_iio_dmaengine_buffer_setup_ext(dev, indio_dev, "tx", 918 IIO_BUFFER_DIRECTION_OUT); 919 if (ret) 920 return dev_err_probe(dev, ret, 921 "Failed to get DMA buffer\n"); 922 923 return devm_iio_device_register(dev, indio_dev); 924 } 925 926 static const struct of_device_id ad8460_of_match[] = { 927 { .compatible = "adi,ad8460" }, 928 { } 929 }; 930 MODULE_DEVICE_TABLE(of, ad8460_of_match); 931 932 static const struct spi_device_id ad8460_spi_match[] = { 933 { .name = "ad8460" }, 934 { } 935 }; 936 MODULE_DEVICE_TABLE(spi, ad8460_spi_match); 937 938 static struct spi_driver ad8460_driver = { 939 .driver = { 940 .name = "ad8460", 941 .of_match_table = ad8460_of_match, 942 }, 943 .probe = ad8460_probe, 944 .id_table = ad8460_spi_match, 945 }; 946 module_spi_driver(ad8460_driver); 947 948 MODULE_AUTHOR("Mariel Tinaco <mariel.tinaco@analog.com"); 949 MODULE_DESCRIPTION("AD8460 DAC driver"); 950 MODULE_LICENSE("GPL"); 951 MODULE_IMPORT_NS(IIO_DMAENGINE_BUFFER); 952