1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD8460 Waveform generator DAC Driver 4 * 5 * Copyright (C) 2024 Analog Devices, Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spi/spi.h> 20 21 #include <linux/iio/buffer.h> 22 #include <linux/iio/buffer-dma.h> 23 #include <linux/iio/buffer-dmaengine.h> 24 #include <linux/iio/consumer.h> 25 #include <linux/iio/events.h> 26 #include <linux/iio/iio.h> 27 28 #define AD8460_CTRL_REG(x) (x) 29 #define AD8460_HVDAC_DATA_WORD(x) (0x60 + (2 * (x))) 30 31 #define AD8460_HV_RESET_MSK BIT(7) 32 #define AD8460_HV_SLEEP_MSK BIT(4) 33 #define AD8460_WAVE_GEN_MODE_MSK BIT(0) 34 35 #define AD8460_HVDAC_SLEEP_MSK BIT(3) 36 37 #define AD8460_FAULT_ARM_MSK BIT(7) 38 #define AD8460_FAULT_LIMIT_MSK GENMASK(6, 0) 39 40 #define AD8460_APG_MODE_ENABLE_MSK BIT(5) 41 #define AD8460_PATTERN_DEPTH_MSK GENMASK(3, 0) 42 43 #define AD8460_QUIESCENT_CURRENT_MSK GENMASK(7, 0) 44 45 #define AD8460_SHUTDOWN_FLAG_MSK BIT(7) 46 47 #define AD8460_DATA_BYTE_LOW_MSK GENMASK(7, 0) 48 #define AD8460_DATA_BYTE_HIGH_MSK GENMASK(5, 0) 49 #define AD8460_DATA_BYTE_FULL_MSK GENMASK(13, 0) 50 51 #define AD8460_DEFAULT_FAULT_PROTECT 0x00 52 #define AD8460_DATA_BYTE_WORD_LENGTH 2 53 #define AD8460_NUM_DATA_WORDS 16 54 #define AD8460_NOMINAL_VOLTAGE_SPAN 80 55 #define AD8460_MIN_EXT_RESISTOR_OHMS 2000 56 #define AD8460_MAX_EXT_RESISTOR_OHMS 20000 57 #define AD8460_MIN_VREFIO_UV 120000 58 #define AD8460_MAX_VREFIO_UV 1200000 59 #define AD8460_ABS_MAX_OVERVOLTAGE_UV 55000000 60 #define AD8460_ABS_MAX_OVERCURRENT_UA 1000000 61 #define AD8460_MAX_OVERTEMPERATURE_MC 150000 62 #define AD8460_MIN_OVERTEMPERATURE_MC 20000 63 #define AD8460_CURRENT_LIMIT_CONV(x) ((x) / 15625) 64 #define AD8460_VOLTAGE_LIMIT_CONV(x) ((x) / 1953000) 65 #define AD8460_TEMP_LIMIT_CONV(x) (((x) + 266640) / 6510) 66 67 enum ad8460_fault_type { 68 AD8460_OVERCURRENT_SRC, 69 AD8460_OVERCURRENT_SNK, 70 AD8460_OVERVOLTAGE_POS, 71 AD8460_OVERVOLTAGE_NEG, 72 AD8460_OVERTEMPERATURE, 73 }; 74 75 struct ad8460_state { 76 struct spi_device *spi; 77 struct regmap *regmap; 78 struct iio_channel *tmp_adc_channel; 79 struct clk *sync_clk; 80 /* lock to protect against multiple access to the device and shared data */ 81 struct mutex lock; 82 int refio_1p2v_mv; 83 u32 ext_resistor_ohms; 84 /* 85 * DMA (thus cache coherency maintenance) requires the 86 * transfer buffers to live in their own cache lines. 87 */ 88 __le16 spi_tx_buf __aligned(IIO_DMA_MINALIGN); 89 }; 90 91 static int ad8460_hv_reset(struct ad8460_state *state) 92 { 93 int ret; 94 95 ret = regmap_set_bits(state->regmap, AD8460_CTRL_REG(0x00), 96 AD8460_HV_RESET_MSK); 97 if (ret) 98 return ret; 99 100 fsleep(20); 101 102 return regmap_clear_bits(state->regmap, AD8460_CTRL_REG(0x00), 103 AD8460_HV_RESET_MSK); 104 } 105 106 static int ad8460_reset(const struct ad8460_state *state) 107 { 108 struct device *dev = &state->spi->dev; 109 struct gpio_desc *reset; 110 111 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 112 if (IS_ERR(reset)) 113 return dev_err_probe(dev, PTR_ERR(reset), 114 "Failed to get reset gpio"); 115 if (reset) { 116 /* minimum duration of 10ns */ 117 ndelay(10); 118 gpiod_set_value_cansleep(reset, 1); 119 return 0; 120 } 121 122 /* bring all registers to their default state */ 123 return regmap_write(state->regmap, AD8460_CTRL_REG(0x03), 1); 124 } 125 126 static int ad8460_enable_apg_mode(struct ad8460_state *state, int val) 127 { 128 int ret; 129 130 ret = regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x02), 131 AD8460_APG_MODE_ENABLE_MSK, 132 FIELD_PREP(AD8460_APG_MODE_ENABLE_MSK, val)); 133 if (ret) 134 return ret; 135 136 return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x00), 137 AD8460_WAVE_GEN_MODE_MSK, 138 FIELD_PREP(AD8460_WAVE_GEN_MODE_MSK, val)); 139 } 140 141 static int ad8460_read_shutdown_flag(struct ad8460_state *state, u64 *flag) 142 { 143 int ret, val; 144 145 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x0E), &val); 146 if (ret) 147 return ret; 148 149 *flag = FIELD_GET(AD8460_SHUTDOWN_FLAG_MSK, val); 150 return 0; 151 } 152 153 static int ad8460_get_hvdac_word(struct ad8460_state *state, int index, int *val) 154 { 155 int ret; 156 157 ret = regmap_bulk_read(state->regmap, AD8460_HVDAC_DATA_WORD(index), 158 &state->spi_tx_buf, AD8460_DATA_BYTE_WORD_LENGTH); 159 if (ret) 160 return ret; 161 162 *val = le16_to_cpu(state->spi_tx_buf); 163 164 return ret; 165 } 166 167 static int ad8460_set_hvdac_word(struct ad8460_state *state, int index, int val) 168 { 169 state->spi_tx_buf = cpu_to_le16(FIELD_PREP(AD8460_DATA_BYTE_FULL_MSK, val)); 170 171 return regmap_bulk_write(state->regmap, AD8460_HVDAC_DATA_WORD(index), 172 &state->spi_tx_buf, AD8460_DATA_BYTE_WORD_LENGTH); 173 } 174 175 static ssize_t ad8460_dac_input_read(struct iio_dev *indio_dev, uintptr_t private, 176 const struct iio_chan_spec *chan, char *buf) 177 { 178 struct ad8460_state *state = iio_priv(indio_dev); 179 unsigned int reg; 180 int ret; 181 182 ret = ad8460_get_hvdac_word(state, private, ®); 183 if (ret) 184 return ret; 185 186 return sysfs_emit(buf, "%u\n", reg); 187 } 188 189 static ssize_t ad8460_dac_input_write(struct iio_dev *indio_dev, uintptr_t private, 190 const struct iio_chan_spec *chan, 191 const char *buf, size_t len) 192 { 193 struct ad8460_state *state = iio_priv(indio_dev); 194 unsigned int reg; 195 int ret; 196 197 ret = kstrtou32(buf, 10, ®); 198 if (ret) 199 return ret; 200 201 guard(mutex)(&state->lock); 202 203 return ad8460_set_hvdac_word(state, private, reg); 204 } 205 206 static ssize_t ad8460_read_symbol(struct iio_dev *indio_dev, uintptr_t private, 207 const struct iio_chan_spec *chan, char *buf) 208 { 209 struct ad8460_state *state = iio_priv(indio_dev); 210 unsigned int reg; 211 int ret; 212 213 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x02), ®); 214 if (ret) 215 return ret; 216 217 return sysfs_emit(buf, "%lu\n", FIELD_GET(AD8460_PATTERN_DEPTH_MSK, reg)); 218 } 219 220 static ssize_t ad8460_write_symbol(struct iio_dev *indio_dev, uintptr_t private, 221 const struct iio_chan_spec *chan, 222 const char *buf, size_t len) 223 { 224 struct ad8460_state *state = iio_priv(indio_dev); 225 uint16_t sym; 226 int ret; 227 228 ret = kstrtou16(buf, 10, &sym); 229 if (ret) 230 return ret; 231 232 guard(mutex)(&state->lock); 233 234 return regmap_update_bits(state->regmap, 235 AD8460_CTRL_REG(0x02), 236 AD8460_PATTERN_DEPTH_MSK, 237 FIELD_PREP(AD8460_PATTERN_DEPTH_MSK, sym)); 238 } 239 240 static ssize_t ad8460_read_toggle_en(struct iio_dev *indio_dev, uintptr_t private, 241 const struct iio_chan_spec *chan, char *buf) 242 { 243 struct ad8460_state *state = iio_priv(indio_dev); 244 unsigned int reg; 245 int ret; 246 247 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x02), ®); 248 if (ret) 249 return ret; 250 251 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD8460_APG_MODE_ENABLE_MSK, reg)); 252 } 253 254 static ssize_t ad8460_write_toggle_en(struct iio_dev *indio_dev, uintptr_t private, 255 const struct iio_chan_spec *chan, 256 const char *buf, size_t len) 257 { 258 struct ad8460_state *state = iio_priv(indio_dev); 259 bool toggle_en; 260 int ret; 261 262 ret = kstrtobool(buf, &toggle_en); 263 if (ret) 264 return ret; 265 266 if (!iio_device_claim_direct(indio_dev)) 267 return -EBUSY; 268 269 ret = ad8460_enable_apg_mode(state, toggle_en); 270 iio_device_release_direct(indio_dev); 271 return ret; 272 } 273 274 static ssize_t ad8460_read_powerdown(struct iio_dev *indio_dev, uintptr_t private, 275 const struct iio_chan_spec *chan, char *buf) 276 { 277 struct ad8460_state *state = iio_priv(indio_dev); 278 unsigned int reg; 279 int ret; 280 281 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x01), ®); 282 if (ret) 283 return ret; 284 285 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD8460_HVDAC_SLEEP_MSK, reg)); 286 } 287 288 static ssize_t ad8460_write_powerdown(struct iio_dev *indio_dev, uintptr_t private, 289 const struct iio_chan_spec *chan, 290 const char *buf, size_t len) 291 { 292 struct ad8460_state *state = iio_priv(indio_dev); 293 bool pwr_down; 294 u64 sdn_flag; 295 int ret; 296 297 ret = kstrtobool(buf, &pwr_down); 298 if (ret) 299 return ret; 300 301 guard(mutex)(&state->lock); 302 303 /* 304 * If powerdown is set, HVDAC is enabled and the HV driver is 305 * enabled via HV_RESET in case it is in shutdown mode, 306 * If powerdown is cleared, HVDAC is set to shutdown state 307 * as well as the HV driver. Quiescent current decreases and ouput is 308 * floating (high impedance). 309 */ 310 311 ret = regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x01), 312 AD8460_HVDAC_SLEEP_MSK, 313 FIELD_PREP(AD8460_HVDAC_SLEEP_MSK, pwr_down)); 314 if (ret) 315 return ret; 316 317 if (!pwr_down) { 318 ret = ad8460_read_shutdown_flag(state, &sdn_flag); 319 if (ret) 320 return ret; 321 322 if (sdn_flag) { 323 ret = ad8460_hv_reset(state); 324 if (ret) 325 return ret; 326 } 327 } 328 329 ret = regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x00), 330 AD8460_HV_SLEEP_MSK, 331 FIELD_PREP(AD8460_HV_SLEEP_MSK, !pwr_down)); 332 if (ret) 333 return ret; 334 335 return len; 336 } 337 338 static const char * const ad8460_powerdown_modes[] = { 339 "three_state", 340 }; 341 342 static int ad8460_get_powerdown_mode(struct iio_dev *indio_dev, 343 const struct iio_chan_spec *chan) 344 { 345 return 0; 346 } 347 348 static int ad8460_set_powerdown_mode(struct iio_dev *indio_dev, 349 const struct iio_chan_spec *chan, 350 unsigned int type) 351 { 352 return 0; 353 } 354 355 static int ad8460_set_sample(struct ad8460_state *state, int val) 356 { 357 int ret; 358 359 ret = ad8460_enable_apg_mode(state, 1); 360 if (ret) 361 return ret; 362 363 guard(mutex)(&state->lock); 364 ret = ad8460_set_hvdac_word(state, 0, val); 365 if (ret) 366 return ret; 367 368 return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x02), 369 AD8460_PATTERN_DEPTH_MSK, 370 FIELD_PREP(AD8460_PATTERN_DEPTH_MSK, 0)); 371 } 372 373 static int ad8460_set_fault_threshold(struct ad8460_state *state, 374 enum ad8460_fault_type fault, 375 unsigned int threshold) 376 { 377 return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x08 + fault), 378 AD8460_FAULT_LIMIT_MSK, 379 FIELD_PREP(AD8460_FAULT_LIMIT_MSK, threshold)); 380 } 381 382 static int ad8460_get_fault_threshold(struct ad8460_state *state, 383 enum ad8460_fault_type fault, 384 unsigned int *threshold) 385 { 386 unsigned int val; 387 int ret; 388 389 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x08 + fault), &val); 390 if (ret) 391 return ret; 392 393 *threshold = FIELD_GET(AD8460_FAULT_LIMIT_MSK, val); 394 395 return ret; 396 } 397 398 static int ad8460_set_fault_threshold_en(struct ad8460_state *state, 399 enum ad8460_fault_type fault, bool en) 400 { 401 return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x08 + fault), 402 AD8460_FAULT_ARM_MSK, 403 FIELD_PREP(AD8460_FAULT_ARM_MSK, en)); 404 } 405 406 static int ad8460_get_fault_threshold_en(struct ad8460_state *state, 407 enum ad8460_fault_type fault, bool *en) 408 { 409 unsigned int val; 410 int ret; 411 412 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x08 + fault), &val); 413 if (ret) 414 return ret; 415 416 *en = FIELD_GET(AD8460_FAULT_ARM_MSK, val); 417 418 return 0; 419 } 420 421 static int ad8460_write_raw(struct iio_dev *indio_dev, 422 struct iio_chan_spec const *chan, int val, int val2, 423 long mask) 424 { 425 struct ad8460_state *state = iio_priv(indio_dev); 426 int ret; 427 428 switch (mask) { 429 case IIO_CHAN_INFO_RAW: 430 switch (chan->type) { 431 case IIO_VOLTAGE: 432 if (!iio_device_claim_direct(indio_dev)) 433 return -EBUSY; 434 ret = ad8460_set_sample(state, val); 435 iio_device_release_direct(indio_dev); 436 return ret; 437 case IIO_CURRENT: 438 return regmap_write(state->regmap, AD8460_CTRL_REG(0x04), 439 FIELD_PREP(AD8460_QUIESCENT_CURRENT_MSK, val)); 440 default: 441 return -EINVAL; 442 } 443 default: 444 return -EINVAL; 445 } 446 } 447 448 static int ad8460_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, 449 int *val, int *val2, long mask) 450 { 451 struct ad8460_state *state = iio_priv(indio_dev); 452 int data, ret; 453 454 switch (mask) { 455 case IIO_CHAN_INFO_RAW: 456 switch (chan->type) { 457 case IIO_VOLTAGE: 458 scoped_guard(mutex, &state->lock) { 459 ret = ad8460_get_hvdac_word(state, 0, &data); 460 if (ret) 461 return ret; 462 } 463 *val = data; 464 return IIO_VAL_INT; 465 case IIO_CURRENT: 466 ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x04), 467 &data); 468 if (ret) 469 return ret; 470 *val = data; 471 return IIO_VAL_INT; 472 case IIO_TEMP: 473 ret = iio_read_channel_raw(state->tmp_adc_channel, &data); 474 if (ret) 475 return ret; 476 *val = data; 477 return IIO_VAL_INT; 478 default: 479 return -EINVAL; 480 } 481 case IIO_CHAN_INFO_SAMP_FREQ: 482 *val = clk_get_rate(state->sync_clk); 483 return IIO_VAL_INT; 484 case IIO_CHAN_INFO_SCALE: 485 /* 486 * vCONV = vNOMINAL_SPAN * (DAC_CODE / 2**14) - 40V 487 * vMAX = vNOMINAL_SPAN * (2**14 / 2**14) - 40V 488 * vMIN = vNOMINAL_SPAN * (0 / 2**14) - 40V 489 * vADJ = vCONV * (2000 / rSET) * (vREF / 1.2) 490 * vSPAN = vADJ_MAX - vADJ_MIN 491 * See datasheet page 49, section FULL-SCALE REDUCTION 492 */ 493 *val = AD8460_NOMINAL_VOLTAGE_SPAN * 2000 * state->refio_1p2v_mv; 494 *val2 = state->ext_resistor_ohms * 1200; 495 return IIO_VAL_FRACTIONAL; 496 default: 497 return -EINVAL; 498 } 499 } 500 501 static int ad8460_select_fault_type(int chan_type, enum iio_event_direction dir) 502 { 503 switch (chan_type) { 504 case IIO_VOLTAGE: 505 switch (dir) { 506 case IIO_EV_DIR_RISING: 507 return AD8460_OVERVOLTAGE_POS; 508 case IIO_EV_DIR_FALLING: 509 return AD8460_OVERVOLTAGE_NEG; 510 default: 511 return -EINVAL; 512 } 513 case IIO_CURRENT: 514 switch (dir) { 515 case IIO_EV_DIR_RISING: 516 return AD8460_OVERCURRENT_SRC; 517 case IIO_EV_DIR_FALLING: 518 return AD8460_OVERCURRENT_SNK; 519 default: 520 return -EINVAL; 521 } 522 case IIO_TEMP: 523 switch (dir) { 524 case IIO_EV_DIR_RISING: 525 return AD8460_OVERTEMPERATURE; 526 default: 527 return -EINVAL; 528 } 529 default: 530 return -EINVAL; 531 } 532 } 533 534 static int ad8460_write_event_value(struct iio_dev *indio_dev, 535 const struct iio_chan_spec *chan, 536 enum iio_event_type type, 537 enum iio_event_direction dir, 538 enum iio_event_info info, int val, int val2) 539 { 540 struct ad8460_state *state = iio_priv(indio_dev); 541 int fault; 542 543 if (type != IIO_EV_TYPE_THRESH) 544 return -EINVAL; 545 546 if (info != IIO_EV_INFO_VALUE) 547 return -EINVAL; 548 549 fault = ad8460_select_fault_type(chan->type, dir); 550 if (fault < 0) 551 return fault; 552 553 return ad8460_set_fault_threshold(state, fault, val); 554 } 555 556 static int ad8460_read_event_value(struct iio_dev *indio_dev, 557 const struct iio_chan_spec *chan, 558 enum iio_event_type type, 559 enum iio_event_direction dir, 560 enum iio_event_info info, int *val, int *val2) 561 { 562 struct ad8460_state *state = iio_priv(indio_dev); 563 int fault; 564 565 if (type != IIO_EV_TYPE_THRESH) 566 return -EINVAL; 567 568 if (info != IIO_EV_INFO_VALUE) 569 return -EINVAL; 570 571 fault = ad8460_select_fault_type(chan->type, dir); 572 if (fault < 0) 573 return fault; 574 575 return ad8460_get_fault_threshold(state, fault, val); 576 } 577 578 static int ad8460_write_event_config(struct iio_dev *indio_dev, 579 const struct iio_chan_spec *chan, 580 enum iio_event_type type, 581 enum iio_event_direction dir, bool val) 582 { 583 struct ad8460_state *state = iio_priv(indio_dev); 584 int fault; 585 586 if (type != IIO_EV_TYPE_THRESH) 587 return -EINVAL; 588 589 fault = ad8460_select_fault_type(chan->type, dir); 590 if (fault < 0) 591 return fault; 592 593 return ad8460_set_fault_threshold_en(state, fault, val); 594 } 595 596 static int ad8460_read_event_config(struct iio_dev *indio_dev, 597 const struct iio_chan_spec *chan, 598 enum iio_event_type type, 599 enum iio_event_direction dir) 600 { 601 struct ad8460_state *state = iio_priv(indio_dev); 602 int fault, ret; 603 bool en; 604 605 if (type != IIO_EV_TYPE_THRESH) 606 return -EINVAL; 607 608 fault = ad8460_select_fault_type(chan->type, dir); 609 if (fault < 0) 610 return fault; 611 612 ret = ad8460_get_fault_threshold_en(state, fault, &en); 613 if (ret) 614 return ret; 615 616 return en; 617 } 618 619 static int ad8460_reg_access(struct iio_dev *indio_dev, unsigned int reg, 620 unsigned int writeval, unsigned int *readval) 621 { 622 struct ad8460_state *state = iio_priv(indio_dev); 623 624 if (readval) 625 return regmap_read(state->regmap, reg, readval); 626 627 return regmap_write(state->regmap, reg, writeval); 628 } 629 630 static int ad8460_buffer_preenable(struct iio_dev *indio_dev) 631 { 632 struct ad8460_state *state = iio_priv(indio_dev); 633 634 return ad8460_enable_apg_mode(state, 0); 635 } 636 637 static int ad8460_buffer_postdisable(struct iio_dev *indio_dev) 638 { 639 struct ad8460_state *state = iio_priv(indio_dev); 640 641 return ad8460_enable_apg_mode(state, 1); 642 } 643 644 static const struct iio_buffer_setup_ops ad8460_buffer_setup_ops = { 645 .preenable = &ad8460_buffer_preenable, 646 .postdisable = &ad8460_buffer_postdisable, 647 }; 648 649 static const struct iio_info ad8460_info = { 650 .read_raw = &ad8460_read_raw, 651 .write_raw = &ad8460_write_raw, 652 .write_event_value = &ad8460_write_event_value, 653 .read_event_value = &ad8460_read_event_value, 654 .write_event_config = &ad8460_write_event_config, 655 .read_event_config = &ad8460_read_event_config, 656 .debugfs_reg_access = &ad8460_reg_access, 657 }; 658 659 static const struct iio_enum ad8460_powerdown_mode_enum = { 660 .items = ad8460_powerdown_modes, 661 .num_items = ARRAY_SIZE(ad8460_powerdown_modes), 662 .get = ad8460_get_powerdown_mode, 663 .set = ad8460_set_powerdown_mode, 664 }; 665 666 #define AD8460_CHAN_EXT_INFO(_name, _what, _read, _write) { \ 667 .name = (_name), \ 668 .read = (_read), \ 669 .write = (_write), \ 670 .private = (_what), \ 671 .shared = IIO_SEPARATE, \ 672 } 673 674 static const struct iio_chan_spec_ext_info ad8460_ext_info[] = { 675 AD8460_CHAN_EXT_INFO("raw0", 0, ad8460_dac_input_read, 676 ad8460_dac_input_write), 677 AD8460_CHAN_EXT_INFO("raw1", 1, ad8460_dac_input_read, 678 ad8460_dac_input_write), 679 AD8460_CHAN_EXT_INFO("raw2", 2, ad8460_dac_input_read, 680 ad8460_dac_input_write), 681 AD8460_CHAN_EXT_INFO("raw3", 3, ad8460_dac_input_read, 682 ad8460_dac_input_write), 683 AD8460_CHAN_EXT_INFO("raw4", 4, ad8460_dac_input_read, 684 ad8460_dac_input_write), 685 AD8460_CHAN_EXT_INFO("raw5", 5, ad8460_dac_input_read, 686 ad8460_dac_input_write), 687 AD8460_CHAN_EXT_INFO("raw6", 6, ad8460_dac_input_read, 688 ad8460_dac_input_write), 689 AD8460_CHAN_EXT_INFO("raw7", 7, ad8460_dac_input_read, 690 ad8460_dac_input_write), 691 AD8460_CHAN_EXT_INFO("raw8", 8, ad8460_dac_input_read, 692 ad8460_dac_input_write), 693 AD8460_CHAN_EXT_INFO("raw9", 9, ad8460_dac_input_read, 694 ad8460_dac_input_write), 695 AD8460_CHAN_EXT_INFO("raw10", 10, ad8460_dac_input_read, 696 ad8460_dac_input_write), 697 AD8460_CHAN_EXT_INFO("raw11", 11, ad8460_dac_input_read, 698 ad8460_dac_input_write), 699 AD8460_CHAN_EXT_INFO("raw12", 12, ad8460_dac_input_read, 700 ad8460_dac_input_write), 701 AD8460_CHAN_EXT_INFO("raw13", 13, ad8460_dac_input_read, 702 ad8460_dac_input_write), 703 AD8460_CHAN_EXT_INFO("raw14", 14, ad8460_dac_input_read, 704 ad8460_dac_input_write), 705 AD8460_CHAN_EXT_INFO("raw15", 15, ad8460_dac_input_read, 706 ad8460_dac_input_write), 707 AD8460_CHAN_EXT_INFO("toggle_en", 0, ad8460_read_toggle_en, 708 ad8460_write_toggle_en), 709 AD8460_CHAN_EXT_INFO("symbol", 0, ad8460_read_symbol, 710 ad8460_write_symbol), 711 AD8460_CHAN_EXT_INFO("powerdown", 0, ad8460_read_powerdown, 712 ad8460_write_powerdown), 713 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad8460_powerdown_mode_enum), 714 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, 715 &ad8460_powerdown_mode_enum), 716 { } 717 }; 718 719 static const struct iio_event_spec ad8460_events[] = { 720 { 721 .type = IIO_EV_TYPE_THRESH, 722 .dir = IIO_EV_DIR_RISING, 723 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 724 BIT(IIO_EV_INFO_ENABLE), 725 }, 726 { 727 .type = IIO_EV_TYPE_THRESH, 728 .dir = IIO_EV_DIR_FALLING, 729 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 730 BIT(IIO_EV_INFO_ENABLE), 731 }, 732 }; 733 734 #define AD8460_VOLTAGE_CHAN { \ 735 .type = IIO_VOLTAGE, \ 736 .info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 737 BIT(IIO_CHAN_INFO_RAW) | \ 738 BIT(IIO_CHAN_INFO_SCALE), \ 739 .output = 1, \ 740 .indexed = 1, \ 741 .channel = 0, \ 742 .scan_index = 0, \ 743 .scan_type = { \ 744 .sign = 'u', \ 745 .realbits = 14, \ 746 .storagebits = 16, \ 747 .endianness = IIO_CPU, \ 748 }, \ 749 .ext_info = ad8460_ext_info, \ 750 .event_spec = ad8460_events, \ 751 .num_event_specs = ARRAY_SIZE(ad8460_events), \ 752 } 753 754 #define AD8460_CURRENT_CHAN { \ 755 .type = IIO_CURRENT, \ 756 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 757 .output = 1, \ 758 .indexed = 1, \ 759 .channel = 0, \ 760 .scan_index = -1, \ 761 .event_spec = ad8460_events, \ 762 .num_event_specs = ARRAY_SIZE(ad8460_events), \ 763 } 764 765 #define AD8460_TEMP_CHAN { \ 766 .type = IIO_TEMP, \ 767 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 768 .indexed = 1, \ 769 .channel = 0, \ 770 .scan_index = -1, \ 771 .event_spec = ad8460_events, \ 772 .num_event_specs = 1, \ 773 } 774 775 static const struct iio_chan_spec ad8460_channels[] = { 776 AD8460_VOLTAGE_CHAN, 777 AD8460_CURRENT_CHAN, 778 }; 779 780 static const struct iio_chan_spec ad8460_channels_with_tmp_adc[] = { 781 AD8460_VOLTAGE_CHAN, 782 AD8460_CURRENT_CHAN, 783 AD8460_TEMP_CHAN, 784 }; 785 786 static const struct regmap_config ad8460_regmap_config = { 787 .reg_bits = 8, 788 .val_bits = 8, 789 .max_register = 0x7F, 790 }; 791 792 static const char * const ad8460_supplies[] = { 793 "avdd_3p3v", "dvdd_3p3v", "vcc_5v", "hvcc", "hvee", "vref_5v" 794 }; 795 796 static int ad8460_probe(struct spi_device *spi) 797 { 798 struct device *dev = &spi->dev; 799 struct ad8460_state *state; 800 struct iio_dev *indio_dev; 801 u32 tmp[2], temp; 802 int ret; 803 804 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state)); 805 if (!indio_dev) 806 return -ENOMEM; 807 808 state = iio_priv(indio_dev); 809 810 indio_dev->name = "ad8460"; 811 indio_dev->info = &ad8460_info; 812 813 state->spi = spi; 814 815 state->regmap = devm_regmap_init_spi(spi, &ad8460_regmap_config); 816 if (IS_ERR(state->regmap)) 817 return dev_err_probe(dev, PTR_ERR(state->regmap), 818 "Failed to initialize regmap"); 819 820 ret = devm_mutex_init(dev, &state->lock); 821 if (ret) 822 return ret; 823 824 state->sync_clk = devm_clk_get_enabled(dev, NULL); 825 if (IS_ERR(state->sync_clk)) 826 return dev_err_probe(dev, PTR_ERR(state->sync_clk), 827 "Failed to get sync clk\n"); 828 829 state->tmp_adc_channel = devm_iio_channel_get(dev, "ad8460-tmp"); 830 if (IS_ERR(state->tmp_adc_channel)) { 831 if (PTR_ERR(state->tmp_adc_channel) == -EPROBE_DEFER) 832 return -EPROBE_DEFER; 833 indio_dev->channels = ad8460_channels; 834 indio_dev->num_channels = ARRAY_SIZE(ad8460_channels); 835 } else { 836 indio_dev->channels = ad8460_channels_with_tmp_adc; 837 indio_dev->num_channels = ARRAY_SIZE(ad8460_channels_with_tmp_adc); 838 } 839 840 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad8460_supplies), 841 ad8460_supplies); 842 if (ret) 843 return dev_err_probe(dev, ret, 844 "Failed to enable power supplies\n"); 845 846 ret = devm_regulator_get_enable_read_voltage(dev, "refio_1p2v"); 847 if (ret < 0 && ret != -ENODEV) 848 return dev_err_probe(dev, ret, "Failed to get reference voltage\n"); 849 850 state->refio_1p2v_mv = ret == -ENODEV ? 1200 : ret / 1000; 851 852 if (!in_range(state->refio_1p2v_mv, AD8460_MIN_VREFIO_UV / 1000, 853 AD8460_MAX_VREFIO_UV / 1000)) 854 return dev_err_probe(dev, -EINVAL, 855 "Invalid ref voltage range(%u mV) [%u mV, %u mV]\n", 856 state->refio_1p2v_mv, 857 AD8460_MIN_VREFIO_UV / 1000, 858 AD8460_MAX_VREFIO_UV / 1000); 859 860 ret = device_property_read_u32(dev, "adi,external-resistor-ohms", 861 &state->ext_resistor_ohms); 862 if (ret) 863 state->ext_resistor_ohms = 2000; 864 else if (!in_range(state->ext_resistor_ohms, AD8460_MIN_EXT_RESISTOR_OHMS, 865 AD8460_MAX_EXT_RESISTOR_OHMS)) 866 return dev_err_probe(dev, -EINVAL, 867 "Invalid resistor set range(%u) [%u, %u]\n", 868 state->ext_resistor_ohms, 869 AD8460_MIN_EXT_RESISTOR_OHMS, 870 AD8460_MAX_EXT_RESISTOR_OHMS); 871 872 ret = device_property_read_u32_array(dev, "adi,range-microamp", 873 tmp, ARRAY_SIZE(tmp)); 874 if (!ret) { 875 if (in_range(tmp[1], 0, AD8460_ABS_MAX_OVERCURRENT_UA)) 876 regmap_write(state->regmap, AD8460_CTRL_REG(0x08), 877 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 878 AD8460_CURRENT_LIMIT_CONV(tmp[1])); 879 880 if (in_range(tmp[0], -AD8460_ABS_MAX_OVERCURRENT_UA, 0)) 881 regmap_write(state->regmap, AD8460_CTRL_REG(0x09), 882 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 883 AD8460_CURRENT_LIMIT_CONV(abs(tmp[0]))); 884 } 885 886 ret = device_property_read_u32_array(dev, "adi,range-microvolt", 887 tmp, ARRAY_SIZE(tmp)); 888 if (!ret) { 889 if (in_range(tmp[1], 0, AD8460_ABS_MAX_OVERVOLTAGE_UV)) 890 regmap_write(state->regmap, AD8460_CTRL_REG(0x0A), 891 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 892 AD8460_VOLTAGE_LIMIT_CONV(tmp[1])); 893 894 if (in_range(tmp[0], -AD8460_ABS_MAX_OVERVOLTAGE_UV, 0)) 895 regmap_write(state->regmap, AD8460_CTRL_REG(0x0B), 896 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 897 AD8460_VOLTAGE_LIMIT_CONV(abs(tmp[0]))); 898 } 899 900 ret = device_property_read_u32(dev, "adi,max-millicelsius", &temp); 901 if (!ret) { 902 if (in_range(temp, AD8460_MIN_OVERTEMPERATURE_MC, 903 AD8460_MAX_OVERTEMPERATURE_MC)) 904 regmap_write(state->regmap, AD8460_CTRL_REG(0x0C), 905 FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) | 906 AD8460_TEMP_LIMIT_CONV(abs(temp))); 907 } 908 909 ret = ad8460_reset(state); 910 if (ret) 911 return ret; 912 913 /* Enables DAC by default */ 914 ret = regmap_clear_bits(state->regmap, AD8460_CTRL_REG(0x01), 915 AD8460_HVDAC_SLEEP_MSK); 916 if (ret) 917 return ret; 918 919 indio_dev->modes = INDIO_DIRECT_MODE; 920 indio_dev->setup_ops = &ad8460_buffer_setup_ops; 921 922 ret = devm_iio_dmaengine_buffer_setup_ext(dev, indio_dev, "tx", 923 IIO_BUFFER_DIRECTION_OUT); 924 if (ret) 925 return dev_err_probe(dev, ret, 926 "Failed to get DMA buffer\n"); 927 928 return devm_iio_device_register(dev, indio_dev); 929 } 930 931 static const struct of_device_id ad8460_of_match[] = { 932 { .compatible = "adi,ad8460" }, 933 { } 934 }; 935 MODULE_DEVICE_TABLE(of, ad8460_of_match); 936 937 static const struct spi_device_id ad8460_spi_match[] = { 938 { .name = "ad8460" }, 939 { } 940 }; 941 MODULE_DEVICE_TABLE(spi, ad8460_spi_match); 942 943 static struct spi_driver ad8460_driver = { 944 .driver = { 945 .name = "ad8460", 946 .of_match_table = ad8460_of_match, 947 }, 948 .probe = ad8460_probe, 949 .id_table = ad8460_spi_match, 950 }; 951 module_spi_driver(ad8460_driver); 952 953 MODULE_AUTHOR("Mariel Tinaco <mariel.tinaco@analog.com"); 954 MODULE_DESCRIPTION("AD8460 DAC driver"); 955 MODULE_LICENSE("GPL"); 956 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 957 MODULE_IMPORT_NS("IIO_CONSUMER"); 958