1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD5760, AD5780, AD5781, AD5790, AD5791 Voltage Output Digital to Analog 4 * Converter 5 * 6 * Copyright 2011 Analog Devices Inc. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/fs.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/slab.h> 18 #include <linux/spi/offload/consumer.h> 19 #include <linux/spi/spi.h> 20 #include <linux/sysfs.h> 21 #include <linux/units.h> 22 23 #include <linux/iio/buffer-dmaengine.h> 24 #include <linux/iio/dac/ad5791.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 28 #define AD5791_DAC_MASK GENMASK(19, 0) 29 30 #define AD5791_CMD_READ BIT(23) 31 #define AD5791_CMD_WRITE 0 32 #define AD5791_ADDR(addr) ((addr) << 20) 33 34 /* Registers */ 35 #define AD5791_ADDR_NOOP 0 36 #define AD5791_ADDR_DAC0 1 37 #define AD5791_ADDR_CTRL 2 38 #define AD5791_ADDR_CLRCODE 3 39 #define AD5791_ADDR_SW_CTRL 4 40 41 /* Control Register */ 42 #define AD5791_CTRL_RBUF BIT(1) 43 #define AD5791_CTRL_OPGND BIT(2) 44 #define AD5791_CTRL_DACTRI BIT(3) 45 #define AD5791_CTRL_BIN2SC BIT(4) 46 #define AD5791_CTRL_SDODIS BIT(5) 47 #define AD5761_CTRL_LINCOMP(x) ((x) << 6) 48 49 #define AD5791_LINCOMP_0_10 0 50 #define AD5791_LINCOMP_10_12 1 51 #define AD5791_LINCOMP_12_16 2 52 #define AD5791_LINCOMP_16_19 3 53 #define AD5791_LINCOMP_19_20 12 54 55 #define AD5780_LINCOMP_0_10 0 56 #define AD5780_LINCOMP_10_20 12 57 58 /* Software Control Register */ 59 #define AD5791_SWCTRL_LDAC BIT(0) 60 #define AD5791_SWCTRL_CLR BIT(1) 61 #define AD5791_SWCTRL_RESET BIT(2) 62 63 #define AD5791_DAC_PWRDN_6K 0 64 #define AD5791_DAC_PWRDN_3STATE 1 65 66 /** 67 * struct ad5791_chip_info - chip specific information 68 * @name: name of the dac chip 69 * @channel: channel specification 70 * @channel_offload: channel specification for offload 71 * @get_lin_comp: function pointer to the device specific function 72 */ 73 struct ad5791_chip_info { 74 const char *name; 75 const struct iio_chan_spec channel; 76 const struct iio_chan_spec channel_offload; 77 int (*get_lin_comp)(unsigned int span); 78 }; 79 80 /** 81 * struct ad5791_state - driver instance specific data 82 * @spi: spi_device 83 * @reg_vdd: positive supply regulator 84 * @reg_vss: negative supply regulator 85 * @gpio_reset: reset gpio 86 * @gpio_clear: clear gpio 87 * @gpio_ldac: load dac gpio 88 * @chip_info: chip model specific constants 89 * @offload_msg: spi message used for offload 90 * @offload_xfer: spi transfer used for offload 91 * @offload: offload device 92 * @offload_trigger: offload trigger 93 * @offload_trigger_hz: offload sample rate 94 * @vref_mv: actual reference voltage used 95 * @vref_neg_mv: voltage of the negative supply 96 * @ctrl: control register cache 97 * @pwr_down_mode: current power down mode 98 * @pwr_down: true if device is powered down 99 * @data: spi transfer buffers 100 */ 101 struct ad5791_state { 102 struct spi_device *spi; 103 struct regulator *reg_vdd; 104 struct regulator *reg_vss; 105 struct gpio_desc *gpio_reset; 106 struct gpio_desc *gpio_clear; 107 struct gpio_desc *gpio_ldac; 108 const struct ad5791_chip_info *chip_info; 109 struct spi_message offload_msg; 110 struct spi_transfer offload_xfer; 111 struct spi_offload *offload; 112 struct spi_offload_trigger *offload_trigger; 113 unsigned int offload_trigger_hz; 114 unsigned short vref_mv; 115 unsigned int vref_neg_mv; 116 unsigned ctrl; 117 unsigned pwr_down_mode; 118 bool pwr_down; 119 120 union { 121 __be32 d32; 122 u8 d8[4]; 123 } data[3] __aligned(IIO_DMA_MINALIGN); 124 }; 125 126 static int ad5791_spi_write(struct ad5791_state *st, u8 addr, u32 val) 127 { 128 st->data[0].d32 = cpu_to_be32(AD5791_CMD_WRITE | 129 AD5791_ADDR(addr) | 130 (val & AD5791_DAC_MASK)); 131 132 return spi_write(st->spi, &st->data[0].d8[1], 3); 133 } 134 135 static int ad5791_spi_read(struct ad5791_state *st, u8 addr, u32 *val) 136 { 137 int ret; 138 struct spi_transfer xfers[] = { 139 { 140 .tx_buf = &st->data[0].d8[1], 141 .bits_per_word = 8, 142 .len = 3, 143 .cs_change = 1, 144 }, { 145 .tx_buf = &st->data[1].d8[1], 146 .rx_buf = &st->data[2].d8[1], 147 .bits_per_word = 8, 148 .len = 3, 149 }, 150 }; 151 152 st->data[0].d32 = cpu_to_be32(AD5791_CMD_READ | 153 AD5791_ADDR(addr)); 154 st->data[1].d32 = cpu_to_be32(AD5791_ADDR(AD5791_ADDR_NOOP)); 155 156 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 157 158 *val = be32_to_cpu(st->data[2].d32); 159 160 return ret; 161 } 162 163 static const char * const ad5791_powerdown_modes[] = { 164 "6kohm_to_gnd", 165 "three_state", 166 }; 167 168 static int ad5791_get_powerdown_mode(struct iio_dev *indio_dev, 169 const struct iio_chan_spec *chan) 170 { 171 struct ad5791_state *st = iio_priv(indio_dev); 172 173 return st->pwr_down_mode; 174 } 175 176 static int ad5791_set_powerdown_mode(struct iio_dev *indio_dev, 177 const struct iio_chan_spec *chan, unsigned int mode) 178 { 179 struct ad5791_state *st = iio_priv(indio_dev); 180 181 st->pwr_down_mode = mode; 182 183 return 0; 184 } 185 186 static const struct iio_enum ad5791_powerdown_mode_enum = { 187 .items = ad5791_powerdown_modes, 188 .num_items = ARRAY_SIZE(ad5791_powerdown_modes), 189 .get = ad5791_get_powerdown_mode, 190 .set = ad5791_set_powerdown_mode, 191 }; 192 193 static ssize_t ad5791_read_dac_powerdown(struct iio_dev *indio_dev, 194 uintptr_t private, const struct iio_chan_spec *chan, char *buf) 195 { 196 struct ad5791_state *st = iio_priv(indio_dev); 197 198 return sysfs_emit(buf, "%d\n", st->pwr_down); 199 } 200 201 static ssize_t ad5791_write_dac_powerdown(struct iio_dev *indio_dev, 202 uintptr_t private, const struct iio_chan_spec *chan, const char *buf, 203 size_t len) 204 { 205 bool pwr_down; 206 int ret; 207 struct ad5791_state *st = iio_priv(indio_dev); 208 209 ret = kstrtobool(buf, &pwr_down); 210 if (ret) 211 return ret; 212 213 if (!pwr_down) { 214 st->ctrl &= ~(AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI); 215 } else { 216 if (st->pwr_down_mode == AD5791_DAC_PWRDN_6K) 217 st->ctrl |= AD5791_CTRL_OPGND; 218 else if (st->pwr_down_mode == AD5791_DAC_PWRDN_3STATE) 219 st->ctrl |= AD5791_CTRL_DACTRI; 220 } 221 st->pwr_down = pwr_down; 222 223 ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl); 224 225 return ret ? ret : len; 226 } 227 228 static int ad5791_get_lin_comp(unsigned int span) 229 { 230 if (span <= 10000) 231 return AD5791_LINCOMP_0_10; 232 else if (span <= 12000) 233 return AD5791_LINCOMP_10_12; 234 else if (span <= 16000) 235 return AD5791_LINCOMP_12_16; 236 else if (span <= 19000) 237 return AD5791_LINCOMP_16_19; 238 else 239 return AD5791_LINCOMP_19_20; 240 } 241 242 static int ad5780_get_lin_comp(unsigned int span) 243 { 244 if (span <= 10000) 245 return AD5780_LINCOMP_0_10; 246 else 247 return AD5780_LINCOMP_10_20; 248 } 249 250 static int ad5791_set_sample_freq(struct ad5791_state *st, int val) 251 { 252 struct spi_offload_trigger_config config = { 253 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 254 .periodic = { 255 .frequency_hz = val, 256 }, 257 }; 258 int ret; 259 260 ret = spi_offload_trigger_validate(st->offload_trigger, &config); 261 if (ret) 262 return ret; 263 264 st->offload_trigger_hz = config.periodic.frequency_hz; 265 266 return 0; 267 } 268 269 static int ad5791_read_raw(struct iio_dev *indio_dev, 270 struct iio_chan_spec const *chan, 271 int *val, 272 int *val2, 273 long m) 274 { 275 struct ad5791_state *st = iio_priv(indio_dev); 276 u64 val64; 277 int ret; 278 279 switch (m) { 280 case IIO_CHAN_INFO_RAW: 281 ret = ad5791_spi_read(st, chan->address, val); 282 if (ret) 283 return ret; 284 *val &= AD5791_DAC_MASK; 285 *val >>= chan->scan_type.shift; 286 return IIO_VAL_INT; 287 case IIO_CHAN_INFO_SCALE: 288 *val = st->vref_mv; 289 *val2 = (1 << chan->scan_type.realbits) - 1; 290 return IIO_VAL_FRACTIONAL; 291 case IIO_CHAN_INFO_OFFSET: 292 val64 = (((u64)st->vref_neg_mv) << chan->scan_type.realbits); 293 do_div(val64, st->vref_mv); 294 *val = -val64; 295 return IIO_VAL_INT; 296 case IIO_CHAN_INFO_SAMP_FREQ: 297 *val = st->offload_trigger_hz; 298 return IIO_VAL_INT; 299 default: 300 return -EINVAL; 301 } 302 303 }; 304 305 static const struct iio_chan_spec_ext_info ad5791_ext_info[] = { 306 { 307 .name = "powerdown", 308 .shared = IIO_SHARED_BY_TYPE, 309 .read = ad5791_read_dac_powerdown, 310 .write = ad5791_write_dac_powerdown, 311 }, 312 IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE, 313 &ad5791_powerdown_mode_enum), 314 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5791_powerdown_mode_enum), 315 { }, 316 }; 317 318 #define AD5791_DEFINE_CHIP_INFO(_name, bits, _shift, _lin_comp) \ 319 static const struct ad5791_chip_info _name##_chip_info = { \ 320 .name = #_name, \ 321 .get_lin_comp = &(_lin_comp), \ 322 .channel = { \ 323 .type = IIO_VOLTAGE, \ 324 .output = 1, \ 325 .indexed = 1, \ 326 .address = AD5791_ADDR_DAC0, \ 327 .channel = 0, \ 328 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 329 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 330 BIT(IIO_CHAN_INFO_OFFSET), \ 331 .scan_type = { \ 332 .sign = 'u', \ 333 .realbits = (bits), \ 334 .storagebits = 32, \ 335 .shift = (_shift), \ 336 }, \ 337 .ext_info = ad5791_ext_info, \ 338 }, \ 339 .channel_offload = { \ 340 .type = IIO_VOLTAGE, \ 341 .output = 1, \ 342 .indexed = 1, \ 343 .address = AD5791_ADDR_DAC0, \ 344 .channel = 0, \ 345 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 346 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 347 BIT(IIO_CHAN_INFO_OFFSET), \ 348 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 349 .scan_type = { \ 350 .sign = 'u', \ 351 .realbits = (bits), \ 352 .storagebits = 32, \ 353 .shift = (_shift), \ 354 }, \ 355 .ext_info = ad5791_ext_info, \ 356 }, \ 357 } 358 359 AD5791_DEFINE_CHIP_INFO(ad5760, 16, 4, ad5780_get_lin_comp); 360 AD5791_DEFINE_CHIP_INFO(ad5780, 18, 2, ad5780_get_lin_comp); 361 AD5791_DEFINE_CHIP_INFO(ad5781, 18, 2, ad5791_get_lin_comp); 362 AD5791_DEFINE_CHIP_INFO(ad5790, 20, 0, ad5791_get_lin_comp); 363 AD5791_DEFINE_CHIP_INFO(ad5791, 20, 0, ad5791_get_lin_comp); 364 365 static int ad5791_write_raw(struct iio_dev *indio_dev, 366 struct iio_chan_spec const *chan, 367 int val, 368 int val2, 369 long mask) 370 { 371 struct ad5791_state *st = iio_priv(indio_dev); 372 373 switch (mask) { 374 case IIO_CHAN_INFO_RAW: 375 val &= GENMASK(chan->scan_type.realbits - 1, 0); 376 val <<= chan->scan_type.shift; 377 378 return ad5791_spi_write(st, chan->address, val); 379 380 case IIO_CHAN_INFO_SAMP_FREQ: 381 if (val < 1) 382 return -EINVAL; 383 return ad5791_set_sample_freq(st, val); 384 default: 385 return -EINVAL; 386 } 387 } 388 389 static int ad5791_write_raw_get_fmt(struct iio_dev *indio_dev, 390 struct iio_chan_spec const *chan, 391 long mask) 392 { 393 switch (mask) { 394 case IIO_CHAN_INFO_SAMP_FREQ: 395 return IIO_VAL_INT; 396 default: 397 return IIO_VAL_INT_PLUS_MICRO; 398 } 399 } 400 401 static int ad5791_buffer_preenable(struct iio_dev *indio_dev) 402 { 403 struct ad5791_state *st = iio_priv(indio_dev); 404 struct spi_offload_trigger_config config = { 405 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 406 .periodic = { 407 .frequency_hz = st->offload_trigger_hz, 408 }, 409 }; 410 411 if (st->pwr_down) 412 return -EINVAL; 413 414 return spi_offload_trigger_enable(st->offload, st->offload_trigger, 415 &config); 416 } 417 418 static int ad5791_buffer_postdisable(struct iio_dev *indio_dev) 419 { 420 struct ad5791_state *st = iio_priv(indio_dev); 421 422 spi_offload_trigger_disable(st->offload, st->offload_trigger); 423 424 return 0; 425 } 426 427 static const struct iio_buffer_setup_ops ad5791_buffer_setup_ops = { 428 .preenable = &ad5791_buffer_preenable, 429 .postdisable = &ad5791_buffer_postdisable, 430 }; 431 432 static int ad5791_offload_setup(struct iio_dev *indio_dev) 433 { 434 struct ad5791_state *st = iio_priv(indio_dev); 435 struct spi_device *spi = st->spi; 436 struct dma_chan *tx_dma; 437 int ret; 438 439 st->offload_trigger = devm_spi_offload_trigger_get(&spi->dev, 440 st->offload, SPI_OFFLOAD_TRIGGER_PERIODIC); 441 if (IS_ERR(st->offload_trigger)) 442 return dev_err_probe(&spi->dev, PTR_ERR(st->offload_trigger), 443 "failed to get offload trigger\n"); 444 445 ret = ad5791_set_sample_freq(st, 1 * MEGA); 446 if (ret) 447 return dev_err_probe(&spi->dev, ret, 448 "failed to init sample rate\n"); 449 450 tx_dma = devm_spi_offload_tx_stream_request_dma_chan(&spi->dev, 451 st->offload); 452 if (IS_ERR(tx_dma)) 453 return dev_err_probe(&spi->dev, PTR_ERR(tx_dma), 454 "failed to get offload TX DMA\n"); 455 456 ret = devm_iio_dmaengine_buffer_setup_with_handle(&spi->dev, 457 indio_dev, tx_dma, IIO_BUFFER_DIRECTION_OUT); 458 if (ret) 459 return ret; 460 461 st->offload_xfer.len = 4; 462 st->offload_xfer.bits_per_word = 24; 463 st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_TX_STREAM; 464 465 spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); 466 st->offload_msg.offload = st->offload; 467 468 return devm_spi_optimize_message(&spi->dev, st->spi, &st->offload_msg); 469 } 470 471 static const struct iio_info ad5791_info = { 472 .read_raw = &ad5791_read_raw, 473 .write_raw = &ad5791_write_raw, 474 .write_raw_get_fmt = &ad5791_write_raw_get_fmt, 475 }; 476 477 static const struct spi_offload_config ad5791_offload_config = { 478 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 479 SPI_OFFLOAD_CAP_TX_STREAM_DMA, 480 }; 481 482 static int ad5791_probe(struct spi_device *spi) 483 { 484 const struct ad5791_platform_data *pdata = dev_get_platdata(&spi->dev); 485 struct iio_dev *indio_dev; 486 struct ad5791_state *st; 487 int ret, pos_voltage_uv = 0, neg_voltage_uv = 0; 488 bool use_rbuf_gain2; 489 490 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 491 if (!indio_dev) 492 return -ENOMEM; 493 st = iio_priv(indio_dev); 494 495 st->gpio_reset = devm_gpiod_get_optional(&spi->dev, "reset", 496 GPIOD_OUT_HIGH); 497 if (IS_ERR(st->gpio_reset)) 498 return PTR_ERR(st->gpio_reset); 499 500 st->gpio_clear = devm_gpiod_get_optional(&spi->dev, "clear", 501 GPIOD_OUT_LOW); 502 if (IS_ERR(st->gpio_clear)) 503 return PTR_ERR(st->gpio_clear); 504 505 st->gpio_ldac = devm_gpiod_get_optional(&spi->dev, "ldac", 506 GPIOD_OUT_HIGH); 507 if (IS_ERR(st->gpio_ldac)) 508 return PTR_ERR(st->gpio_ldac); 509 510 st->pwr_down = true; 511 st->spi = spi; 512 513 if (pdata) 514 use_rbuf_gain2 = pdata->use_rbuf_gain2; 515 else 516 use_rbuf_gain2 = device_property_read_bool(&spi->dev, 517 "adi,rbuf-gain2-en"); 518 519 pos_voltage_uv = devm_regulator_get_enable_read_voltage(&spi->dev, "vdd"); 520 if (pos_voltage_uv < 0 && pos_voltage_uv != -ENODEV) 521 return dev_err_probe(&spi->dev, pos_voltage_uv, 522 "failed to get vdd voltage\n"); 523 524 neg_voltage_uv = devm_regulator_get_enable_read_voltage(&spi->dev, "vss"); 525 if (neg_voltage_uv < 0 && neg_voltage_uv != -ENODEV) 526 return dev_err_probe(&spi->dev, neg_voltage_uv, 527 "failed to get vss voltage\n"); 528 529 if (neg_voltage_uv >= 0 && pos_voltage_uv >= 0) { 530 st->vref_mv = (pos_voltage_uv + neg_voltage_uv) / 1000; 531 st->vref_neg_mv = neg_voltage_uv / 1000; 532 } else if (pdata) { 533 st->vref_mv = pdata->vref_pos_mv + pdata->vref_neg_mv; 534 st->vref_neg_mv = pdata->vref_neg_mv; 535 } else { 536 dev_warn(&spi->dev, "reference voltage unspecified\n"); 537 } 538 539 if (st->gpio_reset) { 540 fsleep(20); 541 gpiod_set_value_cansleep(st->gpio_reset, 0); 542 } else { 543 ret = ad5791_spi_write(st, AD5791_ADDR_SW_CTRL, AD5791_SWCTRL_RESET); 544 if (ret) 545 return dev_err_probe(&spi->dev, ret, "fail to reset\n"); 546 } 547 548 st->chip_info = spi_get_device_match_data(spi); 549 if (!st->chip_info) 550 return dev_err_probe(&spi->dev, -EINVAL, "no chip info\n"); 551 552 st->ctrl = AD5761_CTRL_LINCOMP(st->chip_info->get_lin_comp(st->vref_mv)) 553 | (use_rbuf_gain2 ? 0 : AD5791_CTRL_RBUF) | 554 AD5791_CTRL_BIN2SC; 555 556 ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl | 557 AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI); 558 if (ret) 559 return dev_err_probe(&spi->dev, ret, "fail to write ctrl register\n"); 560 561 indio_dev->info = &ad5791_info; 562 indio_dev->modes = INDIO_DIRECT_MODE; 563 indio_dev->channels = &st->chip_info->channel; 564 indio_dev->num_channels = 1; 565 indio_dev->name = st->chip_info->name; 566 567 st->offload = devm_spi_offload_get(&spi->dev, spi, &ad5791_offload_config); 568 ret = PTR_ERR_OR_ZERO(st->offload); 569 if (ret && ret != -ENODEV) 570 return dev_err_probe(&spi->dev, ret, "failed to get offload\n"); 571 572 if (ret != -ENODEV) { 573 indio_dev->channels = &st->chip_info->channel_offload; 574 indio_dev->setup_ops = &ad5791_buffer_setup_ops; 575 ret = ad5791_offload_setup(indio_dev); 576 if (ret) 577 return dev_err_probe(&spi->dev, ret, 578 "fail to setup offload\n"); 579 } 580 581 return devm_iio_device_register(&spi->dev, indio_dev); 582 } 583 584 static const struct of_device_id ad5791_of_match[] = { 585 { .compatible = "adi,ad5760", .data = &ad5760_chip_info }, 586 { .compatible = "adi,ad5780", .data = &ad5780_chip_info }, 587 { .compatible = "adi,ad5781", .data = &ad5781_chip_info }, 588 { .compatible = "adi,ad5790", .data = &ad5790_chip_info }, 589 { .compatible = "adi,ad5791", .data = &ad5791_chip_info }, 590 { } 591 }; 592 MODULE_DEVICE_TABLE(of, ad5791_of_match); 593 594 static const struct spi_device_id ad5791_id[] = { 595 { "ad5760", (kernel_ulong_t)&ad5760_chip_info }, 596 { "ad5780", (kernel_ulong_t)&ad5780_chip_info }, 597 { "ad5781", (kernel_ulong_t)&ad5781_chip_info }, 598 { "ad5790", (kernel_ulong_t)&ad5790_chip_info }, 599 { "ad5791", (kernel_ulong_t)&ad5791_chip_info }, 600 { } 601 }; 602 MODULE_DEVICE_TABLE(spi, ad5791_id); 603 604 static struct spi_driver ad5791_driver = { 605 .driver = { 606 .name = "ad5791", 607 .of_match_table = ad5791_of_match, 608 }, 609 .probe = ad5791_probe, 610 .id_table = ad5791_id, 611 }; 612 module_spi_driver(ad5791_driver); 613 614 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 615 MODULE_DESCRIPTION("Analog Devices AD5760/AD5780/AD5781/AD5790/AD5791 DAC"); 616 MODULE_LICENSE("GPL v2"); 617 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 618