1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD5760, AD5780, AD5781, AD5790, AD5791 Voltage Output Digital to Analog 4 * Converter 5 * 6 * Copyright 2011 Analog Devices Inc. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/fs.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/slab.h> 18 #include <linux/spi/offload/consumer.h> 19 #include <linux/spi/spi.h> 20 #include <linux/sysfs.h> 21 #include <linux/units.h> 22 23 #include <linux/iio/buffer-dmaengine.h> 24 #include <linux/iio/dac/ad5791.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 28 #define AD5791_DAC_MASK GENMASK(19, 0) 29 30 #define AD5791_CMD_READ BIT(23) 31 #define AD5791_CMD_WRITE 0 32 #define AD5791_ADDR(addr) ((addr) << 20) 33 34 /* Registers */ 35 #define AD5791_ADDR_NOOP 0 36 #define AD5791_ADDR_DAC0 1 37 #define AD5791_ADDR_CTRL 2 38 #define AD5791_ADDR_CLRCODE 3 39 #define AD5791_ADDR_SW_CTRL 4 40 41 /* Control Register */ 42 #define AD5791_CTRL_RBUF BIT(1) 43 #define AD5791_CTRL_OPGND BIT(2) 44 #define AD5791_CTRL_DACTRI BIT(3) 45 #define AD5791_CTRL_BIN2SC BIT(4) 46 #define AD5791_CTRL_SDODIS BIT(5) 47 #define AD5761_CTRL_LINCOMP(x) ((x) << 6) 48 49 #define AD5791_LINCOMP_0_10 0 50 #define AD5791_LINCOMP_10_12 1 51 #define AD5791_LINCOMP_12_16 2 52 #define AD5791_LINCOMP_16_19 3 53 #define AD5791_LINCOMP_19_20 12 54 55 #define AD5780_LINCOMP_0_10 0 56 #define AD5780_LINCOMP_10_20 12 57 58 /* Software Control Register */ 59 #define AD5791_SWCTRL_LDAC BIT(0) 60 #define AD5791_SWCTRL_CLR BIT(1) 61 #define AD5791_SWCTRL_RESET BIT(2) 62 63 #define AD5791_DAC_PWRDN_6K 0 64 #define AD5791_DAC_PWRDN_3STATE 1 65 66 /** 67 * struct ad5791_chip_info - chip specific information 68 * @name: name of the dac chip 69 * @channel: channel specification 70 * @channel_offload: channel specification for offload 71 * @get_lin_comp: function pointer to the device specific function 72 */ 73 struct ad5791_chip_info { 74 const char *name; 75 const struct iio_chan_spec channel; 76 const struct iio_chan_spec channel_offload; 77 int (*get_lin_comp)(unsigned int span); 78 }; 79 80 /** 81 * struct ad5791_state - driver instance specific data 82 * @spi: spi_device 83 * @gpio_reset: reset gpio 84 * @gpio_clear: clear gpio 85 * @gpio_ldac: load dac gpio 86 * @chip_info: chip model specific constants 87 * @offload_msg: spi message used for offload 88 * @offload_xfer: spi transfer used for offload 89 * @offload: offload device 90 * @offload_trigger: offload trigger 91 * @offload_trigger_hz: offload sample rate 92 * @vref_mv: actual reference voltage used 93 * @vref_neg_mv: voltage of the negative supply 94 * @ctrl: control register cache 95 * @pwr_down_mode: current power down mode 96 * @pwr_down: true if device is powered down 97 * @data: spi transfer buffers 98 */ 99 struct ad5791_state { 100 struct spi_device *spi; 101 struct gpio_desc *gpio_reset; 102 struct gpio_desc *gpio_clear; 103 struct gpio_desc *gpio_ldac; 104 const struct ad5791_chip_info *chip_info; 105 struct spi_message offload_msg; 106 struct spi_transfer offload_xfer; 107 struct spi_offload *offload; 108 struct spi_offload_trigger *offload_trigger; 109 unsigned int offload_trigger_hz; 110 unsigned short vref_mv; 111 unsigned int vref_neg_mv; 112 unsigned ctrl; 113 unsigned pwr_down_mode; 114 bool pwr_down; 115 116 union { 117 __be32 d32; 118 u8 d8[4]; 119 } data[3] __aligned(IIO_DMA_MINALIGN); 120 }; 121 122 static int ad5791_spi_write(struct ad5791_state *st, u8 addr, u32 val) 123 { 124 st->data[0].d32 = cpu_to_be32(AD5791_CMD_WRITE | 125 AD5791_ADDR(addr) | 126 (val & AD5791_DAC_MASK)); 127 128 return spi_write(st->spi, &st->data[0].d8[1], 3); 129 } 130 131 static int ad5791_spi_read(struct ad5791_state *st, u8 addr, u32 *val) 132 { 133 int ret; 134 struct spi_transfer xfers[] = { 135 { 136 .tx_buf = &st->data[0].d8[1], 137 .len = 3, 138 .cs_change = 1, 139 }, { 140 .tx_buf = &st->data[1].d8[1], 141 .rx_buf = &st->data[2].d8[1], 142 .len = 3, 143 }, 144 }; 145 146 st->data[0].d32 = cpu_to_be32(AD5791_CMD_READ | 147 AD5791_ADDR(addr)); 148 st->data[1].d32 = cpu_to_be32(AD5791_ADDR(AD5791_ADDR_NOOP)); 149 150 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 151 152 *val = be32_to_cpu(st->data[2].d32); 153 154 return ret; 155 } 156 157 static const char * const ad5791_powerdown_modes[] = { 158 "6kohm_to_gnd", 159 "three_state", 160 }; 161 162 static int ad5791_get_powerdown_mode(struct iio_dev *indio_dev, 163 const struct iio_chan_spec *chan) 164 { 165 struct ad5791_state *st = iio_priv(indio_dev); 166 167 return st->pwr_down_mode; 168 } 169 170 static int ad5791_set_powerdown_mode(struct iio_dev *indio_dev, 171 const struct iio_chan_spec *chan, unsigned int mode) 172 { 173 struct ad5791_state *st = iio_priv(indio_dev); 174 175 st->pwr_down_mode = mode; 176 177 return 0; 178 } 179 180 static const struct iio_enum ad5791_powerdown_mode_enum = { 181 .items = ad5791_powerdown_modes, 182 .num_items = ARRAY_SIZE(ad5791_powerdown_modes), 183 .get = ad5791_get_powerdown_mode, 184 .set = ad5791_set_powerdown_mode, 185 }; 186 187 static ssize_t ad5791_read_dac_powerdown(struct iio_dev *indio_dev, 188 uintptr_t private, const struct iio_chan_spec *chan, char *buf) 189 { 190 struct ad5791_state *st = iio_priv(indio_dev); 191 192 return sysfs_emit(buf, "%d\n", st->pwr_down); 193 } 194 195 static ssize_t ad5791_write_dac_powerdown(struct iio_dev *indio_dev, 196 uintptr_t private, const struct iio_chan_spec *chan, const char *buf, 197 size_t len) 198 { 199 bool pwr_down; 200 int ret; 201 struct ad5791_state *st = iio_priv(indio_dev); 202 203 ret = kstrtobool(buf, &pwr_down); 204 if (ret) 205 return ret; 206 207 if (!pwr_down) { 208 st->ctrl &= ~(AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI); 209 } else { 210 if (st->pwr_down_mode == AD5791_DAC_PWRDN_6K) 211 st->ctrl |= AD5791_CTRL_OPGND; 212 else if (st->pwr_down_mode == AD5791_DAC_PWRDN_3STATE) 213 st->ctrl |= AD5791_CTRL_DACTRI; 214 } 215 st->pwr_down = pwr_down; 216 217 ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl); 218 219 return ret ? ret : len; 220 } 221 222 static int ad5791_get_lin_comp(unsigned int span) 223 { 224 if (span <= 10000) 225 return AD5791_LINCOMP_0_10; 226 else if (span <= 12000) 227 return AD5791_LINCOMP_10_12; 228 else if (span <= 16000) 229 return AD5791_LINCOMP_12_16; 230 else if (span <= 19000) 231 return AD5791_LINCOMP_16_19; 232 else 233 return AD5791_LINCOMP_19_20; 234 } 235 236 static int ad5780_get_lin_comp(unsigned int span) 237 { 238 if (span <= 10000) 239 return AD5780_LINCOMP_0_10; 240 else 241 return AD5780_LINCOMP_10_20; 242 } 243 244 static int ad5791_set_sample_freq(struct ad5791_state *st, int val) 245 { 246 struct spi_offload_trigger_config config = { 247 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 248 .periodic = { 249 .frequency_hz = val, 250 }, 251 }; 252 int ret; 253 254 ret = spi_offload_trigger_validate(st->offload_trigger, &config); 255 if (ret) 256 return ret; 257 258 st->offload_trigger_hz = config.periodic.frequency_hz; 259 260 return 0; 261 } 262 263 static int ad5791_read_raw(struct iio_dev *indio_dev, 264 struct iio_chan_spec const *chan, 265 int *val, 266 int *val2, 267 long m) 268 { 269 struct ad5791_state *st = iio_priv(indio_dev); 270 u64 val64; 271 int ret; 272 273 switch (m) { 274 case IIO_CHAN_INFO_RAW: 275 ret = ad5791_spi_read(st, chan->address, val); 276 if (ret) 277 return ret; 278 *val &= AD5791_DAC_MASK; 279 *val >>= chan->scan_type.shift; 280 return IIO_VAL_INT; 281 case IIO_CHAN_INFO_SCALE: 282 *val = st->vref_mv; 283 *val2 = (1 << chan->scan_type.realbits) - 1; 284 return IIO_VAL_FRACTIONAL; 285 case IIO_CHAN_INFO_OFFSET: 286 val64 = (((u64)st->vref_neg_mv) << chan->scan_type.realbits); 287 do_div(val64, st->vref_mv); 288 *val = -val64; 289 return IIO_VAL_INT; 290 case IIO_CHAN_INFO_SAMP_FREQ: 291 *val = st->offload_trigger_hz; 292 return IIO_VAL_INT; 293 default: 294 return -EINVAL; 295 } 296 297 }; 298 299 static const struct iio_chan_spec_ext_info ad5791_ext_info[] = { 300 { 301 .name = "powerdown", 302 .shared = IIO_SHARED_BY_TYPE, 303 .read = ad5791_read_dac_powerdown, 304 .write = ad5791_write_dac_powerdown, 305 }, 306 IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE, 307 &ad5791_powerdown_mode_enum), 308 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5791_powerdown_mode_enum), 309 { } 310 }; 311 312 #define AD5791_DEFINE_CHIP_INFO(_name, bits, _shift, _lin_comp) \ 313 static const struct ad5791_chip_info _name##_chip_info = { \ 314 .name = #_name, \ 315 .get_lin_comp = &(_lin_comp), \ 316 .channel = { \ 317 .type = IIO_VOLTAGE, \ 318 .output = 1, \ 319 .indexed = 1, \ 320 .address = AD5791_ADDR_DAC0, \ 321 .channel = 0, \ 322 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 323 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 324 BIT(IIO_CHAN_INFO_OFFSET), \ 325 .scan_type = { \ 326 .sign = 'u', \ 327 .realbits = (bits), \ 328 .storagebits = 32, \ 329 .shift = (_shift), \ 330 }, \ 331 .ext_info = ad5791_ext_info, \ 332 }, \ 333 .channel_offload = { \ 334 .type = IIO_VOLTAGE, \ 335 .output = 1, \ 336 .indexed = 1, \ 337 .address = AD5791_ADDR_DAC0, \ 338 .channel = 0, \ 339 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 340 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 341 BIT(IIO_CHAN_INFO_OFFSET), \ 342 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 343 .scan_type = { \ 344 .sign = 'u', \ 345 .realbits = (bits), \ 346 .storagebits = 32, \ 347 .shift = (_shift), \ 348 }, \ 349 .ext_info = ad5791_ext_info, \ 350 }, \ 351 } 352 353 AD5791_DEFINE_CHIP_INFO(ad5760, 16, 4, ad5780_get_lin_comp); 354 AD5791_DEFINE_CHIP_INFO(ad5780, 18, 2, ad5780_get_lin_comp); 355 AD5791_DEFINE_CHIP_INFO(ad5781, 18, 2, ad5791_get_lin_comp); 356 AD5791_DEFINE_CHIP_INFO(ad5790, 20, 0, ad5791_get_lin_comp); 357 AD5791_DEFINE_CHIP_INFO(ad5791, 20, 0, ad5791_get_lin_comp); 358 359 static int ad5791_write_raw(struct iio_dev *indio_dev, 360 struct iio_chan_spec const *chan, 361 int val, 362 int val2, 363 long mask) 364 { 365 struct ad5791_state *st = iio_priv(indio_dev); 366 367 switch (mask) { 368 case IIO_CHAN_INFO_RAW: 369 val &= GENMASK(chan->scan_type.realbits - 1, 0); 370 val <<= chan->scan_type.shift; 371 372 return ad5791_spi_write(st, chan->address, val); 373 374 case IIO_CHAN_INFO_SAMP_FREQ: 375 if (val < 1) 376 return -EINVAL; 377 return ad5791_set_sample_freq(st, val); 378 default: 379 return -EINVAL; 380 } 381 } 382 383 static int ad5791_write_raw_get_fmt(struct iio_dev *indio_dev, 384 struct iio_chan_spec const *chan, 385 long mask) 386 { 387 switch (mask) { 388 case IIO_CHAN_INFO_SAMP_FREQ: 389 return IIO_VAL_INT; 390 default: 391 return IIO_VAL_INT_PLUS_MICRO; 392 } 393 } 394 395 static int ad5791_buffer_preenable(struct iio_dev *indio_dev) 396 { 397 struct ad5791_state *st = iio_priv(indio_dev); 398 struct spi_offload_trigger_config config = { 399 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 400 .periodic = { 401 .frequency_hz = st->offload_trigger_hz, 402 }, 403 }; 404 405 if (st->pwr_down) 406 return -EINVAL; 407 408 return spi_offload_trigger_enable(st->offload, st->offload_trigger, 409 &config); 410 } 411 412 static int ad5791_buffer_postdisable(struct iio_dev *indio_dev) 413 { 414 struct ad5791_state *st = iio_priv(indio_dev); 415 416 spi_offload_trigger_disable(st->offload, st->offload_trigger); 417 418 return 0; 419 } 420 421 static const struct iio_buffer_setup_ops ad5791_buffer_setup_ops = { 422 .preenable = &ad5791_buffer_preenable, 423 .postdisable = &ad5791_buffer_postdisable, 424 }; 425 426 static int ad5791_offload_setup(struct iio_dev *indio_dev) 427 { 428 struct ad5791_state *st = iio_priv(indio_dev); 429 struct spi_device *spi = st->spi; 430 struct dma_chan *tx_dma; 431 int ret; 432 433 st->offload_trigger = devm_spi_offload_trigger_get(&spi->dev, 434 st->offload, SPI_OFFLOAD_TRIGGER_PERIODIC); 435 if (IS_ERR(st->offload_trigger)) 436 return dev_err_probe(&spi->dev, PTR_ERR(st->offload_trigger), 437 "failed to get offload trigger\n"); 438 439 ret = ad5791_set_sample_freq(st, 1 * MEGA); 440 if (ret) 441 return dev_err_probe(&spi->dev, ret, 442 "failed to init sample rate\n"); 443 444 tx_dma = devm_spi_offload_tx_stream_request_dma_chan(&spi->dev, 445 st->offload); 446 if (IS_ERR(tx_dma)) 447 return dev_err_probe(&spi->dev, PTR_ERR(tx_dma), 448 "failed to get offload TX DMA\n"); 449 450 ret = devm_iio_dmaengine_buffer_setup_with_handle(&spi->dev, 451 indio_dev, tx_dma, IIO_BUFFER_DIRECTION_OUT); 452 if (ret) 453 return ret; 454 455 st->offload_xfer.len = 4; 456 st->offload_xfer.bits_per_word = 24; 457 st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_TX_STREAM; 458 459 spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); 460 st->offload_msg.offload = st->offload; 461 462 return devm_spi_optimize_message(&spi->dev, st->spi, &st->offload_msg); 463 } 464 465 static const struct iio_info ad5791_info = { 466 .read_raw = &ad5791_read_raw, 467 .write_raw = &ad5791_write_raw, 468 .write_raw_get_fmt = &ad5791_write_raw_get_fmt, 469 }; 470 471 static const struct spi_offload_config ad5791_offload_config = { 472 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 473 SPI_OFFLOAD_CAP_TX_STREAM_DMA, 474 }; 475 476 static int ad5791_probe(struct spi_device *spi) 477 { 478 const struct ad5791_platform_data *pdata = dev_get_platdata(&spi->dev); 479 struct iio_dev *indio_dev; 480 struct ad5791_state *st; 481 int ret, pos_voltage_uv = 0, neg_voltage_uv = 0; 482 bool use_rbuf_gain2; 483 484 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 485 if (!indio_dev) 486 return -ENOMEM; 487 st = iio_priv(indio_dev); 488 489 st->gpio_reset = devm_gpiod_get_optional(&spi->dev, "reset", 490 GPIOD_OUT_HIGH); 491 if (IS_ERR(st->gpio_reset)) 492 return PTR_ERR(st->gpio_reset); 493 494 st->gpio_clear = devm_gpiod_get_optional(&spi->dev, "clear", 495 GPIOD_OUT_LOW); 496 if (IS_ERR(st->gpio_clear)) 497 return PTR_ERR(st->gpio_clear); 498 499 st->gpio_ldac = devm_gpiod_get_optional(&spi->dev, "ldac", 500 GPIOD_OUT_HIGH); 501 if (IS_ERR(st->gpio_ldac)) 502 return PTR_ERR(st->gpio_ldac); 503 504 st->pwr_down = true; 505 st->spi = spi; 506 507 if (pdata) 508 use_rbuf_gain2 = pdata->use_rbuf_gain2; 509 else 510 use_rbuf_gain2 = device_property_read_bool(&spi->dev, 511 "adi,rbuf-gain2-en"); 512 513 pos_voltage_uv = devm_regulator_get_enable_read_voltage(&spi->dev, "vdd"); 514 if (pos_voltage_uv < 0 && pos_voltage_uv != -ENODEV) 515 return dev_err_probe(&spi->dev, pos_voltage_uv, 516 "failed to get vdd voltage\n"); 517 518 neg_voltage_uv = devm_regulator_get_enable_read_voltage(&spi->dev, "vss"); 519 if (neg_voltage_uv < 0 && neg_voltage_uv != -ENODEV) 520 return dev_err_probe(&spi->dev, neg_voltage_uv, 521 "failed to get vss voltage\n"); 522 523 if (neg_voltage_uv >= 0 && pos_voltage_uv >= 0) { 524 st->vref_mv = (pos_voltage_uv + neg_voltage_uv) / 1000; 525 st->vref_neg_mv = neg_voltage_uv / 1000; 526 } else if (pdata) { 527 st->vref_mv = pdata->vref_pos_mv + pdata->vref_neg_mv; 528 st->vref_neg_mv = pdata->vref_neg_mv; 529 } else { 530 dev_warn(&spi->dev, "reference voltage unspecified\n"); 531 } 532 533 if (st->gpio_reset) { 534 fsleep(20); 535 gpiod_set_value_cansleep(st->gpio_reset, 0); 536 } else { 537 ret = ad5791_spi_write(st, AD5791_ADDR_SW_CTRL, AD5791_SWCTRL_RESET); 538 if (ret) 539 return dev_err_probe(&spi->dev, ret, "fail to reset\n"); 540 } 541 542 st->chip_info = spi_get_device_match_data(spi); 543 if (!st->chip_info) 544 return dev_err_probe(&spi->dev, -EINVAL, "no chip info\n"); 545 546 st->ctrl = AD5761_CTRL_LINCOMP(st->chip_info->get_lin_comp(st->vref_mv)) 547 | (use_rbuf_gain2 ? 0 : AD5791_CTRL_RBUF) | 548 AD5791_CTRL_BIN2SC; 549 550 ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl | 551 AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI); 552 if (ret) 553 return dev_err_probe(&spi->dev, ret, "fail to write ctrl register\n"); 554 555 indio_dev->info = &ad5791_info; 556 indio_dev->modes = INDIO_DIRECT_MODE; 557 indio_dev->channels = &st->chip_info->channel; 558 indio_dev->num_channels = 1; 559 indio_dev->name = st->chip_info->name; 560 561 st->offload = devm_spi_offload_get(&spi->dev, spi, &ad5791_offload_config); 562 ret = PTR_ERR_OR_ZERO(st->offload); 563 if (ret && ret != -ENODEV) 564 return dev_err_probe(&spi->dev, ret, "failed to get offload\n"); 565 566 if (ret != -ENODEV) { 567 indio_dev->channels = &st->chip_info->channel_offload; 568 indio_dev->setup_ops = &ad5791_buffer_setup_ops; 569 ret = ad5791_offload_setup(indio_dev); 570 if (ret) 571 return dev_err_probe(&spi->dev, ret, 572 "fail to setup offload\n"); 573 } 574 575 return devm_iio_device_register(&spi->dev, indio_dev); 576 } 577 578 static const struct of_device_id ad5791_of_match[] = { 579 { .compatible = "adi,ad5760", .data = &ad5760_chip_info }, 580 { .compatible = "adi,ad5780", .data = &ad5780_chip_info }, 581 { .compatible = "adi,ad5781", .data = &ad5781_chip_info }, 582 { .compatible = "adi,ad5790", .data = &ad5790_chip_info }, 583 { .compatible = "adi,ad5791", .data = &ad5791_chip_info }, 584 { } 585 }; 586 MODULE_DEVICE_TABLE(of, ad5791_of_match); 587 588 static const struct spi_device_id ad5791_id[] = { 589 { "ad5760", (kernel_ulong_t)&ad5760_chip_info }, 590 { "ad5780", (kernel_ulong_t)&ad5780_chip_info }, 591 { "ad5781", (kernel_ulong_t)&ad5781_chip_info }, 592 { "ad5790", (kernel_ulong_t)&ad5790_chip_info }, 593 { "ad5791", (kernel_ulong_t)&ad5791_chip_info }, 594 { } 595 }; 596 MODULE_DEVICE_TABLE(spi, ad5791_id); 597 598 static struct spi_driver ad5791_driver = { 599 .driver = { 600 .name = "ad5791", 601 .of_match_table = ad5791_of_match, 602 }, 603 .probe = ad5791_probe, 604 .id_table = ad5791_id, 605 }; 606 module_spi_driver(ad5791_driver); 607 608 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 609 MODULE_DESCRIPTION("Analog Devices AD5760/AD5780/AD5781/AD5790/AD5791 DAC"); 610 MODULE_LICENSE("GPL v2"); 611 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 612